1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "internal.h"
24 #include "disas/disas.h"
25 #include "exec/exec-all.h"
26 #include "tcg-op.h"
27 #include "qemu/host-utils.h"
28 #include "exec/cpu_ldst.h"
29
30 #include "exec/helper-proto.h"
31 #include "exec/helper-gen.h"
32
33 #include "trace-tcg.h"
34 #include "exec/translator.h"
35 #include "exec/log.h"
36
37
38 #define CPU_SINGLE_STEP 0x1
39 #define CPU_BRANCH_STEP 0x2
40 #define GDBSTUB_SINGLE_STEP 0x4
41
42 /* Include definitions for instructions classes and implementations flags */
43 //#define PPC_DEBUG_DISAS
44 //#define DO_PPC_STATISTICS
45
46 #ifdef PPC_DEBUG_DISAS
47 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
48 #else
49 # define LOG_DISAS(...) do { } while (0)
50 #endif
51 /*****************************************************************************/
52 /* Code translation helpers */
53
54 /* global register indexes */
55 static char cpu_reg_names[10*3 + 22*4 /* GPR */
56 + 10*4 + 22*5 /* SPE GPRh */
57 + 10*4 + 22*5 /* FPR */
58 + 2*(10*6 + 22*7) /* AVRh, AVRl */
59 + 10*5 + 22*6 /* VSR */
60 + 8*5 /* CRF */];
61 static TCGv cpu_gpr[32];
62 static TCGv cpu_gprh[32];
63 static TCGv_i64 cpu_fpr[32];
64 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
65 static TCGv_i64 cpu_vsr[32];
66 static TCGv_i32 cpu_crf[8];
67 static TCGv cpu_nip;
68 static TCGv cpu_msr;
69 static TCGv cpu_ctr;
70 static TCGv cpu_lr;
71 #if defined(TARGET_PPC64)
72 static TCGv cpu_cfar;
73 #endif
74 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32;
75 static TCGv cpu_reserve;
76 static TCGv cpu_reserve_val;
77 static TCGv cpu_fpscr;
78 static TCGv_i32 cpu_access_type;
79
80 #include "exec/gen-icount.h"
81
ppc_translate_init(void)82 void ppc_translate_init(void)
83 {
84 int i;
85 char* p;
86 size_t cpu_reg_names_size;
87
88 p = cpu_reg_names;
89 cpu_reg_names_size = sizeof(cpu_reg_names);
90
91 for (i = 0; i < 8; i++) {
92 snprintf(p, cpu_reg_names_size, "crf%d", i);
93 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
94 offsetof(CPUPPCState, crf[i]), p);
95 p += 5;
96 cpu_reg_names_size -= 5;
97 }
98
99 for (i = 0; i < 32; i++) {
100 snprintf(p, cpu_reg_names_size, "r%d", i);
101 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
102 offsetof(CPUPPCState, gpr[i]), p);
103 p += (i < 10) ? 3 : 4;
104 cpu_reg_names_size -= (i < 10) ? 3 : 4;
105 snprintf(p, cpu_reg_names_size, "r%dH", i);
106 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
107 offsetof(CPUPPCState, gprh[i]), p);
108 p += (i < 10) ? 4 : 5;
109 cpu_reg_names_size -= (i < 10) ? 4 : 5;
110
111 snprintf(p, cpu_reg_names_size, "fp%d", i);
112 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
113 offsetof(CPUPPCState, fpr[i]), p);
114 p += (i < 10) ? 4 : 5;
115 cpu_reg_names_size -= (i < 10) ? 4 : 5;
116
117 snprintf(p, cpu_reg_names_size, "avr%dH", i);
118 #ifdef HOST_WORDS_BIGENDIAN
119 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
120 offsetof(CPUPPCState, avr[i].u64[0]), p);
121 #else
122 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
123 offsetof(CPUPPCState, avr[i].u64[1]), p);
124 #endif
125 p += (i < 10) ? 6 : 7;
126 cpu_reg_names_size -= (i < 10) ? 6 : 7;
127
128 snprintf(p, cpu_reg_names_size, "avr%dL", i);
129 #ifdef HOST_WORDS_BIGENDIAN
130 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
131 offsetof(CPUPPCState, avr[i].u64[1]), p);
132 #else
133 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
134 offsetof(CPUPPCState, avr[i].u64[0]), p);
135 #endif
136 p += (i < 10) ? 6 : 7;
137 cpu_reg_names_size -= (i < 10) ? 6 : 7;
138 snprintf(p, cpu_reg_names_size, "vsr%d", i);
139 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
140 offsetof(CPUPPCState, vsr[i]), p);
141 p += (i < 10) ? 5 : 6;
142 cpu_reg_names_size -= (i < 10) ? 5 : 6;
143 }
144
145 cpu_nip = tcg_global_mem_new(cpu_env,
146 offsetof(CPUPPCState, nip), "nip");
147
148 cpu_msr = tcg_global_mem_new(cpu_env,
149 offsetof(CPUPPCState, msr), "msr");
150
151 cpu_ctr = tcg_global_mem_new(cpu_env,
152 offsetof(CPUPPCState, ctr), "ctr");
153
154 cpu_lr = tcg_global_mem_new(cpu_env,
155 offsetof(CPUPPCState, lr), "lr");
156
157 #if defined(TARGET_PPC64)
158 cpu_cfar = tcg_global_mem_new(cpu_env,
159 offsetof(CPUPPCState, cfar), "cfar");
160 #endif
161
162 cpu_xer = tcg_global_mem_new(cpu_env,
163 offsetof(CPUPPCState, xer), "xer");
164 cpu_so = tcg_global_mem_new(cpu_env,
165 offsetof(CPUPPCState, so), "SO");
166 cpu_ov = tcg_global_mem_new(cpu_env,
167 offsetof(CPUPPCState, ov), "OV");
168 cpu_ca = tcg_global_mem_new(cpu_env,
169 offsetof(CPUPPCState, ca), "CA");
170 cpu_ov32 = tcg_global_mem_new(cpu_env,
171 offsetof(CPUPPCState, ov32), "OV32");
172 cpu_ca32 = tcg_global_mem_new(cpu_env,
173 offsetof(CPUPPCState, ca32), "CA32");
174
175 cpu_reserve = tcg_global_mem_new(cpu_env,
176 offsetof(CPUPPCState, reserve_addr),
177 "reserve_addr");
178 cpu_reserve_val = tcg_global_mem_new(cpu_env,
179 offsetof(CPUPPCState, reserve_val),
180 "reserve_val");
181
182 cpu_fpscr = tcg_global_mem_new(cpu_env,
183 offsetof(CPUPPCState, fpscr), "fpscr");
184
185 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
186 offsetof(CPUPPCState, access_type), "access_type");
187 }
188
189 /* internal defines */
190 struct DisasContext {
191 DisasContextBase base;
192 uint32_t opcode;
193 uint32_t exception;
194 /* Routine used to access memory */
195 bool pr, hv, dr, le_mode;
196 bool lazy_tlb_flush;
197 bool need_access_type;
198 int mem_idx;
199 int access_type;
200 /* Translation flags */
201 TCGMemOp default_tcg_memop_mask;
202 #if defined(TARGET_PPC64)
203 bool sf_mode;
204 bool has_cfar;
205 #endif
206 bool fpu_enabled;
207 bool altivec_enabled;
208 bool vsx_enabled;
209 bool spe_enabled;
210 bool tm_enabled;
211 bool gtse;
212 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
213 int singlestep_enabled;
214 uint32_t flags;
215 uint64_t insns_flags;
216 uint64_t insns_flags2;
217 };
218
219 /* Return true iff byteswap is needed in a scalar memop */
need_byteswap(const DisasContext * ctx)220 static inline bool need_byteswap(const DisasContext *ctx)
221 {
222 #if defined(TARGET_WORDS_BIGENDIAN)
223 return ctx->le_mode;
224 #else
225 return !ctx->le_mode;
226 #endif
227 }
228
229 /* True when active word size < size of target_long. */
230 #ifdef TARGET_PPC64
231 # define NARROW_MODE(C) (!(C)->sf_mode)
232 #else
233 # define NARROW_MODE(C) 0
234 #endif
235
236 struct opc_handler_t {
237 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
238 uint32_t inval1;
239 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
240 uint32_t inval2;
241 /* instruction type */
242 uint64_t type;
243 /* extended instruction type */
244 uint64_t type2;
245 /* handler */
246 void (*handler)(DisasContext *ctx);
247 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
248 const char *oname;
249 #endif
250 #if defined(DO_PPC_STATISTICS)
251 uint64_t count;
252 #endif
253 };
254
255 /* SPR load/store helpers */
gen_load_spr(TCGv t,int reg)256 static inline void gen_load_spr(TCGv t, int reg)
257 {
258 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
259 }
260
gen_store_spr(int reg,TCGv t)261 static inline void gen_store_spr(int reg, TCGv t)
262 {
263 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
264 }
265
gen_set_access_type(DisasContext * ctx,int access_type)266 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
267 {
268 if (ctx->need_access_type && ctx->access_type != access_type) {
269 tcg_gen_movi_i32(cpu_access_type, access_type);
270 ctx->access_type = access_type;
271 }
272 }
273
gen_update_nip(DisasContext * ctx,target_ulong nip)274 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
275 {
276 if (NARROW_MODE(ctx)) {
277 nip = (uint32_t)nip;
278 }
279 tcg_gen_movi_tl(cpu_nip, nip);
280 }
281
gen_exception_err(DisasContext * ctx,uint32_t excp,uint32_t error)282 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
283 {
284 TCGv_i32 t0, t1;
285
286 /* These are all synchronous exceptions, we set the PC back to
287 * the faulting instruction
288 */
289 if (ctx->exception == POWERPC_EXCP_NONE) {
290 gen_update_nip(ctx, ctx->base.pc_next - 4);
291 }
292 t0 = tcg_const_i32(excp);
293 t1 = tcg_const_i32(error);
294 gen_helper_raise_exception_err(cpu_env, t0, t1);
295 tcg_temp_free_i32(t0);
296 tcg_temp_free_i32(t1);
297 ctx->exception = (excp);
298 }
299
gen_exception(DisasContext * ctx,uint32_t excp)300 static void gen_exception(DisasContext *ctx, uint32_t excp)
301 {
302 TCGv_i32 t0;
303
304 /* These are all synchronous exceptions, we set the PC back to
305 * the faulting instruction
306 */
307 if (ctx->exception == POWERPC_EXCP_NONE) {
308 gen_update_nip(ctx, ctx->base.pc_next - 4);
309 }
310 t0 = tcg_const_i32(excp);
311 gen_helper_raise_exception(cpu_env, t0);
312 tcg_temp_free_i32(t0);
313 ctx->exception = (excp);
314 }
315
gen_exception_nip(DisasContext * ctx,uint32_t excp,target_ulong nip)316 static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
317 target_ulong nip)
318 {
319 TCGv_i32 t0;
320
321 gen_update_nip(ctx, nip);
322 t0 = tcg_const_i32(excp);
323 gen_helper_raise_exception(cpu_env, t0);
324 tcg_temp_free_i32(t0);
325 ctx->exception = (excp);
326 }
327
328 /* Translates the EXCP_TRACE/BRANCH exceptions used on most PowerPCs to
329 * EXCP_DEBUG, if we are running on cores using the debug enable bit (e.g.
330 * BookE).
331 */
gen_prep_dbgex(DisasContext * ctx,uint32_t excp)332 static uint32_t gen_prep_dbgex(DisasContext *ctx, uint32_t excp)
333 {
334 if ((ctx->singlestep_enabled & CPU_SINGLE_STEP)
335 && (excp == POWERPC_EXCP_BRANCH)) {
336 /* Trace excpt. has priority */
337 excp = POWERPC_EXCP_TRACE;
338 }
339 if (ctx->flags & POWERPC_FLAG_DE) {
340 target_ulong dbsr = 0;
341 switch (excp) {
342 case POWERPC_EXCP_TRACE:
343 dbsr = DBCR0_ICMP;
344 break;
345 case POWERPC_EXCP_BRANCH:
346 dbsr = DBCR0_BRT;
347 break;
348 }
349 TCGv t0 = tcg_temp_new();
350 gen_load_spr(t0, SPR_BOOKE_DBSR);
351 tcg_gen_ori_tl(t0, t0, dbsr);
352 gen_store_spr(SPR_BOOKE_DBSR, t0);
353 tcg_temp_free(t0);
354 return POWERPC_EXCP_DEBUG;
355 } else {
356 return excp;
357 }
358 }
359
gen_debug_exception(DisasContext * ctx)360 static void gen_debug_exception(DisasContext *ctx)
361 {
362 TCGv_i32 t0;
363
364 /* These are all synchronous exceptions, we set the PC back to
365 * the faulting instruction
366 */
367 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
368 (ctx->exception != POWERPC_EXCP_SYNC)) {
369 gen_update_nip(ctx, ctx->base.pc_next);
370 }
371 t0 = tcg_const_i32(EXCP_DEBUG);
372 gen_helper_raise_exception(cpu_env, t0);
373 tcg_temp_free_i32(t0);
374 }
375
gen_inval_exception(DisasContext * ctx,uint32_t error)376 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
377 {
378 /* Will be converted to program check if needed */
379 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
380 }
381
gen_priv_exception(DisasContext * ctx,uint32_t error)382 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
383 {
384 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
385 }
386
gen_hvpriv_exception(DisasContext * ctx,uint32_t error)387 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
388 {
389 /* Will be converted to program check if needed */
390 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
391 }
392
393 /* Stop translation */
gen_stop_exception(DisasContext * ctx)394 static inline void gen_stop_exception(DisasContext *ctx)
395 {
396 gen_update_nip(ctx, ctx->base.pc_next);
397 ctx->exception = POWERPC_EXCP_STOP;
398 }
399
400 #ifndef CONFIG_USER_ONLY
401 /* No need to update nip here, as execution flow will change */
gen_sync_exception(DisasContext * ctx)402 static inline void gen_sync_exception(DisasContext *ctx)
403 {
404 ctx->exception = POWERPC_EXCP_SYNC;
405 }
406 #endif
407
408 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
409 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
410
411 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
412 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
413
414 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
415 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
416
417 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
418 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
419
420 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
421 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
422
423 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
424 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
425
426 typedef struct opcode_t {
427 unsigned char opc1, opc2, opc3, opc4;
428 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
429 unsigned char pad[4];
430 #endif
431 opc_handler_t handler;
432 const char *oname;
433 } opcode_t;
434
435 /* Helpers for priv. check */
436 #define GEN_PRIV \
437 do { \
438 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
439 } while (0)
440
441 #if defined(CONFIG_USER_ONLY)
442 #define CHK_HV GEN_PRIV
443 #define CHK_SV GEN_PRIV
444 #define CHK_HVRM GEN_PRIV
445 #else
446 #define CHK_HV \
447 do { \
448 if (unlikely(ctx->pr || !ctx->hv)) { \
449 GEN_PRIV; \
450 } \
451 } while (0)
452 #define CHK_SV \
453 do { \
454 if (unlikely(ctx->pr)) { \
455 GEN_PRIV; \
456 } \
457 } while (0)
458 #define CHK_HVRM \
459 do { \
460 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
461 GEN_PRIV; \
462 } \
463 } while (0)
464 #endif
465
466 #define CHK_NONE
467
468 /*****************************************************************************/
469 /* PowerPC instructions table */
470
471 #if defined(DO_PPC_STATISTICS)
472 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
473 { \
474 .opc1 = op1, \
475 .opc2 = op2, \
476 .opc3 = op3, \
477 .opc4 = 0xff, \
478 .handler = { \
479 .inval1 = invl, \
480 .type = _typ, \
481 .type2 = _typ2, \
482 .handler = &gen_##name, \
483 .oname = stringify(name), \
484 }, \
485 .oname = stringify(name), \
486 }
487 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
488 { \
489 .opc1 = op1, \
490 .opc2 = op2, \
491 .opc3 = op3, \
492 .opc4 = 0xff, \
493 .handler = { \
494 .inval1 = invl1, \
495 .inval2 = invl2, \
496 .type = _typ, \
497 .type2 = _typ2, \
498 .handler = &gen_##name, \
499 .oname = stringify(name), \
500 }, \
501 .oname = stringify(name), \
502 }
503 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
504 { \
505 .opc1 = op1, \
506 .opc2 = op2, \
507 .opc3 = op3, \
508 .opc4 = 0xff, \
509 .handler = { \
510 .inval1 = invl, \
511 .type = _typ, \
512 .type2 = _typ2, \
513 .handler = &gen_##name, \
514 .oname = onam, \
515 }, \
516 .oname = onam, \
517 }
518 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
519 { \
520 .opc1 = op1, \
521 .opc2 = op2, \
522 .opc3 = op3, \
523 .opc4 = op4, \
524 .handler = { \
525 .inval1 = invl, \
526 .type = _typ, \
527 .type2 = _typ2, \
528 .handler = &gen_##name, \
529 .oname = stringify(name), \
530 }, \
531 .oname = stringify(name), \
532 }
533 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
534 { \
535 .opc1 = op1, \
536 .opc2 = op2, \
537 .opc3 = op3, \
538 .opc4 = op4, \
539 .handler = { \
540 .inval1 = invl, \
541 .type = _typ, \
542 .type2 = _typ2, \
543 .handler = &gen_##name, \
544 .oname = onam, \
545 }, \
546 .oname = onam, \
547 }
548 #else
549 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
550 { \
551 .opc1 = op1, \
552 .opc2 = op2, \
553 .opc3 = op3, \
554 .opc4 = 0xff, \
555 .handler = { \
556 .inval1 = invl, \
557 .type = _typ, \
558 .type2 = _typ2, \
559 .handler = &gen_##name, \
560 }, \
561 .oname = stringify(name), \
562 }
563 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
564 { \
565 .opc1 = op1, \
566 .opc2 = op2, \
567 .opc3 = op3, \
568 .opc4 = 0xff, \
569 .handler = { \
570 .inval1 = invl1, \
571 .inval2 = invl2, \
572 .type = _typ, \
573 .type2 = _typ2, \
574 .handler = &gen_##name, \
575 }, \
576 .oname = stringify(name), \
577 }
578 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
579 { \
580 .opc1 = op1, \
581 .opc2 = op2, \
582 .opc3 = op3, \
583 .opc4 = 0xff, \
584 .handler = { \
585 .inval1 = invl, \
586 .type = _typ, \
587 .type2 = _typ2, \
588 .handler = &gen_##name, \
589 }, \
590 .oname = onam, \
591 }
592 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
593 { \
594 .opc1 = op1, \
595 .opc2 = op2, \
596 .opc3 = op3, \
597 .opc4 = op4, \
598 .handler = { \
599 .inval1 = invl, \
600 .type = _typ, \
601 .type2 = _typ2, \
602 .handler = &gen_##name, \
603 }, \
604 .oname = stringify(name), \
605 }
606 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
607 { \
608 .opc1 = op1, \
609 .opc2 = op2, \
610 .opc3 = op3, \
611 .opc4 = op4, \
612 .handler = { \
613 .inval1 = invl, \
614 .type = _typ, \
615 .type2 = _typ2, \
616 .handler = &gen_##name, \
617 }, \
618 .oname = onam, \
619 }
620 #endif
621
622 /* Invalid instruction */
gen_invalid(DisasContext * ctx)623 static void gen_invalid(DisasContext *ctx)
624 {
625 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
626 }
627
628 static opc_handler_t invalid_handler = {
629 .inval1 = 0xFFFFFFFF,
630 .inval2 = 0xFFFFFFFF,
631 .type = PPC_NONE,
632 .type2 = PPC_NONE,
633 .handler = gen_invalid,
634 };
635
636 /*** Integer comparison ***/
637
gen_op_cmp(TCGv arg0,TCGv arg1,int s,int crf)638 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
639 {
640 TCGv t0 = tcg_temp_new();
641 TCGv t1 = tcg_temp_new();
642 TCGv_i32 t = tcg_temp_new_i32();
643
644 tcg_gen_movi_tl(t0, CRF_EQ);
645 tcg_gen_movi_tl(t1, CRF_LT);
646 tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), t0, arg0, arg1, t1, t0);
647 tcg_gen_movi_tl(t1, CRF_GT);
648 tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), t0, arg0, arg1, t1, t0);
649
650 tcg_gen_trunc_tl_i32(t, t0);
651 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
652 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t);
653
654 tcg_temp_free(t0);
655 tcg_temp_free(t1);
656 tcg_temp_free_i32(t);
657 }
658
gen_op_cmpi(TCGv arg0,target_ulong arg1,int s,int crf)659 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
660 {
661 TCGv t0 = tcg_const_tl(arg1);
662 gen_op_cmp(arg0, t0, s, crf);
663 tcg_temp_free(t0);
664 }
665
gen_op_cmp32(TCGv arg0,TCGv arg1,int s,int crf)666 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
667 {
668 TCGv t0, t1;
669 t0 = tcg_temp_new();
670 t1 = tcg_temp_new();
671 if (s) {
672 tcg_gen_ext32s_tl(t0, arg0);
673 tcg_gen_ext32s_tl(t1, arg1);
674 } else {
675 tcg_gen_ext32u_tl(t0, arg0);
676 tcg_gen_ext32u_tl(t1, arg1);
677 }
678 gen_op_cmp(t0, t1, s, crf);
679 tcg_temp_free(t1);
680 tcg_temp_free(t0);
681 }
682
gen_op_cmpi32(TCGv arg0,target_ulong arg1,int s,int crf)683 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
684 {
685 TCGv t0 = tcg_const_tl(arg1);
686 gen_op_cmp32(arg0, t0, s, crf);
687 tcg_temp_free(t0);
688 }
689
gen_set_Rc0(DisasContext * ctx,TCGv reg)690 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
691 {
692 if (NARROW_MODE(ctx)) {
693 gen_op_cmpi32(reg, 0, 1, 0);
694 } else {
695 gen_op_cmpi(reg, 0, 1, 0);
696 }
697 }
698
699 /* cmp */
gen_cmp(DisasContext * ctx)700 static void gen_cmp(DisasContext *ctx)
701 {
702 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
703 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
704 1, crfD(ctx->opcode));
705 } else {
706 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
707 1, crfD(ctx->opcode));
708 }
709 }
710
711 /* cmpi */
gen_cmpi(DisasContext * ctx)712 static void gen_cmpi(DisasContext *ctx)
713 {
714 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
715 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
716 1, crfD(ctx->opcode));
717 } else {
718 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
719 1, crfD(ctx->opcode));
720 }
721 }
722
723 /* cmpl */
gen_cmpl(DisasContext * ctx)724 static void gen_cmpl(DisasContext *ctx)
725 {
726 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
727 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
728 0, crfD(ctx->opcode));
729 } else {
730 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
731 0, crfD(ctx->opcode));
732 }
733 }
734
735 /* cmpli */
gen_cmpli(DisasContext * ctx)736 static void gen_cmpli(DisasContext *ctx)
737 {
738 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
739 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
740 0, crfD(ctx->opcode));
741 } else {
742 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
743 0, crfD(ctx->opcode));
744 }
745 }
746
747 /* cmprb - range comparison: isupper, isaplha, islower*/
gen_cmprb(DisasContext * ctx)748 static void gen_cmprb(DisasContext *ctx)
749 {
750 TCGv_i32 src1 = tcg_temp_new_i32();
751 TCGv_i32 src2 = tcg_temp_new_i32();
752 TCGv_i32 src2lo = tcg_temp_new_i32();
753 TCGv_i32 src2hi = tcg_temp_new_i32();
754 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
755
756 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
757 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
758
759 tcg_gen_andi_i32(src1, src1, 0xFF);
760 tcg_gen_ext8u_i32(src2lo, src2);
761 tcg_gen_shri_i32(src2, src2, 8);
762 tcg_gen_ext8u_i32(src2hi, src2);
763
764 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
765 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
766 tcg_gen_and_i32(crf, src2lo, src2hi);
767
768 if (ctx->opcode & 0x00200000) {
769 tcg_gen_shri_i32(src2, src2, 8);
770 tcg_gen_ext8u_i32(src2lo, src2);
771 tcg_gen_shri_i32(src2, src2, 8);
772 tcg_gen_ext8u_i32(src2hi, src2);
773 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
774 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
775 tcg_gen_and_i32(src2lo, src2lo, src2hi);
776 tcg_gen_or_i32(crf, crf, src2lo);
777 }
778 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT);
779 tcg_temp_free_i32(src1);
780 tcg_temp_free_i32(src2);
781 tcg_temp_free_i32(src2lo);
782 tcg_temp_free_i32(src2hi);
783 }
784
785 #if defined(TARGET_PPC64)
786 /* cmpeqb */
gen_cmpeqb(DisasContext * ctx)787 static void gen_cmpeqb(DisasContext *ctx)
788 {
789 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
790 cpu_gpr[rB(ctx->opcode)]);
791 }
792 #endif
793
794 /* isel (PowerPC 2.03 specification) */
gen_isel(DisasContext * ctx)795 static void gen_isel(DisasContext *ctx)
796 {
797 uint32_t bi = rC(ctx->opcode);
798 uint32_t mask = 0x08 >> (bi & 0x03);
799 TCGv t0 = tcg_temp_new();
800 TCGv zr;
801
802 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
803 tcg_gen_andi_tl(t0, t0, mask);
804
805 zr = tcg_const_tl(0);
806 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
807 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
808 cpu_gpr[rB(ctx->opcode)]);
809 tcg_temp_free(zr);
810 tcg_temp_free(t0);
811 }
812
813 /* cmpb: PowerPC 2.05 specification */
gen_cmpb(DisasContext * ctx)814 static void gen_cmpb(DisasContext *ctx)
815 {
816 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
817 cpu_gpr[rB(ctx->opcode)]);
818 }
819
820 /*** Integer arithmetic ***/
821
gen_op_arith_compute_ov(DisasContext * ctx,TCGv arg0,TCGv arg1,TCGv arg2,int sub)822 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
823 TCGv arg1, TCGv arg2, int sub)
824 {
825 TCGv t0 = tcg_temp_new();
826
827 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
828 tcg_gen_xor_tl(t0, arg1, arg2);
829 if (sub) {
830 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
831 } else {
832 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
833 }
834 tcg_temp_free(t0);
835 if (NARROW_MODE(ctx)) {
836 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1);
837 if (is_isa300(ctx)) {
838 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
839 }
840 } else {
841 if (is_isa300(ctx)) {
842 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
843 }
844 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1);
845 }
846 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
847 }
848
gen_op_arith_compute_ca32(DisasContext * ctx,TCGv res,TCGv arg0,TCGv arg1,int sub)849 static inline void gen_op_arith_compute_ca32(DisasContext *ctx,
850 TCGv res, TCGv arg0, TCGv arg1,
851 int sub)
852 {
853 TCGv t0;
854
855 if (!is_isa300(ctx)) {
856 return;
857 }
858
859 t0 = tcg_temp_new();
860 if (sub) {
861 tcg_gen_eqv_tl(t0, arg0, arg1);
862 } else {
863 tcg_gen_xor_tl(t0, arg0, arg1);
864 }
865 tcg_gen_xor_tl(t0, t0, res);
866 tcg_gen_extract_tl(cpu_ca32, t0, 32, 1);
867 tcg_temp_free(t0);
868 }
869
870 /* Common add function */
gen_op_arith_add(DisasContext * ctx,TCGv ret,TCGv arg1,TCGv arg2,bool add_ca,bool compute_ca,bool compute_ov,bool compute_rc0)871 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
872 TCGv arg2, bool add_ca, bool compute_ca,
873 bool compute_ov, bool compute_rc0)
874 {
875 TCGv t0 = ret;
876
877 if (compute_ca || compute_ov) {
878 t0 = tcg_temp_new();
879 }
880
881 if (compute_ca) {
882 if (NARROW_MODE(ctx)) {
883 /* Caution: a non-obvious corner case of the spec is that we
884 must produce the *entire* 64-bit addition, but produce the
885 carry into bit 32. */
886 TCGv t1 = tcg_temp_new();
887 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
888 tcg_gen_add_tl(t0, arg1, arg2);
889 if (add_ca) {
890 tcg_gen_add_tl(t0, t0, cpu_ca);
891 }
892 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
893 tcg_temp_free(t1);
894 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
895 if (is_isa300(ctx)) {
896 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
897 }
898 } else {
899 TCGv zero = tcg_const_tl(0);
900 if (add_ca) {
901 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
902 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
903 } else {
904 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
905 }
906 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 0);
907 tcg_temp_free(zero);
908 }
909 } else {
910 tcg_gen_add_tl(t0, arg1, arg2);
911 if (add_ca) {
912 tcg_gen_add_tl(t0, t0, cpu_ca);
913 }
914 }
915
916 if (compute_ov) {
917 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
918 }
919 if (unlikely(compute_rc0)) {
920 gen_set_Rc0(ctx, t0);
921 }
922
923 if (t0 != ret) {
924 tcg_gen_mov_tl(ret, t0);
925 tcg_temp_free(t0);
926 }
927 }
928 /* Add functions with two operands */
929 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
930 static void glue(gen_, name)(DisasContext *ctx) \
931 { \
932 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
933 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
934 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
935 }
936 /* Add functions with one operand and one immediate */
937 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
938 add_ca, compute_ca, compute_ov) \
939 static void glue(gen_, name)(DisasContext *ctx) \
940 { \
941 TCGv t0 = tcg_const_tl(const_val); \
942 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
943 cpu_gpr[rA(ctx->opcode)], t0, \
944 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
945 tcg_temp_free(t0); \
946 }
947
948 /* add add. addo addo. */
949 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
950 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
951 /* addc addc. addco addco. */
952 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
953 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
954 /* adde adde. addeo addeo. */
955 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
956 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
957 /* addme addme. addmeo addmeo. */
958 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
959 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
960 /* addze addze. addzeo addzeo.*/
961 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
962 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
963 /* addi */
gen_addi(DisasContext * ctx)964 static void gen_addi(DisasContext *ctx)
965 {
966 target_long simm = SIMM(ctx->opcode);
967
968 if (rA(ctx->opcode) == 0) {
969 /* li case */
970 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
971 } else {
972 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
973 cpu_gpr[rA(ctx->opcode)], simm);
974 }
975 }
976 /* addic addic.*/
gen_op_addic(DisasContext * ctx,bool compute_rc0)977 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
978 {
979 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
980 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
981 c, 0, 1, 0, compute_rc0);
982 tcg_temp_free(c);
983 }
984
gen_addic(DisasContext * ctx)985 static void gen_addic(DisasContext *ctx)
986 {
987 gen_op_addic(ctx, 0);
988 }
989
gen_addic_(DisasContext * ctx)990 static void gen_addic_(DisasContext *ctx)
991 {
992 gen_op_addic(ctx, 1);
993 }
994
995 /* addis */
gen_addis(DisasContext * ctx)996 static void gen_addis(DisasContext *ctx)
997 {
998 target_long simm = SIMM(ctx->opcode);
999
1000 if (rA(ctx->opcode) == 0) {
1001 /* lis case */
1002 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1003 } else {
1004 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1005 cpu_gpr[rA(ctx->opcode)], simm << 16);
1006 }
1007 }
1008
1009 /* addpcis */
gen_addpcis(DisasContext * ctx)1010 static void gen_addpcis(DisasContext *ctx)
1011 {
1012 target_long d = DX(ctx->opcode);
1013
1014 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16));
1015 }
1016
gen_op_arith_divw(DisasContext * ctx,TCGv ret,TCGv arg1,TCGv arg2,int sign,int compute_ov)1017 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
1018 TCGv arg2, int sign, int compute_ov)
1019 {
1020 TCGv_i32 t0 = tcg_temp_new_i32();
1021 TCGv_i32 t1 = tcg_temp_new_i32();
1022 TCGv_i32 t2 = tcg_temp_new_i32();
1023 TCGv_i32 t3 = tcg_temp_new_i32();
1024
1025 tcg_gen_trunc_tl_i32(t0, arg1);
1026 tcg_gen_trunc_tl_i32(t1, arg2);
1027 if (sign) {
1028 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1029 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1030 tcg_gen_and_i32(t2, t2, t3);
1031 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1032 tcg_gen_or_i32(t2, t2, t3);
1033 tcg_gen_movi_i32(t3, 0);
1034 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1035 tcg_gen_div_i32(t3, t0, t1);
1036 tcg_gen_extu_i32_tl(ret, t3);
1037 } else {
1038 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0);
1039 tcg_gen_movi_i32(t3, 0);
1040 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1041 tcg_gen_divu_i32(t3, t0, t1);
1042 tcg_gen_extu_i32_tl(ret, t3);
1043 }
1044 if (compute_ov) {
1045 tcg_gen_extu_i32_tl(cpu_ov, t2);
1046 if (is_isa300(ctx)) {
1047 tcg_gen_extu_i32_tl(cpu_ov32, t2);
1048 }
1049 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1050 }
1051 tcg_temp_free_i32(t0);
1052 tcg_temp_free_i32(t1);
1053 tcg_temp_free_i32(t2);
1054 tcg_temp_free_i32(t3);
1055
1056 if (unlikely(Rc(ctx->opcode) != 0))
1057 gen_set_Rc0(ctx, ret);
1058 }
1059 /* Div functions */
1060 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1061 static void glue(gen_, name)(DisasContext *ctx) \
1062 { \
1063 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1064 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1065 sign, compute_ov); \
1066 }
1067 /* divwu divwu. divwuo divwuo. */
1068 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1069 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1070 /* divw divw. divwo divwo. */
1071 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1072 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1073
1074 /* div[wd]eu[o][.] */
1075 #define GEN_DIVE(name, hlpr, compute_ov) \
1076 static void gen_##name(DisasContext *ctx) \
1077 { \
1078 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1079 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1080 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1081 tcg_temp_free_i32(t0); \
1082 if (unlikely(Rc(ctx->opcode) != 0)) { \
1083 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1084 } \
1085 }
1086
1087 GEN_DIVE(divweu, divweu, 0);
1088 GEN_DIVE(divweuo, divweu, 1);
1089 GEN_DIVE(divwe, divwe, 0);
1090 GEN_DIVE(divweo, divwe, 1);
1091
1092 #if defined(TARGET_PPC64)
gen_op_arith_divd(DisasContext * ctx,TCGv ret,TCGv arg1,TCGv arg2,int sign,int compute_ov)1093 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1094 TCGv arg2, int sign, int compute_ov)
1095 {
1096 TCGv_i64 t0 = tcg_temp_new_i64();
1097 TCGv_i64 t1 = tcg_temp_new_i64();
1098 TCGv_i64 t2 = tcg_temp_new_i64();
1099 TCGv_i64 t3 = tcg_temp_new_i64();
1100
1101 tcg_gen_mov_i64(t0, arg1);
1102 tcg_gen_mov_i64(t1, arg2);
1103 if (sign) {
1104 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1105 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1106 tcg_gen_and_i64(t2, t2, t3);
1107 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1108 tcg_gen_or_i64(t2, t2, t3);
1109 tcg_gen_movi_i64(t3, 0);
1110 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1111 tcg_gen_div_i64(ret, t0, t1);
1112 } else {
1113 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0);
1114 tcg_gen_movi_i64(t3, 0);
1115 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1116 tcg_gen_divu_i64(ret, t0, t1);
1117 }
1118 if (compute_ov) {
1119 tcg_gen_mov_tl(cpu_ov, t2);
1120 if (is_isa300(ctx)) {
1121 tcg_gen_mov_tl(cpu_ov32, t2);
1122 }
1123 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1124 }
1125 tcg_temp_free_i64(t0);
1126 tcg_temp_free_i64(t1);
1127 tcg_temp_free_i64(t2);
1128 tcg_temp_free_i64(t3);
1129
1130 if (unlikely(Rc(ctx->opcode) != 0))
1131 gen_set_Rc0(ctx, ret);
1132 }
1133
1134 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1135 static void glue(gen_, name)(DisasContext *ctx) \
1136 { \
1137 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1138 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1139 sign, compute_ov); \
1140 }
1141 /* divdu divdu. divduo divduo. */
1142 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1143 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1144 /* divd divd. divdo divdo. */
1145 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1146 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1147
1148 GEN_DIVE(divdeu, divdeu, 0);
1149 GEN_DIVE(divdeuo, divdeu, 1);
1150 GEN_DIVE(divde, divde, 0);
1151 GEN_DIVE(divdeo, divde, 1);
1152 #endif
1153
gen_op_arith_modw(DisasContext * ctx,TCGv ret,TCGv arg1,TCGv arg2,int sign)1154 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1155 TCGv arg2, int sign)
1156 {
1157 TCGv_i32 t0 = tcg_temp_new_i32();
1158 TCGv_i32 t1 = tcg_temp_new_i32();
1159
1160 tcg_gen_trunc_tl_i32(t0, arg1);
1161 tcg_gen_trunc_tl_i32(t1, arg2);
1162 if (sign) {
1163 TCGv_i32 t2 = tcg_temp_new_i32();
1164 TCGv_i32 t3 = tcg_temp_new_i32();
1165 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1166 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1167 tcg_gen_and_i32(t2, t2, t3);
1168 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1169 tcg_gen_or_i32(t2, t2, t3);
1170 tcg_gen_movi_i32(t3, 0);
1171 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1172 tcg_gen_rem_i32(t3, t0, t1);
1173 tcg_gen_ext_i32_tl(ret, t3);
1174 tcg_temp_free_i32(t2);
1175 tcg_temp_free_i32(t3);
1176 } else {
1177 TCGv_i32 t2 = tcg_const_i32(1);
1178 TCGv_i32 t3 = tcg_const_i32(0);
1179 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1180 tcg_gen_remu_i32(t3, t0, t1);
1181 tcg_gen_extu_i32_tl(ret, t3);
1182 tcg_temp_free_i32(t2);
1183 tcg_temp_free_i32(t3);
1184 }
1185 tcg_temp_free_i32(t0);
1186 tcg_temp_free_i32(t1);
1187 }
1188
1189 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1190 static void glue(gen_, name)(DisasContext *ctx) \
1191 { \
1192 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1193 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1194 sign); \
1195 }
1196
1197 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1198 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1199
1200 #if defined(TARGET_PPC64)
gen_op_arith_modd(DisasContext * ctx,TCGv ret,TCGv arg1,TCGv arg2,int sign)1201 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1202 TCGv arg2, int sign)
1203 {
1204 TCGv_i64 t0 = tcg_temp_new_i64();
1205 TCGv_i64 t1 = tcg_temp_new_i64();
1206
1207 tcg_gen_mov_i64(t0, arg1);
1208 tcg_gen_mov_i64(t1, arg2);
1209 if (sign) {
1210 TCGv_i64 t2 = tcg_temp_new_i64();
1211 TCGv_i64 t3 = tcg_temp_new_i64();
1212 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1213 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1214 tcg_gen_and_i64(t2, t2, t3);
1215 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1216 tcg_gen_or_i64(t2, t2, t3);
1217 tcg_gen_movi_i64(t3, 0);
1218 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1219 tcg_gen_rem_i64(ret, t0, t1);
1220 tcg_temp_free_i64(t2);
1221 tcg_temp_free_i64(t3);
1222 } else {
1223 TCGv_i64 t2 = tcg_const_i64(1);
1224 TCGv_i64 t3 = tcg_const_i64(0);
1225 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1226 tcg_gen_remu_i64(ret, t0, t1);
1227 tcg_temp_free_i64(t2);
1228 tcg_temp_free_i64(t3);
1229 }
1230 tcg_temp_free_i64(t0);
1231 tcg_temp_free_i64(t1);
1232 }
1233
1234 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1235 static void glue(gen_, name)(DisasContext *ctx) \
1236 { \
1237 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1238 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1239 sign); \
1240 }
1241
1242 GEN_INT_ARITH_MODD(modud, 0x08, 0);
1243 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1244 #endif
1245
1246 /* mulhw mulhw. */
gen_mulhw(DisasContext * ctx)1247 static void gen_mulhw(DisasContext *ctx)
1248 {
1249 TCGv_i32 t0 = tcg_temp_new_i32();
1250 TCGv_i32 t1 = tcg_temp_new_i32();
1251
1252 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1253 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1254 tcg_gen_muls2_i32(t0, t1, t0, t1);
1255 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1256 tcg_temp_free_i32(t0);
1257 tcg_temp_free_i32(t1);
1258 if (unlikely(Rc(ctx->opcode) != 0))
1259 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1260 }
1261
1262 /* mulhwu mulhwu. */
gen_mulhwu(DisasContext * ctx)1263 static void gen_mulhwu(DisasContext *ctx)
1264 {
1265 TCGv_i32 t0 = tcg_temp_new_i32();
1266 TCGv_i32 t1 = tcg_temp_new_i32();
1267
1268 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1269 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1270 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1271 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1272 tcg_temp_free_i32(t0);
1273 tcg_temp_free_i32(t1);
1274 if (unlikely(Rc(ctx->opcode) != 0))
1275 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1276 }
1277
1278 /* mullw mullw. */
gen_mullw(DisasContext * ctx)1279 static void gen_mullw(DisasContext *ctx)
1280 {
1281 #if defined(TARGET_PPC64)
1282 TCGv_i64 t0, t1;
1283 t0 = tcg_temp_new_i64();
1284 t1 = tcg_temp_new_i64();
1285 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1286 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1287 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1288 tcg_temp_free(t0);
1289 tcg_temp_free(t1);
1290 #else
1291 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1292 cpu_gpr[rB(ctx->opcode)]);
1293 #endif
1294 if (unlikely(Rc(ctx->opcode) != 0))
1295 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1296 }
1297
1298 /* mullwo mullwo. */
gen_mullwo(DisasContext * ctx)1299 static void gen_mullwo(DisasContext *ctx)
1300 {
1301 TCGv_i32 t0 = tcg_temp_new_i32();
1302 TCGv_i32 t1 = tcg_temp_new_i32();
1303
1304 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1305 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1306 tcg_gen_muls2_i32(t0, t1, t0, t1);
1307 #if defined(TARGET_PPC64)
1308 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1309 #else
1310 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1311 #endif
1312
1313 tcg_gen_sari_i32(t0, t0, 31);
1314 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1315 tcg_gen_extu_i32_tl(cpu_ov, t0);
1316 if (is_isa300(ctx)) {
1317 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1318 }
1319 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1320
1321 tcg_temp_free_i32(t0);
1322 tcg_temp_free_i32(t1);
1323 if (unlikely(Rc(ctx->opcode) != 0))
1324 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1325 }
1326
1327 /* mulli */
gen_mulli(DisasContext * ctx)1328 static void gen_mulli(DisasContext *ctx)
1329 {
1330 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1331 SIMM(ctx->opcode));
1332 }
1333
1334 #if defined(TARGET_PPC64)
1335 /* mulhd mulhd. */
gen_mulhd(DisasContext * ctx)1336 static void gen_mulhd(DisasContext *ctx)
1337 {
1338 TCGv lo = tcg_temp_new();
1339 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1340 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1341 tcg_temp_free(lo);
1342 if (unlikely(Rc(ctx->opcode) != 0)) {
1343 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1344 }
1345 }
1346
1347 /* mulhdu mulhdu. */
gen_mulhdu(DisasContext * ctx)1348 static void gen_mulhdu(DisasContext *ctx)
1349 {
1350 TCGv lo = tcg_temp_new();
1351 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1352 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1353 tcg_temp_free(lo);
1354 if (unlikely(Rc(ctx->opcode) != 0)) {
1355 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1356 }
1357 }
1358
1359 /* mulld mulld. */
gen_mulld(DisasContext * ctx)1360 static void gen_mulld(DisasContext *ctx)
1361 {
1362 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1363 cpu_gpr[rB(ctx->opcode)]);
1364 if (unlikely(Rc(ctx->opcode) != 0))
1365 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1366 }
1367
1368 /* mulldo mulldo. */
gen_mulldo(DisasContext * ctx)1369 static void gen_mulldo(DisasContext *ctx)
1370 {
1371 TCGv_i64 t0 = tcg_temp_new_i64();
1372 TCGv_i64 t1 = tcg_temp_new_i64();
1373
1374 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1375 cpu_gpr[rB(ctx->opcode)]);
1376 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1377
1378 tcg_gen_sari_i64(t0, t0, 63);
1379 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1380 if (is_isa300(ctx)) {
1381 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1382 }
1383 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1384
1385 tcg_temp_free_i64(t0);
1386 tcg_temp_free_i64(t1);
1387
1388 if (unlikely(Rc(ctx->opcode) != 0)) {
1389 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1390 }
1391 }
1392 #endif
1393
1394 /* Common subf function */
gen_op_arith_subf(DisasContext * ctx,TCGv ret,TCGv arg1,TCGv arg2,bool add_ca,bool compute_ca,bool compute_ov,bool compute_rc0)1395 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1396 TCGv arg2, bool add_ca, bool compute_ca,
1397 bool compute_ov, bool compute_rc0)
1398 {
1399 TCGv t0 = ret;
1400
1401 if (compute_ca || compute_ov) {
1402 t0 = tcg_temp_new();
1403 }
1404
1405 if (compute_ca) {
1406 /* dest = ~arg1 + arg2 [+ ca]. */
1407 if (NARROW_MODE(ctx)) {
1408 /* Caution: a non-obvious corner case of the spec is that we
1409 must produce the *entire* 64-bit addition, but produce the
1410 carry into bit 32. */
1411 TCGv inv1 = tcg_temp_new();
1412 TCGv t1 = tcg_temp_new();
1413 tcg_gen_not_tl(inv1, arg1);
1414 if (add_ca) {
1415 tcg_gen_add_tl(t0, arg2, cpu_ca);
1416 } else {
1417 tcg_gen_addi_tl(t0, arg2, 1);
1418 }
1419 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1420 tcg_gen_add_tl(t0, t0, inv1);
1421 tcg_temp_free(inv1);
1422 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1423 tcg_temp_free(t1);
1424 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
1425 if (is_isa300(ctx)) {
1426 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
1427 }
1428 } else if (add_ca) {
1429 TCGv zero, inv1 = tcg_temp_new();
1430 tcg_gen_not_tl(inv1, arg1);
1431 zero = tcg_const_tl(0);
1432 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1433 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1434 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, 0);
1435 tcg_temp_free(zero);
1436 tcg_temp_free(inv1);
1437 } else {
1438 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1439 tcg_gen_sub_tl(t0, arg2, arg1);
1440 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 1);
1441 }
1442 } else if (add_ca) {
1443 /* Since we're ignoring carry-out, we can simplify the
1444 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1445 tcg_gen_sub_tl(t0, arg2, arg1);
1446 tcg_gen_add_tl(t0, t0, cpu_ca);
1447 tcg_gen_subi_tl(t0, t0, 1);
1448 } else {
1449 tcg_gen_sub_tl(t0, arg2, arg1);
1450 }
1451
1452 if (compute_ov) {
1453 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1454 }
1455 if (unlikely(compute_rc0)) {
1456 gen_set_Rc0(ctx, t0);
1457 }
1458
1459 if (t0 != ret) {
1460 tcg_gen_mov_tl(ret, t0);
1461 tcg_temp_free(t0);
1462 }
1463 }
1464 /* Sub functions with Two operands functions */
1465 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1466 static void glue(gen_, name)(DisasContext *ctx) \
1467 { \
1468 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1469 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1470 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1471 }
1472 /* Sub functions with one operand and one immediate */
1473 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1474 add_ca, compute_ca, compute_ov) \
1475 static void glue(gen_, name)(DisasContext *ctx) \
1476 { \
1477 TCGv t0 = tcg_const_tl(const_val); \
1478 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1479 cpu_gpr[rA(ctx->opcode)], t0, \
1480 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1481 tcg_temp_free(t0); \
1482 }
1483 /* subf subf. subfo subfo. */
1484 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1485 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1486 /* subfc subfc. subfco subfco. */
1487 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1488 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1489 /* subfe subfe. subfeo subfo. */
1490 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1491 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1492 /* subfme subfme. subfmeo subfmeo. */
1493 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1494 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1495 /* subfze subfze. subfzeo subfzeo.*/
1496 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1497 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1498
1499 /* subfic */
gen_subfic(DisasContext * ctx)1500 static void gen_subfic(DisasContext *ctx)
1501 {
1502 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1503 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1504 c, 0, 1, 0, 0);
1505 tcg_temp_free(c);
1506 }
1507
1508 /* neg neg. nego nego. */
gen_op_arith_neg(DisasContext * ctx,bool compute_ov)1509 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1510 {
1511 TCGv zero = tcg_const_tl(0);
1512 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1513 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1514 tcg_temp_free(zero);
1515 }
1516
gen_neg(DisasContext * ctx)1517 static void gen_neg(DisasContext *ctx)
1518 {
1519 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1520 if (unlikely(Rc(ctx->opcode))) {
1521 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1522 }
1523 }
1524
gen_nego(DisasContext * ctx)1525 static void gen_nego(DisasContext *ctx)
1526 {
1527 gen_op_arith_neg(ctx, 1);
1528 }
1529
1530 /*** Integer logical ***/
1531 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1532 static void glue(gen_, name)(DisasContext *ctx) \
1533 { \
1534 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1535 cpu_gpr[rB(ctx->opcode)]); \
1536 if (unlikely(Rc(ctx->opcode) != 0)) \
1537 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1538 }
1539
1540 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1541 static void glue(gen_, name)(DisasContext *ctx) \
1542 { \
1543 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1544 if (unlikely(Rc(ctx->opcode) != 0)) \
1545 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1546 }
1547
1548 /* and & and. */
1549 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1550 /* andc & andc. */
1551 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1552
1553 /* andi. */
gen_andi_(DisasContext * ctx)1554 static void gen_andi_(DisasContext *ctx)
1555 {
1556 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1557 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1558 }
1559
1560 /* andis. */
gen_andis_(DisasContext * ctx)1561 static void gen_andis_(DisasContext *ctx)
1562 {
1563 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1564 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1565 }
1566
1567 /* cntlzw */
gen_cntlzw(DisasContext * ctx)1568 static void gen_cntlzw(DisasContext *ctx)
1569 {
1570 TCGv_i32 t = tcg_temp_new_i32();
1571
1572 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
1573 tcg_gen_clzi_i32(t, t, 32);
1574 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
1575 tcg_temp_free_i32(t);
1576
1577 if (unlikely(Rc(ctx->opcode) != 0))
1578 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1579 }
1580
1581 /* cnttzw */
gen_cnttzw(DisasContext * ctx)1582 static void gen_cnttzw(DisasContext *ctx)
1583 {
1584 TCGv_i32 t = tcg_temp_new_i32();
1585
1586 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
1587 tcg_gen_ctzi_i32(t, t, 32);
1588 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
1589 tcg_temp_free_i32(t);
1590
1591 if (unlikely(Rc(ctx->opcode) != 0)) {
1592 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1593 }
1594 }
1595
1596 /* eqv & eqv. */
1597 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1598 /* extsb & extsb. */
1599 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1600 /* extsh & extsh. */
1601 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1602 /* nand & nand. */
1603 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1604 /* nor & nor. */
1605 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1606
1607 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
gen_pause(DisasContext * ctx)1608 static void gen_pause(DisasContext *ctx)
1609 {
1610 TCGv_i32 t0 = tcg_const_i32(0);
1611 tcg_gen_st_i32(t0, cpu_env,
1612 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1613 tcg_temp_free_i32(t0);
1614
1615 /* Stop translation, this gives other CPUs a chance to run */
1616 gen_exception_nip(ctx, EXCP_INTERRUPT, ctx->base.pc_next);
1617 }
1618 #endif /* defined(TARGET_PPC64) */
1619
1620 /* or & or. */
gen_or(DisasContext * ctx)1621 static void gen_or(DisasContext *ctx)
1622 {
1623 int rs, ra, rb;
1624
1625 rs = rS(ctx->opcode);
1626 ra = rA(ctx->opcode);
1627 rb = rB(ctx->opcode);
1628 /* Optimisation for mr. ri case */
1629 if (rs != ra || rs != rb) {
1630 if (rs != rb)
1631 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1632 else
1633 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1634 if (unlikely(Rc(ctx->opcode) != 0))
1635 gen_set_Rc0(ctx, cpu_gpr[ra]);
1636 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1637 gen_set_Rc0(ctx, cpu_gpr[rs]);
1638 #if defined(TARGET_PPC64)
1639 } else if (rs != 0) { /* 0 is nop */
1640 int prio = 0;
1641
1642 switch (rs) {
1643 case 1:
1644 /* Set process priority to low */
1645 prio = 2;
1646 break;
1647 case 6:
1648 /* Set process priority to medium-low */
1649 prio = 3;
1650 break;
1651 case 2:
1652 /* Set process priority to normal */
1653 prio = 4;
1654 break;
1655 #if !defined(CONFIG_USER_ONLY)
1656 case 31:
1657 if (!ctx->pr) {
1658 /* Set process priority to very low */
1659 prio = 1;
1660 }
1661 break;
1662 case 5:
1663 if (!ctx->pr) {
1664 /* Set process priority to medium-hight */
1665 prio = 5;
1666 }
1667 break;
1668 case 3:
1669 if (!ctx->pr) {
1670 /* Set process priority to high */
1671 prio = 6;
1672 }
1673 break;
1674 case 7:
1675 if (ctx->hv && !ctx->pr) {
1676 /* Set process priority to very high */
1677 prio = 7;
1678 }
1679 break;
1680 #endif
1681 default:
1682 break;
1683 }
1684 if (prio) {
1685 TCGv t0 = tcg_temp_new();
1686 gen_load_spr(t0, SPR_PPR);
1687 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1688 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1689 gen_store_spr(SPR_PPR, t0);
1690 tcg_temp_free(t0);
1691 }
1692 #if !defined(CONFIG_USER_ONLY)
1693 /* Pause out of TCG otherwise spin loops with smt_low eat too much
1694 * CPU and the kernel hangs. This applies to all encodings other
1695 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1696 * and all currently undefined.
1697 */
1698 if (!mttcg_enabled) {
1699 gen_pause(ctx);
1700 }
1701 #endif
1702 #endif
1703 }
1704 }
1705 /* orc & orc. */
1706 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1707
1708 /* xor & xor. */
gen_xor(DisasContext * ctx)1709 static void gen_xor(DisasContext *ctx)
1710 {
1711 /* Optimisation for "set to zero" case */
1712 if (rS(ctx->opcode) != rB(ctx->opcode))
1713 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1714 else
1715 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1716 if (unlikely(Rc(ctx->opcode) != 0))
1717 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1718 }
1719
1720 /* ori */
gen_ori(DisasContext * ctx)1721 static void gen_ori(DisasContext *ctx)
1722 {
1723 target_ulong uimm = UIMM(ctx->opcode);
1724
1725 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1726 return;
1727 }
1728 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1729 }
1730
1731 /* oris */
gen_oris(DisasContext * ctx)1732 static void gen_oris(DisasContext *ctx)
1733 {
1734 target_ulong uimm = UIMM(ctx->opcode);
1735
1736 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1737 /* NOP */
1738 return;
1739 }
1740 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1741 }
1742
1743 /* xori */
gen_xori(DisasContext * ctx)1744 static void gen_xori(DisasContext *ctx)
1745 {
1746 target_ulong uimm = UIMM(ctx->opcode);
1747
1748 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1749 /* NOP */
1750 return;
1751 }
1752 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1753 }
1754
1755 /* xoris */
gen_xoris(DisasContext * ctx)1756 static void gen_xoris(DisasContext *ctx)
1757 {
1758 target_ulong uimm = UIMM(ctx->opcode);
1759
1760 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1761 /* NOP */
1762 return;
1763 }
1764 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1765 }
1766
1767 /* popcntb : PowerPC 2.03 specification */
gen_popcntb(DisasContext * ctx)1768 static void gen_popcntb(DisasContext *ctx)
1769 {
1770 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1771 }
1772
gen_popcntw(DisasContext * ctx)1773 static void gen_popcntw(DisasContext *ctx)
1774 {
1775 #if defined(TARGET_PPC64)
1776 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1777 #else
1778 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1779 #endif
1780 }
1781
1782 #if defined(TARGET_PPC64)
1783 /* popcntd: PowerPC 2.06 specification */
gen_popcntd(DisasContext * ctx)1784 static void gen_popcntd(DisasContext *ctx)
1785 {
1786 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1787 }
1788 #endif
1789
1790 /* prtyw: PowerPC 2.05 specification */
gen_prtyw(DisasContext * ctx)1791 static void gen_prtyw(DisasContext *ctx)
1792 {
1793 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1794 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1795 TCGv t0 = tcg_temp_new();
1796 tcg_gen_shri_tl(t0, rs, 16);
1797 tcg_gen_xor_tl(ra, rs, t0);
1798 tcg_gen_shri_tl(t0, ra, 8);
1799 tcg_gen_xor_tl(ra, ra, t0);
1800 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1801 tcg_temp_free(t0);
1802 }
1803
1804 #if defined(TARGET_PPC64)
1805 /* prtyd: PowerPC 2.05 specification */
gen_prtyd(DisasContext * ctx)1806 static void gen_prtyd(DisasContext *ctx)
1807 {
1808 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1809 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1810 TCGv t0 = tcg_temp_new();
1811 tcg_gen_shri_tl(t0, rs, 32);
1812 tcg_gen_xor_tl(ra, rs, t0);
1813 tcg_gen_shri_tl(t0, ra, 16);
1814 tcg_gen_xor_tl(ra, ra, t0);
1815 tcg_gen_shri_tl(t0, ra, 8);
1816 tcg_gen_xor_tl(ra, ra, t0);
1817 tcg_gen_andi_tl(ra, ra, 1);
1818 tcg_temp_free(t0);
1819 }
1820 #endif
1821
1822 #if defined(TARGET_PPC64)
1823 /* bpermd */
gen_bpermd(DisasContext * ctx)1824 static void gen_bpermd(DisasContext *ctx)
1825 {
1826 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1827 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1828 }
1829 #endif
1830
1831 #if defined(TARGET_PPC64)
1832 /* extsw & extsw. */
1833 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1834
1835 /* cntlzd */
gen_cntlzd(DisasContext * ctx)1836 static void gen_cntlzd(DisasContext *ctx)
1837 {
1838 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
1839 if (unlikely(Rc(ctx->opcode) != 0))
1840 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1841 }
1842
1843 /* cnttzd */
gen_cnttzd(DisasContext * ctx)1844 static void gen_cnttzd(DisasContext *ctx)
1845 {
1846 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
1847 if (unlikely(Rc(ctx->opcode) != 0)) {
1848 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1849 }
1850 }
1851
1852 /* darn */
gen_darn(DisasContext * ctx)1853 static void gen_darn(DisasContext *ctx)
1854 {
1855 int l = L(ctx->opcode);
1856
1857 if (l == 0) {
1858 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)], cpu_env);
1859 } else if (l <= 2) {
1860 /* Return 64-bit random for both CRN and RRN */
1861 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)], cpu_env);
1862 } else {
1863 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
1864 }
1865 }
1866 #endif
1867
1868 /*** Integer rotate ***/
1869
1870 /* rlwimi & rlwimi. */
gen_rlwimi(DisasContext * ctx)1871 static void gen_rlwimi(DisasContext *ctx)
1872 {
1873 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1874 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1875 uint32_t sh = SH(ctx->opcode);
1876 uint32_t mb = MB(ctx->opcode);
1877 uint32_t me = ME(ctx->opcode);
1878
1879 if (sh == (31-me) && mb <= me) {
1880 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1881 } else {
1882 target_ulong mask;
1883 TCGv t1;
1884
1885 #if defined(TARGET_PPC64)
1886 mb += 32;
1887 me += 32;
1888 #endif
1889 mask = MASK(mb, me);
1890
1891 t1 = tcg_temp_new();
1892 if (mask <= 0xffffffffu) {
1893 TCGv_i32 t0 = tcg_temp_new_i32();
1894 tcg_gen_trunc_tl_i32(t0, t_rs);
1895 tcg_gen_rotli_i32(t0, t0, sh);
1896 tcg_gen_extu_i32_tl(t1, t0);
1897 tcg_temp_free_i32(t0);
1898 } else {
1899 #if defined(TARGET_PPC64)
1900 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1901 tcg_gen_rotli_i64(t1, t1, sh);
1902 #else
1903 g_assert_not_reached();
1904 #endif
1905 }
1906
1907 tcg_gen_andi_tl(t1, t1, mask);
1908 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1909 tcg_gen_or_tl(t_ra, t_ra, t1);
1910 tcg_temp_free(t1);
1911 }
1912 if (unlikely(Rc(ctx->opcode) != 0)) {
1913 gen_set_Rc0(ctx, t_ra);
1914 }
1915 }
1916
1917 /* rlwinm & rlwinm. */
gen_rlwinm(DisasContext * ctx)1918 static void gen_rlwinm(DisasContext *ctx)
1919 {
1920 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1921 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1922 int sh = SH(ctx->opcode);
1923 int mb = MB(ctx->opcode);
1924 int me = ME(ctx->opcode);
1925 int len = me - mb + 1;
1926 int rsh = (32 - sh) & 31;
1927
1928 if (sh != 0 && len > 0 && me == (31 - sh)) {
1929 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
1930 } else if (me == 31 && rsh + len <= 32) {
1931 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
1932 } else {
1933 target_ulong mask;
1934 #if defined(TARGET_PPC64)
1935 mb += 32;
1936 me += 32;
1937 #endif
1938 mask = MASK(mb, me);
1939 if (sh == 0) {
1940 tcg_gen_andi_tl(t_ra, t_rs, mask);
1941 } else if (mask <= 0xffffffffu) {
1942 TCGv_i32 t0 = tcg_temp_new_i32();
1943 tcg_gen_trunc_tl_i32(t0, t_rs);
1944 tcg_gen_rotli_i32(t0, t0, sh);
1945 tcg_gen_andi_i32(t0, t0, mask);
1946 tcg_gen_extu_i32_tl(t_ra, t0);
1947 tcg_temp_free_i32(t0);
1948 } else {
1949 #if defined(TARGET_PPC64)
1950 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1951 tcg_gen_rotli_i64(t_ra, t_ra, sh);
1952 tcg_gen_andi_i64(t_ra, t_ra, mask);
1953 #else
1954 g_assert_not_reached();
1955 #endif
1956 }
1957 }
1958 if (unlikely(Rc(ctx->opcode) != 0)) {
1959 gen_set_Rc0(ctx, t_ra);
1960 }
1961 }
1962
1963 /* rlwnm & rlwnm. */
gen_rlwnm(DisasContext * ctx)1964 static void gen_rlwnm(DisasContext *ctx)
1965 {
1966 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1967 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1968 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1969 uint32_t mb = MB(ctx->opcode);
1970 uint32_t me = ME(ctx->opcode);
1971 target_ulong mask;
1972
1973 #if defined(TARGET_PPC64)
1974 mb += 32;
1975 me += 32;
1976 #endif
1977 mask = MASK(mb, me);
1978
1979 if (mask <= 0xffffffffu) {
1980 TCGv_i32 t0 = tcg_temp_new_i32();
1981 TCGv_i32 t1 = tcg_temp_new_i32();
1982 tcg_gen_trunc_tl_i32(t0, t_rb);
1983 tcg_gen_trunc_tl_i32(t1, t_rs);
1984 tcg_gen_andi_i32(t0, t0, 0x1f);
1985 tcg_gen_rotl_i32(t1, t1, t0);
1986 tcg_gen_extu_i32_tl(t_ra, t1);
1987 tcg_temp_free_i32(t0);
1988 tcg_temp_free_i32(t1);
1989 } else {
1990 #if defined(TARGET_PPC64)
1991 TCGv_i64 t0 = tcg_temp_new_i64();
1992 tcg_gen_andi_i64(t0, t_rb, 0x1f);
1993 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1994 tcg_gen_rotl_i64(t_ra, t_ra, t0);
1995 tcg_temp_free_i64(t0);
1996 #else
1997 g_assert_not_reached();
1998 #endif
1999 }
2000
2001 tcg_gen_andi_tl(t_ra, t_ra, mask);
2002
2003 if (unlikely(Rc(ctx->opcode) != 0)) {
2004 gen_set_Rc0(ctx, t_ra);
2005 }
2006 }
2007
2008 #if defined(TARGET_PPC64)
2009 #define GEN_PPC64_R2(name, opc1, opc2) \
2010 static void glue(gen_, name##0)(DisasContext *ctx) \
2011 { \
2012 gen_##name(ctx, 0); \
2013 } \
2014 \
2015 static void glue(gen_, name##1)(DisasContext *ctx) \
2016 { \
2017 gen_##name(ctx, 1); \
2018 }
2019 #define GEN_PPC64_R4(name, opc1, opc2) \
2020 static void glue(gen_, name##0)(DisasContext *ctx) \
2021 { \
2022 gen_##name(ctx, 0, 0); \
2023 } \
2024 \
2025 static void glue(gen_, name##1)(DisasContext *ctx) \
2026 { \
2027 gen_##name(ctx, 0, 1); \
2028 } \
2029 \
2030 static void glue(gen_, name##2)(DisasContext *ctx) \
2031 { \
2032 gen_##name(ctx, 1, 0); \
2033 } \
2034 \
2035 static void glue(gen_, name##3)(DisasContext *ctx) \
2036 { \
2037 gen_##name(ctx, 1, 1); \
2038 }
2039
gen_rldinm(DisasContext * ctx,int mb,int me,int sh)2040 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
2041 {
2042 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2043 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2044 int len = me - mb + 1;
2045 int rsh = (64 - sh) & 63;
2046
2047 if (sh != 0 && len > 0 && me == (63 - sh)) {
2048 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
2049 } else if (me == 63 && rsh + len <= 64) {
2050 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
2051 } else {
2052 tcg_gen_rotli_tl(t_ra, t_rs, sh);
2053 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2054 }
2055 if (unlikely(Rc(ctx->opcode) != 0)) {
2056 gen_set_Rc0(ctx, t_ra);
2057 }
2058 }
2059
2060 /* rldicl - rldicl. */
gen_rldicl(DisasContext * ctx,int mbn,int shn)2061 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
2062 {
2063 uint32_t sh, mb;
2064
2065 sh = SH(ctx->opcode) | (shn << 5);
2066 mb = MB(ctx->opcode) | (mbn << 5);
2067 gen_rldinm(ctx, mb, 63, sh);
2068 }
2069 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
2070
2071 /* rldicr - rldicr. */
gen_rldicr(DisasContext * ctx,int men,int shn)2072 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
2073 {
2074 uint32_t sh, me;
2075
2076 sh = SH(ctx->opcode) | (shn << 5);
2077 me = MB(ctx->opcode) | (men << 5);
2078 gen_rldinm(ctx, 0, me, sh);
2079 }
2080 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
2081
2082 /* rldic - rldic. */
gen_rldic(DisasContext * ctx,int mbn,int shn)2083 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
2084 {
2085 uint32_t sh, mb;
2086
2087 sh = SH(ctx->opcode) | (shn << 5);
2088 mb = MB(ctx->opcode) | (mbn << 5);
2089 gen_rldinm(ctx, mb, 63 - sh, sh);
2090 }
2091 GEN_PPC64_R4(rldic, 0x1E, 0x04);
2092
gen_rldnm(DisasContext * ctx,int mb,int me)2093 static void gen_rldnm(DisasContext *ctx, int mb, int me)
2094 {
2095 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2096 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2097 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2098 TCGv t0;
2099
2100 t0 = tcg_temp_new();
2101 tcg_gen_andi_tl(t0, t_rb, 0x3f);
2102 tcg_gen_rotl_tl(t_ra, t_rs, t0);
2103 tcg_temp_free(t0);
2104
2105 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2106 if (unlikely(Rc(ctx->opcode) != 0)) {
2107 gen_set_Rc0(ctx, t_ra);
2108 }
2109 }
2110
2111 /* rldcl - rldcl. */
gen_rldcl(DisasContext * ctx,int mbn)2112 static inline void gen_rldcl(DisasContext *ctx, int mbn)
2113 {
2114 uint32_t mb;
2115
2116 mb = MB(ctx->opcode) | (mbn << 5);
2117 gen_rldnm(ctx, mb, 63);
2118 }
2119 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
2120
2121 /* rldcr - rldcr. */
gen_rldcr(DisasContext * ctx,int men)2122 static inline void gen_rldcr(DisasContext *ctx, int men)
2123 {
2124 uint32_t me;
2125
2126 me = MB(ctx->opcode) | (men << 5);
2127 gen_rldnm(ctx, 0, me);
2128 }
2129 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
2130
2131 /* rldimi - rldimi. */
gen_rldimi(DisasContext * ctx,int mbn,int shn)2132 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
2133 {
2134 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2135 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2136 uint32_t sh = SH(ctx->opcode) | (shn << 5);
2137 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2138 uint32_t me = 63 - sh;
2139
2140 if (mb <= me) {
2141 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2142 } else {
2143 target_ulong mask = MASK(mb, me);
2144 TCGv t1 = tcg_temp_new();
2145
2146 tcg_gen_rotli_tl(t1, t_rs, sh);
2147 tcg_gen_andi_tl(t1, t1, mask);
2148 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2149 tcg_gen_or_tl(t_ra, t_ra, t1);
2150 tcg_temp_free(t1);
2151 }
2152 if (unlikely(Rc(ctx->opcode) != 0)) {
2153 gen_set_Rc0(ctx, t_ra);
2154 }
2155 }
2156 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2157 #endif
2158
2159 /*** Integer shift ***/
2160
2161 /* slw & slw. */
gen_slw(DisasContext * ctx)2162 static void gen_slw(DisasContext *ctx)
2163 {
2164 TCGv t0, t1;
2165
2166 t0 = tcg_temp_new();
2167 /* AND rS with a mask that is 0 when rB >= 0x20 */
2168 #if defined(TARGET_PPC64)
2169 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2170 tcg_gen_sari_tl(t0, t0, 0x3f);
2171 #else
2172 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2173 tcg_gen_sari_tl(t0, t0, 0x1f);
2174 #endif
2175 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2176 t1 = tcg_temp_new();
2177 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2178 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2179 tcg_temp_free(t1);
2180 tcg_temp_free(t0);
2181 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2182 if (unlikely(Rc(ctx->opcode) != 0))
2183 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2184 }
2185
2186 /* sraw & sraw. */
gen_sraw(DisasContext * ctx)2187 static void gen_sraw(DisasContext *ctx)
2188 {
2189 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
2190 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2191 if (unlikely(Rc(ctx->opcode) != 0))
2192 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2193 }
2194
2195 /* srawi & srawi. */
gen_srawi(DisasContext * ctx)2196 static void gen_srawi(DisasContext *ctx)
2197 {
2198 int sh = SH(ctx->opcode);
2199 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2200 TCGv src = cpu_gpr[rS(ctx->opcode)];
2201 if (sh == 0) {
2202 tcg_gen_ext32s_tl(dst, src);
2203 tcg_gen_movi_tl(cpu_ca, 0);
2204 if (is_isa300(ctx)) {
2205 tcg_gen_movi_tl(cpu_ca32, 0);
2206 }
2207 } else {
2208 TCGv t0;
2209 tcg_gen_ext32s_tl(dst, src);
2210 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2211 t0 = tcg_temp_new();
2212 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2213 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2214 tcg_temp_free(t0);
2215 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2216 if (is_isa300(ctx)) {
2217 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2218 }
2219 tcg_gen_sari_tl(dst, dst, sh);
2220 }
2221 if (unlikely(Rc(ctx->opcode) != 0)) {
2222 gen_set_Rc0(ctx, dst);
2223 }
2224 }
2225
2226 /* srw & srw. */
gen_srw(DisasContext * ctx)2227 static void gen_srw(DisasContext *ctx)
2228 {
2229 TCGv t0, t1;
2230
2231 t0 = tcg_temp_new();
2232 /* AND rS with a mask that is 0 when rB >= 0x20 */
2233 #if defined(TARGET_PPC64)
2234 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2235 tcg_gen_sari_tl(t0, t0, 0x3f);
2236 #else
2237 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2238 tcg_gen_sari_tl(t0, t0, 0x1f);
2239 #endif
2240 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2241 tcg_gen_ext32u_tl(t0, t0);
2242 t1 = tcg_temp_new();
2243 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2244 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2245 tcg_temp_free(t1);
2246 tcg_temp_free(t0);
2247 if (unlikely(Rc(ctx->opcode) != 0))
2248 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2249 }
2250
2251 #if defined(TARGET_PPC64)
2252 /* sld & sld. */
gen_sld(DisasContext * ctx)2253 static void gen_sld(DisasContext *ctx)
2254 {
2255 TCGv t0, t1;
2256
2257 t0 = tcg_temp_new();
2258 /* AND rS with a mask that is 0 when rB >= 0x40 */
2259 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2260 tcg_gen_sari_tl(t0, t0, 0x3f);
2261 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2262 t1 = tcg_temp_new();
2263 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2264 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2265 tcg_temp_free(t1);
2266 tcg_temp_free(t0);
2267 if (unlikely(Rc(ctx->opcode) != 0))
2268 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2269 }
2270
2271 /* srad & srad. */
gen_srad(DisasContext * ctx)2272 static void gen_srad(DisasContext *ctx)
2273 {
2274 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2275 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2276 if (unlikely(Rc(ctx->opcode) != 0))
2277 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2278 }
2279 /* sradi & sradi. */
gen_sradi(DisasContext * ctx,int n)2280 static inline void gen_sradi(DisasContext *ctx, int n)
2281 {
2282 int sh = SH(ctx->opcode) + (n << 5);
2283 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2284 TCGv src = cpu_gpr[rS(ctx->opcode)];
2285 if (sh == 0) {
2286 tcg_gen_mov_tl(dst, src);
2287 tcg_gen_movi_tl(cpu_ca, 0);
2288 if (is_isa300(ctx)) {
2289 tcg_gen_movi_tl(cpu_ca32, 0);
2290 }
2291 } else {
2292 TCGv t0;
2293 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2294 t0 = tcg_temp_new();
2295 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2296 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2297 tcg_temp_free(t0);
2298 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2299 if (is_isa300(ctx)) {
2300 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2301 }
2302 tcg_gen_sari_tl(dst, src, sh);
2303 }
2304 if (unlikely(Rc(ctx->opcode) != 0)) {
2305 gen_set_Rc0(ctx, dst);
2306 }
2307 }
2308
gen_sradi0(DisasContext * ctx)2309 static void gen_sradi0(DisasContext *ctx)
2310 {
2311 gen_sradi(ctx, 0);
2312 }
2313
gen_sradi1(DisasContext * ctx)2314 static void gen_sradi1(DisasContext *ctx)
2315 {
2316 gen_sradi(ctx, 1);
2317 }
2318
2319 /* extswsli & extswsli. */
gen_extswsli(DisasContext * ctx,int n)2320 static inline void gen_extswsli(DisasContext *ctx, int n)
2321 {
2322 int sh = SH(ctx->opcode) + (n << 5);
2323 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2324 TCGv src = cpu_gpr[rS(ctx->opcode)];
2325
2326 tcg_gen_ext32s_tl(dst, src);
2327 tcg_gen_shli_tl(dst, dst, sh);
2328 if (unlikely(Rc(ctx->opcode) != 0)) {
2329 gen_set_Rc0(ctx, dst);
2330 }
2331 }
2332
gen_extswsli0(DisasContext * ctx)2333 static void gen_extswsli0(DisasContext *ctx)
2334 {
2335 gen_extswsli(ctx, 0);
2336 }
2337
gen_extswsli1(DisasContext * ctx)2338 static void gen_extswsli1(DisasContext *ctx)
2339 {
2340 gen_extswsli(ctx, 1);
2341 }
2342
2343 /* srd & srd. */
gen_srd(DisasContext * ctx)2344 static void gen_srd(DisasContext *ctx)
2345 {
2346 TCGv t0, t1;
2347
2348 t0 = tcg_temp_new();
2349 /* AND rS with a mask that is 0 when rB >= 0x40 */
2350 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2351 tcg_gen_sari_tl(t0, t0, 0x3f);
2352 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2353 t1 = tcg_temp_new();
2354 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2355 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2356 tcg_temp_free(t1);
2357 tcg_temp_free(t0);
2358 if (unlikely(Rc(ctx->opcode) != 0))
2359 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2360 }
2361 #endif
2362
2363 /*** Addressing modes ***/
2364 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
gen_addr_imm_index(DisasContext * ctx,TCGv EA,target_long maskl)2365 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2366 target_long maskl)
2367 {
2368 target_long simm = SIMM(ctx->opcode);
2369
2370 simm &= ~maskl;
2371 if (rA(ctx->opcode) == 0) {
2372 if (NARROW_MODE(ctx)) {
2373 simm = (uint32_t)simm;
2374 }
2375 tcg_gen_movi_tl(EA, simm);
2376 } else if (likely(simm != 0)) {
2377 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2378 if (NARROW_MODE(ctx)) {
2379 tcg_gen_ext32u_tl(EA, EA);
2380 }
2381 } else {
2382 if (NARROW_MODE(ctx)) {
2383 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2384 } else {
2385 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2386 }
2387 }
2388 }
2389
gen_addr_reg_index(DisasContext * ctx,TCGv EA)2390 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2391 {
2392 if (rA(ctx->opcode) == 0) {
2393 if (NARROW_MODE(ctx)) {
2394 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2395 } else {
2396 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2397 }
2398 } else {
2399 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2400 if (NARROW_MODE(ctx)) {
2401 tcg_gen_ext32u_tl(EA, EA);
2402 }
2403 }
2404 }
2405
gen_addr_register(DisasContext * ctx,TCGv EA)2406 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2407 {
2408 if (rA(ctx->opcode) == 0) {
2409 tcg_gen_movi_tl(EA, 0);
2410 } else if (NARROW_MODE(ctx)) {
2411 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2412 } else {
2413 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2414 }
2415 }
2416
gen_addr_add(DisasContext * ctx,TCGv ret,TCGv arg1,target_long val)2417 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2418 target_long val)
2419 {
2420 tcg_gen_addi_tl(ret, arg1, val);
2421 if (NARROW_MODE(ctx)) {
2422 tcg_gen_ext32u_tl(ret, ret);
2423 }
2424 }
2425
gen_align_no_le(DisasContext * ctx)2426 static inline void gen_align_no_le(DisasContext *ctx)
2427 {
2428 gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
2429 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
2430 }
2431
2432 /*** Integer load ***/
2433 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
2434 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
2435
2436 #define GEN_QEMU_LOAD_TL(ldop, op) \
2437 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \
2438 TCGv val, \
2439 TCGv addr) \
2440 { \
2441 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
2442 }
2443
2444 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB))
2445 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW))
2446 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW))
2447 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL))
2448 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL))
2449
2450 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW))
2451 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL))
2452
2453 #define GEN_QEMU_LOAD_64(ldop, op) \
2454 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
2455 TCGv_i64 val, \
2456 TCGv addr) \
2457 { \
2458 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \
2459 }
2460
2461 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB))
2462 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW))
2463 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL))
2464 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL))
2465 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q))
2466
2467 #if defined(TARGET_PPC64)
2468 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q))
2469 #endif
2470
2471 #define GEN_QEMU_STORE_TL(stop, op) \
2472 static void glue(gen_qemu_, stop)(DisasContext *ctx, \
2473 TCGv val, \
2474 TCGv addr) \
2475 { \
2476 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
2477 }
2478
2479 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
2480 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
2481 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
2482
2483 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW))
2484 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL))
2485
2486 #define GEN_QEMU_STORE_64(stop, op) \
2487 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
2488 TCGv_i64 val, \
2489 TCGv addr) \
2490 { \
2491 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
2492 }
2493
2494 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB))
2495 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW))
2496 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))
2497 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q))
2498
2499 #if defined(TARGET_PPC64)
2500 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q))
2501 #endif
2502
2503 #define GEN_LD(name, ldop, opc, type) \
2504 static void glue(gen_, name)(DisasContext *ctx) \
2505 { \
2506 TCGv EA; \
2507 gen_set_access_type(ctx, ACCESS_INT); \
2508 EA = tcg_temp_new(); \
2509 gen_addr_imm_index(ctx, EA, 0); \
2510 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2511 tcg_temp_free(EA); \
2512 }
2513
2514 #define GEN_LDU(name, ldop, opc, type) \
2515 static void glue(gen_, name##u)(DisasContext *ctx) \
2516 { \
2517 TCGv EA; \
2518 if (unlikely(rA(ctx->opcode) == 0 || \
2519 rA(ctx->opcode) == rD(ctx->opcode))) { \
2520 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2521 return; \
2522 } \
2523 gen_set_access_type(ctx, ACCESS_INT); \
2524 EA = tcg_temp_new(); \
2525 if (type == PPC_64B) \
2526 gen_addr_imm_index(ctx, EA, 0x03); \
2527 else \
2528 gen_addr_imm_index(ctx, EA, 0); \
2529 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2530 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2531 tcg_temp_free(EA); \
2532 }
2533
2534 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2535 static void glue(gen_, name##ux)(DisasContext *ctx) \
2536 { \
2537 TCGv EA; \
2538 if (unlikely(rA(ctx->opcode) == 0 || \
2539 rA(ctx->opcode) == rD(ctx->opcode))) { \
2540 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2541 return; \
2542 } \
2543 gen_set_access_type(ctx, ACCESS_INT); \
2544 EA = tcg_temp_new(); \
2545 gen_addr_reg_index(ctx, EA); \
2546 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2547 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2548 tcg_temp_free(EA); \
2549 }
2550
2551 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2552 static void glue(gen_, name##x)(DisasContext *ctx) \
2553 { \
2554 TCGv EA; \
2555 chk; \
2556 gen_set_access_type(ctx, ACCESS_INT); \
2557 EA = tcg_temp_new(); \
2558 gen_addr_reg_index(ctx, EA); \
2559 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2560 tcg_temp_free(EA); \
2561 }
2562
2563 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2564 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2565
2566 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2567 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2568
2569 #define GEN_LDS(name, ldop, op, type) \
2570 GEN_LD(name, ldop, op | 0x20, type); \
2571 GEN_LDU(name, ldop, op | 0x21, type); \
2572 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2573 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2574
2575 /* lbz lbzu lbzux lbzx */
2576 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2577 /* lha lhau lhaux lhax */
2578 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2579 /* lhz lhzu lhzux lhzx */
2580 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2581 /* lwz lwzu lwzux lwzx */
2582 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2583
2584 #define GEN_LDEPX(name, ldop, opc2, opc3) \
2585 static void glue(gen_, name##epx)(DisasContext *ctx) \
2586 { \
2587 TCGv EA; \
2588 CHK_SV; \
2589 gen_set_access_type(ctx, ACCESS_INT); \
2590 EA = tcg_temp_new(); \
2591 gen_addr_reg_index(ctx, EA); \
2592 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\
2593 tcg_temp_free(EA); \
2594 }
2595
2596 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)
2597 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08)
2598 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
2599 #if defined(TARGET_PPC64)
2600 GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)
2601 #endif
2602
2603 #if defined(TARGET_PPC64)
2604 /* lwaux */
2605 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2606 /* lwax */
2607 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2608 /* ldux */
2609 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B);
2610 /* ldx */
2611 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B);
2612
2613 /* CI load/store variants */
2614 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
2615 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
2616 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
2617 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
2618
gen_ld(DisasContext * ctx)2619 static void gen_ld(DisasContext *ctx)
2620 {
2621 TCGv EA;
2622 if (Rc(ctx->opcode)) {
2623 if (unlikely(rA(ctx->opcode) == 0 ||
2624 rA(ctx->opcode) == rD(ctx->opcode))) {
2625 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2626 return;
2627 }
2628 }
2629 gen_set_access_type(ctx, ACCESS_INT);
2630 EA = tcg_temp_new();
2631 gen_addr_imm_index(ctx, EA, 0x03);
2632 if (ctx->opcode & 0x02) {
2633 /* lwa (lwau is undefined) */
2634 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2635 } else {
2636 /* ld - ldu */
2637 gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2638 }
2639 if (Rc(ctx->opcode))
2640 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2641 tcg_temp_free(EA);
2642 }
2643
2644 /* lq */
gen_lq(DisasContext * ctx)2645 static void gen_lq(DisasContext *ctx)
2646 {
2647 int ra, rd;
2648 TCGv EA, hi, lo;
2649
2650 /* lq is a legal user mode instruction starting in ISA 2.07 */
2651 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2652 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2653
2654 if (!legal_in_user_mode && ctx->pr) {
2655 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2656 return;
2657 }
2658
2659 if (!le_is_supported && ctx->le_mode) {
2660 gen_align_no_le(ctx);
2661 return;
2662 }
2663 ra = rA(ctx->opcode);
2664 rd = rD(ctx->opcode);
2665 if (unlikely((rd & 1) || rd == ra)) {
2666 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2667 return;
2668 }
2669
2670 gen_set_access_type(ctx, ACCESS_INT);
2671 EA = tcg_temp_new();
2672 gen_addr_imm_index(ctx, EA, 0x0F);
2673
2674 /* Note that the low part is always in RD+1, even in LE mode. */
2675 lo = cpu_gpr[rd + 1];
2676 hi = cpu_gpr[rd];
2677
2678 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
2679 #ifdef CONFIG_ATOMIC128
2680 TCGv_i32 oi = tcg_temp_new_i32();
2681 if (ctx->le_mode) {
2682 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx));
2683 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi);
2684 } else {
2685 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx));
2686 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
2687 }
2688 tcg_temp_free_i32(oi);
2689 tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));
2690 #else
2691 /* Restart with exclusive lock. */
2692 gen_helper_exit_atomic(cpu_env);
2693 ctx->base.is_jmp = DISAS_NORETURN;
2694 #endif
2695 } else if (ctx->le_mode) {
2696 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ);
2697 gen_addr_add(ctx, EA, EA, 8);
2698 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ);
2699 } else {
2700 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ);
2701 gen_addr_add(ctx, EA, EA, 8);
2702 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ);
2703 }
2704 tcg_temp_free(EA);
2705 }
2706 #endif
2707
2708 /*** Integer store ***/
2709 #define GEN_ST(name, stop, opc, type) \
2710 static void glue(gen_, name)(DisasContext *ctx) \
2711 { \
2712 TCGv EA; \
2713 gen_set_access_type(ctx, ACCESS_INT); \
2714 EA = tcg_temp_new(); \
2715 gen_addr_imm_index(ctx, EA, 0); \
2716 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2717 tcg_temp_free(EA); \
2718 }
2719
2720 #define GEN_STU(name, stop, opc, type) \
2721 static void glue(gen_, stop##u)(DisasContext *ctx) \
2722 { \
2723 TCGv EA; \
2724 if (unlikely(rA(ctx->opcode) == 0)) { \
2725 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2726 return; \
2727 } \
2728 gen_set_access_type(ctx, ACCESS_INT); \
2729 EA = tcg_temp_new(); \
2730 if (type == PPC_64B) \
2731 gen_addr_imm_index(ctx, EA, 0x03); \
2732 else \
2733 gen_addr_imm_index(ctx, EA, 0); \
2734 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2735 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2736 tcg_temp_free(EA); \
2737 }
2738
2739 #define GEN_STUX(name, stop, opc2, opc3, type) \
2740 static void glue(gen_, name##ux)(DisasContext *ctx) \
2741 { \
2742 TCGv EA; \
2743 if (unlikely(rA(ctx->opcode) == 0)) { \
2744 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2745 return; \
2746 } \
2747 gen_set_access_type(ctx, ACCESS_INT); \
2748 EA = tcg_temp_new(); \
2749 gen_addr_reg_index(ctx, EA); \
2750 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2751 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2752 tcg_temp_free(EA); \
2753 }
2754
2755 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2756 static void glue(gen_, name##x)(DisasContext *ctx) \
2757 { \
2758 TCGv EA; \
2759 chk; \
2760 gen_set_access_type(ctx, ACCESS_INT); \
2761 EA = tcg_temp_new(); \
2762 gen_addr_reg_index(ctx, EA); \
2763 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2764 tcg_temp_free(EA); \
2765 }
2766 #define GEN_STX(name, stop, opc2, opc3, type) \
2767 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2768
2769 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2770 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2771
2772 #define GEN_STS(name, stop, op, type) \
2773 GEN_ST(name, stop, op | 0x20, type); \
2774 GEN_STU(name, stop, op | 0x21, type); \
2775 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2776 GEN_STX(name, stop, 0x17, op | 0x00, type)
2777
2778 /* stb stbu stbux stbx */
2779 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2780 /* sth sthu sthux sthx */
2781 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2782 /* stw stwu stwux stwx */
2783 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2784
2785 #define GEN_STEPX(name, stop, opc2, opc3) \
2786 static void glue(gen_, name##epx)(DisasContext *ctx) \
2787 { \
2788 TCGv EA; \
2789 CHK_SV; \
2790 gen_set_access_type(ctx, ACCESS_INT); \
2791 EA = tcg_temp_new(); \
2792 gen_addr_reg_index(ctx, EA); \
2793 tcg_gen_qemu_st_tl( \
2794 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \
2795 tcg_temp_free(EA); \
2796 }
2797
2798 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)
2799 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C)
2800 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)
2801 #if defined(TARGET_PPC64)
2802 GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04)
2803 #endif
2804
2805 #if defined(TARGET_PPC64)
2806 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B);
2807 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B);
2808 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
2809 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
2810 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
2811 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
2812
gen_std(DisasContext * ctx)2813 static void gen_std(DisasContext *ctx)
2814 {
2815 int rs;
2816 TCGv EA;
2817
2818 rs = rS(ctx->opcode);
2819 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
2820 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2821 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2822 TCGv hi, lo;
2823
2824 if (!(ctx->insns_flags & PPC_64BX)) {
2825 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2826 }
2827
2828 if (!legal_in_user_mode && ctx->pr) {
2829 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2830 return;
2831 }
2832
2833 if (!le_is_supported && ctx->le_mode) {
2834 gen_align_no_le(ctx);
2835 return;
2836 }
2837
2838 if (unlikely(rs & 1)) {
2839 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2840 return;
2841 }
2842 gen_set_access_type(ctx, ACCESS_INT);
2843 EA = tcg_temp_new();
2844 gen_addr_imm_index(ctx, EA, 0x03);
2845
2846 /* Note that the low part is always in RS+1, even in LE mode. */
2847 lo = cpu_gpr[rs + 1];
2848 hi = cpu_gpr[rs];
2849
2850 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
2851 #ifdef CONFIG_ATOMIC128
2852 TCGv_i32 oi = tcg_temp_new_i32();
2853 if (ctx->le_mode) {
2854 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx));
2855 gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi);
2856 } else {
2857 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx));
2858 gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi);
2859 }
2860 tcg_temp_free_i32(oi);
2861 #else
2862 /* Restart with exclusive lock. */
2863 gen_helper_exit_atomic(cpu_env);
2864 ctx->base.is_jmp = DISAS_NORETURN;
2865 #endif
2866 } else if (ctx->le_mode) {
2867 tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ);
2868 gen_addr_add(ctx, EA, EA, 8);
2869 tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ);
2870 } else {
2871 tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ);
2872 gen_addr_add(ctx, EA, EA, 8);
2873 tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ);
2874 }
2875 tcg_temp_free(EA);
2876 } else {
2877 /* std / stdu */
2878 if (Rc(ctx->opcode)) {
2879 if (unlikely(rA(ctx->opcode) == 0)) {
2880 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2881 return;
2882 }
2883 }
2884 gen_set_access_type(ctx, ACCESS_INT);
2885 EA = tcg_temp_new();
2886 gen_addr_imm_index(ctx, EA, 0x03);
2887 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2888 if (Rc(ctx->opcode))
2889 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2890 tcg_temp_free(EA);
2891 }
2892 }
2893 #endif
2894 /*** Integer load and store with byte reverse ***/
2895
2896 /* lhbrx */
2897 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2898
2899 /* lwbrx */
2900 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2901
2902 #if defined(TARGET_PPC64)
2903 /* ldbrx */
2904 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
2905 /* stdbrx */
2906 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
2907 #endif /* TARGET_PPC64 */
2908
2909 /* sthbrx */
2910 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2911 /* stwbrx */
2912 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2913
2914 /*** Integer load and store multiple ***/
2915
2916 /* lmw */
gen_lmw(DisasContext * ctx)2917 static void gen_lmw(DisasContext *ctx)
2918 {
2919 TCGv t0;
2920 TCGv_i32 t1;
2921
2922 if (ctx->le_mode) {
2923 gen_align_no_le(ctx);
2924 return;
2925 }
2926 gen_set_access_type(ctx, ACCESS_INT);
2927 t0 = tcg_temp_new();
2928 t1 = tcg_const_i32(rD(ctx->opcode));
2929 gen_addr_imm_index(ctx, t0, 0);
2930 gen_helper_lmw(cpu_env, t0, t1);
2931 tcg_temp_free(t0);
2932 tcg_temp_free_i32(t1);
2933 }
2934
2935 /* stmw */
gen_stmw(DisasContext * ctx)2936 static void gen_stmw(DisasContext *ctx)
2937 {
2938 TCGv t0;
2939 TCGv_i32 t1;
2940
2941 if (ctx->le_mode) {
2942 gen_align_no_le(ctx);
2943 return;
2944 }
2945 gen_set_access_type(ctx, ACCESS_INT);
2946 t0 = tcg_temp_new();
2947 t1 = tcg_const_i32(rS(ctx->opcode));
2948 gen_addr_imm_index(ctx, t0, 0);
2949 gen_helper_stmw(cpu_env, t0, t1);
2950 tcg_temp_free(t0);
2951 tcg_temp_free_i32(t1);
2952 }
2953
2954 /*** Integer load and store strings ***/
2955
2956 /* lswi */
2957 /* PowerPC32 specification says we must generate an exception if
2958 * rA is in the range of registers to be loaded.
2959 * In an other hand, IBM says this is valid, but rA won't be loaded.
2960 * For now, I'll follow the spec...
2961 */
gen_lswi(DisasContext * ctx)2962 static void gen_lswi(DisasContext *ctx)
2963 {
2964 TCGv t0;
2965 TCGv_i32 t1, t2;
2966 int nb = NB(ctx->opcode);
2967 int start = rD(ctx->opcode);
2968 int ra = rA(ctx->opcode);
2969 int nr;
2970
2971 if (ctx->le_mode) {
2972 gen_align_no_le(ctx);
2973 return;
2974 }
2975 if (nb == 0)
2976 nb = 32;
2977 nr = DIV_ROUND_UP(nb, 4);
2978 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
2979 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2980 return;
2981 }
2982 gen_set_access_type(ctx, ACCESS_INT);
2983 t0 = tcg_temp_new();
2984 gen_addr_register(ctx, t0);
2985 t1 = tcg_const_i32(nb);
2986 t2 = tcg_const_i32(start);
2987 gen_helper_lsw(cpu_env, t0, t1, t2);
2988 tcg_temp_free(t0);
2989 tcg_temp_free_i32(t1);
2990 tcg_temp_free_i32(t2);
2991 }
2992
2993 /* lswx */
gen_lswx(DisasContext * ctx)2994 static void gen_lswx(DisasContext *ctx)
2995 {
2996 TCGv t0;
2997 TCGv_i32 t1, t2, t3;
2998
2999 if (ctx->le_mode) {
3000 gen_align_no_le(ctx);
3001 return;
3002 }
3003 gen_set_access_type(ctx, ACCESS_INT);
3004 t0 = tcg_temp_new();
3005 gen_addr_reg_index(ctx, t0);
3006 t1 = tcg_const_i32(rD(ctx->opcode));
3007 t2 = tcg_const_i32(rA(ctx->opcode));
3008 t3 = tcg_const_i32(rB(ctx->opcode));
3009 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3010 tcg_temp_free(t0);
3011 tcg_temp_free_i32(t1);
3012 tcg_temp_free_i32(t2);
3013 tcg_temp_free_i32(t3);
3014 }
3015
3016 /* stswi */
gen_stswi(DisasContext * ctx)3017 static void gen_stswi(DisasContext *ctx)
3018 {
3019 TCGv t0;
3020 TCGv_i32 t1, t2;
3021 int nb = NB(ctx->opcode);
3022
3023 if (ctx->le_mode) {
3024 gen_align_no_le(ctx);
3025 return;
3026 }
3027 gen_set_access_type(ctx, ACCESS_INT);
3028 t0 = tcg_temp_new();
3029 gen_addr_register(ctx, t0);
3030 if (nb == 0)
3031 nb = 32;
3032 t1 = tcg_const_i32(nb);
3033 t2 = tcg_const_i32(rS(ctx->opcode));
3034 gen_helper_stsw(cpu_env, t0, t1, t2);
3035 tcg_temp_free(t0);
3036 tcg_temp_free_i32(t1);
3037 tcg_temp_free_i32(t2);
3038 }
3039
3040 /* stswx */
gen_stswx(DisasContext * ctx)3041 static void gen_stswx(DisasContext *ctx)
3042 {
3043 TCGv t0;
3044 TCGv_i32 t1, t2;
3045
3046 if (ctx->le_mode) {
3047 gen_align_no_le(ctx);
3048 return;
3049 }
3050 gen_set_access_type(ctx, ACCESS_INT);
3051 t0 = tcg_temp_new();
3052 gen_addr_reg_index(ctx, t0);
3053 t1 = tcg_temp_new_i32();
3054 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3055 tcg_gen_andi_i32(t1, t1, 0x7F);
3056 t2 = tcg_const_i32(rS(ctx->opcode));
3057 gen_helper_stsw(cpu_env, t0, t1, t2);
3058 tcg_temp_free(t0);
3059 tcg_temp_free_i32(t1);
3060 tcg_temp_free_i32(t2);
3061 }
3062
3063 /*** Memory synchronisation ***/
3064 /* eieio */
gen_eieio(DisasContext * ctx)3065 static void gen_eieio(DisasContext *ctx)
3066 {
3067 TCGBar bar = TCG_MO_LD_ST;
3068
3069 /*
3070 * POWER9 has a eieio instruction variant using bit 6 as a hint to
3071 * tell the CPU it is a store-forwarding barrier.
3072 */
3073 if (ctx->opcode & 0x2000000) {
3074 /*
3075 * ISA says that "Reserved fields in instructions are ignored
3076 * by the processor". So ignore the bit 6 on non-POWER9 CPU but
3077 * as this is not an instruction software should be using,
3078 * complain to the user.
3079 */
3080 if (!(ctx->insns_flags2 & PPC2_ISA300)) {
3081 qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @"
3082 TARGET_FMT_lx "\n", ctx->base.pc_next - 4);
3083 } else {
3084 bar = TCG_MO_ST_LD;
3085 }
3086 }
3087
3088 tcg_gen_mb(bar | TCG_BAR_SC);
3089 }
3090
3091 #if !defined(CONFIG_USER_ONLY)
gen_check_tlb_flush(DisasContext * ctx,bool global)3092 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global)
3093 {
3094 TCGv_i32 t;
3095 TCGLabel *l;
3096
3097 if (!ctx->lazy_tlb_flush) {
3098 return;
3099 }
3100 l = gen_new_label();
3101 t = tcg_temp_new_i32();
3102 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3103 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3104 if (global) {
3105 gen_helper_check_tlb_flush_global(cpu_env);
3106 } else {
3107 gen_helper_check_tlb_flush_local(cpu_env);
3108 }
3109 gen_set_label(l);
3110 tcg_temp_free_i32(t);
3111 }
3112 #else
gen_check_tlb_flush(DisasContext * ctx,bool global)3113 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { }
3114 #endif
3115
3116 /* isync */
gen_isync(DisasContext * ctx)3117 static void gen_isync(DisasContext *ctx)
3118 {
3119 /*
3120 * We need to check for a pending TLB flush. This can only happen in
3121 * kernel mode however so check MSR_PR
3122 */
3123 if (!ctx->pr) {
3124 gen_check_tlb_flush(ctx, false);
3125 }
3126 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
3127 gen_stop_exception(ctx);
3128 }
3129
3130 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
3131
gen_load_locked(DisasContext * ctx,TCGMemOp memop)3132 static void gen_load_locked(DisasContext *ctx, TCGMemOp memop)
3133 {
3134 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3135 TCGv t0 = tcg_temp_new();
3136
3137 gen_set_access_type(ctx, ACCESS_RES);
3138 gen_addr_reg_index(ctx, t0);
3139 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN);
3140 tcg_gen_mov_tl(cpu_reserve, t0);
3141 tcg_gen_mov_tl(cpu_reserve_val, gpr);
3142 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
3143 tcg_temp_free(t0);
3144 }
3145
3146 #define LARX(name, memop) \
3147 static void gen_##name(DisasContext *ctx) \
3148 { \
3149 gen_load_locked(ctx, memop); \
3150 }
3151
3152 /* lwarx */
LARX(lbarx,DEF_MEMOP (MO_UB))3153 LARX(lbarx, DEF_MEMOP(MO_UB))
3154 LARX(lharx, DEF_MEMOP(MO_UW))
3155 LARX(lwarx, DEF_MEMOP(MO_UL))
3156
3157 static void gen_fetch_inc_conditional(DisasContext *ctx, TCGMemOp memop,
3158 TCGv EA, TCGCond cond, int addend)
3159 {
3160 TCGv t = tcg_temp_new();
3161 TCGv t2 = tcg_temp_new();
3162 TCGv u = tcg_temp_new();
3163
3164 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
3165 tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop));
3166 tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop);
3167 tcg_gen_addi_tl(u, t, addend);
3168
3169 /* E.g. for fetch and increment bounded... */
3170 /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */
3171 tcg_gen_movcond_tl(cond, u, t, t2, u, t);
3172 tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop);
3173
3174 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */
3175 tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1));
3176 tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u);
3177
3178 tcg_temp_free(t);
3179 tcg_temp_free(t2);
3180 tcg_temp_free(u);
3181 }
3182
gen_ld_atomic(DisasContext * ctx,TCGMemOp memop)3183 static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop)
3184 {
3185 uint32_t gpr_FC = FC(ctx->opcode);
3186 TCGv EA = tcg_temp_new();
3187 int rt = rD(ctx->opcode);
3188 bool need_serial;
3189 TCGv src, dst;
3190
3191 gen_addr_register(ctx, EA);
3192 dst = cpu_gpr[rt];
3193 src = cpu_gpr[(rt + 1) & 31];
3194
3195 need_serial = false;
3196 memop |= MO_ALIGN;
3197 switch (gpr_FC) {
3198 case 0: /* Fetch and add */
3199 tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop);
3200 break;
3201 case 1: /* Fetch and xor */
3202 tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop);
3203 break;
3204 case 2: /* Fetch and or */
3205 tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop);
3206 break;
3207 case 3: /* Fetch and 'and' */
3208 tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop);
3209 break;
3210 case 4: /* Fetch and max unsigned */
3211 tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop);
3212 break;
3213 case 5: /* Fetch and max signed */
3214 tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop);
3215 break;
3216 case 6: /* Fetch and min unsigned */
3217 tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop);
3218 break;
3219 case 7: /* Fetch and min signed */
3220 tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop);
3221 break;
3222 case 8: /* Swap */
3223 tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop);
3224 break;
3225
3226 case 16: /* Compare and swap not equal */
3227 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3228 need_serial = true;
3229 } else {
3230 TCGv t0 = tcg_temp_new();
3231 TCGv t1 = tcg_temp_new();
3232
3233 tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop);
3234 if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) {
3235 tcg_gen_mov_tl(t1, src);
3236 } else {
3237 tcg_gen_ext32u_tl(t1, src);
3238 }
3239 tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1,
3240 cpu_gpr[(rt + 2) & 31], t0);
3241 tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop);
3242 tcg_gen_mov_tl(dst, t0);
3243
3244 tcg_temp_free(t0);
3245 tcg_temp_free(t1);
3246 }
3247 break;
3248
3249 case 24: /* Fetch and increment bounded */
3250 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3251 need_serial = true;
3252 } else {
3253 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1);
3254 }
3255 break;
3256 case 25: /* Fetch and increment equal */
3257 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3258 need_serial = true;
3259 } else {
3260 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1);
3261 }
3262 break;
3263 case 28: /* Fetch and decrement bounded */
3264 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3265 need_serial = true;
3266 } else {
3267 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1);
3268 }
3269 break;
3270
3271 default:
3272 /* invoke data storage error handler */
3273 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
3274 }
3275 tcg_temp_free(EA);
3276
3277 if (need_serial) {
3278 /* Restart with exclusive lock. */
3279 gen_helper_exit_atomic(cpu_env);
3280 ctx->base.is_jmp = DISAS_NORETURN;
3281 }
3282 }
3283
gen_lwat(DisasContext * ctx)3284 static void gen_lwat(DisasContext *ctx)
3285 {
3286 gen_ld_atomic(ctx, DEF_MEMOP(MO_UL));
3287 }
3288
3289 #ifdef TARGET_PPC64
gen_ldat(DisasContext * ctx)3290 static void gen_ldat(DisasContext *ctx)
3291 {
3292 gen_ld_atomic(ctx, DEF_MEMOP(MO_Q));
3293 }
3294 #endif
3295
gen_st_atomic(DisasContext * ctx,TCGMemOp memop)3296 static void gen_st_atomic(DisasContext *ctx, TCGMemOp memop)
3297 {
3298 uint32_t gpr_FC = FC(ctx->opcode);
3299 TCGv EA = tcg_temp_new();
3300 TCGv src, discard;
3301
3302 gen_addr_register(ctx, EA);
3303 src = cpu_gpr[rD(ctx->opcode)];
3304 discard = tcg_temp_new();
3305
3306 memop |= MO_ALIGN;
3307 switch (gpr_FC) {
3308 case 0: /* add and Store */
3309 tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3310 break;
3311 case 1: /* xor and Store */
3312 tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3313 break;
3314 case 2: /* Or and Store */
3315 tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3316 break;
3317 case 3: /* 'and' and Store */
3318 tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3319 break;
3320 case 4: /* Store max unsigned */
3321 tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3322 break;
3323 case 5: /* Store max signed */
3324 tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3325 break;
3326 case 6: /* Store min unsigned */
3327 tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3328 break;
3329 case 7: /* Store min signed */
3330 tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3331 break;
3332 case 24: /* Store twin */
3333 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3334 /* Restart with exclusive lock. */
3335 gen_helper_exit_atomic(cpu_env);
3336 ctx->base.is_jmp = DISAS_NORETURN;
3337 } else {
3338 TCGv t = tcg_temp_new();
3339 TCGv t2 = tcg_temp_new();
3340 TCGv s = tcg_temp_new();
3341 TCGv s2 = tcg_temp_new();
3342 TCGv ea_plus_s = tcg_temp_new();
3343
3344 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
3345 tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop));
3346 tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop);
3347 tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t);
3348 tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2);
3349 tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop);
3350 tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop);
3351
3352 tcg_temp_free(ea_plus_s);
3353 tcg_temp_free(s2);
3354 tcg_temp_free(s);
3355 tcg_temp_free(t2);
3356 tcg_temp_free(t);
3357 }
3358 break;
3359 default:
3360 /* invoke data storage error handler */
3361 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
3362 }
3363 tcg_temp_free(discard);
3364 tcg_temp_free(EA);
3365 }
3366
gen_stwat(DisasContext * ctx)3367 static void gen_stwat(DisasContext *ctx)
3368 {
3369 gen_st_atomic(ctx, DEF_MEMOP(MO_UL));
3370 }
3371
3372 #ifdef TARGET_PPC64
gen_stdat(DisasContext * ctx)3373 static void gen_stdat(DisasContext *ctx)
3374 {
3375 gen_st_atomic(ctx, DEF_MEMOP(MO_Q));
3376 }
3377 #endif
3378
gen_conditional_store(DisasContext * ctx,TCGMemOp memop)3379 static void gen_conditional_store(DisasContext *ctx, TCGMemOp memop)
3380 {
3381 TCGLabel *l1 = gen_new_label();
3382 TCGLabel *l2 = gen_new_label();
3383 TCGv t0 = tcg_temp_new();
3384 int reg = rS(ctx->opcode);
3385
3386 gen_set_access_type(ctx, ACCESS_RES);
3387 gen_addr_reg_index(ctx, t0);
3388 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3389 tcg_temp_free(t0);
3390
3391 t0 = tcg_temp_new();
3392 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
3393 cpu_gpr[reg], ctx->mem_idx,
3394 DEF_MEMOP(memop) | MO_ALIGN);
3395 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val);
3396 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
3397 tcg_gen_or_tl(t0, t0, cpu_so);
3398 tcg_gen_trunc_tl_i32(cpu_crf[0], t0);
3399 tcg_temp_free(t0);
3400 tcg_gen_br(l2);
3401
3402 gen_set_label(l1);
3403
3404 /* Address mismatch implies failure. But we still need to provide the
3405 memory barrier semantics of the instruction. */
3406 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
3407 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3408
3409 gen_set_label(l2);
3410 tcg_gen_movi_tl(cpu_reserve, -1);
3411 }
3412
3413 #define STCX(name, memop) \
3414 static void gen_##name(DisasContext *ctx) \
3415 { \
3416 gen_conditional_store(ctx, memop); \
3417 }
3418
STCX(stbcx_,DEF_MEMOP (MO_UB))3419 STCX(stbcx_, DEF_MEMOP(MO_UB))
3420 STCX(sthcx_, DEF_MEMOP(MO_UW))
3421 STCX(stwcx_, DEF_MEMOP(MO_UL))
3422
3423 #if defined(TARGET_PPC64)
3424 /* ldarx */
3425 LARX(ldarx, DEF_MEMOP(MO_Q))
3426 /* stdcx. */
3427 STCX(stdcx_, DEF_MEMOP(MO_Q))
3428
3429 /* lqarx */
3430 static void gen_lqarx(DisasContext *ctx)
3431 {
3432 int rd = rD(ctx->opcode);
3433 TCGv EA, hi, lo;
3434
3435 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3436 (rd == rB(ctx->opcode)))) {
3437 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3438 return;
3439 }
3440
3441 gen_set_access_type(ctx, ACCESS_RES);
3442 EA = tcg_temp_new();
3443 gen_addr_reg_index(ctx, EA);
3444
3445 /* Note that the low part is always in RD+1, even in LE mode. */
3446 lo = cpu_gpr[rd + 1];
3447 hi = cpu_gpr[rd];
3448
3449 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3450 #ifdef CONFIG_ATOMIC128
3451 TCGv_i32 oi = tcg_temp_new_i32();
3452 if (ctx->le_mode) {
3453 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16,
3454 ctx->mem_idx));
3455 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi);
3456 } else {
3457 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16,
3458 ctx->mem_idx));
3459 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
3460 }
3461 tcg_temp_free_i32(oi);
3462 tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));
3463 #else
3464 /* Restart with exclusive lock. */
3465 gen_helper_exit_atomic(cpu_env);
3466 ctx->base.is_jmp = DISAS_NORETURN;
3467 tcg_temp_free(EA);
3468 return;
3469 #endif
3470 } else if (ctx->le_mode) {
3471 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16);
3472 tcg_gen_mov_tl(cpu_reserve, EA);
3473 gen_addr_add(ctx, EA, EA, 8);
3474 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ);
3475 } else {
3476 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16);
3477 tcg_gen_mov_tl(cpu_reserve, EA);
3478 gen_addr_add(ctx, EA, EA, 8);
3479 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ);
3480 }
3481 tcg_temp_free(EA);
3482
3483 tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val));
3484 tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2));
3485 }
3486
3487 /* stqcx. */
gen_stqcx_(DisasContext * ctx)3488 static void gen_stqcx_(DisasContext *ctx)
3489 {
3490 int rs = rS(ctx->opcode);
3491 TCGv EA, hi, lo;
3492
3493 if (unlikely(rs & 1)) {
3494 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3495 return;
3496 }
3497
3498 gen_set_access_type(ctx, ACCESS_RES);
3499 EA = tcg_temp_new();
3500 gen_addr_reg_index(ctx, EA);
3501
3502 /* Note that the low part is always in RS+1, even in LE mode. */
3503 lo = cpu_gpr[rs + 1];
3504 hi = cpu_gpr[rs];
3505
3506 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3507 TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16);
3508 #ifdef CONFIG_ATOMIC128
3509 if (ctx->le_mode) {
3510 gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, EA, lo, hi, oi);
3511 } else {
3512 gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, EA, lo, hi, oi);
3513 }
3514 #else
3515 /* Restart with exclusive lock. */
3516 gen_helper_exit_atomic(cpu_env);
3517 ctx->base.is_jmp = DISAS_NORETURN;
3518 #endif
3519 tcg_temp_free(EA);
3520 tcg_temp_free_i32(oi);
3521 } else {
3522 TCGLabel *lab_fail = gen_new_label();
3523 TCGLabel *lab_over = gen_new_label();
3524 TCGv_i64 t0 = tcg_temp_new_i64();
3525 TCGv_i64 t1 = tcg_temp_new_i64();
3526
3527 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail);
3528 tcg_temp_free(EA);
3529
3530 gen_qemu_ld64_i64(ctx, t0, cpu_reserve);
3531 tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode
3532 ? offsetof(CPUPPCState, reserve_val2)
3533 : offsetof(CPUPPCState, reserve_val)));
3534 tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail);
3535
3536 tcg_gen_addi_i64(t0, cpu_reserve, 8);
3537 gen_qemu_ld64_i64(ctx, t0, t0);
3538 tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode
3539 ? offsetof(CPUPPCState, reserve_val)
3540 : offsetof(CPUPPCState, reserve_val2)));
3541 tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail);
3542
3543 /* Success */
3544 gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve);
3545 tcg_gen_addi_i64(t0, cpu_reserve, 8);
3546 gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0);
3547
3548 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3549 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
3550 tcg_gen_br(lab_over);
3551
3552 gen_set_label(lab_fail);
3553 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3554
3555 gen_set_label(lab_over);
3556 tcg_gen_movi_tl(cpu_reserve, -1);
3557 tcg_temp_free_i64(t0);
3558 tcg_temp_free_i64(t1);
3559 }
3560 }
3561 #endif /* defined(TARGET_PPC64) */
3562
3563 /* sync */
gen_sync(DisasContext * ctx)3564 static void gen_sync(DisasContext *ctx)
3565 {
3566 uint32_t l = (ctx->opcode >> 21) & 3;
3567
3568 /*
3569 * We may need to check for a pending TLB flush.
3570 *
3571 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3572 *
3573 * Additionally, this can only happen in kernel mode however so
3574 * check MSR_PR as well.
3575 */
3576 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3577 gen_check_tlb_flush(ctx, true);
3578 }
3579 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
3580 }
3581
3582 /* wait */
gen_wait(DisasContext * ctx)3583 static void gen_wait(DisasContext *ctx)
3584 {
3585 TCGv_i32 t0 = tcg_const_i32(1);
3586 tcg_gen_st_i32(t0, cpu_env,
3587 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3588 tcg_temp_free_i32(t0);
3589 /* Stop translation, as the CPU is supposed to sleep from now */
3590 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3591 }
3592
3593 #if defined(TARGET_PPC64)
gen_doze(DisasContext * ctx)3594 static void gen_doze(DisasContext *ctx)
3595 {
3596 #if defined(CONFIG_USER_ONLY)
3597 GEN_PRIV;
3598 #else
3599 TCGv_i32 t;
3600
3601 CHK_HV;
3602 t = tcg_const_i32(PPC_PM_DOZE);
3603 gen_helper_pminsn(cpu_env, t);
3604 tcg_temp_free_i32(t);
3605 /* Stop translation, as the CPU is supposed to sleep from now */
3606 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3607 #endif /* defined(CONFIG_USER_ONLY) */
3608 }
3609
gen_nap(DisasContext * ctx)3610 static void gen_nap(DisasContext *ctx)
3611 {
3612 #if defined(CONFIG_USER_ONLY)
3613 GEN_PRIV;
3614 #else
3615 TCGv_i32 t;
3616
3617 CHK_HV;
3618 t = tcg_const_i32(PPC_PM_NAP);
3619 gen_helper_pminsn(cpu_env, t);
3620 tcg_temp_free_i32(t);
3621 /* Stop translation, as the CPU is supposed to sleep from now */
3622 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3623 #endif /* defined(CONFIG_USER_ONLY) */
3624 }
3625
gen_stop(DisasContext * ctx)3626 static void gen_stop(DisasContext *ctx)
3627 {
3628 #if defined(CONFIG_USER_ONLY)
3629 GEN_PRIV;
3630 #else
3631 TCGv_i32 t;
3632
3633 CHK_HV;
3634 t = tcg_const_i32(PPC_PM_STOP);
3635 gen_helper_pminsn(cpu_env, t);
3636 tcg_temp_free_i32(t);
3637 /* Stop translation, as the CPU is supposed to sleep from now */
3638 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3639 #endif /* defined(CONFIG_USER_ONLY) */
3640 }
3641
gen_sleep(DisasContext * ctx)3642 static void gen_sleep(DisasContext *ctx)
3643 {
3644 #if defined(CONFIG_USER_ONLY)
3645 GEN_PRIV;
3646 #else
3647 TCGv_i32 t;
3648
3649 CHK_HV;
3650 t = tcg_const_i32(PPC_PM_SLEEP);
3651 gen_helper_pminsn(cpu_env, t);
3652 tcg_temp_free_i32(t);
3653 /* Stop translation, as the CPU is supposed to sleep from now */
3654 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3655 #endif /* defined(CONFIG_USER_ONLY) */
3656 }
3657
gen_rvwinkle(DisasContext * ctx)3658 static void gen_rvwinkle(DisasContext *ctx)
3659 {
3660 #if defined(CONFIG_USER_ONLY)
3661 GEN_PRIV;
3662 #else
3663 TCGv_i32 t;
3664
3665 CHK_HV;
3666 t = tcg_const_i32(PPC_PM_RVWINKLE);
3667 gen_helper_pminsn(cpu_env, t);
3668 tcg_temp_free_i32(t);
3669 /* Stop translation, as the CPU is supposed to sleep from now */
3670 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3671 #endif /* defined(CONFIG_USER_ONLY) */
3672 }
3673 #endif /* #if defined(TARGET_PPC64) */
3674
gen_update_cfar(DisasContext * ctx,target_ulong nip)3675 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3676 {
3677 #if defined(TARGET_PPC64)
3678 if (ctx->has_cfar)
3679 tcg_gen_movi_tl(cpu_cfar, nip);
3680 #endif
3681 }
3682
use_goto_tb(DisasContext * ctx,target_ulong dest)3683 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3684 {
3685 if (unlikely(ctx->singlestep_enabled)) {
3686 return false;
3687 }
3688
3689 #ifndef CONFIG_USER_ONLY
3690 return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3691 #else
3692 return true;
3693 #endif
3694 }
3695
gen_lookup_and_goto_ptr(DisasContext * ctx)3696 static void gen_lookup_and_goto_ptr(DisasContext *ctx)
3697 {
3698 int sse = ctx->singlestep_enabled;
3699 if (unlikely(sse)) {
3700 if (sse & GDBSTUB_SINGLE_STEP) {
3701 gen_debug_exception(ctx);
3702 } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) {
3703 uint32_t excp = gen_prep_dbgex(ctx, POWERPC_EXCP_BRANCH);
3704 if (excp != POWERPC_EXCP_NONE) {
3705 gen_exception(ctx, excp);
3706 }
3707 }
3708 tcg_gen_exit_tb(NULL, 0);
3709 } else {
3710 tcg_gen_lookup_and_goto_ptr();
3711 }
3712 }
3713
3714 /*** Branch ***/
gen_goto_tb(DisasContext * ctx,int n,target_ulong dest)3715 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3716 {
3717 if (NARROW_MODE(ctx)) {
3718 dest = (uint32_t) dest;
3719 }
3720 if (use_goto_tb(ctx, dest)) {
3721 tcg_gen_goto_tb(n);
3722 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3723 tcg_gen_exit_tb(ctx->base.tb, n);
3724 } else {
3725 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3726 gen_lookup_and_goto_ptr(ctx);
3727 }
3728 }
3729
gen_setlr(DisasContext * ctx,target_ulong nip)3730 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3731 {
3732 if (NARROW_MODE(ctx)) {
3733 nip = (uint32_t)nip;
3734 }
3735 tcg_gen_movi_tl(cpu_lr, nip);
3736 }
3737
3738 /* b ba bl bla */
gen_b(DisasContext * ctx)3739 static void gen_b(DisasContext *ctx)
3740 {
3741 target_ulong li, target;
3742
3743 ctx->exception = POWERPC_EXCP_BRANCH;
3744 /* sign extend LI */
3745 li = LI(ctx->opcode);
3746 li = (li ^ 0x02000000) - 0x02000000;
3747 if (likely(AA(ctx->opcode) == 0)) {
3748 target = ctx->base.pc_next + li - 4;
3749 } else {
3750 target = li;
3751 }
3752 if (LK(ctx->opcode)) {
3753 gen_setlr(ctx, ctx->base.pc_next);
3754 }
3755 gen_update_cfar(ctx, ctx->base.pc_next - 4);
3756 gen_goto_tb(ctx, 0, target);
3757 }
3758
3759 #define BCOND_IM 0
3760 #define BCOND_LR 1
3761 #define BCOND_CTR 2
3762 #define BCOND_TAR 3
3763
gen_bcond(DisasContext * ctx,int type)3764 static void gen_bcond(DisasContext *ctx, int type)
3765 {
3766 uint32_t bo = BO(ctx->opcode);
3767 TCGLabel *l1;
3768 TCGv target;
3769 ctx->exception = POWERPC_EXCP_BRANCH;
3770
3771 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3772 target = tcg_temp_local_new();
3773 if (type == BCOND_CTR)
3774 tcg_gen_mov_tl(target, cpu_ctr);
3775 else if (type == BCOND_TAR)
3776 gen_load_spr(target, SPR_TAR);
3777 else
3778 tcg_gen_mov_tl(target, cpu_lr);
3779 } else {
3780 target = NULL;
3781 }
3782 if (LK(ctx->opcode))
3783 gen_setlr(ctx, ctx->base.pc_next);
3784 l1 = gen_new_label();
3785 if ((bo & 0x4) == 0) {
3786 /* Decrement and test CTR */
3787 TCGv temp = tcg_temp_new();
3788 if (unlikely(type == BCOND_CTR)) {
3789 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3790 return;
3791 }
3792 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3793 if (NARROW_MODE(ctx)) {
3794 tcg_gen_ext32u_tl(temp, cpu_ctr);
3795 } else {
3796 tcg_gen_mov_tl(temp, cpu_ctr);
3797 }
3798 if (bo & 0x2) {
3799 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3800 } else {
3801 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3802 }
3803 tcg_temp_free(temp);
3804 }
3805 if ((bo & 0x10) == 0) {
3806 /* Test CR */
3807 uint32_t bi = BI(ctx->opcode);
3808 uint32_t mask = 0x08 >> (bi & 0x03);
3809 TCGv_i32 temp = tcg_temp_new_i32();
3810
3811 if (bo & 0x8) {
3812 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3813 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3814 } else {
3815 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3816 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3817 }
3818 tcg_temp_free_i32(temp);
3819 }
3820 gen_update_cfar(ctx, ctx->base.pc_next - 4);
3821 if (type == BCOND_IM) {
3822 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3823 if (likely(AA(ctx->opcode) == 0)) {
3824 gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4);
3825 } else {
3826 gen_goto_tb(ctx, 0, li);
3827 }
3828 } else {
3829 if (NARROW_MODE(ctx)) {
3830 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3831 } else {
3832 tcg_gen_andi_tl(cpu_nip, target, ~3);
3833 }
3834 gen_lookup_and_goto_ptr(ctx);
3835 tcg_temp_free(target);
3836 }
3837 if ((bo & 0x14) != 0x14) {
3838 /* fallthrough case */
3839 gen_set_label(l1);
3840 gen_goto_tb(ctx, 1, ctx->base.pc_next);
3841 }
3842 }
3843
gen_bc(DisasContext * ctx)3844 static void gen_bc(DisasContext *ctx)
3845 {
3846 gen_bcond(ctx, BCOND_IM);
3847 }
3848
gen_bcctr(DisasContext * ctx)3849 static void gen_bcctr(DisasContext *ctx)
3850 {
3851 gen_bcond(ctx, BCOND_CTR);
3852 }
3853
gen_bclr(DisasContext * ctx)3854 static void gen_bclr(DisasContext *ctx)
3855 {
3856 gen_bcond(ctx, BCOND_LR);
3857 }
3858
gen_bctar(DisasContext * ctx)3859 static void gen_bctar(DisasContext *ctx)
3860 {
3861 gen_bcond(ctx, BCOND_TAR);
3862 }
3863
3864 /*** Condition register logical ***/
3865 #define GEN_CRLOGIC(name, tcg_op, opc) \
3866 static void glue(gen_, name)(DisasContext *ctx) \
3867 { \
3868 uint8_t bitmask; \
3869 int sh; \
3870 TCGv_i32 t0, t1; \
3871 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3872 t0 = tcg_temp_new_i32(); \
3873 if (sh > 0) \
3874 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3875 else if (sh < 0) \
3876 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3877 else \
3878 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3879 t1 = tcg_temp_new_i32(); \
3880 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3881 if (sh > 0) \
3882 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3883 else if (sh < 0) \
3884 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3885 else \
3886 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3887 tcg_op(t0, t0, t1); \
3888 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3889 tcg_gen_andi_i32(t0, t0, bitmask); \
3890 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3891 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3892 tcg_temp_free_i32(t0); \
3893 tcg_temp_free_i32(t1); \
3894 }
3895
3896 /* crand */
3897 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3898 /* crandc */
3899 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3900 /* creqv */
3901 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3902 /* crnand */
3903 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3904 /* crnor */
3905 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3906 /* cror */
3907 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3908 /* crorc */
3909 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3910 /* crxor */
3911 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3912
3913 /* mcrf */
gen_mcrf(DisasContext * ctx)3914 static void gen_mcrf(DisasContext *ctx)
3915 {
3916 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3917 }
3918
3919 /*** System linkage ***/
3920
3921 /* rfi (supervisor only) */
gen_rfi(DisasContext * ctx)3922 static void gen_rfi(DisasContext *ctx)
3923 {
3924 #if defined(CONFIG_USER_ONLY)
3925 GEN_PRIV;
3926 #else
3927 /* This instruction doesn't exist anymore on 64-bit server
3928 * processors compliant with arch 2.x
3929 */
3930 if (ctx->insns_flags & PPC_SEGMENT_64B) {
3931 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3932 return;
3933 }
3934 /* Restore CPU state */
3935 CHK_SV;
3936 gen_update_cfar(ctx, ctx->base.pc_next - 4);
3937 gen_helper_rfi(cpu_env);
3938 gen_sync_exception(ctx);
3939 #endif
3940 }
3941
3942 #if defined(TARGET_PPC64)
gen_rfid(DisasContext * ctx)3943 static void gen_rfid(DisasContext *ctx)
3944 {
3945 #if defined(CONFIG_USER_ONLY)
3946 GEN_PRIV;
3947 #else
3948 /* Restore CPU state */
3949 CHK_SV;
3950 gen_update_cfar(ctx, ctx->base.pc_next - 4);
3951 gen_helper_rfid(cpu_env);
3952 gen_sync_exception(ctx);
3953 #endif
3954 }
3955
gen_hrfid(DisasContext * ctx)3956 static void gen_hrfid(DisasContext *ctx)
3957 {
3958 #if defined(CONFIG_USER_ONLY)
3959 GEN_PRIV;
3960 #else
3961 /* Restore CPU state */
3962 CHK_HV;
3963 gen_helper_hrfid(cpu_env);
3964 gen_sync_exception(ctx);
3965 #endif
3966 }
3967 #endif
3968
3969 /* sc */
3970 #if defined(CONFIG_USER_ONLY)
3971 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3972 #else
3973 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3974 #endif
gen_sc(DisasContext * ctx)3975 static void gen_sc(DisasContext *ctx)
3976 {
3977 uint32_t lev;
3978
3979 lev = (ctx->opcode >> 5) & 0x7F;
3980 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3981 }
3982
3983 /*** Trap ***/
3984
3985 /* Check for unconditional traps (always or never) */
check_unconditional_trap(DisasContext * ctx)3986 static bool check_unconditional_trap(DisasContext *ctx)
3987 {
3988 /* Trap never */
3989 if (TO(ctx->opcode) == 0) {
3990 return true;
3991 }
3992 /* Trap always */
3993 if (TO(ctx->opcode) == 31) {
3994 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
3995 return true;
3996 }
3997 return false;
3998 }
3999
4000 /* tw */
gen_tw(DisasContext * ctx)4001 static void gen_tw(DisasContext *ctx)
4002 {
4003 TCGv_i32 t0;
4004
4005 if (check_unconditional_trap(ctx)) {
4006 return;
4007 }
4008 t0 = tcg_const_i32(TO(ctx->opcode));
4009 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4010 t0);
4011 tcg_temp_free_i32(t0);
4012 }
4013
4014 /* twi */
gen_twi(DisasContext * ctx)4015 static void gen_twi(DisasContext *ctx)
4016 {
4017 TCGv t0;
4018 TCGv_i32 t1;
4019
4020 if (check_unconditional_trap(ctx)) {
4021 return;
4022 }
4023 t0 = tcg_const_tl(SIMM(ctx->opcode));
4024 t1 = tcg_const_i32(TO(ctx->opcode));
4025 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4026 tcg_temp_free(t0);
4027 tcg_temp_free_i32(t1);
4028 }
4029
4030 #if defined(TARGET_PPC64)
4031 /* td */
gen_td(DisasContext * ctx)4032 static void gen_td(DisasContext *ctx)
4033 {
4034 TCGv_i32 t0;
4035
4036 if (check_unconditional_trap(ctx)) {
4037 return;
4038 }
4039 t0 = tcg_const_i32(TO(ctx->opcode));
4040 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4041 t0);
4042 tcg_temp_free_i32(t0);
4043 }
4044
4045 /* tdi */
gen_tdi(DisasContext * ctx)4046 static void gen_tdi(DisasContext *ctx)
4047 {
4048 TCGv t0;
4049 TCGv_i32 t1;
4050
4051 if (check_unconditional_trap(ctx)) {
4052 return;
4053 }
4054 t0 = tcg_const_tl(SIMM(ctx->opcode));
4055 t1 = tcg_const_i32(TO(ctx->opcode));
4056 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4057 tcg_temp_free(t0);
4058 tcg_temp_free_i32(t1);
4059 }
4060 #endif
4061
4062 /*** Processor control ***/
4063
gen_read_xer(DisasContext * ctx,TCGv dst)4064 static void gen_read_xer(DisasContext *ctx, TCGv dst)
4065 {
4066 TCGv t0 = tcg_temp_new();
4067 TCGv t1 = tcg_temp_new();
4068 TCGv t2 = tcg_temp_new();
4069 tcg_gen_mov_tl(dst, cpu_xer);
4070 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4071 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4072 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4073 tcg_gen_or_tl(t0, t0, t1);
4074 tcg_gen_or_tl(dst, dst, t2);
4075 tcg_gen_or_tl(dst, dst, t0);
4076 if (is_isa300(ctx)) {
4077 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
4078 tcg_gen_or_tl(dst, dst, t0);
4079 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
4080 tcg_gen_or_tl(dst, dst, t0);
4081 }
4082 tcg_temp_free(t0);
4083 tcg_temp_free(t1);
4084 tcg_temp_free(t2);
4085 }
4086
gen_write_xer(TCGv src)4087 static void gen_write_xer(TCGv src)
4088 {
4089 /* Write all flags, while reading back check for isa300 */
4090 tcg_gen_andi_tl(cpu_xer, src,
4091 ~((1u << XER_SO) |
4092 (1u << XER_OV) | (1u << XER_OV32) |
4093 (1u << XER_CA) | (1u << XER_CA32)));
4094 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
4095 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
4096 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
4097 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
4098 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
4099 }
4100
4101 /* mcrxr */
gen_mcrxr(DisasContext * ctx)4102 static void gen_mcrxr(DisasContext *ctx)
4103 {
4104 TCGv_i32 t0 = tcg_temp_new_i32();
4105 TCGv_i32 t1 = tcg_temp_new_i32();
4106 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4107
4108 tcg_gen_trunc_tl_i32(t0, cpu_so);
4109 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4110 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4111 tcg_gen_shli_i32(t0, t0, 3);
4112 tcg_gen_shli_i32(t1, t1, 2);
4113 tcg_gen_shli_i32(dst, dst, 1);
4114 tcg_gen_or_i32(dst, dst, t0);
4115 tcg_gen_or_i32(dst, dst, t1);
4116 tcg_temp_free_i32(t0);
4117 tcg_temp_free_i32(t1);
4118
4119 tcg_gen_movi_tl(cpu_so, 0);
4120 tcg_gen_movi_tl(cpu_ov, 0);
4121 tcg_gen_movi_tl(cpu_ca, 0);
4122 }
4123
4124 #ifdef TARGET_PPC64
4125 /* mcrxrx */
gen_mcrxrx(DisasContext * ctx)4126 static void gen_mcrxrx(DisasContext *ctx)
4127 {
4128 TCGv t0 = tcg_temp_new();
4129 TCGv t1 = tcg_temp_new();
4130 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4131
4132 /* copy OV and OV32 */
4133 tcg_gen_shli_tl(t0, cpu_ov, 1);
4134 tcg_gen_or_tl(t0, t0, cpu_ov32);
4135 tcg_gen_shli_tl(t0, t0, 2);
4136 /* copy CA and CA32 */
4137 tcg_gen_shli_tl(t1, cpu_ca, 1);
4138 tcg_gen_or_tl(t1, t1, cpu_ca32);
4139 tcg_gen_or_tl(t0, t0, t1);
4140 tcg_gen_trunc_tl_i32(dst, t0);
4141 tcg_temp_free(t0);
4142 tcg_temp_free(t1);
4143 }
4144 #endif
4145
4146 /* mfcr mfocrf */
gen_mfcr(DisasContext * ctx)4147 static void gen_mfcr(DisasContext *ctx)
4148 {
4149 uint32_t crm, crn;
4150
4151 if (likely(ctx->opcode & 0x00100000)) {
4152 crm = CRM(ctx->opcode);
4153 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4154 crn = ctz32 (crm);
4155 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4156 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4157 cpu_gpr[rD(ctx->opcode)], crn * 4);
4158 }
4159 } else {
4160 TCGv_i32 t0 = tcg_temp_new_i32();
4161 tcg_gen_mov_i32(t0, cpu_crf[0]);
4162 tcg_gen_shli_i32(t0, t0, 4);
4163 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4164 tcg_gen_shli_i32(t0, t0, 4);
4165 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4166 tcg_gen_shli_i32(t0, t0, 4);
4167 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4168 tcg_gen_shli_i32(t0, t0, 4);
4169 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4170 tcg_gen_shli_i32(t0, t0, 4);
4171 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4172 tcg_gen_shli_i32(t0, t0, 4);
4173 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4174 tcg_gen_shli_i32(t0, t0, 4);
4175 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4176 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4177 tcg_temp_free_i32(t0);
4178 }
4179 }
4180
4181 /* mfmsr */
gen_mfmsr(DisasContext * ctx)4182 static void gen_mfmsr(DisasContext *ctx)
4183 {
4184 CHK_SV;
4185 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4186 }
4187
spr_noaccess(DisasContext * ctx,int gprn,int sprn)4188 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
4189 {
4190 #if 0
4191 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4192 printf("ERROR: try to access SPR %d !\n", sprn);
4193 #endif
4194 }
4195 #define SPR_NOACCESS (&spr_noaccess)
4196
4197 /* mfspr */
gen_op_mfspr(DisasContext * ctx)4198 static inline void gen_op_mfspr(DisasContext *ctx)
4199 {
4200 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
4201 uint32_t sprn = SPR(ctx->opcode);
4202
4203 #if defined(CONFIG_USER_ONLY)
4204 read_cb = ctx->spr_cb[sprn].uea_read;
4205 #else
4206 if (ctx->pr) {
4207 read_cb = ctx->spr_cb[sprn].uea_read;
4208 } else if (ctx->hv) {
4209 read_cb = ctx->spr_cb[sprn].hea_read;
4210 } else {
4211 read_cb = ctx->spr_cb[sprn].oea_read;
4212 }
4213 #endif
4214 if (likely(read_cb != NULL)) {
4215 if (likely(read_cb != SPR_NOACCESS)) {
4216 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4217 } else {
4218 /* Privilege exception */
4219 /* This is a hack to avoid warnings when running Linux:
4220 * this OS breaks the PowerPC virtualisation model,
4221 * allowing userland application to read the PVR
4222 */
4223 if (sprn != SPR_PVR) {
4224 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr "
4225 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
4226 ctx->base.pc_next - 4);
4227 }
4228 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4229 }
4230 } else {
4231 /* ISA 2.07 defines these as no-ops */
4232 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4233 (sprn >= 808 && sprn <= 811)) {
4234 /* This is a nop */
4235 return;
4236 }
4237 /* Not defined */
4238 qemu_log_mask(LOG_GUEST_ERROR,
4239 "Trying to read invalid spr %d (0x%03x) at "
4240 TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4);
4241
4242 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4243 * it can generate a priv, a hv emu or a no-op
4244 */
4245 if (sprn & 0x10) {
4246 if (ctx->pr) {
4247 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4248 }
4249 } else {
4250 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
4251 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4252 }
4253 }
4254 }
4255 }
4256
gen_mfspr(DisasContext * ctx)4257 static void gen_mfspr(DisasContext *ctx)
4258 {
4259 gen_op_mfspr(ctx);
4260 }
4261
4262 /* mftb */
gen_mftb(DisasContext * ctx)4263 static void gen_mftb(DisasContext *ctx)
4264 {
4265 gen_op_mfspr(ctx);
4266 }
4267
4268 /* mtcrf mtocrf*/
gen_mtcrf(DisasContext * ctx)4269 static void gen_mtcrf(DisasContext *ctx)
4270 {
4271 uint32_t crm, crn;
4272
4273 crm = CRM(ctx->opcode);
4274 if (likely((ctx->opcode & 0x00100000))) {
4275 if (crm && ((crm & (crm - 1)) == 0)) {
4276 TCGv_i32 temp = tcg_temp_new_i32();
4277 crn = ctz32 (crm);
4278 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4279 tcg_gen_shri_i32(temp, temp, crn * 4);
4280 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4281 tcg_temp_free_i32(temp);
4282 }
4283 } else {
4284 TCGv_i32 temp = tcg_temp_new_i32();
4285 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4286 for (crn = 0 ; crn < 8 ; crn++) {
4287 if (crm & (1 << crn)) {
4288 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4289 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4290 }
4291 }
4292 tcg_temp_free_i32(temp);
4293 }
4294 }
4295
4296 /* mtmsr */
4297 #if defined(TARGET_PPC64)
gen_mtmsrd(DisasContext * ctx)4298 static void gen_mtmsrd(DisasContext *ctx)
4299 {
4300 CHK_SV;
4301
4302 #if !defined(CONFIG_USER_ONLY)
4303 if (ctx->opcode & 0x00010000) {
4304 /* Special form that does not need any synchronisation */
4305 TCGv t0 = tcg_temp_new();
4306 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4307 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4308 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4309 tcg_temp_free(t0);
4310 } else {
4311 /* XXX: we need to update nip before the store
4312 * if we enter power saving mode, we will exit the loop
4313 * directly from ppc_store_msr
4314 */
4315 gen_update_nip(ctx, ctx->base.pc_next);
4316 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4317 /* Must stop the translation as machine state (may have) changed */
4318 /* Note that mtmsr is not always defined as context-synchronizing */
4319 gen_stop_exception(ctx);
4320 }
4321 #endif /* !defined(CONFIG_USER_ONLY) */
4322 }
4323 #endif /* defined(TARGET_PPC64) */
4324
gen_mtmsr(DisasContext * ctx)4325 static void gen_mtmsr(DisasContext *ctx)
4326 {
4327 CHK_SV;
4328
4329 #if !defined(CONFIG_USER_ONLY)
4330 if (ctx->opcode & 0x00010000) {
4331 /* Special form that does not need any synchronisation */
4332 TCGv t0 = tcg_temp_new();
4333 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4334 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4335 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4336 tcg_temp_free(t0);
4337 } else {
4338 TCGv msr = tcg_temp_new();
4339
4340 /* XXX: we need to update nip before the store
4341 * if we enter power saving mode, we will exit the loop
4342 * directly from ppc_store_msr
4343 */
4344 gen_update_nip(ctx, ctx->base.pc_next);
4345 #if defined(TARGET_PPC64)
4346 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4347 #else
4348 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4349 #endif
4350 gen_helper_store_msr(cpu_env, msr);
4351 tcg_temp_free(msr);
4352 /* Must stop the translation as machine state (may have) changed */
4353 /* Note that mtmsr is not always defined as context-synchronizing */
4354 gen_stop_exception(ctx);
4355 }
4356 #endif
4357 }
4358
4359 /* mtspr */
gen_mtspr(DisasContext * ctx)4360 static void gen_mtspr(DisasContext *ctx)
4361 {
4362 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4363 uint32_t sprn = SPR(ctx->opcode);
4364
4365 #if defined(CONFIG_USER_ONLY)
4366 write_cb = ctx->spr_cb[sprn].uea_write;
4367 #else
4368 if (ctx->pr) {
4369 write_cb = ctx->spr_cb[sprn].uea_write;
4370 } else if (ctx->hv) {
4371 write_cb = ctx->spr_cb[sprn].hea_write;
4372 } else {
4373 write_cb = ctx->spr_cb[sprn].oea_write;
4374 }
4375 #endif
4376 if (likely(write_cb != NULL)) {
4377 if (likely(write_cb != SPR_NOACCESS)) {
4378 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4379 } else {
4380 /* Privilege exception */
4381 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr "
4382 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
4383 ctx->base.pc_next - 4);
4384 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4385 }
4386 } else {
4387 /* ISA 2.07 defines these as no-ops */
4388 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4389 (sprn >= 808 && sprn <= 811)) {
4390 /* This is a nop */
4391 return;
4392 }
4393
4394 /* Not defined */
4395 qemu_log_mask(LOG_GUEST_ERROR,
4396 "Trying to write invalid spr %d (0x%03x) at "
4397 TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4);
4398
4399
4400 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4401 * it can generate a priv, a hv emu or a no-op
4402 */
4403 if (sprn & 0x10) {
4404 if (ctx->pr) {
4405 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4406 }
4407 } else {
4408 if (ctx->pr || sprn == 0) {
4409 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4410 }
4411 }
4412 }
4413 }
4414
4415 #if defined(TARGET_PPC64)
4416 /* setb */
gen_setb(DisasContext * ctx)4417 static void gen_setb(DisasContext *ctx)
4418 {
4419 TCGv_i32 t0 = tcg_temp_new_i32();
4420 TCGv_i32 t8 = tcg_temp_new_i32();
4421 TCGv_i32 tm1 = tcg_temp_new_i32();
4422 int crf = crfS(ctx->opcode);
4423
4424 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
4425 tcg_gen_movi_i32(t8, 8);
4426 tcg_gen_movi_i32(tm1, -1);
4427 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
4428 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4429
4430 tcg_temp_free_i32(t0);
4431 tcg_temp_free_i32(t8);
4432 tcg_temp_free_i32(tm1);
4433 }
4434 #endif
4435
4436 /*** Cache management ***/
4437
4438 /* dcbf */
gen_dcbf(DisasContext * ctx)4439 static void gen_dcbf(DisasContext *ctx)
4440 {
4441 /* XXX: specification says this is treated as a load by the MMU */
4442 TCGv t0;
4443 gen_set_access_type(ctx, ACCESS_CACHE);
4444 t0 = tcg_temp_new();
4445 gen_addr_reg_index(ctx, t0);
4446 gen_qemu_ld8u(ctx, t0, t0);
4447 tcg_temp_free(t0);
4448 }
4449
4450 /* dcbfep (external PID dcbf) */
gen_dcbfep(DisasContext * ctx)4451 static void gen_dcbfep(DisasContext *ctx)
4452 {
4453 /* XXX: specification says this is treated as a load by the MMU */
4454 TCGv t0;
4455 CHK_SV;
4456 gen_set_access_type(ctx, ACCESS_CACHE);
4457 t0 = tcg_temp_new();
4458 gen_addr_reg_index(ctx, t0);
4459 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB));
4460 tcg_temp_free(t0);
4461 }
4462
4463 /* dcbi (Supervisor only) */
gen_dcbi(DisasContext * ctx)4464 static void gen_dcbi(DisasContext *ctx)
4465 {
4466 #if defined(CONFIG_USER_ONLY)
4467 GEN_PRIV;
4468 #else
4469 TCGv EA, val;
4470
4471 CHK_SV;
4472 EA = tcg_temp_new();
4473 gen_set_access_type(ctx, ACCESS_CACHE);
4474 gen_addr_reg_index(ctx, EA);
4475 val = tcg_temp_new();
4476 /* XXX: specification says this should be treated as a store by the MMU */
4477 gen_qemu_ld8u(ctx, val, EA);
4478 gen_qemu_st8(ctx, val, EA);
4479 tcg_temp_free(val);
4480 tcg_temp_free(EA);
4481 #endif /* defined(CONFIG_USER_ONLY) */
4482 }
4483
4484 /* dcdst */
gen_dcbst(DisasContext * ctx)4485 static void gen_dcbst(DisasContext *ctx)
4486 {
4487 /* XXX: specification say this is treated as a load by the MMU */
4488 TCGv t0;
4489 gen_set_access_type(ctx, ACCESS_CACHE);
4490 t0 = tcg_temp_new();
4491 gen_addr_reg_index(ctx, t0);
4492 gen_qemu_ld8u(ctx, t0, t0);
4493 tcg_temp_free(t0);
4494 }
4495
4496 /* dcbstep (dcbstep External PID version) */
gen_dcbstep(DisasContext * ctx)4497 static void gen_dcbstep(DisasContext *ctx)
4498 {
4499 /* XXX: specification say this is treated as a load by the MMU */
4500 TCGv t0;
4501 gen_set_access_type(ctx, ACCESS_CACHE);
4502 t0 = tcg_temp_new();
4503 gen_addr_reg_index(ctx, t0);
4504 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB));
4505 tcg_temp_free(t0);
4506 }
4507
4508 /* dcbt */
gen_dcbt(DisasContext * ctx)4509 static void gen_dcbt(DisasContext *ctx)
4510 {
4511 /* interpreted as no-op */
4512 /* XXX: specification say this is treated as a load by the MMU
4513 * but does not generate any exception
4514 */
4515 }
4516
4517 /* dcbtep */
gen_dcbtep(DisasContext * ctx)4518 static void gen_dcbtep(DisasContext *ctx)
4519 {
4520 /* interpreted as no-op */
4521 /* XXX: specification say this is treated as a load by the MMU
4522 * but does not generate any exception
4523 */
4524 }
4525
4526 /* dcbtst */
gen_dcbtst(DisasContext * ctx)4527 static void gen_dcbtst(DisasContext *ctx)
4528 {
4529 /* interpreted as no-op */
4530 /* XXX: specification say this is treated as a load by the MMU
4531 * but does not generate any exception
4532 */
4533 }
4534
4535 /* dcbtstep */
gen_dcbtstep(DisasContext * ctx)4536 static void gen_dcbtstep(DisasContext *ctx)
4537 {
4538 /* interpreted as no-op */
4539 /* XXX: specification say this is treated as a load by the MMU
4540 * but does not generate any exception
4541 */
4542 }
4543
4544 /* dcbtls */
gen_dcbtls(DisasContext * ctx)4545 static void gen_dcbtls(DisasContext *ctx)
4546 {
4547 /* Always fails locking the cache */
4548 TCGv t0 = tcg_temp_new();
4549 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4550 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4551 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4552 tcg_temp_free(t0);
4553 }
4554
4555 /* dcbz */
gen_dcbz(DisasContext * ctx)4556 static void gen_dcbz(DisasContext *ctx)
4557 {
4558 TCGv tcgv_addr;
4559 TCGv_i32 tcgv_op;
4560
4561 gen_set_access_type(ctx, ACCESS_CACHE);
4562 tcgv_addr = tcg_temp_new();
4563 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
4564 gen_addr_reg_index(ctx, tcgv_addr);
4565 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
4566 tcg_temp_free(tcgv_addr);
4567 tcg_temp_free_i32(tcgv_op);
4568 }
4569
4570 /* dcbzep */
gen_dcbzep(DisasContext * ctx)4571 static void gen_dcbzep(DisasContext *ctx)
4572 {
4573 TCGv tcgv_addr;
4574 TCGv_i32 tcgv_op;
4575
4576 gen_set_access_type(ctx, ACCESS_CACHE);
4577 tcgv_addr = tcg_temp_new();
4578 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
4579 gen_addr_reg_index(ctx, tcgv_addr);
4580 gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op);
4581 tcg_temp_free(tcgv_addr);
4582 tcg_temp_free_i32(tcgv_op);
4583 }
4584
4585 /* dst / dstt */
gen_dst(DisasContext * ctx)4586 static void gen_dst(DisasContext *ctx)
4587 {
4588 if (rA(ctx->opcode) == 0) {
4589 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4590 } else {
4591 /* interpreted as no-op */
4592 }
4593 }
4594
4595 /* dstst /dststt */
gen_dstst(DisasContext * ctx)4596 static void gen_dstst(DisasContext *ctx)
4597 {
4598 if (rA(ctx->opcode) == 0) {
4599 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4600 } else {
4601 /* interpreted as no-op */
4602 }
4603
4604 }
4605
4606 /* dss / dssall */
gen_dss(DisasContext * ctx)4607 static void gen_dss(DisasContext *ctx)
4608 {
4609 /* interpreted as no-op */
4610 }
4611
4612 /* icbi */
gen_icbi(DisasContext * ctx)4613 static void gen_icbi(DisasContext *ctx)
4614 {
4615 TCGv t0;
4616 gen_set_access_type(ctx, ACCESS_CACHE);
4617 t0 = tcg_temp_new();
4618 gen_addr_reg_index(ctx, t0);
4619 gen_helper_icbi(cpu_env, t0);
4620 tcg_temp_free(t0);
4621 }
4622
4623 /* icbiep */
gen_icbiep(DisasContext * ctx)4624 static void gen_icbiep(DisasContext *ctx)
4625 {
4626 TCGv t0;
4627 gen_set_access_type(ctx, ACCESS_CACHE);
4628 t0 = tcg_temp_new();
4629 gen_addr_reg_index(ctx, t0);
4630 gen_helper_icbiep(cpu_env, t0);
4631 tcg_temp_free(t0);
4632 }
4633
4634 /* Optional: */
4635 /* dcba */
gen_dcba(DisasContext * ctx)4636 static void gen_dcba(DisasContext *ctx)
4637 {
4638 /* interpreted as no-op */
4639 /* XXX: specification say this is treated as a store by the MMU
4640 * but does not generate any exception
4641 */
4642 }
4643
4644 /*** Segment register manipulation ***/
4645 /* Supervisor only: */
4646
4647 /* mfsr */
gen_mfsr(DisasContext * ctx)4648 static void gen_mfsr(DisasContext *ctx)
4649 {
4650 #if defined(CONFIG_USER_ONLY)
4651 GEN_PRIV;
4652 #else
4653 TCGv t0;
4654
4655 CHK_SV;
4656 t0 = tcg_const_tl(SR(ctx->opcode));
4657 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4658 tcg_temp_free(t0);
4659 #endif /* defined(CONFIG_USER_ONLY) */
4660 }
4661
4662 /* mfsrin */
gen_mfsrin(DisasContext * ctx)4663 static void gen_mfsrin(DisasContext *ctx)
4664 {
4665 #if defined(CONFIG_USER_ONLY)
4666 GEN_PRIV;
4667 #else
4668 TCGv t0;
4669
4670 CHK_SV;
4671 t0 = tcg_temp_new();
4672 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4673 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4674 tcg_temp_free(t0);
4675 #endif /* defined(CONFIG_USER_ONLY) */
4676 }
4677
4678 /* mtsr */
gen_mtsr(DisasContext * ctx)4679 static void gen_mtsr(DisasContext *ctx)
4680 {
4681 #if defined(CONFIG_USER_ONLY)
4682 GEN_PRIV;
4683 #else
4684 TCGv t0;
4685
4686 CHK_SV;
4687 t0 = tcg_const_tl(SR(ctx->opcode));
4688 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4689 tcg_temp_free(t0);
4690 #endif /* defined(CONFIG_USER_ONLY) */
4691 }
4692
4693 /* mtsrin */
gen_mtsrin(DisasContext * ctx)4694 static void gen_mtsrin(DisasContext *ctx)
4695 {
4696 #if defined(CONFIG_USER_ONLY)
4697 GEN_PRIV;
4698 #else
4699 TCGv t0;
4700 CHK_SV;
4701
4702 t0 = tcg_temp_new();
4703 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4704 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4705 tcg_temp_free(t0);
4706 #endif /* defined(CONFIG_USER_ONLY) */
4707 }
4708
4709 #if defined(TARGET_PPC64)
4710 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4711
4712 /* mfsr */
gen_mfsr_64b(DisasContext * ctx)4713 static void gen_mfsr_64b(DisasContext *ctx)
4714 {
4715 #if defined(CONFIG_USER_ONLY)
4716 GEN_PRIV;
4717 #else
4718 TCGv t0;
4719
4720 CHK_SV;
4721 t0 = tcg_const_tl(SR(ctx->opcode));
4722 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4723 tcg_temp_free(t0);
4724 #endif /* defined(CONFIG_USER_ONLY) */
4725 }
4726
4727 /* mfsrin */
gen_mfsrin_64b(DisasContext * ctx)4728 static void gen_mfsrin_64b(DisasContext *ctx)
4729 {
4730 #if defined(CONFIG_USER_ONLY)
4731 GEN_PRIV;
4732 #else
4733 TCGv t0;
4734
4735 CHK_SV;
4736 t0 = tcg_temp_new();
4737 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4738 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4739 tcg_temp_free(t0);
4740 #endif /* defined(CONFIG_USER_ONLY) */
4741 }
4742
4743 /* mtsr */
gen_mtsr_64b(DisasContext * ctx)4744 static void gen_mtsr_64b(DisasContext *ctx)
4745 {
4746 #if defined(CONFIG_USER_ONLY)
4747 GEN_PRIV;
4748 #else
4749 TCGv t0;
4750
4751 CHK_SV;
4752 t0 = tcg_const_tl(SR(ctx->opcode));
4753 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4754 tcg_temp_free(t0);
4755 #endif /* defined(CONFIG_USER_ONLY) */
4756 }
4757
4758 /* mtsrin */
gen_mtsrin_64b(DisasContext * ctx)4759 static void gen_mtsrin_64b(DisasContext *ctx)
4760 {
4761 #if defined(CONFIG_USER_ONLY)
4762 GEN_PRIV;
4763 #else
4764 TCGv t0;
4765
4766 CHK_SV;
4767 t0 = tcg_temp_new();
4768 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4769 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4770 tcg_temp_free(t0);
4771 #endif /* defined(CONFIG_USER_ONLY) */
4772 }
4773
4774 /* slbmte */
gen_slbmte(DisasContext * ctx)4775 static void gen_slbmte(DisasContext *ctx)
4776 {
4777 #if defined(CONFIG_USER_ONLY)
4778 GEN_PRIV;
4779 #else
4780 CHK_SV;
4781
4782 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4783 cpu_gpr[rS(ctx->opcode)]);
4784 #endif /* defined(CONFIG_USER_ONLY) */
4785 }
4786
gen_slbmfee(DisasContext * ctx)4787 static void gen_slbmfee(DisasContext *ctx)
4788 {
4789 #if defined(CONFIG_USER_ONLY)
4790 GEN_PRIV;
4791 #else
4792 CHK_SV;
4793
4794 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4795 cpu_gpr[rB(ctx->opcode)]);
4796 #endif /* defined(CONFIG_USER_ONLY) */
4797 }
4798
gen_slbmfev(DisasContext * ctx)4799 static void gen_slbmfev(DisasContext *ctx)
4800 {
4801 #if defined(CONFIG_USER_ONLY)
4802 GEN_PRIV;
4803 #else
4804 CHK_SV;
4805
4806 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4807 cpu_gpr[rB(ctx->opcode)]);
4808 #endif /* defined(CONFIG_USER_ONLY) */
4809 }
4810
gen_slbfee_(DisasContext * ctx)4811 static void gen_slbfee_(DisasContext *ctx)
4812 {
4813 #if defined(CONFIG_USER_ONLY)
4814 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4815 #else
4816 TCGLabel *l1, *l2;
4817
4818 if (unlikely(ctx->pr)) {
4819 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4820 return;
4821 }
4822 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4823 cpu_gpr[rB(ctx->opcode)]);
4824 l1 = gen_new_label();
4825 l2 = gen_new_label();
4826 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4827 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
4828 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
4829 tcg_gen_br(l2);
4830 gen_set_label(l1);
4831 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4832 gen_set_label(l2);
4833 #endif
4834 }
4835 #endif /* defined(TARGET_PPC64) */
4836
4837 /*** Lookaside buffer management ***/
4838 /* Optional & supervisor only: */
4839
4840 /* tlbia */
gen_tlbia(DisasContext * ctx)4841 static void gen_tlbia(DisasContext *ctx)
4842 {
4843 #if defined(CONFIG_USER_ONLY)
4844 GEN_PRIV;
4845 #else
4846 CHK_HV;
4847
4848 gen_helper_tlbia(cpu_env);
4849 #endif /* defined(CONFIG_USER_ONLY) */
4850 }
4851
4852 /* tlbiel */
gen_tlbiel(DisasContext * ctx)4853 static void gen_tlbiel(DisasContext *ctx)
4854 {
4855 #if defined(CONFIG_USER_ONLY)
4856 GEN_PRIV;
4857 #else
4858 CHK_SV;
4859
4860 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4861 #endif /* defined(CONFIG_USER_ONLY) */
4862 }
4863
4864 /* tlbie */
gen_tlbie(DisasContext * ctx)4865 static void gen_tlbie(DisasContext *ctx)
4866 {
4867 #if defined(CONFIG_USER_ONLY)
4868 GEN_PRIV;
4869 #else
4870 TCGv_i32 t1;
4871
4872 if (ctx->gtse) {
4873 CHK_SV; /* If gtse is set then tlbie is supervisor privileged */
4874 } else {
4875 CHK_HV; /* Else hypervisor privileged */
4876 }
4877
4878 if (NARROW_MODE(ctx)) {
4879 TCGv t0 = tcg_temp_new();
4880 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4881 gen_helper_tlbie(cpu_env, t0);
4882 tcg_temp_free(t0);
4883 } else {
4884 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4885 }
4886 t1 = tcg_temp_new_i32();
4887 tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4888 tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH);
4889 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4890 tcg_temp_free_i32(t1);
4891 #endif /* defined(CONFIG_USER_ONLY) */
4892 }
4893
4894 /* tlbsync */
gen_tlbsync(DisasContext * ctx)4895 static void gen_tlbsync(DisasContext *ctx)
4896 {
4897 #if defined(CONFIG_USER_ONLY)
4898 GEN_PRIV;
4899 #else
4900
4901 if (ctx->gtse) {
4902 CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */
4903 } else {
4904 CHK_HV; /* Else hypervisor privileged */
4905 }
4906
4907 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
4908 if (ctx->insns_flags & PPC_BOOKE) {
4909 gen_check_tlb_flush(ctx, true);
4910 }
4911 #endif /* defined(CONFIG_USER_ONLY) */
4912 }
4913
4914 #if defined(TARGET_PPC64)
4915 /* slbia */
gen_slbia(DisasContext * ctx)4916 static void gen_slbia(DisasContext *ctx)
4917 {
4918 #if defined(CONFIG_USER_ONLY)
4919 GEN_PRIV;
4920 #else
4921 CHK_SV;
4922
4923 gen_helper_slbia(cpu_env);
4924 #endif /* defined(CONFIG_USER_ONLY) */
4925 }
4926
4927 /* slbie */
gen_slbie(DisasContext * ctx)4928 static void gen_slbie(DisasContext *ctx)
4929 {
4930 #if defined(CONFIG_USER_ONLY)
4931 GEN_PRIV;
4932 #else
4933 CHK_SV;
4934
4935 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4936 #endif /* defined(CONFIG_USER_ONLY) */
4937 }
4938
4939 /* slbieg */
gen_slbieg(DisasContext * ctx)4940 static void gen_slbieg(DisasContext *ctx)
4941 {
4942 #if defined(CONFIG_USER_ONLY)
4943 GEN_PRIV;
4944 #else
4945 CHK_SV;
4946
4947 gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4948 #endif /* defined(CONFIG_USER_ONLY) */
4949 }
4950
4951 /* slbsync */
gen_slbsync(DisasContext * ctx)4952 static void gen_slbsync(DisasContext *ctx)
4953 {
4954 #if defined(CONFIG_USER_ONLY)
4955 GEN_PRIV;
4956 #else
4957 CHK_SV;
4958 gen_check_tlb_flush(ctx, true);
4959 #endif /* defined(CONFIG_USER_ONLY) */
4960 }
4961
4962 #endif /* defined(TARGET_PPC64) */
4963
4964 /*** External control ***/
4965 /* Optional: */
4966
4967 /* eciwx */
gen_eciwx(DisasContext * ctx)4968 static void gen_eciwx(DisasContext *ctx)
4969 {
4970 TCGv t0;
4971 /* Should check EAR[E] ! */
4972 gen_set_access_type(ctx, ACCESS_EXT);
4973 t0 = tcg_temp_new();
4974 gen_addr_reg_index(ctx, t0);
4975 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
4976 DEF_MEMOP(MO_UL | MO_ALIGN));
4977 tcg_temp_free(t0);
4978 }
4979
4980 /* ecowx */
gen_ecowx(DisasContext * ctx)4981 static void gen_ecowx(DisasContext *ctx)
4982 {
4983 TCGv t0;
4984 /* Should check EAR[E] ! */
4985 gen_set_access_type(ctx, ACCESS_EXT);
4986 t0 = tcg_temp_new();
4987 gen_addr_reg_index(ctx, t0);
4988 tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
4989 DEF_MEMOP(MO_UL | MO_ALIGN));
4990 tcg_temp_free(t0);
4991 }
4992
4993 /* PowerPC 601 specific instructions */
4994
4995 /* abs - abs. */
gen_abs(DisasContext * ctx)4996 static void gen_abs(DisasContext *ctx)
4997 {
4998 TCGLabel *l1 = gen_new_label();
4999 TCGLabel *l2 = gen_new_label();
5000 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
5001 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5002 tcg_gen_br(l2);
5003 gen_set_label(l1);
5004 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5005 gen_set_label(l2);
5006 if (unlikely(Rc(ctx->opcode) != 0))
5007 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5008 }
5009
5010 /* abso - abso. */
gen_abso(DisasContext * ctx)5011 static void gen_abso(DisasContext *ctx)
5012 {
5013 TCGLabel *l1 = gen_new_label();
5014 TCGLabel *l2 = gen_new_label();
5015 TCGLabel *l3 = gen_new_label();
5016 /* Start with XER OV disabled, the most likely case */
5017 tcg_gen_movi_tl(cpu_ov, 0);
5018 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
5019 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
5020 tcg_gen_movi_tl(cpu_ov, 1);
5021 tcg_gen_movi_tl(cpu_so, 1);
5022 tcg_gen_br(l2);
5023 gen_set_label(l1);
5024 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5025 tcg_gen_br(l3);
5026 gen_set_label(l2);
5027 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5028 gen_set_label(l3);
5029 if (unlikely(Rc(ctx->opcode) != 0))
5030 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5031 }
5032
5033 /* clcs */
gen_clcs(DisasContext * ctx)5034 static void gen_clcs(DisasContext *ctx)
5035 {
5036 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
5037 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5038 tcg_temp_free_i32(t0);
5039 /* Rc=1 sets CR0 to an undefined state */
5040 }
5041
5042 /* div - div. */
gen_div(DisasContext * ctx)5043 static void gen_div(DisasContext *ctx)
5044 {
5045 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5046 cpu_gpr[rB(ctx->opcode)]);
5047 if (unlikely(Rc(ctx->opcode) != 0))
5048 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5049 }
5050
5051 /* divo - divo. */
gen_divo(DisasContext * ctx)5052 static void gen_divo(DisasContext *ctx)
5053 {
5054 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5055 cpu_gpr[rB(ctx->opcode)]);
5056 if (unlikely(Rc(ctx->opcode) != 0))
5057 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5058 }
5059
5060 /* divs - divs. */
gen_divs(DisasContext * ctx)5061 static void gen_divs(DisasContext *ctx)
5062 {
5063 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5064 cpu_gpr[rB(ctx->opcode)]);
5065 if (unlikely(Rc(ctx->opcode) != 0))
5066 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5067 }
5068
5069 /* divso - divso. */
gen_divso(DisasContext * ctx)5070 static void gen_divso(DisasContext *ctx)
5071 {
5072 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
5073 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5074 if (unlikely(Rc(ctx->opcode) != 0))
5075 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5076 }
5077
5078 /* doz - doz. */
gen_doz(DisasContext * ctx)5079 static void gen_doz(DisasContext *ctx)
5080 {
5081 TCGLabel *l1 = gen_new_label();
5082 TCGLabel *l2 = gen_new_label();
5083 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5084 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5085 tcg_gen_br(l2);
5086 gen_set_label(l1);
5087 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5088 gen_set_label(l2);
5089 if (unlikely(Rc(ctx->opcode) != 0))
5090 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5091 }
5092
5093 /* dozo - dozo. */
gen_dozo(DisasContext * ctx)5094 static void gen_dozo(DisasContext *ctx)
5095 {
5096 TCGLabel *l1 = gen_new_label();
5097 TCGLabel *l2 = gen_new_label();
5098 TCGv t0 = tcg_temp_new();
5099 TCGv t1 = tcg_temp_new();
5100 TCGv t2 = tcg_temp_new();
5101 /* Start with XER OV disabled, the most likely case */
5102 tcg_gen_movi_tl(cpu_ov, 0);
5103 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5104 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5105 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5106 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
5107 tcg_gen_andc_tl(t1, t1, t2);
5108 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
5109 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5110 tcg_gen_movi_tl(cpu_ov, 1);
5111 tcg_gen_movi_tl(cpu_so, 1);
5112 tcg_gen_br(l2);
5113 gen_set_label(l1);
5114 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5115 gen_set_label(l2);
5116 tcg_temp_free(t0);
5117 tcg_temp_free(t1);
5118 tcg_temp_free(t2);
5119 if (unlikely(Rc(ctx->opcode) != 0))
5120 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5121 }
5122
5123 /* dozi */
gen_dozi(DisasContext * ctx)5124 static void gen_dozi(DisasContext *ctx)
5125 {
5126 target_long simm = SIMM(ctx->opcode);
5127 TCGLabel *l1 = gen_new_label();
5128 TCGLabel *l2 = gen_new_label();
5129 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5130 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5131 tcg_gen_br(l2);
5132 gen_set_label(l1);
5133 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5134 gen_set_label(l2);
5135 if (unlikely(Rc(ctx->opcode) != 0))
5136 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5137 }
5138
5139 /* lscbx - lscbx. */
gen_lscbx(DisasContext * ctx)5140 static void gen_lscbx(DisasContext *ctx)
5141 {
5142 TCGv t0 = tcg_temp_new();
5143 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5144 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5145 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
5146
5147 gen_addr_reg_index(ctx, t0);
5148 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
5149 tcg_temp_free_i32(t1);
5150 tcg_temp_free_i32(t2);
5151 tcg_temp_free_i32(t3);
5152 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5153 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5154 if (unlikely(Rc(ctx->opcode) != 0))
5155 gen_set_Rc0(ctx, t0);
5156 tcg_temp_free(t0);
5157 }
5158
5159 /* maskg - maskg. */
gen_maskg(DisasContext * ctx)5160 static void gen_maskg(DisasContext *ctx)
5161 {
5162 TCGLabel *l1 = gen_new_label();
5163 TCGv t0 = tcg_temp_new();
5164 TCGv t1 = tcg_temp_new();
5165 TCGv t2 = tcg_temp_new();
5166 TCGv t3 = tcg_temp_new();
5167 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5168 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5169 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5170 tcg_gen_addi_tl(t2, t0, 1);
5171 tcg_gen_shr_tl(t2, t3, t2);
5172 tcg_gen_shr_tl(t3, t3, t1);
5173 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5174 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5175 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5176 gen_set_label(l1);
5177 tcg_temp_free(t0);
5178 tcg_temp_free(t1);
5179 tcg_temp_free(t2);
5180 tcg_temp_free(t3);
5181 if (unlikely(Rc(ctx->opcode) != 0))
5182 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5183 }
5184
5185 /* maskir - maskir. */
gen_maskir(DisasContext * ctx)5186 static void gen_maskir(DisasContext *ctx)
5187 {
5188 TCGv t0 = tcg_temp_new();
5189 TCGv t1 = tcg_temp_new();
5190 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5191 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5192 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5193 tcg_temp_free(t0);
5194 tcg_temp_free(t1);
5195 if (unlikely(Rc(ctx->opcode) != 0))
5196 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5197 }
5198
5199 /* mul - mul. */
gen_mul(DisasContext * ctx)5200 static void gen_mul(DisasContext *ctx)
5201 {
5202 TCGv_i64 t0 = tcg_temp_new_i64();
5203 TCGv_i64 t1 = tcg_temp_new_i64();
5204 TCGv t2 = tcg_temp_new();
5205 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5206 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5207 tcg_gen_mul_i64(t0, t0, t1);
5208 tcg_gen_trunc_i64_tl(t2, t0);
5209 gen_store_spr(SPR_MQ, t2);
5210 tcg_gen_shri_i64(t1, t0, 32);
5211 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5212 tcg_temp_free_i64(t0);
5213 tcg_temp_free_i64(t1);
5214 tcg_temp_free(t2);
5215 if (unlikely(Rc(ctx->opcode) != 0))
5216 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5217 }
5218
5219 /* mulo - mulo. */
gen_mulo(DisasContext * ctx)5220 static void gen_mulo(DisasContext *ctx)
5221 {
5222 TCGLabel *l1 = gen_new_label();
5223 TCGv_i64 t0 = tcg_temp_new_i64();
5224 TCGv_i64 t1 = tcg_temp_new_i64();
5225 TCGv t2 = tcg_temp_new();
5226 /* Start with XER OV disabled, the most likely case */
5227 tcg_gen_movi_tl(cpu_ov, 0);
5228 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5229 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5230 tcg_gen_mul_i64(t0, t0, t1);
5231 tcg_gen_trunc_i64_tl(t2, t0);
5232 gen_store_spr(SPR_MQ, t2);
5233 tcg_gen_shri_i64(t1, t0, 32);
5234 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5235 tcg_gen_ext32s_i64(t1, t0);
5236 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5237 tcg_gen_movi_tl(cpu_ov, 1);
5238 tcg_gen_movi_tl(cpu_so, 1);
5239 gen_set_label(l1);
5240 tcg_temp_free_i64(t0);
5241 tcg_temp_free_i64(t1);
5242 tcg_temp_free(t2);
5243 if (unlikely(Rc(ctx->opcode) != 0))
5244 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5245 }
5246
5247 /* nabs - nabs. */
gen_nabs(DisasContext * ctx)5248 static void gen_nabs(DisasContext *ctx)
5249 {
5250 TCGLabel *l1 = gen_new_label();
5251 TCGLabel *l2 = gen_new_label();
5252 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5253 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5254 tcg_gen_br(l2);
5255 gen_set_label(l1);
5256 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5257 gen_set_label(l2);
5258 if (unlikely(Rc(ctx->opcode) != 0))
5259 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5260 }
5261
5262 /* nabso - nabso. */
gen_nabso(DisasContext * ctx)5263 static void gen_nabso(DisasContext *ctx)
5264 {
5265 TCGLabel *l1 = gen_new_label();
5266 TCGLabel *l2 = gen_new_label();
5267 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5268 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5269 tcg_gen_br(l2);
5270 gen_set_label(l1);
5271 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5272 gen_set_label(l2);
5273 /* nabs never overflows */
5274 tcg_gen_movi_tl(cpu_ov, 0);
5275 if (unlikely(Rc(ctx->opcode) != 0))
5276 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5277 }
5278
5279 /* rlmi - rlmi. */
gen_rlmi(DisasContext * ctx)5280 static void gen_rlmi(DisasContext *ctx)
5281 {
5282 uint32_t mb = MB(ctx->opcode);
5283 uint32_t me = ME(ctx->opcode);
5284 TCGv t0 = tcg_temp_new();
5285 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5286 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5287 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5288 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5289 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5290 tcg_temp_free(t0);
5291 if (unlikely(Rc(ctx->opcode) != 0))
5292 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5293 }
5294
5295 /* rrib - rrib. */
gen_rrib(DisasContext * ctx)5296 static void gen_rrib(DisasContext *ctx)
5297 {
5298 TCGv t0 = tcg_temp_new();
5299 TCGv t1 = tcg_temp_new();
5300 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5301 tcg_gen_movi_tl(t1, 0x80000000);
5302 tcg_gen_shr_tl(t1, t1, t0);
5303 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5304 tcg_gen_and_tl(t0, t0, t1);
5305 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5306 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5307 tcg_temp_free(t0);
5308 tcg_temp_free(t1);
5309 if (unlikely(Rc(ctx->opcode) != 0))
5310 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5311 }
5312
5313 /* sle - sle. */
gen_sle(DisasContext * ctx)5314 static void gen_sle(DisasContext *ctx)
5315 {
5316 TCGv t0 = tcg_temp_new();
5317 TCGv t1 = tcg_temp_new();
5318 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5319 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5320 tcg_gen_subfi_tl(t1, 32, t1);
5321 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5322 tcg_gen_or_tl(t1, t0, t1);
5323 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5324 gen_store_spr(SPR_MQ, t1);
5325 tcg_temp_free(t0);
5326 tcg_temp_free(t1);
5327 if (unlikely(Rc(ctx->opcode) != 0))
5328 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5329 }
5330
5331 /* sleq - sleq. */
gen_sleq(DisasContext * ctx)5332 static void gen_sleq(DisasContext *ctx)
5333 {
5334 TCGv t0 = tcg_temp_new();
5335 TCGv t1 = tcg_temp_new();
5336 TCGv t2 = tcg_temp_new();
5337 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5338 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5339 tcg_gen_shl_tl(t2, t2, t0);
5340 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5341 gen_load_spr(t1, SPR_MQ);
5342 gen_store_spr(SPR_MQ, t0);
5343 tcg_gen_and_tl(t0, t0, t2);
5344 tcg_gen_andc_tl(t1, t1, t2);
5345 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5346 tcg_temp_free(t0);
5347 tcg_temp_free(t1);
5348 tcg_temp_free(t2);
5349 if (unlikely(Rc(ctx->opcode) != 0))
5350 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5351 }
5352
5353 /* sliq - sliq. */
gen_sliq(DisasContext * ctx)5354 static void gen_sliq(DisasContext *ctx)
5355 {
5356 int sh = SH(ctx->opcode);
5357 TCGv t0 = tcg_temp_new();
5358 TCGv t1 = tcg_temp_new();
5359 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5360 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5361 tcg_gen_or_tl(t1, t0, t1);
5362 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5363 gen_store_spr(SPR_MQ, t1);
5364 tcg_temp_free(t0);
5365 tcg_temp_free(t1);
5366 if (unlikely(Rc(ctx->opcode) != 0))
5367 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5368 }
5369
5370 /* slliq - slliq. */
gen_slliq(DisasContext * ctx)5371 static void gen_slliq(DisasContext *ctx)
5372 {
5373 int sh = SH(ctx->opcode);
5374 TCGv t0 = tcg_temp_new();
5375 TCGv t1 = tcg_temp_new();
5376 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5377 gen_load_spr(t1, SPR_MQ);
5378 gen_store_spr(SPR_MQ, t0);
5379 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5380 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5381 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5382 tcg_temp_free(t0);
5383 tcg_temp_free(t1);
5384 if (unlikely(Rc(ctx->opcode) != 0))
5385 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5386 }
5387
5388 /* sllq - sllq. */
gen_sllq(DisasContext * ctx)5389 static void gen_sllq(DisasContext *ctx)
5390 {
5391 TCGLabel *l1 = gen_new_label();
5392 TCGLabel *l2 = gen_new_label();
5393 TCGv t0 = tcg_temp_local_new();
5394 TCGv t1 = tcg_temp_local_new();
5395 TCGv t2 = tcg_temp_local_new();
5396 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5397 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5398 tcg_gen_shl_tl(t1, t1, t2);
5399 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5400 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5401 gen_load_spr(t0, SPR_MQ);
5402 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5403 tcg_gen_br(l2);
5404 gen_set_label(l1);
5405 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5406 gen_load_spr(t2, SPR_MQ);
5407 tcg_gen_andc_tl(t1, t2, t1);
5408 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5409 gen_set_label(l2);
5410 tcg_temp_free(t0);
5411 tcg_temp_free(t1);
5412 tcg_temp_free(t2);
5413 if (unlikely(Rc(ctx->opcode) != 0))
5414 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5415 }
5416
5417 /* slq - slq. */
gen_slq(DisasContext * ctx)5418 static void gen_slq(DisasContext *ctx)
5419 {
5420 TCGLabel *l1 = gen_new_label();
5421 TCGv t0 = tcg_temp_new();
5422 TCGv t1 = tcg_temp_new();
5423 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5424 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5425 tcg_gen_subfi_tl(t1, 32, t1);
5426 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5427 tcg_gen_or_tl(t1, t0, t1);
5428 gen_store_spr(SPR_MQ, t1);
5429 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5430 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5431 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5432 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5433 gen_set_label(l1);
5434 tcg_temp_free(t0);
5435 tcg_temp_free(t1);
5436 if (unlikely(Rc(ctx->opcode) != 0))
5437 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5438 }
5439
5440 /* sraiq - sraiq. */
gen_sraiq(DisasContext * ctx)5441 static void gen_sraiq(DisasContext *ctx)
5442 {
5443 int sh = SH(ctx->opcode);
5444 TCGLabel *l1 = gen_new_label();
5445 TCGv t0 = tcg_temp_new();
5446 TCGv t1 = tcg_temp_new();
5447 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5448 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5449 tcg_gen_or_tl(t0, t0, t1);
5450 gen_store_spr(SPR_MQ, t0);
5451 tcg_gen_movi_tl(cpu_ca, 0);
5452 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5453 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5454 tcg_gen_movi_tl(cpu_ca, 1);
5455 gen_set_label(l1);
5456 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5457 tcg_temp_free(t0);
5458 tcg_temp_free(t1);
5459 if (unlikely(Rc(ctx->opcode) != 0))
5460 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5461 }
5462
5463 /* sraq - sraq. */
gen_sraq(DisasContext * ctx)5464 static void gen_sraq(DisasContext *ctx)
5465 {
5466 TCGLabel *l1 = gen_new_label();
5467 TCGLabel *l2 = gen_new_label();
5468 TCGv t0 = tcg_temp_new();
5469 TCGv t1 = tcg_temp_local_new();
5470 TCGv t2 = tcg_temp_local_new();
5471 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5472 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5473 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5474 tcg_gen_subfi_tl(t2, 32, t2);
5475 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5476 tcg_gen_or_tl(t0, t0, t2);
5477 gen_store_spr(SPR_MQ, t0);
5478 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5479 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5480 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5481 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5482 gen_set_label(l1);
5483 tcg_temp_free(t0);
5484 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5485 tcg_gen_movi_tl(cpu_ca, 0);
5486 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5487 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5488 tcg_gen_movi_tl(cpu_ca, 1);
5489 gen_set_label(l2);
5490 tcg_temp_free(t1);
5491 tcg_temp_free(t2);
5492 if (unlikely(Rc(ctx->opcode) != 0))
5493 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5494 }
5495
5496 /* sre - sre. */
gen_sre(DisasContext * ctx)5497 static void gen_sre(DisasContext *ctx)
5498 {
5499 TCGv t0 = tcg_temp_new();
5500 TCGv t1 = tcg_temp_new();
5501 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5502 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5503 tcg_gen_subfi_tl(t1, 32, t1);
5504 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5505 tcg_gen_or_tl(t1, t0, t1);
5506 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5507 gen_store_spr(SPR_MQ, t1);
5508 tcg_temp_free(t0);
5509 tcg_temp_free(t1);
5510 if (unlikely(Rc(ctx->opcode) != 0))
5511 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5512 }
5513
5514 /* srea - srea. */
gen_srea(DisasContext * ctx)5515 static void gen_srea(DisasContext *ctx)
5516 {
5517 TCGv t0 = tcg_temp_new();
5518 TCGv t1 = tcg_temp_new();
5519 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5520 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5521 gen_store_spr(SPR_MQ, t0);
5522 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5523 tcg_temp_free(t0);
5524 tcg_temp_free(t1);
5525 if (unlikely(Rc(ctx->opcode) != 0))
5526 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5527 }
5528
5529 /* sreq */
gen_sreq(DisasContext * ctx)5530 static void gen_sreq(DisasContext *ctx)
5531 {
5532 TCGv t0 = tcg_temp_new();
5533 TCGv t1 = tcg_temp_new();
5534 TCGv t2 = tcg_temp_new();
5535 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5536 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5537 tcg_gen_shr_tl(t1, t1, t0);
5538 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5539 gen_load_spr(t2, SPR_MQ);
5540 gen_store_spr(SPR_MQ, t0);
5541 tcg_gen_and_tl(t0, t0, t1);
5542 tcg_gen_andc_tl(t2, t2, t1);
5543 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5544 tcg_temp_free(t0);
5545 tcg_temp_free(t1);
5546 tcg_temp_free(t2);
5547 if (unlikely(Rc(ctx->opcode) != 0))
5548 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5549 }
5550
5551 /* sriq */
gen_sriq(DisasContext * ctx)5552 static void gen_sriq(DisasContext *ctx)
5553 {
5554 int sh = SH(ctx->opcode);
5555 TCGv t0 = tcg_temp_new();
5556 TCGv t1 = tcg_temp_new();
5557 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5558 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5559 tcg_gen_or_tl(t1, t0, t1);
5560 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5561 gen_store_spr(SPR_MQ, t1);
5562 tcg_temp_free(t0);
5563 tcg_temp_free(t1);
5564 if (unlikely(Rc(ctx->opcode) != 0))
5565 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5566 }
5567
5568 /* srliq */
gen_srliq(DisasContext * ctx)5569 static void gen_srliq(DisasContext *ctx)
5570 {
5571 int sh = SH(ctx->opcode);
5572 TCGv t0 = tcg_temp_new();
5573 TCGv t1 = tcg_temp_new();
5574 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5575 gen_load_spr(t1, SPR_MQ);
5576 gen_store_spr(SPR_MQ, t0);
5577 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5578 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5579 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5580 tcg_temp_free(t0);
5581 tcg_temp_free(t1);
5582 if (unlikely(Rc(ctx->opcode) != 0))
5583 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5584 }
5585
5586 /* srlq */
gen_srlq(DisasContext * ctx)5587 static void gen_srlq(DisasContext *ctx)
5588 {
5589 TCGLabel *l1 = gen_new_label();
5590 TCGLabel *l2 = gen_new_label();
5591 TCGv t0 = tcg_temp_local_new();
5592 TCGv t1 = tcg_temp_local_new();
5593 TCGv t2 = tcg_temp_local_new();
5594 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5595 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5596 tcg_gen_shr_tl(t2, t1, t2);
5597 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5598 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5599 gen_load_spr(t0, SPR_MQ);
5600 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5601 tcg_gen_br(l2);
5602 gen_set_label(l1);
5603 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5604 tcg_gen_and_tl(t0, t0, t2);
5605 gen_load_spr(t1, SPR_MQ);
5606 tcg_gen_andc_tl(t1, t1, t2);
5607 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5608 gen_set_label(l2);
5609 tcg_temp_free(t0);
5610 tcg_temp_free(t1);
5611 tcg_temp_free(t2);
5612 if (unlikely(Rc(ctx->opcode) != 0))
5613 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5614 }
5615
5616 /* srq */
gen_srq(DisasContext * ctx)5617 static void gen_srq(DisasContext *ctx)
5618 {
5619 TCGLabel *l1 = gen_new_label();
5620 TCGv t0 = tcg_temp_new();
5621 TCGv t1 = tcg_temp_new();
5622 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5623 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5624 tcg_gen_subfi_tl(t1, 32, t1);
5625 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5626 tcg_gen_or_tl(t1, t0, t1);
5627 gen_store_spr(SPR_MQ, t1);
5628 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5629 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5630 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5631 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5632 gen_set_label(l1);
5633 tcg_temp_free(t0);
5634 tcg_temp_free(t1);
5635 if (unlikely(Rc(ctx->opcode) != 0))
5636 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5637 }
5638
5639 /* PowerPC 602 specific instructions */
5640
5641 /* dsa */
gen_dsa(DisasContext * ctx)5642 static void gen_dsa(DisasContext *ctx)
5643 {
5644 /* XXX: TODO */
5645 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5646 }
5647
5648 /* esa */
gen_esa(DisasContext * ctx)5649 static void gen_esa(DisasContext *ctx)
5650 {
5651 /* XXX: TODO */
5652 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5653 }
5654
5655 /* mfrom */
gen_mfrom(DisasContext * ctx)5656 static void gen_mfrom(DisasContext *ctx)
5657 {
5658 #if defined(CONFIG_USER_ONLY)
5659 GEN_PRIV;
5660 #else
5661 CHK_SV;
5662 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5663 #endif /* defined(CONFIG_USER_ONLY) */
5664 }
5665
5666 /* 602 - 603 - G2 TLB management */
5667
5668 /* tlbld */
gen_tlbld_6xx(DisasContext * ctx)5669 static void gen_tlbld_6xx(DisasContext *ctx)
5670 {
5671 #if defined(CONFIG_USER_ONLY)
5672 GEN_PRIV;
5673 #else
5674 CHK_SV;
5675 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5676 #endif /* defined(CONFIG_USER_ONLY) */
5677 }
5678
5679 /* tlbli */
gen_tlbli_6xx(DisasContext * ctx)5680 static void gen_tlbli_6xx(DisasContext *ctx)
5681 {
5682 #if defined(CONFIG_USER_ONLY)
5683 GEN_PRIV;
5684 #else
5685 CHK_SV;
5686 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5687 #endif /* defined(CONFIG_USER_ONLY) */
5688 }
5689
5690 /* 74xx TLB management */
5691
5692 /* tlbld */
gen_tlbld_74xx(DisasContext * ctx)5693 static void gen_tlbld_74xx(DisasContext *ctx)
5694 {
5695 #if defined(CONFIG_USER_ONLY)
5696 GEN_PRIV;
5697 #else
5698 CHK_SV;
5699 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5700 #endif /* defined(CONFIG_USER_ONLY) */
5701 }
5702
5703 /* tlbli */
gen_tlbli_74xx(DisasContext * ctx)5704 static void gen_tlbli_74xx(DisasContext *ctx)
5705 {
5706 #if defined(CONFIG_USER_ONLY)
5707 GEN_PRIV;
5708 #else
5709 CHK_SV;
5710 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5711 #endif /* defined(CONFIG_USER_ONLY) */
5712 }
5713
5714 /* POWER instructions not in PowerPC 601 */
5715
5716 /* clf */
gen_clf(DisasContext * ctx)5717 static void gen_clf(DisasContext *ctx)
5718 {
5719 /* Cache line flush: implemented as no-op */
5720 }
5721
5722 /* cli */
gen_cli(DisasContext * ctx)5723 static void gen_cli(DisasContext *ctx)
5724 {
5725 #if defined(CONFIG_USER_ONLY)
5726 GEN_PRIV;
5727 #else
5728 /* Cache line invalidate: privileged and treated as no-op */
5729 CHK_SV;
5730 #endif /* defined(CONFIG_USER_ONLY) */
5731 }
5732
5733 /* dclst */
gen_dclst(DisasContext * ctx)5734 static void gen_dclst(DisasContext *ctx)
5735 {
5736 /* Data cache line store: treated as no-op */
5737 }
5738
gen_mfsri(DisasContext * ctx)5739 static void gen_mfsri(DisasContext *ctx)
5740 {
5741 #if defined(CONFIG_USER_ONLY)
5742 GEN_PRIV;
5743 #else
5744 int ra = rA(ctx->opcode);
5745 int rd = rD(ctx->opcode);
5746 TCGv t0;
5747
5748 CHK_SV;
5749 t0 = tcg_temp_new();
5750 gen_addr_reg_index(ctx, t0);
5751 tcg_gen_extract_tl(t0, t0, 28, 4);
5752 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5753 tcg_temp_free(t0);
5754 if (ra != 0 && ra != rd)
5755 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5756 #endif /* defined(CONFIG_USER_ONLY) */
5757 }
5758
gen_rac(DisasContext * ctx)5759 static void gen_rac(DisasContext *ctx)
5760 {
5761 #if defined(CONFIG_USER_ONLY)
5762 GEN_PRIV;
5763 #else
5764 TCGv t0;
5765
5766 CHK_SV;
5767 t0 = tcg_temp_new();
5768 gen_addr_reg_index(ctx, t0);
5769 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5770 tcg_temp_free(t0);
5771 #endif /* defined(CONFIG_USER_ONLY) */
5772 }
5773
gen_rfsvc(DisasContext * ctx)5774 static void gen_rfsvc(DisasContext *ctx)
5775 {
5776 #if defined(CONFIG_USER_ONLY)
5777 GEN_PRIV;
5778 #else
5779 CHK_SV;
5780
5781 gen_helper_rfsvc(cpu_env);
5782 gen_sync_exception(ctx);
5783 #endif /* defined(CONFIG_USER_ONLY) */
5784 }
5785
5786 /* svc is not implemented for now */
5787
5788 /* BookE specific instructions */
5789
5790 /* XXX: not implemented on 440 ? */
gen_mfapidi(DisasContext * ctx)5791 static void gen_mfapidi(DisasContext *ctx)
5792 {
5793 /* XXX: TODO */
5794 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5795 }
5796
5797 /* XXX: not implemented on 440 ? */
gen_tlbiva(DisasContext * ctx)5798 static void gen_tlbiva(DisasContext *ctx)
5799 {
5800 #if defined(CONFIG_USER_ONLY)
5801 GEN_PRIV;
5802 #else
5803 TCGv t0;
5804
5805 CHK_SV;
5806 t0 = tcg_temp_new();
5807 gen_addr_reg_index(ctx, t0);
5808 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5809 tcg_temp_free(t0);
5810 #endif /* defined(CONFIG_USER_ONLY) */
5811 }
5812
5813 /* All 405 MAC instructions are translated here */
gen_405_mulladd_insn(DisasContext * ctx,int opc2,int opc3,int ra,int rb,int rt,int Rc)5814 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5815 int ra, int rb, int rt, int Rc)
5816 {
5817 TCGv t0, t1;
5818
5819 t0 = tcg_temp_local_new();
5820 t1 = tcg_temp_local_new();
5821
5822 switch (opc3 & 0x0D) {
5823 case 0x05:
5824 /* macchw - macchw. - macchwo - macchwo. */
5825 /* macchws - macchws. - macchwso - macchwso. */
5826 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5827 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5828 /* mulchw - mulchw. */
5829 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5830 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5831 tcg_gen_ext16s_tl(t1, t1);
5832 break;
5833 case 0x04:
5834 /* macchwu - macchwu. - macchwuo - macchwuo. */
5835 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5836 /* mulchwu - mulchwu. */
5837 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5838 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5839 tcg_gen_ext16u_tl(t1, t1);
5840 break;
5841 case 0x01:
5842 /* machhw - machhw. - machhwo - machhwo. */
5843 /* machhws - machhws. - machhwso - machhwso. */
5844 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5845 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5846 /* mulhhw - mulhhw. */
5847 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5848 tcg_gen_ext16s_tl(t0, t0);
5849 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5850 tcg_gen_ext16s_tl(t1, t1);
5851 break;
5852 case 0x00:
5853 /* machhwu - machhwu. - machhwuo - machhwuo. */
5854 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5855 /* mulhhwu - mulhhwu. */
5856 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5857 tcg_gen_ext16u_tl(t0, t0);
5858 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5859 tcg_gen_ext16u_tl(t1, t1);
5860 break;
5861 case 0x0D:
5862 /* maclhw - maclhw. - maclhwo - maclhwo. */
5863 /* maclhws - maclhws. - maclhwso - maclhwso. */
5864 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5865 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5866 /* mullhw - mullhw. */
5867 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5868 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5869 break;
5870 case 0x0C:
5871 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5872 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5873 /* mullhwu - mullhwu. */
5874 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5875 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5876 break;
5877 }
5878 if (opc2 & 0x04) {
5879 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5880 tcg_gen_mul_tl(t1, t0, t1);
5881 if (opc2 & 0x02) {
5882 /* nmultiply-and-accumulate (0x0E) */
5883 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5884 } else {
5885 /* multiply-and-accumulate (0x0C) */
5886 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5887 }
5888
5889 if (opc3 & 0x12) {
5890 /* Check overflow and/or saturate */
5891 TCGLabel *l1 = gen_new_label();
5892
5893 if (opc3 & 0x10) {
5894 /* Start with XER OV disabled, the most likely case */
5895 tcg_gen_movi_tl(cpu_ov, 0);
5896 }
5897 if (opc3 & 0x01) {
5898 /* Signed */
5899 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5900 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5901 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5902 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5903 if (opc3 & 0x02) {
5904 /* Saturate */
5905 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5906 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5907 }
5908 } else {
5909 /* Unsigned */
5910 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5911 if (opc3 & 0x02) {
5912 /* Saturate */
5913 tcg_gen_movi_tl(t0, UINT32_MAX);
5914 }
5915 }
5916 if (opc3 & 0x10) {
5917 /* Check overflow */
5918 tcg_gen_movi_tl(cpu_ov, 1);
5919 tcg_gen_movi_tl(cpu_so, 1);
5920 }
5921 gen_set_label(l1);
5922 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5923 }
5924 } else {
5925 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5926 }
5927 tcg_temp_free(t0);
5928 tcg_temp_free(t1);
5929 if (unlikely(Rc) != 0) {
5930 /* Update Rc0 */
5931 gen_set_Rc0(ctx, cpu_gpr[rt]);
5932 }
5933 }
5934
5935 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5936 static void glue(gen_, name)(DisasContext *ctx) \
5937 { \
5938 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5939 rD(ctx->opcode), Rc(ctx->opcode)); \
5940 }
5941
5942 /* macchw - macchw. */
5943 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5944 /* macchwo - macchwo. */
5945 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5946 /* macchws - macchws. */
5947 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5948 /* macchwso - macchwso. */
5949 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5950 /* macchwsu - macchwsu. */
5951 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5952 /* macchwsuo - macchwsuo. */
5953 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5954 /* macchwu - macchwu. */
5955 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5956 /* macchwuo - macchwuo. */
5957 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5958 /* machhw - machhw. */
5959 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5960 /* machhwo - machhwo. */
5961 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5962 /* machhws - machhws. */
5963 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5964 /* machhwso - machhwso. */
5965 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5966 /* machhwsu - machhwsu. */
5967 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5968 /* machhwsuo - machhwsuo. */
5969 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5970 /* machhwu - machhwu. */
5971 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5972 /* machhwuo - machhwuo. */
5973 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5974 /* maclhw - maclhw. */
5975 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5976 /* maclhwo - maclhwo. */
5977 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5978 /* maclhws - maclhws. */
5979 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5980 /* maclhwso - maclhwso. */
5981 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5982 /* maclhwu - maclhwu. */
5983 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5984 /* maclhwuo - maclhwuo. */
5985 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5986 /* maclhwsu - maclhwsu. */
5987 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5988 /* maclhwsuo - maclhwsuo. */
5989 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5990 /* nmacchw - nmacchw. */
5991 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5992 /* nmacchwo - nmacchwo. */
5993 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5994 /* nmacchws - nmacchws. */
5995 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5996 /* nmacchwso - nmacchwso. */
5997 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5998 /* nmachhw - nmachhw. */
5999 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
6000 /* nmachhwo - nmachhwo. */
6001 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
6002 /* nmachhws - nmachhws. */
6003 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
6004 /* nmachhwso - nmachhwso. */
6005 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
6006 /* nmaclhw - nmaclhw. */
6007 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
6008 /* nmaclhwo - nmaclhwo. */
6009 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
6010 /* nmaclhws - nmaclhws. */
6011 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
6012 /* nmaclhwso - nmaclhwso. */
6013 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6014
6015 /* mulchw - mulchw. */
6016 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6017 /* mulchwu - mulchwu. */
6018 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6019 /* mulhhw - mulhhw. */
6020 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6021 /* mulhhwu - mulhhwu. */
6022 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6023 /* mullhw - mullhw. */
6024 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6025 /* mullhwu - mullhwu. */
6026 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6027
6028 /* mfdcr */
gen_mfdcr(DisasContext * ctx)6029 static void gen_mfdcr(DisasContext *ctx)
6030 {
6031 #if defined(CONFIG_USER_ONLY)
6032 GEN_PRIV;
6033 #else
6034 TCGv dcrn;
6035
6036 CHK_SV;
6037 dcrn = tcg_const_tl(SPR(ctx->opcode));
6038 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6039 tcg_temp_free(dcrn);
6040 #endif /* defined(CONFIG_USER_ONLY) */
6041 }
6042
6043 /* mtdcr */
gen_mtdcr(DisasContext * ctx)6044 static void gen_mtdcr(DisasContext *ctx)
6045 {
6046 #if defined(CONFIG_USER_ONLY)
6047 GEN_PRIV;
6048 #else
6049 TCGv dcrn;
6050
6051 CHK_SV;
6052 dcrn = tcg_const_tl(SPR(ctx->opcode));
6053 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6054 tcg_temp_free(dcrn);
6055 #endif /* defined(CONFIG_USER_ONLY) */
6056 }
6057
6058 /* mfdcrx */
6059 /* XXX: not implemented on 440 ? */
gen_mfdcrx(DisasContext * ctx)6060 static void gen_mfdcrx(DisasContext *ctx)
6061 {
6062 #if defined(CONFIG_USER_ONLY)
6063 GEN_PRIV;
6064 #else
6065 CHK_SV;
6066 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6067 cpu_gpr[rA(ctx->opcode)]);
6068 /* Note: Rc update flag set leads to undefined state of Rc0 */
6069 #endif /* defined(CONFIG_USER_ONLY) */
6070 }
6071
6072 /* mtdcrx */
6073 /* XXX: not implemented on 440 ? */
gen_mtdcrx(DisasContext * ctx)6074 static void gen_mtdcrx(DisasContext *ctx)
6075 {
6076 #if defined(CONFIG_USER_ONLY)
6077 GEN_PRIV;
6078 #else
6079 CHK_SV;
6080 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6081 cpu_gpr[rS(ctx->opcode)]);
6082 /* Note: Rc update flag set leads to undefined state of Rc0 */
6083 #endif /* defined(CONFIG_USER_ONLY) */
6084 }
6085
6086 /* mfdcrux (PPC 460) : user-mode access to DCR */
gen_mfdcrux(DisasContext * ctx)6087 static void gen_mfdcrux(DisasContext *ctx)
6088 {
6089 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6090 cpu_gpr[rA(ctx->opcode)]);
6091 /* Note: Rc update flag set leads to undefined state of Rc0 */
6092 }
6093
6094 /* mtdcrux (PPC 460) : user-mode access to DCR */
gen_mtdcrux(DisasContext * ctx)6095 static void gen_mtdcrux(DisasContext *ctx)
6096 {
6097 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6098 cpu_gpr[rS(ctx->opcode)]);
6099 /* Note: Rc update flag set leads to undefined state of Rc0 */
6100 }
6101
6102 /* dccci */
gen_dccci(DisasContext * ctx)6103 static void gen_dccci(DisasContext *ctx)
6104 {
6105 CHK_SV;
6106 /* interpreted as no-op */
6107 }
6108
6109 /* dcread */
gen_dcread(DisasContext * ctx)6110 static void gen_dcread(DisasContext *ctx)
6111 {
6112 #if defined(CONFIG_USER_ONLY)
6113 GEN_PRIV;
6114 #else
6115 TCGv EA, val;
6116
6117 CHK_SV;
6118 gen_set_access_type(ctx, ACCESS_CACHE);
6119 EA = tcg_temp_new();
6120 gen_addr_reg_index(ctx, EA);
6121 val = tcg_temp_new();
6122 gen_qemu_ld32u(ctx, val, EA);
6123 tcg_temp_free(val);
6124 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6125 tcg_temp_free(EA);
6126 #endif /* defined(CONFIG_USER_ONLY) */
6127 }
6128
6129 /* icbt */
gen_icbt_40x(DisasContext * ctx)6130 static void gen_icbt_40x(DisasContext *ctx)
6131 {
6132 /* interpreted as no-op */
6133 /* XXX: specification say this is treated as a load by the MMU
6134 * but does not generate any exception
6135 */
6136 }
6137
6138 /* iccci */
gen_iccci(DisasContext * ctx)6139 static void gen_iccci(DisasContext *ctx)
6140 {
6141 CHK_SV;
6142 /* interpreted as no-op */
6143 }
6144
6145 /* icread */
gen_icread(DisasContext * ctx)6146 static void gen_icread(DisasContext *ctx)
6147 {
6148 CHK_SV;
6149 /* interpreted as no-op */
6150 }
6151
6152 /* rfci (supervisor only) */
gen_rfci_40x(DisasContext * ctx)6153 static void gen_rfci_40x(DisasContext *ctx)
6154 {
6155 #if defined(CONFIG_USER_ONLY)
6156 GEN_PRIV;
6157 #else
6158 CHK_SV;
6159 /* Restore CPU state */
6160 gen_helper_40x_rfci(cpu_env);
6161 gen_sync_exception(ctx);
6162 #endif /* defined(CONFIG_USER_ONLY) */
6163 }
6164
gen_rfci(DisasContext * ctx)6165 static void gen_rfci(DisasContext *ctx)
6166 {
6167 #if defined(CONFIG_USER_ONLY)
6168 GEN_PRIV;
6169 #else
6170 CHK_SV;
6171 /* Restore CPU state */
6172 gen_helper_rfci(cpu_env);
6173 gen_sync_exception(ctx);
6174 #endif /* defined(CONFIG_USER_ONLY) */
6175 }
6176
6177 /* BookE specific */
6178
6179 /* XXX: not implemented on 440 ? */
gen_rfdi(DisasContext * ctx)6180 static void gen_rfdi(DisasContext *ctx)
6181 {
6182 #if defined(CONFIG_USER_ONLY)
6183 GEN_PRIV;
6184 #else
6185 CHK_SV;
6186 /* Restore CPU state */
6187 gen_helper_rfdi(cpu_env);
6188 gen_sync_exception(ctx);
6189 #endif /* defined(CONFIG_USER_ONLY) */
6190 }
6191
6192 /* XXX: not implemented on 440 ? */
gen_rfmci(DisasContext * ctx)6193 static void gen_rfmci(DisasContext *ctx)
6194 {
6195 #if defined(CONFIG_USER_ONLY)
6196 GEN_PRIV;
6197 #else
6198 CHK_SV;
6199 /* Restore CPU state */
6200 gen_helper_rfmci(cpu_env);
6201 gen_sync_exception(ctx);
6202 #endif /* defined(CONFIG_USER_ONLY) */
6203 }
6204
6205 /* TLB management - PowerPC 405 implementation */
6206
6207 /* tlbre */
gen_tlbre_40x(DisasContext * ctx)6208 static void gen_tlbre_40x(DisasContext *ctx)
6209 {
6210 #if defined(CONFIG_USER_ONLY)
6211 GEN_PRIV;
6212 #else
6213 CHK_SV;
6214 switch (rB(ctx->opcode)) {
6215 case 0:
6216 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6217 cpu_gpr[rA(ctx->opcode)]);
6218 break;
6219 case 1:
6220 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6221 cpu_gpr[rA(ctx->opcode)]);
6222 break;
6223 default:
6224 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6225 break;
6226 }
6227 #endif /* defined(CONFIG_USER_ONLY) */
6228 }
6229
6230 /* tlbsx - tlbsx. */
gen_tlbsx_40x(DisasContext * ctx)6231 static void gen_tlbsx_40x(DisasContext *ctx)
6232 {
6233 #if defined(CONFIG_USER_ONLY)
6234 GEN_PRIV;
6235 #else
6236 TCGv t0;
6237
6238 CHK_SV;
6239 t0 = tcg_temp_new();
6240 gen_addr_reg_index(ctx, t0);
6241 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6242 tcg_temp_free(t0);
6243 if (Rc(ctx->opcode)) {
6244 TCGLabel *l1 = gen_new_label();
6245 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6246 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6247 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6248 gen_set_label(l1);
6249 }
6250 #endif /* defined(CONFIG_USER_ONLY) */
6251 }
6252
6253 /* tlbwe */
gen_tlbwe_40x(DisasContext * ctx)6254 static void gen_tlbwe_40x(DisasContext *ctx)
6255 {
6256 #if defined(CONFIG_USER_ONLY)
6257 GEN_PRIV;
6258 #else
6259 CHK_SV;
6260
6261 switch (rB(ctx->opcode)) {
6262 case 0:
6263 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6264 cpu_gpr[rS(ctx->opcode)]);
6265 break;
6266 case 1:
6267 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6268 cpu_gpr[rS(ctx->opcode)]);
6269 break;
6270 default:
6271 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6272 break;
6273 }
6274 #endif /* defined(CONFIG_USER_ONLY) */
6275 }
6276
6277 /* TLB management - PowerPC 440 implementation */
6278
6279 /* tlbre */
gen_tlbre_440(DisasContext * ctx)6280 static void gen_tlbre_440(DisasContext *ctx)
6281 {
6282 #if defined(CONFIG_USER_ONLY)
6283 GEN_PRIV;
6284 #else
6285 CHK_SV;
6286
6287 switch (rB(ctx->opcode)) {
6288 case 0:
6289 case 1:
6290 case 2:
6291 {
6292 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6293 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6294 t0, cpu_gpr[rA(ctx->opcode)]);
6295 tcg_temp_free_i32(t0);
6296 }
6297 break;
6298 default:
6299 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6300 break;
6301 }
6302 #endif /* defined(CONFIG_USER_ONLY) */
6303 }
6304
6305 /* tlbsx - tlbsx. */
gen_tlbsx_440(DisasContext * ctx)6306 static void gen_tlbsx_440(DisasContext *ctx)
6307 {
6308 #if defined(CONFIG_USER_ONLY)
6309 GEN_PRIV;
6310 #else
6311 TCGv t0;
6312
6313 CHK_SV;
6314 t0 = tcg_temp_new();
6315 gen_addr_reg_index(ctx, t0);
6316 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6317 tcg_temp_free(t0);
6318 if (Rc(ctx->opcode)) {
6319 TCGLabel *l1 = gen_new_label();
6320 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6321 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6322 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6323 gen_set_label(l1);
6324 }
6325 #endif /* defined(CONFIG_USER_ONLY) */
6326 }
6327
6328 /* tlbwe */
gen_tlbwe_440(DisasContext * ctx)6329 static void gen_tlbwe_440(DisasContext *ctx)
6330 {
6331 #if defined(CONFIG_USER_ONLY)
6332 GEN_PRIV;
6333 #else
6334 CHK_SV;
6335 switch (rB(ctx->opcode)) {
6336 case 0:
6337 case 1:
6338 case 2:
6339 {
6340 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6341 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6342 cpu_gpr[rS(ctx->opcode)]);
6343 tcg_temp_free_i32(t0);
6344 }
6345 break;
6346 default:
6347 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6348 break;
6349 }
6350 #endif /* defined(CONFIG_USER_ONLY) */
6351 }
6352
6353 /* TLB management - PowerPC BookE 2.06 implementation */
6354
6355 /* tlbre */
gen_tlbre_booke206(DisasContext * ctx)6356 static void gen_tlbre_booke206(DisasContext *ctx)
6357 {
6358 #if defined(CONFIG_USER_ONLY)
6359 GEN_PRIV;
6360 #else
6361 CHK_SV;
6362 gen_helper_booke206_tlbre(cpu_env);
6363 #endif /* defined(CONFIG_USER_ONLY) */
6364 }
6365
6366 /* tlbsx - tlbsx. */
gen_tlbsx_booke206(DisasContext * ctx)6367 static void gen_tlbsx_booke206(DisasContext *ctx)
6368 {
6369 #if defined(CONFIG_USER_ONLY)
6370 GEN_PRIV;
6371 #else
6372 TCGv t0;
6373
6374 CHK_SV;
6375 if (rA(ctx->opcode)) {
6376 t0 = tcg_temp_new();
6377 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6378 } else {
6379 t0 = tcg_const_tl(0);
6380 }
6381
6382 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6383 gen_helper_booke206_tlbsx(cpu_env, t0);
6384 tcg_temp_free(t0);
6385 #endif /* defined(CONFIG_USER_ONLY) */
6386 }
6387
6388 /* tlbwe */
gen_tlbwe_booke206(DisasContext * ctx)6389 static void gen_tlbwe_booke206(DisasContext *ctx)
6390 {
6391 #if defined(CONFIG_USER_ONLY)
6392 GEN_PRIV;
6393 #else
6394 CHK_SV;
6395 gen_helper_booke206_tlbwe(cpu_env);
6396 #endif /* defined(CONFIG_USER_ONLY) */
6397 }
6398
gen_tlbivax_booke206(DisasContext * ctx)6399 static void gen_tlbivax_booke206(DisasContext *ctx)
6400 {
6401 #if defined(CONFIG_USER_ONLY)
6402 GEN_PRIV;
6403 #else
6404 TCGv t0;
6405
6406 CHK_SV;
6407 t0 = tcg_temp_new();
6408 gen_addr_reg_index(ctx, t0);
6409 gen_helper_booke206_tlbivax(cpu_env, t0);
6410 tcg_temp_free(t0);
6411 #endif /* defined(CONFIG_USER_ONLY) */
6412 }
6413
gen_tlbilx_booke206(DisasContext * ctx)6414 static void gen_tlbilx_booke206(DisasContext *ctx)
6415 {
6416 #if defined(CONFIG_USER_ONLY)
6417 GEN_PRIV;
6418 #else
6419 TCGv t0;
6420
6421 CHK_SV;
6422 t0 = tcg_temp_new();
6423 gen_addr_reg_index(ctx, t0);
6424
6425 switch((ctx->opcode >> 21) & 0x3) {
6426 case 0:
6427 gen_helper_booke206_tlbilx0(cpu_env, t0);
6428 break;
6429 case 1:
6430 gen_helper_booke206_tlbilx1(cpu_env, t0);
6431 break;
6432 case 3:
6433 gen_helper_booke206_tlbilx3(cpu_env, t0);
6434 break;
6435 default:
6436 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6437 break;
6438 }
6439
6440 tcg_temp_free(t0);
6441 #endif /* defined(CONFIG_USER_ONLY) */
6442 }
6443
6444
6445 /* wrtee */
gen_wrtee(DisasContext * ctx)6446 static void gen_wrtee(DisasContext *ctx)
6447 {
6448 #if defined(CONFIG_USER_ONLY)
6449 GEN_PRIV;
6450 #else
6451 TCGv t0;
6452
6453 CHK_SV;
6454 t0 = tcg_temp_new();
6455 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6456 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6457 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6458 tcg_temp_free(t0);
6459 /* Stop translation to have a chance to raise an exception
6460 * if we just set msr_ee to 1
6461 */
6462 gen_stop_exception(ctx);
6463 #endif /* defined(CONFIG_USER_ONLY) */
6464 }
6465
6466 /* wrteei */
gen_wrteei(DisasContext * ctx)6467 static void gen_wrteei(DisasContext *ctx)
6468 {
6469 #if defined(CONFIG_USER_ONLY)
6470 GEN_PRIV;
6471 #else
6472 CHK_SV;
6473 if (ctx->opcode & 0x00008000) {
6474 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6475 /* Stop translation to have a chance to raise an exception */
6476 gen_stop_exception(ctx);
6477 } else {
6478 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6479 }
6480 #endif /* defined(CONFIG_USER_ONLY) */
6481 }
6482
6483 /* PowerPC 440 specific instructions */
6484
6485 /* dlmzb */
gen_dlmzb(DisasContext * ctx)6486 static void gen_dlmzb(DisasContext *ctx)
6487 {
6488 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6489 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6490 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6491 tcg_temp_free_i32(t0);
6492 }
6493
6494 /* mbar replaces eieio on 440 */
gen_mbar(DisasContext * ctx)6495 static void gen_mbar(DisasContext *ctx)
6496 {
6497 /* interpreted as no-op */
6498 }
6499
6500 /* msync replaces sync on 440 */
gen_msync_4xx(DisasContext * ctx)6501 static void gen_msync_4xx(DisasContext *ctx)
6502 {
6503 /* interpreted as no-op */
6504 }
6505
6506 /* icbt */
gen_icbt_440(DisasContext * ctx)6507 static void gen_icbt_440(DisasContext *ctx)
6508 {
6509 /* interpreted as no-op */
6510 /* XXX: specification say this is treated as a load by the MMU
6511 * but does not generate any exception
6512 */
6513 }
6514
6515 /* Embedded.Processor Control */
6516
gen_msgclr(DisasContext * ctx)6517 static void gen_msgclr(DisasContext *ctx)
6518 {
6519 #if defined(CONFIG_USER_ONLY)
6520 GEN_PRIV;
6521 #else
6522 CHK_HV;
6523 /* 64-bit server processors compliant with arch 2.x */
6524 if (ctx->insns_flags & PPC_SEGMENT_64B) {
6525 gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6526 } else {
6527 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6528 }
6529 #endif /* defined(CONFIG_USER_ONLY) */
6530 }
6531
gen_msgsnd(DisasContext * ctx)6532 static void gen_msgsnd(DisasContext *ctx)
6533 {
6534 #if defined(CONFIG_USER_ONLY)
6535 GEN_PRIV;
6536 #else
6537 CHK_HV;
6538 /* 64-bit server processors compliant with arch 2.x */
6539 if (ctx->insns_flags & PPC_SEGMENT_64B) {
6540 gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6541 } else {
6542 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6543 }
6544 #endif /* defined(CONFIG_USER_ONLY) */
6545 }
6546
gen_msgsync(DisasContext * ctx)6547 static void gen_msgsync(DisasContext *ctx)
6548 {
6549 #if defined(CONFIG_USER_ONLY)
6550 GEN_PRIV;
6551 #else
6552 CHK_HV;
6553 #endif /* defined(CONFIG_USER_ONLY) */
6554 /* interpreted as no-op */
6555 }
6556
6557 #if defined(TARGET_PPC64)
gen_maddld(DisasContext * ctx)6558 static void gen_maddld(DisasContext *ctx)
6559 {
6560 TCGv_i64 t1 = tcg_temp_new_i64();
6561
6562 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6563 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
6564 tcg_temp_free_i64(t1);
6565 }
6566
6567 /* maddhd maddhdu */
gen_maddhd_maddhdu(DisasContext * ctx)6568 static void gen_maddhd_maddhdu(DisasContext *ctx)
6569 {
6570 TCGv_i64 lo = tcg_temp_new_i64();
6571 TCGv_i64 hi = tcg_temp_new_i64();
6572 TCGv_i64 t1 = tcg_temp_new_i64();
6573
6574 if (Rc(ctx->opcode)) {
6575 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6576 cpu_gpr[rB(ctx->opcode)]);
6577 tcg_gen_movi_i64(t1, 0);
6578 } else {
6579 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6580 cpu_gpr[rB(ctx->opcode)]);
6581 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
6582 }
6583 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
6584 cpu_gpr[rC(ctx->opcode)], t1);
6585 tcg_temp_free_i64(lo);
6586 tcg_temp_free_i64(hi);
6587 tcg_temp_free_i64(t1);
6588 }
6589 #endif /* defined(TARGET_PPC64) */
6590
gen_tbegin(DisasContext * ctx)6591 static void gen_tbegin(DisasContext *ctx)
6592 {
6593 if (unlikely(!ctx->tm_enabled)) {
6594 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6595 return;
6596 }
6597 gen_helper_tbegin(cpu_env);
6598 }
6599
6600 #define GEN_TM_NOOP(name) \
6601 static inline void gen_##name(DisasContext *ctx) \
6602 { \
6603 if (unlikely(!ctx->tm_enabled)) { \
6604 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6605 return; \
6606 } \
6607 /* Because tbegin always fails in QEMU, these user \
6608 * space instructions all have a simple implementation: \
6609 * \
6610 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6611 * = 0b0 || 0b00 || 0b0 \
6612 */ \
6613 tcg_gen_movi_i32(cpu_crf[0], 0); \
6614 }
6615
6616 GEN_TM_NOOP(tend);
6617 GEN_TM_NOOP(tabort);
6618 GEN_TM_NOOP(tabortwc);
6619 GEN_TM_NOOP(tabortwci);
6620 GEN_TM_NOOP(tabortdc);
6621 GEN_TM_NOOP(tabortdci);
6622 GEN_TM_NOOP(tsr);
gen_cp_abort(DisasContext * ctx)6623 static inline void gen_cp_abort(DisasContext *ctx)
6624 {
6625 // Do Nothing
6626 }
6627
6628 #define GEN_CP_PASTE_NOOP(name) \
6629 static inline void gen_##name(DisasContext *ctx) \
6630 { \
6631 /* Generate invalid exception until \
6632 * we have an implementation of the copy \
6633 * paste facility \
6634 */ \
6635 gen_invalid(ctx); \
6636 }
6637
6638 GEN_CP_PASTE_NOOP(copy)
GEN_CP_PASTE_NOOP(paste)6639 GEN_CP_PASTE_NOOP(paste)
6640
6641 static void gen_tcheck(DisasContext *ctx)
6642 {
6643 if (unlikely(!ctx->tm_enabled)) {
6644 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6645 return;
6646 }
6647 /* Because tbegin always fails, the tcheck implementation
6648 * is simple:
6649 *
6650 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6651 * = 0b1 || 0b00 || 0b0
6652 */
6653 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
6654 }
6655
6656 #if defined(CONFIG_USER_ONLY)
6657 #define GEN_TM_PRIV_NOOP(name) \
6658 static inline void gen_##name(DisasContext *ctx) \
6659 { \
6660 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
6661 }
6662
6663 #else
6664
6665 #define GEN_TM_PRIV_NOOP(name) \
6666 static inline void gen_##name(DisasContext *ctx) \
6667 { \
6668 CHK_SV; \
6669 if (unlikely(!ctx->tm_enabled)) { \
6670 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6671 return; \
6672 } \
6673 /* Because tbegin always fails, the implementation is \
6674 * simple: \
6675 * \
6676 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6677 * = 0b0 || 0b00 | 0b0 \
6678 */ \
6679 tcg_gen_movi_i32(cpu_crf[0], 0); \
6680 }
6681
6682 #endif
6683
6684 GEN_TM_PRIV_NOOP(treclaim);
6685 GEN_TM_PRIV_NOOP(trechkpt);
6686
6687 #include "translate/fp-impl.inc.c"
6688
6689 #include "translate/vmx-impl.inc.c"
6690
6691 #include "translate/vsx-impl.inc.c"
6692
6693 #include "translate/dfp-impl.inc.c"
6694
6695 #include "translate/spe-impl.inc.c"
6696
6697 /* Handles lfdp, lxsd, lxssp */
gen_dform39(DisasContext * ctx)6698 static void gen_dform39(DisasContext *ctx)
6699 {
6700 switch (ctx->opcode & 0x3) {
6701 case 0: /* lfdp */
6702 if (ctx->insns_flags2 & PPC2_ISA205) {
6703 return gen_lfdp(ctx);
6704 }
6705 break;
6706 case 2: /* lxsd */
6707 if (ctx->insns_flags2 & PPC2_ISA300) {
6708 return gen_lxsd(ctx);
6709 }
6710 break;
6711 case 3: /* lxssp */
6712 if (ctx->insns_flags2 & PPC2_ISA300) {
6713 return gen_lxssp(ctx);
6714 }
6715 break;
6716 }
6717 return gen_invalid(ctx);
6718 }
6719
6720 /* handles stfdp, lxv, stxsd, stxssp lxvx */
gen_dform3D(DisasContext * ctx)6721 static void gen_dform3D(DisasContext *ctx)
6722 {
6723 if ((ctx->opcode & 3) == 1) { /* DQ-FORM */
6724 switch (ctx->opcode & 0x7) {
6725 case 1: /* lxv */
6726 if (ctx->insns_flags2 & PPC2_ISA300) {
6727 return gen_lxv(ctx);
6728 }
6729 break;
6730 case 5: /* stxv */
6731 if (ctx->insns_flags2 & PPC2_ISA300) {
6732 return gen_stxv(ctx);
6733 }
6734 break;
6735 }
6736 } else { /* DS-FORM */
6737 switch (ctx->opcode & 0x3) {
6738 case 0: /* stfdp */
6739 if (ctx->insns_flags2 & PPC2_ISA205) {
6740 return gen_stfdp(ctx);
6741 }
6742 break;
6743 case 2: /* stxsd */
6744 if (ctx->insns_flags2 & PPC2_ISA300) {
6745 return gen_stxsd(ctx);
6746 }
6747 break;
6748 case 3: /* stxssp */
6749 if (ctx->insns_flags2 & PPC2_ISA300) {
6750 return gen_stxssp(ctx);
6751 }
6752 break;
6753 }
6754 }
6755 return gen_invalid(ctx);
6756 }
6757
6758 static opcode_t opcodes[] = {
6759 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
6760 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
6761 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6762 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER),
6763 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6764 #if defined(TARGET_PPC64)
6765 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
6766 #endif
6767 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
6768 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
6769 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
6770 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6771 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6772 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6773 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6774 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6775 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
6776 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
6777 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
6778 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
6779 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6780 #if defined(TARGET_PPC64)
6781 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
6782 #endif
6783 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
6784 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
6785 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6786 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6787 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6788 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
6789 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
6790 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300),
6791 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6792 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300),
6793 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
6794 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
6795 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6796 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6797 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6798 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6799 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
6800 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
6801 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
6802 #if defined(TARGET_PPC64)
6803 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
6804 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
6805 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
6806 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300),
6807 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
6808 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
6809 #endif
6810 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6811 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6812 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6813 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
6814 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
6815 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
6816 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
6817 #if defined(TARGET_PPC64)
6818 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
6819 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
6820 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
6821 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
6822 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
6823 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
6824 PPC_NONE, PPC2_ISA300),
6825 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
6826 PPC_NONE, PPC2_ISA300),
6827 #endif
6828 #if defined(TARGET_PPC64)
6829 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
6830 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
6831 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
6832 #endif
6833 /* handles lfdp, lxsd, lxssp */
6834 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6835 /* handles stfdp, lxv, stxsd, stxssp, stxv */
6836 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6837 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6838 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6839 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
6840 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
6841 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
6842 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
6843 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO),
6844 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
6845 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6846 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6847 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
6848 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
6849 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300),
6850 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6851 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6852 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
6853 #if defined(TARGET_PPC64)
6854 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
6855 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300),
6856 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
6857 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
6858 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
6859 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
6860 #endif
6861 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
6862 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
6863 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300),
6864 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6865 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6866 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
6867 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
6868 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207),
6869 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
6870 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
6871 #if defined(TARGET_PPC64)
6872 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
6873 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6874 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6875 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6876 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6877 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6878 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
6879 #endif
6880 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
6881 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
6882 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6883 #if defined(TARGET_PPC64)
6884 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
6885 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
6886 #endif
6887 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
6888 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
6889 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
6890 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
6891 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
6892 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
6893 #if defined(TARGET_PPC64)
6894 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
6895 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
6896 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300),
6897 #endif
6898 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
6899 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
6900 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
6901 GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206),
6902 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
6903 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
6904 GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206),
6905 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
6906 GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206),
6907 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
6908 GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206),
6909 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
6910 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
6911 GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206),
6912 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
6913 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC),
6914 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
6915 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
6916 GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206),
6917 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
6918 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
6919 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
6920 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
6921 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
6922 #if defined(TARGET_PPC64)
6923 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
6924 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6925 PPC_SEGMENT_64B),
6926 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
6927 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6928 PPC_SEGMENT_64B),
6929 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
6930 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
6931 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
6932 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
6933 #endif
6934 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
6935 /* XXX Those instructions will need to be handled differently for
6936 * different ISA versions */
6937 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
6938 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
6939 GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300),
6940 GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300),
6941 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
6942 #if defined(TARGET_PPC64)
6943 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
6944 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
6945 GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
6946 GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6947 #endif
6948 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
6949 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
6950 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
6951 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
6952 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
6953 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
6954 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
6955 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
6956 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
6957 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
6958 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
6959 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6960 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
6961 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
6962 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
6963 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
6964 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
6965 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
6966 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
6967 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6968 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
6969 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
6970 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
6971 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
6972 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
6973 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
6974 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
6975 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
6976 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
6977 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
6978 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
6979 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
6980 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
6981 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
6982 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
6983 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
6984 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
6985 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
6986 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
6987 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
6988 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
6989 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
6990 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
6991 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
6992 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
6993 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
6994 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
6995 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
6996 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
6997 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6998 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6999 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
7000 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
7001 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
7002 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
7003 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
7004 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
7005 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
7006 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
7007 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
7008 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
7009 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
7010 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
7011 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
7012 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
7013 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
7014 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
7015 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
7016 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
7017 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
7018 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
7019 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
7020 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
7021 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
7022 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
7023 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
7024 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
7025 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
7026 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
7027 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
7028 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
7029 PPC_NONE, PPC2_BOOKE206),
7030 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
7031 PPC_NONE, PPC2_BOOKE206),
7032 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
7033 PPC_NONE, PPC2_BOOKE206),
7034 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
7035 PPC_NONE, PPC2_BOOKE206),
7036 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
7037 PPC_NONE, PPC2_BOOKE206),
7038 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
7039 PPC_NONE, PPC2_PRCNTL),
7040 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
7041 PPC_NONE, PPC2_PRCNTL),
7042 GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000,
7043 PPC_NONE, PPC2_PRCNTL),
7044 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
7045 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
7046 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
7047 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
7048 PPC_BOOKE, PPC2_BOOKE206),
7049 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
7050 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
7051 PPC_BOOKE, PPC2_BOOKE206),
7052 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001,
7053 PPC_440_SPEC),
7054 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
7055 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
7056 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
7057 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
7058 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
7059 #if defined(TARGET_PPC64)
7060 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
7061 PPC2_ISA300),
7062 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
7063 #endif
7064
7065 #undef GEN_INT_ARITH_ADD
7066 #undef GEN_INT_ARITH_ADD_CONST
7067 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
7068 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
7069 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
7070 add_ca, compute_ca, compute_ov) \
7071 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
7072 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
7073 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
7074 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
7075 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
7076 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
7077 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
7078 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
7079 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
7080 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
7081 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
7082
7083 #undef GEN_INT_ARITH_DIVW
7084 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
7085 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
7086 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
7087 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
7088 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
7089 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
7090 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
7091 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
7092 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
7093 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
7094 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
7095 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
7096
7097 #if defined(TARGET_PPC64)
7098 #undef GEN_INT_ARITH_DIVD
7099 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
7100 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
7101 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
7102 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
7103 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
7104 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
7105
7106 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
7107 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
7108 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
7109 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
7110 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
7111 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
7112
7113 #undef GEN_INT_ARITH_MUL_HELPER
7114 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
7115 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
7116 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
7117 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
7118 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
7119 #endif
7120
7121 #undef GEN_INT_ARITH_SUBF
7122 #undef GEN_INT_ARITH_SUBF_CONST
7123 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
7124 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
7125 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
7126 add_ca, compute_ca, compute_ov) \
7127 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
7128 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
7129 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
7130 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
7131 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
7132 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
7133 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
7134 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
7135 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
7136 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
7137 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
7138
7139 #undef GEN_LOGICAL1
7140 #undef GEN_LOGICAL2
7141 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
7142 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
7143 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
7144 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
7145 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
7146 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
7147 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
7148 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
7149 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
7150 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
7151 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
7152 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
7153 #if defined(TARGET_PPC64)
7154 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
7155 #endif
7156
7157 #if defined(TARGET_PPC64)
7158 #undef GEN_PPC64_R2
7159 #undef GEN_PPC64_R4
7160 #define GEN_PPC64_R2(name, opc1, opc2) \
7161 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
7162 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
7163 PPC_64B)
7164 #define GEN_PPC64_R4(name, opc1, opc2) \
7165 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
7166 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
7167 PPC_64B), \
7168 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
7169 PPC_64B), \
7170 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
7171 PPC_64B)
7172 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
7173 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
7174 GEN_PPC64_R4(rldic, 0x1E, 0x04),
7175 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
7176 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
7177 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
7178 #endif
7179
7180 #undef GEN_LD
7181 #undef GEN_LDU
7182 #undef GEN_LDUX
7183 #undef GEN_LDX_E
7184 #undef GEN_LDS
7185 #define GEN_LD(name, ldop, opc, type) \
7186 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
7187 #define GEN_LDU(name, ldop, opc, type) \
7188 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
7189 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
7190 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
7191 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
7192 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
7193 #define GEN_LDS(name, ldop, op, type) \
7194 GEN_LD(name, ldop, op | 0x20, type) \
7195 GEN_LDU(name, ldop, op | 0x21, type) \
7196 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
7197 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
7198
7199 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
7200 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
7201 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
7202 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
7203 #if defined(TARGET_PPC64)
7204 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
7205 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
7206 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B)
7207 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B)
7208 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
7209
7210 /* HV/P7 and later only */
7211 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
7212 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
7213 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
7214 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
7215 #endif
7216 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
7217 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
7218
7219 /* External PID based load */
7220 #undef GEN_LDEPX
7221 #define GEN_LDEPX(name, ldop, opc2, opc3) \
7222 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \
7223 0x00000001, PPC_NONE, PPC2_BOOKE206),
7224
7225 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)
7226 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08)
7227 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
7228 #if defined(TARGET_PPC64)
7229 GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)
7230 #endif
7231
7232 #undef GEN_ST
7233 #undef GEN_STU
7234 #undef GEN_STUX
7235 #undef GEN_STX_E
7236 #undef GEN_STS
7237 #define GEN_ST(name, stop, opc, type) \
7238 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
7239 #define GEN_STU(name, stop, opc, type) \
7240 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
7241 #define GEN_STUX(name, stop, opc2, opc3, type) \
7242 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
7243 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
7244 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2),
7245 #define GEN_STS(name, stop, op, type) \
7246 GEN_ST(name, stop, op | 0x20, type) \
7247 GEN_STU(name, stop, op | 0x21, type) \
7248 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
7249 GEN_STX(name, stop, 0x17, op | 0x00, type)
7250
7251 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
7252 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
7253 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
7254 #if defined(TARGET_PPC64)
7255 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B)
7256 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B)
7257 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
7258 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
7259 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
7260 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
7261 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
7262 #endif
7263 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
7264 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
7265
7266 #undef GEN_STEPX
7267 #define GEN_STEPX(name, ldop, opc2, opc3) \
7268 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \
7269 0x00000001, PPC_NONE, PPC2_BOOKE206),
7270
7271 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)
7272 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C)
7273 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)
7274 #if defined(TARGET_PPC64)
7275 GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04)
7276 #endif
7277
7278 #undef GEN_CRLOGIC
7279 #define GEN_CRLOGIC(name, tcg_op, opc) \
7280 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
7281 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
7282 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
7283 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
7284 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
7285 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
7286 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
7287 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
7288 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
7289
7290 #undef GEN_MAC_HANDLER
7291 #define GEN_MAC_HANDLER(name, opc2, opc3) \
7292 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
7293 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
7294 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
7295 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
7296 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
7297 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
7298 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
7299 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
7300 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
7301 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
7302 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
7303 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
7304 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
7305 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
7306 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
7307 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
7308 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
7309 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
7310 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
7311 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
7312 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
7313 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
7314 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
7315 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
7316 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
7317 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
7318 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
7319 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
7320 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
7321 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
7322 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
7323 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
7324 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
7325 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
7326 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
7327 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
7328 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
7329 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
7330 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
7331 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
7332 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
7333 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
7334 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
7335
7336 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
7337 PPC_NONE, PPC2_TM),
7338 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
7339 PPC_NONE, PPC2_TM),
7340 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
7341 PPC_NONE, PPC2_TM),
7342 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
7343 PPC_NONE, PPC2_TM),
7344 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
7345 PPC_NONE, PPC2_TM),
7346 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
7347 PPC_NONE, PPC2_TM),
7348 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
7349 PPC_NONE, PPC2_TM),
7350 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
7351 PPC_NONE, PPC2_TM),
7352 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
7353 PPC_NONE, PPC2_TM),
7354 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
7355 PPC_NONE, PPC2_TM),
7356 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
7357 PPC_NONE, PPC2_TM),
7358
7359 #include "translate/fp-ops.inc.c"
7360
7361 #include "translate/vmx-ops.inc.c"
7362
7363 #include "translate/vsx-ops.inc.c"
7364
7365 #include "translate/dfp-ops.inc.c"
7366
7367 #include "translate/spe-ops.inc.c"
7368 };
7369
7370 #include "helper_regs.h"
7371 #include "translate_init.inc.c"
7372
7373 /*****************************************************************************/
7374 /* Misc PowerPC helpers */
ppc_cpu_dump_state(CPUState * cs,FILE * f,fprintf_function cpu_fprintf,int flags)7375 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
7376 int flags)
7377 {
7378 #define RGPL 4
7379 #define RFPL 4
7380
7381 PowerPCCPU *cpu = POWERPC_CPU(cs);
7382 CPUPPCState *env = &cpu->env;
7383 int i;
7384
7385 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
7386 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
7387 env->nip, env->lr, env->ctr, cpu_read_xer(env),
7388 cs->cpu_index);
7389 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
7390 TARGET_FMT_lx " iidx %d didx %d\n",
7391 env->msr, env->spr[SPR_HID0],
7392 env->hflags, env->immu_idx, env->dmmu_idx);
7393 #if !defined(NO_TIMER_DUMP)
7394 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
7395 #if !defined(CONFIG_USER_ONLY)
7396 " DECR " TARGET_FMT_lu
7397 #endif
7398 "\n",
7399 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
7400 #if !defined(CONFIG_USER_ONLY)
7401 , cpu_ppc_load_decr(env)
7402 #endif
7403 );
7404 #endif
7405 for (i = 0; i < 32; i++) {
7406 if ((i & (RGPL - 1)) == 0)
7407 cpu_fprintf(f, "GPR%02d", i);
7408 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
7409 if ((i & (RGPL - 1)) == (RGPL - 1))
7410 cpu_fprintf(f, "\n");
7411 }
7412 cpu_fprintf(f, "CR ");
7413 for (i = 0; i < 8; i++)
7414 cpu_fprintf(f, "%01x", env->crf[i]);
7415 cpu_fprintf(f, " [");
7416 for (i = 0; i < 8; i++) {
7417 char a = '-';
7418 if (env->crf[i] & 0x08)
7419 a = 'L';
7420 else if (env->crf[i] & 0x04)
7421 a = 'G';
7422 else if (env->crf[i] & 0x02)
7423 a = 'E';
7424 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
7425 }
7426 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
7427 env->reserve_addr);
7428
7429 if (flags & CPU_DUMP_FPU) {
7430 for (i = 0; i < 32; i++) {
7431 if ((i & (RFPL - 1)) == 0) {
7432 cpu_fprintf(f, "FPR%02d", i);
7433 }
7434 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
7435 if ((i & (RFPL - 1)) == (RFPL - 1)) {
7436 cpu_fprintf(f, "\n");
7437 }
7438 }
7439 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
7440 }
7441
7442 #if !defined(CONFIG_USER_ONLY)
7443 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
7444 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
7445 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
7446 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
7447
7448 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
7449 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
7450 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
7451 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
7452
7453 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
7454 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
7455 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
7456 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
7457
7458 #if defined(TARGET_PPC64)
7459 if (env->excp_model == POWERPC_EXCP_POWER7 ||
7460 env->excp_model == POWERPC_EXCP_POWER8 ||
7461 env->excp_model == POWERPC_EXCP_POWER9) {
7462 cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
7463 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
7464 }
7465 #endif
7466 if (env->excp_model == POWERPC_EXCP_BOOKE) {
7467 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
7468 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
7469 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
7470 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
7471
7472 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7473 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
7474 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
7475 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
7476
7477 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
7478 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
7479 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
7480 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
7481
7482 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
7483 " EPR " TARGET_FMT_lx "\n",
7484 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
7485 env->spr[SPR_BOOKE_EPR]);
7486
7487 /* FSL-specific */
7488 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
7489 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
7490 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
7491 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
7492
7493 /*
7494 * IVORs are left out as they are large and do not change often --
7495 * they can be read with "p $ivor0", "p $ivor1", etc.
7496 */
7497 }
7498
7499 #if defined(TARGET_PPC64)
7500 if (env->flags & POWERPC_FLAG_CFAR) {
7501 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
7502 }
7503 #endif
7504
7505 if (env->spr_cb[SPR_LPCR].name)
7506 cpu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
7507
7508 switch (env->mmu_model) {
7509 case POWERPC_MMU_32B:
7510 case POWERPC_MMU_601:
7511 case POWERPC_MMU_SOFT_6xx:
7512 case POWERPC_MMU_SOFT_74xx:
7513 #if defined(TARGET_PPC64)
7514 case POWERPC_MMU_64B:
7515 case POWERPC_MMU_2_03:
7516 case POWERPC_MMU_2_06:
7517 case POWERPC_MMU_2_07:
7518 case POWERPC_MMU_3_00:
7519 #endif
7520 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
7521 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
7522 }
7523 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
7524 cpu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
7525 }
7526 cpu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
7527 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
7528 break;
7529 case POWERPC_MMU_BOOKE206:
7530 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
7531 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
7532 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
7533 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
7534
7535 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
7536 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7537 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
7538 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
7539
7540 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
7541 " TLB1CFG " TARGET_FMT_lx "\n",
7542 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
7543 env->spr[SPR_BOOKE_TLB1CFG]);
7544 break;
7545 default:
7546 break;
7547 }
7548 #endif
7549
7550 #undef RGPL
7551 #undef RFPL
7552 }
7553
ppc_cpu_dump_statistics(CPUState * cs,FILE * f,fprintf_function cpu_fprintf,int flags)7554 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
7555 fprintf_function cpu_fprintf, int flags)
7556 {
7557 #if defined(DO_PPC_STATISTICS)
7558 PowerPCCPU *cpu = POWERPC_CPU(cs);
7559 opc_handler_t **t1, **t2, **t3, *handler;
7560 int op1, op2, op3;
7561
7562 t1 = cpu->env.opcodes;
7563 for (op1 = 0; op1 < 64; op1++) {
7564 handler = t1[op1];
7565 if (is_indirect_opcode(handler)) {
7566 t2 = ind_table(handler);
7567 for (op2 = 0; op2 < 32; op2++) {
7568 handler = t2[op2];
7569 if (is_indirect_opcode(handler)) {
7570 t3 = ind_table(handler);
7571 for (op3 = 0; op3 < 32; op3++) {
7572 handler = t3[op3];
7573 if (handler->count == 0)
7574 continue;
7575 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
7576 "%016" PRIx64 " %" PRId64 "\n",
7577 op1, op2, op3, op1, (op3 << 5) | op2,
7578 handler->oname,
7579 handler->count, handler->count);
7580 }
7581 } else {
7582 if (handler->count == 0)
7583 continue;
7584 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
7585 "%016" PRIx64 " %" PRId64 "\n",
7586 op1, op2, op1, op2, handler->oname,
7587 handler->count, handler->count);
7588 }
7589 }
7590 } else {
7591 if (handler->count == 0)
7592 continue;
7593 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
7594 " %" PRId64 "\n",
7595 op1, op1, handler->oname,
7596 handler->count, handler->count);
7597 }
7598 }
7599 #endif
7600 }
7601
ppc_tr_init_disas_context(DisasContextBase * dcbase,CPUState * cs)7602 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
7603 {
7604 DisasContext *ctx = container_of(dcbase, DisasContext, base);
7605 CPUPPCState *env = cs->env_ptr;
7606 int bound;
7607
7608 ctx->exception = POWERPC_EXCP_NONE;
7609 ctx->spr_cb = env->spr_cb;
7610 ctx->pr = msr_pr;
7611 ctx->mem_idx = env->dmmu_idx;
7612 ctx->dr = msr_dr;
7613 #if !defined(CONFIG_USER_ONLY)
7614 ctx->hv = msr_hv || !env->has_hv_mode;
7615 #endif
7616 ctx->insns_flags = env->insns_flags;
7617 ctx->insns_flags2 = env->insns_flags2;
7618 ctx->access_type = -1;
7619 ctx->need_access_type = !(env->mmu_model & POWERPC_MMU_64B);
7620 ctx->le_mode = !!(env->hflags & (1 << MSR_LE));
7621 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE;
7622 ctx->flags = env->flags;
7623 #if defined(TARGET_PPC64)
7624 ctx->sf_mode = msr_is_64bit(env, env->msr);
7625 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
7626 #endif
7627 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B
7628 || env->mmu_model == POWERPC_MMU_601
7629 || (env->mmu_model & POWERPC_MMU_64B);
7630
7631 ctx->fpu_enabled = !!msr_fp;
7632 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
7633 ctx->spe_enabled = !!msr_spe;
7634 else
7635 ctx->spe_enabled = false;
7636 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
7637 ctx->altivec_enabled = !!msr_vr;
7638 else
7639 ctx->altivec_enabled = false;
7640 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
7641 ctx->vsx_enabled = !!msr_vsx;
7642 } else {
7643 ctx->vsx_enabled = false;
7644 }
7645 #if defined(TARGET_PPC64)
7646 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
7647 ctx->tm_enabled = !!msr_tm;
7648 } else {
7649 ctx->tm_enabled = false;
7650 }
7651 #endif
7652 ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE);
7653 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
7654 ctx->singlestep_enabled = CPU_SINGLE_STEP;
7655 else
7656 ctx->singlestep_enabled = 0;
7657 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
7658 ctx->singlestep_enabled |= CPU_BRANCH_STEP;
7659 if ((env->flags & POWERPC_FLAG_DE) && msr_de) {
7660 ctx->singlestep_enabled = 0;
7661 target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0];
7662 if (dbcr0 & DBCR0_ICMP) {
7663 ctx->singlestep_enabled |= CPU_SINGLE_STEP;
7664 }
7665 if (dbcr0 & DBCR0_BRT) {
7666 ctx->singlestep_enabled |= CPU_BRANCH_STEP;
7667 }
7668
7669 }
7670 if (unlikely(ctx->base.singlestep_enabled)) {
7671 ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP;
7672 }
7673 #if defined (DO_SINGLE_STEP) && 0
7674 /* Single step trace mode */
7675 msr_se = 1;
7676 #endif
7677
7678 bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
7679 ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
7680 }
7681
ppc_tr_tb_start(DisasContextBase * db,CPUState * cs)7682 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
7683 {
7684 }
7685
ppc_tr_insn_start(DisasContextBase * dcbase,CPUState * cs)7686 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
7687 {
7688 tcg_gen_insn_start(dcbase->pc_next);
7689 }
7690
ppc_tr_breakpoint_check(DisasContextBase * dcbase,CPUState * cs,const CPUBreakpoint * bp)7691 static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
7692 const CPUBreakpoint *bp)
7693 {
7694 DisasContext *ctx = container_of(dcbase, DisasContext, base);
7695
7696 gen_debug_exception(ctx);
7697 dcbase->is_jmp = DISAS_NORETURN;
7698 /* The address covered by the breakpoint must be included in
7699 [tb->pc, tb->pc + tb->size) in order to for it to be
7700 properly cleared -- thus we increment the PC here so that
7701 the logic setting tb->size below does the right thing. */
7702 ctx->base.pc_next += 4;
7703 return true;
7704 }
7705
ppc_tr_translate_insn(DisasContextBase * dcbase,CPUState * cs)7706 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
7707 {
7708 DisasContext *ctx = container_of(dcbase, DisasContext, base);
7709 CPUPPCState *env = cs->env_ptr;
7710 opc_handler_t **table, *handler;
7711
7712 LOG_DISAS("----------------\n");
7713 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
7714 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
7715
7716 if (unlikely(need_byteswap(ctx))) {
7717 ctx->opcode = bswap32(cpu_ldl_code(env, ctx->base.pc_next));
7718 } else {
7719 ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
7720 }
7721 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7722 ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode),
7723 opc3(ctx->opcode), opc4(ctx->opcode),
7724 ctx->le_mode ? "little" : "big");
7725 ctx->base.pc_next += 4;
7726 table = env->opcodes;
7727 handler = table[opc1(ctx->opcode)];
7728 if (is_indirect_opcode(handler)) {
7729 table = ind_table(handler);
7730 handler = table[opc2(ctx->opcode)];
7731 if (is_indirect_opcode(handler)) {
7732 table = ind_table(handler);
7733 handler = table[opc3(ctx->opcode)];
7734 if (is_indirect_opcode(handler)) {
7735 table = ind_table(handler);
7736 handler = table[opc4(ctx->opcode)];
7737 }
7738 }
7739 }
7740 /* Is opcode *REALLY* valid ? */
7741 if (unlikely(handler->handler == &gen_invalid)) {
7742 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
7743 "%02x - %02x - %02x - %02x (%08x) "
7744 TARGET_FMT_lx " %d\n",
7745 opc1(ctx->opcode), opc2(ctx->opcode),
7746 opc3(ctx->opcode), opc4(ctx->opcode),
7747 ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir);
7748 } else {
7749 uint32_t inval;
7750
7751 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE)
7752 && Rc(ctx->opcode))) {
7753 inval = handler->inval2;
7754 } else {
7755 inval = handler->inval1;
7756 }
7757
7758 if (unlikely((ctx->opcode & inval) != 0)) {
7759 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
7760 "%02x - %02x - %02x - %02x (%08x) "
7761 TARGET_FMT_lx "\n", ctx->opcode & inval,
7762 opc1(ctx->opcode), opc2(ctx->opcode),
7763 opc3(ctx->opcode), opc4(ctx->opcode),
7764 ctx->opcode, ctx->base.pc_next - 4);
7765 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7766 ctx->base.is_jmp = DISAS_NORETURN;
7767 return;
7768 }
7769 }
7770 (*(handler->handler))(ctx);
7771 #if defined(DO_PPC_STATISTICS)
7772 handler->count++;
7773 #endif
7774 /* Check trace mode exceptions */
7775 if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP &&
7776 (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) &&
7777 ctx->exception != POWERPC_SYSCALL &&
7778 ctx->exception != POWERPC_EXCP_TRAP &&
7779 ctx->exception != POWERPC_EXCP_BRANCH)) {
7780 uint32_t excp = gen_prep_dbgex(ctx, POWERPC_EXCP_TRACE);
7781 if (excp != POWERPC_EXCP_NONE)
7782 gen_exception_nip(ctx, excp, ctx->base.pc_next);
7783 }
7784
7785 if (tcg_check_temp_count()) {
7786 qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked "
7787 "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode),
7788 opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode);
7789 }
7790
7791 ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ?
7792 DISAS_NEXT : DISAS_NORETURN;
7793 }
7794
ppc_tr_tb_stop(DisasContextBase * dcbase,CPUState * cs)7795 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
7796 {
7797 DisasContext *ctx = container_of(dcbase, DisasContext, base);
7798
7799 if (ctx->exception == POWERPC_EXCP_NONE) {
7800 gen_goto_tb(ctx, 0, ctx->base.pc_next);
7801 } else if (ctx->exception != POWERPC_EXCP_BRANCH) {
7802 if (unlikely(ctx->base.singlestep_enabled)) {
7803 gen_debug_exception(ctx);
7804 }
7805 /* Generate the return instruction */
7806 tcg_gen_exit_tb(NULL, 0);
7807 }
7808 }
7809
ppc_tr_disas_log(const DisasContextBase * dcbase,CPUState * cs)7810 static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs)
7811 {
7812 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
7813 log_target_disas(cs, dcbase->pc_first, dcbase->tb->size);
7814 }
7815
7816 static const TranslatorOps ppc_tr_ops = {
7817 .init_disas_context = ppc_tr_init_disas_context,
7818 .tb_start = ppc_tr_tb_start,
7819 .insn_start = ppc_tr_insn_start,
7820 .breakpoint_check = ppc_tr_breakpoint_check,
7821 .translate_insn = ppc_tr_translate_insn,
7822 .tb_stop = ppc_tr_tb_stop,
7823 .disas_log = ppc_tr_disas_log,
7824 };
7825
gen_intermediate_code(CPUState * cs,struct TranslationBlock * tb)7826 void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
7827 {
7828 DisasContext ctx;
7829
7830 translator_loop(&ppc_tr_ops, &ctx.base, cs, tb);
7831 }
7832
restore_state_to_opc(CPUPPCState * env,TranslationBlock * tb,target_ulong * data)7833 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
7834 target_ulong *data)
7835 {
7836 env->nip = data[0];
7837 }
7838