1 /*
2 * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 *
25 * PCI bus layout on a real G5 (U3 based):
26 *
27 * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b]
28 * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150]
29 * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a]
30 * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
31 * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
32 * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045]
33 * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046]
34 * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047]
35 * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048]
36 * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049]
37 * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20)
38 * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
39 * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
40 * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
41 * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
42 * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04)
43 * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043]
44 * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042]
45 * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c]
46 * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240]
47 */
48
49 #include "qemu/osdep.h"
50 #include "qemu-common.h"
51 #include "qapi/error.h"
52 #include "hw/ppc/ppc.h"
53 #include "hw/qdev-properties.h"
54 #include "hw/ppc/mac.h"
55 #include "hw/input/adb.h"
56 #include "hw/ppc/mac_dbdma.h"
57 #include "hw/pci/pci.h"
58 #include "net/net.h"
59 #include "sysemu/sysemu.h"
60 #include "hw/boards.h"
61 #include "hw/nvram/fw_cfg.h"
62 #include "hw/char/escc.h"
63 #include "hw/misc/macio/macio.h"
64 #include "hw/ppc/openpic.h"
65 #include "hw/ide.h"
66 #include "hw/loader.h"
67 #include "hw/fw-path-provider.h"
68 #include "elf.h"
69 #include "qemu/error-report.h"
70 #include "sysemu/kvm.h"
71 #include "sysemu/reset.h"
72 #include "kvm_ppc.h"
73 #include "hw/usb.h"
74 #include "exec/address-spaces.h"
75 #include "hw/sysbus.h"
76 #include "trace.h"
77
78 /* FreeBSD headers define this */
79 #ifdef round_page
80 #undef round_page
81 #endif
82
83 #define MAX_IDE_BUS 2
84 #define CFG_ADDR 0xf0000510
85 #define TBFREQ (100UL * 1000UL * 1000UL)
86 #define CLOCKFREQ (900UL * 1000UL * 1000UL)
87 #define BUSFREQ (100UL * 1000UL * 1000UL)
88
89 #define NDRV_VGA_FILENAME "qemu_vga.ndrv"
90
91
fw_cfg_boot_set(void * opaque,const char * boot_device,Error ** errp)92 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
93 Error **errp)
94 {
95 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
96 }
97
translate_kernel_address(void * opaque,uint64_t addr)98 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
99 {
100 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
101 }
102
ppc_core99_reset(void * opaque)103 static void ppc_core99_reset(void *opaque)
104 {
105 PowerPCCPU *cpu = opaque;
106
107 cpu_reset(CPU(cpu));
108 /* 970 CPUs want to get their initial IP as part of their boot protocol */
109 cpu->env.nip = PROM_ADDR + 0x100;
110 }
111
112 /* PowerPC Mac99 hardware initialisation */
ppc_core99_init(MachineState * machine)113 static void ppc_core99_init(MachineState *machine)
114 {
115 ram_addr_t ram_size = machine->ram_size;
116 const char *kernel_filename = machine->kernel_filename;
117 const char *kernel_cmdline = machine->kernel_cmdline;
118 const char *initrd_filename = machine->initrd_filename;
119 const char *boot_device = machine->boot_order;
120 Core99MachineState *core99_machine = CORE99_MACHINE(machine);
121 PowerPCCPU *cpu = NULL;
122 CPUPPCState *env = NULL;
123 char *filename;
124 IrqLines *openpic_irqs;
125 int linux_boot, i, j, k;
126 MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1);
127 hwaddr kernel_base, initrd_base, cmdline_base = 0;
128 long kernel_size, initrd_size;
129 UNINHostState *uninorth_pci;
130 PCIBus *pci_bus;
131 NewWorldMacIOState *macio;
132 bool has_pmu, has_adb;
133 MACIOIDEState *macio_ide;
134 BusState *adb_bus;
135 MacIONVRAMState *nvr;
136 int bios_size;
137 int ppc_boot_device;
138 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
139 void *fw_cfg;
140 int machine_arch;
141 SysBusDevice *s;
142 DeviceState *dev, *pic_dev;
143 hwaddr nvram_addr = 0xFFF04000;
144 uint64_t tbfreq;
145 unsigned int smp_cpus = machine->smp.cpus;
146
147 linux_boot = (kernel_filename != NULL);
148
149 /* init CPUs */
150 for (i = 0; i < smp_cpus; i++) {
151 cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
152 env = &cpu->env;
153
154 /* Set time-base frequency to 100 Mhz */
155 cpu_ppc_tb_init(env, TBFREQ);
156 qemu_register_reset(ppc_core99_reset, cpu);
157 }
158
159 /* allocate RAM */
160 memory_region_allocate_system_memory(ram, NULL, "ppc_core99.ram", ram_size);
161 memory_region_add_subregion(get_system_memory(), 0, ram);
162
163 /* allocate and load BIOS */
164 memory_region_init_ram(bios, NULL, "ppc_core99.bios", BIOS_SIZE,
165 &error_fatal);
166
167 if (bios_name == NULL)
168 bios_name = PROM_FILENAME;
169 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
170 memory_region_set_readonly(bios, true);
171 memory_region_add_subregion(get_system_memory(), PROM_ADDR, bios);
172
173 /* Load OpenBIOS (ELF) */
174 if (filename) {
175 bios_size = load_elf(filename, NULL, NULL, NULL, NULL,
176 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
177
178 g_free(filename);
179 } else {
180 bios_size = -1;
181 }
182 if (bios_size < 0 || bios_size > BIOS_SIZE) {
183 error_report("could not load PowerPC bios '%s'", bios_name);
184 exit(1);
185 }
186
187 if (linux_boot) {
188 uint64_t lowaddr = 0;
189 int bswap_needed;
190
191 #ifdef BSWAP_NEEDED
192 bswap_needed = 1;
193 #else
194 bswap_needed = 0;
195 #endif
196 kernel_base = KERNEL_LOAD_ADDR;
197
198 kernel_size = load_elf(kernel_filename, NULL,
199 translate_kernel_address, NULL,
200 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE,
201 0, 0);
202 if (kernel_size < 0)
203 kernel_size = load_aout(kernel_filename, kernel_base,
204 ram_size - kernel_base, bswap_needed,
205 TARGET_PAGE_SIZE);
206 if (kernel_size < 0)
207 kernel_size = load_image_targphys(kernel_filename,
208 kernel_base,
209 ram_size - kernel_base);
210 if (kernel_size < 0) {
211 error_report("could not load kernel '%s'", kernel_filename);
212 exit(1);
213 }
214 /* load initrd */
215 if (initrd_filename) {
216 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
217 initrd_size = load_image_targphys(initrd_filename, initrd_base,
218 ram_size - initrd_base);
219 if (initrd_size < 0) {
220 error_report("could not load initial ram disk '%s'",
221 initrd_filename);
222 exit(1);
223 }
224 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size);
225 } else {
226 initrd_base = 0;
227 initrd_size = 0;
228 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
229 }
230 ppc_boot_device = 'm';
231 } else {
232 kernel_base = 0;
233 kernel_size = 0;
234 initrd_base = 0;
235 initrd_size = 0;
236 ppc_boot_device = '\0';
237 /* We consider that NewWorld PowerMac never have any floppy drive
238 * For now, OHW cannot boot from the network.
239 */
240 for (i = 0; boot_device[i] != '\0'; i++) {
241 if (boot_device[i] >= 'c' && boot_device[i] <= 'f') {
242 ppc_boot_device = boot_device[i];
243 break;
244 }
245 }
246 if (ppc_boot_device == '\0') {
247 error_report("No valid boot device for Mac99 machine");
248 exit(1);
249 }
250 }
251
252 /* UniN init */
253 dev = qdev_create(NULL, TYPE_UNI_NORTH);
254 qdev_init_nofail(dev);
255 s = SYS_BUS_DEVICE(dev);
256 memory_region_add_subregion(get_system_memory(), 0xf8000000,
257 sysbus_mmio_get_region(s, 0));
258
259 openpic_irqs = g_new0(IrqLines, smp_cpus);
260 for (i = 0; i < smp_cpus; i++) {
261 /* Mac99 IRQ connection between OpenPIC outputs pins
262 * and PowerPC input pins
263 */
264 switch (PPC_INPUT(env)) {
265 case PPC_FLAGS_INPUT_6xx:
266 openpic_irqs[i].irq[OPENPIC_OUTPUT_INT] =
267 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
268 openpic_irqs[i].irq[OPENPIC_OUTPUT_CINT] =
269 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
270 openpic_irqs[i].irq[OPENPIC_OUTPUT_MCK] =
271 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];
272 /* Not connected ? */
273 openpic_irqs[i].irq[OPENPIC_OUTPUT_DEBUG] = NULL;
274 /* Check this */
275 openpic_irqs[i].irq[OPENPIC_OUTPUT_RESET] =
276 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];
277 break;
278 #if defined(TARGET_PPC64)
279 case PPC_FLAGS_INPUT_970:
280 openpic_irqs[i].irq[OPENPIC_OUTPUT_INT] =
281 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
282 openpic_irqs[i].irq[OPENPIC_OUTPUT_CINT] =
283 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
284 openpic_irqs[i].irq[OPENPIC_OUTPUT_MCK] =
285 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];
286 /* Not connected ? */
287 openpic_irqs[i].irq[OPENPIC_OUTPUT_DEBUG] = NULL;
288 /* Check this */
289 openpic_irqs[i].irq[OPENPIC_OUTPUT_RESET] =
290 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
291 break;
292 #endif /* defined(TARGET_PPC64) */
293 default:
294 error_report("Bus model not supported on mac99 machine");
295 exit(1);
296 }
297 }
298
299 pic_dev = qdev_create(NULL, TYPE_OPENPIC);
300 qdev_prop_set_uint32(pic_dev, "model", OPENPIC_MODEL_KEYLARGO);
301 qdev_init_nofail(pic_dev);
302 s = SYS_BUS_DEVICE(pic_dev);
303 k = 0;
304 for (i = 0; i < smp_cpus; i++) {
305 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
306 sysbus_connect_irq(s, k++, openpic_irqs[i].irq[j]);
307 }
308 }
309 g_free(openpic_irqs);
310
311 if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
312 /* 970 gets a U3 bus */
313 /* Uninorth AGP bus */
314 dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE);
315 object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
316 &error_abort);
317 qdev_init_nofail(dev);
318 uninorth_pci = U3_AGP_HOST_BRIDGE(dev);
319 s = SYS_BUS_DEVICE(dev);
320 /* PCI hole */
321 memory_region_add_subregion(get_system_memory(), 0x80000000ULL,
322 sysbus_mmio_get_region(s, 2));
323 /* Register 8 MB of ISA IO space */
324 memory_region_add_subregion(get_system_memory(), 0xf2000000,
325 sysbus_mmio_get_region(s, 3));
326 sysbus_mmio_map(s, 0, 0xf0800000);
327 sysbus_mmio_map(s, 1, 0xf0c00000);
328
329 machine_arch = ARCH_MAC99_U3;
330 } else {
331 /* Use values found on a real PowerMac */
332 /* Uninorth AGP bus */
333 dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
334 object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
335 &error_abort);
336 qdev_init_nofail(dev);
337 s = SYS_BUS_DEVICE(dev);
338 sysbus_mmio_map(s, 0, 0xf0800000);
339 sysbus_mmio_map(s, 1, 0xf0c00000);
340
341 /* Uninorth internal bus */
342 dev = qdev_create(NULL, TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
343 object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
344 &error_abort);
345 qdev_init_nofail(dev);
346 s = SYS_BUS_DEVICE(dev);
347 sysbus_mmio_map(s, 0, 0xf4800000);
348 sysbus_mmio_map(s, 1, 0xf4c00000);
349
350 /* Uninorth main bus */
351 dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
352 qdev_prop_set_uint32(dev, "ofw-addr", 0xf2000000);
353 object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
354 &error_abort);
355 qdev_init_nofail(dev);
356 uninorth_pci = UNI_NORTH_PCI_HOST_BRIDGE(dev);
357 s = SYS_BUS_DEVICE(dev);
358 /* PCI hole */
359 memory_region_add_subregion(get_system_memory(), 0x80000000ULL,
360 sysbus_mmio_get_region(s, 2));
361 /* Register 8 MB of ISA IO space */
362 memory_region_add_subregion(get_system_memory(), 0xf2000000,
363 sysbus_mmio_get_region(s, 3));
364 sysbus_mmio_map(s, 0, 0xf2800000);
365 sysbus_mmio_map(s, 1, 0xf2c00000);
366
367 machine_arch = ARCH_MAC99;
368 }
369
370 machine->usb |= defaults_enabled() && !machine->usb_disabled;
371 has_pmu = (core99_machine->via_config != CORE99_VIA_CONFIG_CUDA);
372 has_adb = (core99_machine->via_config == CORE99_VIA_CONFIG_CUDA ||
373 core99_machine->via_config == CORE99_VIA_CONFIG_PMU_ADB);
374
375 /* Timebase Frequency */
376 if (kvm_enabled()) {
377 tbfreq = kvmppc_get_tbfreq();
378 } else {
379 tbfreq = TBFREQ;
380 }
381
382 /* init basic PC hardware */
383 pci_bus = PCI_HOST_BRIDGE(uninorth_pci)->bus;
384
385 /* MacIO */
386 macio = NEWWORLD_MACIO(pci_create(pci_bus, -1, TYPE_NEWWORLD_MACIO));
387 dev = DEVICE(macio);
388 qdev_prop_set_uint64(dev, "frequency", tbfreq);
389 qdev_prop_set_bit(dev, "has-pmu", has_pmu);
390 qdev_prop_set_bit(dev, "has-adb", has_adb);
391 object_property_set_link(OBJECT(macio), OBJECT(pic_dev), "pic",
392 &error_abort);
393 qdev_init_nofail(dev);
394
395 /* We only emulate 2 out of 3 IDE controllers for now */
396 ide_drive_get(hd, ARRAY_SIZE(hd));
397
398 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
399 "ide[0]"));
400 macio_ide_init_drives(macio_ide, hd);
401
402 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
403 "ide[1]"));
404 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
405
406 if (has_adb) {
407 if (has_pmu) {
408 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "pmu"));
409 } else {
410 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
411 }
412
413 adb_bus = qdev_get_child_bus(dev, "adb.0");
414 dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
415 qdev_prop_set_bit(dev, "disable-direct-reg3-writes", true);
416 qdev_init_nofail(dev);
417
418 dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
419 qdev_prop_set_bit(dev, "disable-direct-reg3-writes", true);
420 qdev_init_nofail(dev);
421 }
422
423 if (machine->usb) {
424 pci_create_simple(pci_bus, -1, "pci-ohci");
425
426 /* U3 needs to use USB for input because Linux doesn't support via-cuda
427 on PPC64 */
428 if (!has_adb || machine_arch == ARCH_MAC99_U3) {
429 USBBus *usb_bus = usb_bus_find(-1);
430
431 usb_create_simple(usb_bus, "usb-kbd");
432 usb_create_simple(usb_bus, "usb-mouse");
433 }
434 }
435
436 pci_vga_init(pci_bus);
437
438 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) {
439 graphic_depth = 15;
440 }
441
442 for (i = 0; i < nb_nics; i++) {
443 pci_nic_init_nofail(&nd_table[i], pci_bus, "sungem", NULL);
444 }
445
446 /* The NewWorld NVRAM is not located in the MacIO device */
447 if (kvm_enabled() && qemu_real_host_page_size > 4096) {
448 /* We can't combine read-write and read-only in a single page, so
449 move the NVRAM out of ROM again for KVM */
450 nvram_addr = 0xFFE00000;
451 }
452 dev = qdev_create(NULL, TYPE_MACIO_NVRAM);
453 qdev_prop_set_uint32(dev, "size", 0x2000);
454 qdev_prop_set_uint32(dev, "it_shift", 1);
455 qdev_init_nofail(dev);
456 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr);
457 nvr = MACIO_NVRAM(dev);
458 pmac_format_nvram_partition(nvr, 0x2000);
459 /* No PCI init: the BIOS will do it */
460
461 dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
462 fw_cfg = FW_CFG(dev);
463 qdev_prop_set_uint32(dev, "data_width", 1);
464 qdev_prop_set_bit(dev, "dma_enabled", false);
465 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
466 OBJECT(fw_cfg), NULL);
467 qdev_init_nofail(dev);
468 s = SYS_BUS_DEVICE(dev);
469 sysbus_mmio_map(s, 0, CFG_ADDR);
470 sysbus_mmio_map(s, 1, CFG_ADDR + 2);
471
472 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
473 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
474 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
475 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch);
476 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
477 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
478 if (kernel_cmdline) {
479 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
480 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
481 } else {
482 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
483 }
484 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
485 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
486 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
487
488 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
489 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
490 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
491
492 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_VIACONFIG, core99_machine->via_config);
493
494 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
495 if (kvm_enabled()) {
496 uint8_t *hypercall;
497
498 hypercall = g_malloc(16);
499 kvmppc_get_hypercall(env, hypercall, 16);
500 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
501 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
502 }
503 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq);
504 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */
505 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ);
506 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ);
507 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_NVRAM_ADDR, nvram_addr);
508
509 /* MacOS NDRV VGA driver */
510 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME);
511 if (filename) {
512 gchar *ndrv_file;
513 gsize ndrv_size;
514
515 if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) {
516 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size);
517 }
518 g_free(filename);
519 }
520
521 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
522 }
523
524 /*
525 * Implementation of an interface to adjust firmware path
526 * for the bootindex property handling.
527 */
core99_fw_dev_path(FWPathProvider * p,BusState * bus,DeviceState * dev)528 static char *core99_fw_dev_path(FWPathProvider *p, BusState *bus,
529 DeviceState *dev)
530 {
531 PCIDevice *pci;
532 IDEBus *ide_bus;
533 IDEState *ide_s;
534 MACIOIDEState *macio_ide;
535
536 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-newworld")) {
537 pci = PCI_DEVICE(dev);
538 return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn));
539 }
540
541 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) {
542 macio_ide = MACIO_IDE(dev);
543 return g_strdup_printf("ata-3@%x", macio_ide->addr);
544 }
545
546 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-drive")) {
547 ide_bus = IDE_BUS(qdev_get_parent_bus(dev));
548 ide_s = idebus_active_if(ide_bus);
549
550 if (ide_s->drive_kind == IDE_CD) {
551 return g_strdup("cdrom");
552 }
553
554 return g_strdup("disk");
555 }
556
557 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) {
558 return g_strdup("disk");
559 }
560
561 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) {
562 return g_strdup("cdrom");
563 }
564
565 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) {
566 return g_strdup("disk");
567 }
568
569 return NULL;
570 }
core99_kvm_type(MachineState * machine,const char * arg)571 static int core99_kvm_type(MachineState *machine, const char *arg)
572 {
573 /* Always force PR KVM */
574 return 2;
575 }
576
core99_machine_class_init(ObjectClass * oc,void * data)577 static void core99_machine_class_init(ObjectClass *oc, void *data)
578 {
579 MachineClass *mc = MACHINE_CLASS(oc);
580 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
581
582 mc->desc = "Mac99 based PowerMAC";
583 mc->init = ppc_core99_init;
584 mc->block_default_type = IF_IDE;
585 mc->max_cpus = MAX_CPUS;
586 mc->default_boot_order = "cd";
587 mc->default_display = "std";
588 mc->kvm_type = core99_kvm_type;
589 #ifdef TARGET_PPC64
590 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("970fx_v3.1");
591 #else
592 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7400_v2.9");
593 #endif
594 mc->ignore_boot_device_suffixes = true;
595 fwc->get_dev_path = core99_fw_dev_path;
596 }
597
core99_get_via_config(Object * obj,Error ** errp)598 static char *core99_get_via_config(Object *obj, Error **errp)
599 {
600 Core99MachineState *cms = CORE99_MACHINE(obj);
601
602 switch (cms->via_config) {
603 default:
604 case CORE99_VIA_CONFIG_CUDA:
605 return g_strdup("cuda");
606
607 case CORE99_VIA_CONFIG_PMU:
608 return g_strdup("pmu");
609
610 case CORE99_VIA_CONFIG_PMU_ADB:
611 return g_strdup("pmu-adb");
612 }
613 }
614
core99_set_via_config(Object * obj,const char * value,Error ** errp)615 static void core99_set_via_config(Object *obj, const char *value, Error **errp)
616 {
617 Core99MachineState *cms = CORE99_MACHINE(obj);
618
619 if (!strcmp(value, "cuda")) {
620 cms->via_config = CORE99_VIA_CONFIG_CUDA;
621 } else if (!strcmp(value, "pmu")) {
622 cms->via_config = CORE99_VIA_CONFIG_PMU;
623 } else if (!strcmp(value, "pmu-adb")) {
624 cms->via_config = CORE99_VIA_CONFIG_PMU_ADB;
625 } else {
626 error_setg(errp, "Invalid via value");
627 error_append_hint(errp, "Valid values are cuda, pmu, pmu-adb.\n");
628 }
629 }
630
core99_instance_init(Object * obj)631 static void core99_instance_init(Object *obj)
632 {
633 Core99MachineState *cms = CORE99_MACHINE(obj);
634
635 /* Default via_config is CORE99_VIA_CONFIG_CUDA */
636 cms->via_config = CORE99_VIA_CONFIG_CUDA;
637 object_property_add_str(obj, "via", core99_get_via_config,
638 core99_set_via_config, NULL);
639 object_property_set_description(obj, "via",
640 "Set VIA configuration. "
641 "Valid values are cuda, pmu and pmu-adb",
642 NULL);
643
644 return;
645 }
646
647 static const TypeInfo core99_machine_info = {
648 .name = MACHINE_TYPE_NAME("mac99"),
649 .parent = TYPE_MACHINE,
650 .class_init = core99_machine_class_init,
651 .instance_init = core99_instance_init,
652 .instance_size = sizeof(Core99MachineState),
653 .interfaces = (InterfaceInfo[]) {
654 { TYPE_FW_PATH_PROVIDER },
655 { }
656 },
657 };
658
mac_machine_register_types(void)659 static void mac_machine_register_types(void)
660 {
661 type_register_static(&core99_machine_info);
662 }
663
664 type_init(mac_machine_register_types)
665