1 /*
2 * OSTimer device simulation in PKUnity SoC
3 *
4 * Copyright (C) 2010-2012 Guan Xuetao
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation, or any later version.
9 * See the COPYING file in the top-level directory.
10 */
11
12 #include "qemu/osdep.h"
13 #include "hw/sysbus.h"
14 #include "hw/irq.h"
15 #include "hw/ptimer.h"
16 #include "qemu/module.h"
17
18 #undef DEBUG_PUV3
19 #include "hw/unicore32/puv3.h"
20
21 #define TYPE_PUV3_OST "puv3_ost"
22 #define PUV3_OST(obj) OBJECT_CHECK(PUV3OSTState, (obj), TYPE_PUV3_OST)
23
24 /* puv3 ostimer implementation. */
25 typedef struct PUV3OSTState {
26 SysBusDevice parent_obj;
27
28 MemoryRegion iomem;
29 qemu_irq irq;
30 ptimer_state *ptimer;
31
32 uint32_t reg_OSMR0;
33 uint32_t reg_OSCR;
34 uint32_t reg_OSSR;
35 uint32_t reg_OIER;
36 } PUV3OSTState;
37
puv3_ost_read(void * opaque,hwaddr offset,unsigned size)38 static uint64_t puv3_ost_read(void *opaque, hwaddr offset,
39 unsigned size)
40 {
41 PUV3OSTState *s = opaque;
42 uint32_t ret = 0;
43
44 switch (offset) {
45 case 0x10: /* Counter Register */
46 ret = s->reg_OSMR0 - (uint32_t)ptimer_get_count(s->ptimer);
47 break;
48 case 0x14: /* Status Register */
49 ret = s->reg_OSSR;
50 break;
51 case 0x1c: /* Interrupt Enable Register */
52 ret = s->reg_OIER;
53 break;
54 default:
55 DPRINTF("Bad offset %x\n", (int)offset);
56 }
57 DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
58 return ret;
59 }
60
puv3_ost_write(void * opaque,hwaddr offset,uint64_t value,unsigned size)61 static void puv3_ost_write(void *opaque, hwaddr offset,
62 uint64_t value, unsigned size)
63 {
64 PUV3OSTState *s = opaque;
65
66 DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
67 switch (offset) {
68 case 0x00: /* Match Register 0 */
69 ptimer_transaction_begin(s->ptimer);
70 s->reg_OSMR0 = value;
71 if (s->reg_OSMR0 > s->reg_OSCR) {
72 ptimer_set_count(s->ptimer, s->reg_OSMR0 - s->reg_OSCR);
73 } else {
74 ptimer_set_count(s->ptimer, s->reg_OSMR0 +
75 (0xffffffff - s->reg_OSCR));
76 }
77 ptimer_run(s->ptimer, 2);
78 ptimer_transaction_commit(s->ptimer);
79 break;
80 case 0x14: /* Status Register */
81 assert(value == 0);
82 if (s->reg_OSSR) {
83 s->reg_OSSR = value;
84 qemu_irq_lower(s->irq);
85 }
86 break;
87 case 0x1c: /* Interrupt Enable Register */
88 s->reg_OIER = value;
89 break;
90 default:
91 DPRINTF("Bad offset %x\n", (int)offset);
92 }
93 }
94
95 static const MemoryRegionOps puv3_ost_ops = {
96 .read = puv3_ost_read,
97 .write = puv3_ost_write,
98 .impl = {
99 .min_access_size = 4,
100 .max_access_size = 4,
101 },
102 .endianness = DEVICE_NATIVE_ENDIAN,
103 };
104
puv3_ost_tick(void * opaque)105 static void puv3_ost_tick(void *opaque)
106 {
107 PUV3OSTState *s = opaque;
108
109 DPRINTF("ost hit when ptimer counter from 0x%x to 0x%x!\n",
110 s->reg_OSCR, s->reg_OSMR0);
111
112 s->reg_OSCR = s->reg_OSMR0;
113 if (s->reg_OIER) {
114 s->reg_OSSR = 1;
115 qemu_irq_raise(s->irq);
116 }
117 }
118
puv3_ost_realize(DeviceState * dev,Error ** errp)119 static void puv3_ost_realize(DeviceState *dev, Error **errp)
120 {
121 PUV3OSTState *s = PUV3_OST(dev);
122 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
123
124 s->reg_OIER = 0;
125 s->reg_OSSR = 0;
126 s->reg_OSMR0 = 0;
127 s->reg_OSCR = 0;
128
129 sysbus_init_irq(sbd, &s->irq);
130
131 s->ptimer = ptimer_init(puv3_ost_tick, s, PTIMER_POLICY_DEFAULT);
132 ptimer_transaction_begin(s->ptimer);
133 ptimer_set_freq(s->ptimer, 50 * 1000 * 1000);
134 ptimer_transaction_commit(s->ptimer);
135
136 memory_region_init_io(&s->iomem, OBJECT(s), &puv3_ost_ops, s, "puv3_ost",
137 PUV3_REGS_OFFSET);
138 sysbus_init_mmio(sbd, &s->iomem);
139 }
140
puv3_ost_class_init(ObjectClass * klass,void * data)141 static void puv3_ost_class_init(ObjectClass *klass, void *data)
142 {
143 DeviceClass *dc = DEVICE_CLASS(klass);
144
145 dc->realize = puv3_ost_realize;
146 }
147
148 static const TypeInfo puv3_ost_info = {
149 .name = TYPE_PUV3_OST,
150 .parent = TYPE_SYS_BUS_DEVICE,
151 .instance_size = sizeof(PUV3OSTState),
152 .class_init = puv3_ost_class_init,
153 };
154
puv3_ost_register_type(void)155 static void puv3_ost_register_type(void)
156 {
157 type_register_static(&puv3_ost_info);
158 }
159
160 type_init(puv3_ost_register_type)
161