1 /** @file
2   Internal function to get spin lock alignment.
3 
4   Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
5   SPDX-License-Identifier: BSD-2-Clause-Patent
6 
7 **/
8 
9 #include "BaseSynchronizationLibInternals.h"
10 
11 /**
12   Internal function to retrieve the architecture specific spin lock alignment
13   requirements for optimal spin lock performance.
14 
15   @return The architecture specific spin lock alignment.
16 
17 **/
18 UINTN
InternalGetSpinLockProperties(VOID)19 InternalGetSpinLockProperties (
20   VOID
21   )
22 {
23   UINT32  RegEax;
24   UINT32  RegEbx;
25   UINTN   FamilyId;
26   UINTN   ModelId;
27   UINTN   CacheLineSize;
28 
29   //
30   // Retrieve CPUID Version Information
31   //
32   AsmCpuid (0x01, &RegEax, &RegEbx, NULL, NULL);
33   //
34   // EBX: Bits 15 - 08: CLFLUSH line size (Value * 8 = cache line size)
35   //
36   CacheLineSize = ((RegEbx >> 8) & 0xff) * 8;
37   //
38   // Retrieve CPU Family and Model
39   //
40   FamilyId = (RegEax >> 8) & 0xf;
41   ModelId  = (RegEax >> 4) & 0xf;
42   if (FamilyId == 0x0f) {
43     //
44     // In processors based on Intel NetBurst microarchitecture, use two cache lines
45     //
46     ModelId = ModelId | ((RegEax >> 12) & 0xf0);
47     if (ModelId <= 0x04 || ModelId == 0x06) {
48       CacheLineSize *= 2;
49     }
50   }
51 
52   if (CacheLineSize < 32) {
53     CacheLineSize = 32;
54   }
55 
56   return CacheLineSize;
57 }
58 
59