1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
5 * Original from Linux kernel 3.0.1
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 #include <ipxe/io.h>
21
22 #include "hw.h"
23
24 #define AR_BufLen 0x00000fff
25
ar9002_hw_rx_enable(struct ath_hw * ah)26 static void ar9002_hw_rx_enable(struct ath_hw *ah)
27 {
28 REG_WRITE(ah, AR_CR, AR_CR_RXE);
29 }
30
ar9002_hw_set_desc_link(void * ds,u32 ds_link)31 static void ar9002_hw_set_desc_link(void *ds, u32 ds_link)
32 {
33 ((struct ath_desc*) ds)->ds_link = ds_link;
34 }
35
ar9002_hw_get_desc_link(void * ds,u32 ** ds_link)36 static void ar9002_hw_get_desc_link(void *ds, u32 **ds_link)
37 {
38 *ds_link = &((struct ath_desc *)ds)->ds_link;
39 }
40
ar9002_hw_get_isr(struct ath_hw * ah,enum ath9k_int * masked)41 static int ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
42 {
43 u32 isr = 0;
44 u32 mask2 = 0;
45 struct ath9k_hw_capabilities *pCap = &ah->caps;
46 u32 sync_cause = 0;
47 int fatal_int = 0;
48
49 if (!AR_SREV_9100(ah) && (ah->ah_ier & AR_IER_ENABLE)) {
50 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
51 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
52 == AR_RTC_STATUS_ON) {
53 isr = REG_READ(ah, AR_ISR);
54 }
55 }
56
57 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
58 AR_INTR_SYNC_DEFAULT;
59
60 *masked = 0;
61
62 if (!isr && !sync_cause)
63 return 0;
64 } else {
65 *masked = 0;
66 isr = REG_READ(ah, AR_ISR);
67 }
68
69 if (isr) {
70 if (isr & AR_ISR_BCNMISC) {
71 u32 isr2;
72 isr2 = REG_READ(ah, AR_ISR_S2);
73 if (isr2 & AR_ISR_S2_TIM)
74 mask2 |= ATH9K_INT_TIM;
75 if (isr2 & AR_ISR_S2_DTIM)
76 mask2 |= ATH9K_INT_DTIM;
77 if (isr2 & AR_ISR_S2_DTIMSYNC)
78 mask2 |= ATH9K_INT_DTIMSYNC;
79 if (isr2 & (AR_ISR_S2_CABEND))
80 mask2 |= ATH9K_INT_CABEND;
81 if (isr2 & AR_ISR_S2_GTT)
82 mask2 |= ATH9K_INT_GTT;
83 if (isr2 & AR_ISR_S2_CST)
84 mask2 |= ATH9K_INT_CST;
85 if (isr2 & AR_ISR_S2_TSFOOR)
86 mask2 |= ATH9K_INT_TSFOOR;
87 }
88
89 isr = REG_READ(ah, AR_ISR_RAC);
90 if (isr == 0xffffffff) {
91 *masked = 0;
92 return 0;
93 }
94
95 *masked = isr & ATH9K_INT_COMMON;
96
97 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM |
98 AR_ISR_RXOK | AR_ISR_RXERR))
99 *masked |= ATH9K_INT_RX;
100
101 if (isr &
102 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
103 AR_ISR_TXEOL)) {
104 u32 s0_s, s1_s;
105
106 *masked |= ATH9K_INT_TX;
107
108 s0_s = REG_READ(ah, AR_ISR_S0_S);
109 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
110 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
111
112 s1_s = REG_READ(ah, AR_ISR_S1_S);
113 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
114 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
115 }
116
117 if (isr & AR_ISR_RXORN) {
118 DBG("ath9k: "
119 "receive FIFO overrun interrupt\n");
120 }
121
122 *masked |= mask2;
123 }
124
125 if (AR_SREV_9100(ah))
126 return 1;
127
128 if (isr & AR_ISR_GENTMR) {
129 u32 s5_s;
130
131 s5_s = REG_READ(ah, AR_ISR_S5_S);
132 ah->intr_gen_timer_trigger =
133 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
134
135 ah->intr_gen_timer_thresh =
136 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
137
138 if (ah->intr_gen_timer_trigger)
139 *masked |= ATH9K_INT_GENTIMER;
140
141 if ((s5_s & AR_ISR_S5_TIM_TIMER) &&
142 !(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
143 *masked |= ATH9K_INT_TIM_TIMER;
144 }
145
146 if (sync_cause) {
147 fatal_int =
148 (sync_cause &
149 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
150 ? 1 : 0;
151
152 if (fatal_int) {
153 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
154 DBG("ath9k: "
155 "received PCI FATAL interrupt\n");
156 }
157 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
158 DBG("ath9k: "
159 "received PCI PERR interrupt\n");
160 }
161 *masked |= ATH9K_INT_FATAL;
162 }
163 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
164 DBG("ath9k: "
165 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
166 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
167 REG_WRITE(ah, AR_RC, 0);
168 *masked |= ATH9K_INT_FATAL;
169 }
170 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
171 DBG("ath9k: "
172 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
173 }
174
175 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
176 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
177 }
178
179 return 1;
180 }
181
ar9002_hw_fill_txdesc(struct ath_hw * ah __unused,void * ds,u32 seglen,int is_firstseg,int is_lastseg,const void * ds0,u32 buf_addr,unsigned int qcu __unused)182 static void ar9002_hw_fill_txdesc(struct ath_hw *ah __unused, void *ds, u32 seglen,
183 int is_firstseg, int is_lastseg,
184 const void *ds0, u32 buf_addr,
185 unsigned int qcu __unused)
186 {
187 struct ar5416_desc *ads = AR5416DESC(ds);
188
189 ads->ds_data = buf_addr;
190
191 if (is_firstseg) {
192 ads->ds_ctl1 |= seglen | (is_lastseg ? 0 : AR_TxMore);
193 } else if (is_lastseg) {
194 ads->ds_ctl0 = 0;
195 ads->ds_ctl1 = seglen;
196 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
197 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
198 } else {
199 ads->ds_ctl0 = 0;
200 ads->ds_ctl1 = seglen | AR_TxMore;
201 ads->ds_ctl2 = 0;
202 ads->ds_ctl3 = 0;
203 }
204 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
205 ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
206 ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
207 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
208 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
209 }
210
ar9002_hw_proc_txdesc(struct ath_hw * ah,void * ds,struct ath_tx_status * ts)211 static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds,
212 struct ath_tx_status *ts)
213 {
214 struct ar5416_desc *ads = AR5416DESC(ds);
215 u32 status;
216
217 status = *(volatile typeof(ads->ds_txstatus9) *)&(ads->ds_txstatus9);
218 if ((status & AR_TxDone) == 0)
219 return -EINPROGRESS;
220
221 ts->ts_tstamp = ads->AR_SendTimestamp;
222 ts->ts_status = 0;
223 ts->ts_flags = 0;
224
225 if (status & AR_TxOpExceeded)
226 ts->ts_status |= ATH9K_TXERR_XTXOP;
227 ts->tid = MS(status, AR_TxTid);
228 ts->ts_rateindex = MS(status, AR_FinalTxIdx);
229 ts->ts_seqnum = MS(status, AR_SeqNum);
230
231 status = *(volatile typeof(ads->ds_txstatus0) *)&(ads->ds_txstatus0);
232 ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00);
233 ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01);
234 ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02);
235 if (status & AR_TxBaStatus) {
236 ts->ts_flags |= ATH9K_TX_BA;
237 ts->ba_low = ads->AR_BaBitmapLow;
238 ts->ba_high = ads->AR_BaBitmapHigh;
239 }
240
241 status = *(volatile typeof(ads->ds_txstatus1) *)&(ads->ds_txstatus1);
242 if (status & AR_FrmXmitOK)
243 ts->ts_status |= ATH9K_TX_ACKED;
244 else {
245 if (status & AR_ExcessiveRetries)
246 ts->ts_status |= ATH9K_TXERR_XRETRY;
247 if (status & AR_Filtered)
248 ts->ts_status |= ATH9K_TXERR_FILT;
249 if (status & AR_FIFOUnderrun) {
250 ts->ts_status |= ATH9K_TXERR_FIFO;
251 ath9k_hw_updatetxtriglevel(ah, 1);
252 }
253 }
254 if (status & AR_TxTimerExpired)
255 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
256 if (status & AR_DescCfgErr)
257 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
258 if (status & AR_TxDataUnderrun) {
259 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
260 ath9k_hw_updatetxtriglevel(ah, 1);
261 }
262 if (status & AR_TxDelimUnderrun) {
263 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
264 ath9k_hw_updatetxtriglevel(ah, 1);
265 }
266 ts->ts_shortretry = MS(status, AR_RTSFailCnt);
267 ts->ts_longretry = MS(status, AR_DataFailCnt);
268 ts->ts_virtcol = MS(status, AR_VirtRetryCnt);
269
270 status = *(volatile typeof(ads->ds_txstatus5) *)&(ads->ds_txstatus5);
271 ts->ts_rssi = MS(status, AR_TxRSSICombined);
272 ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10);
273 ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11);
274 ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12);
275
276 ts->evm0 = ads->AR_TxEVM0;
277 ts->evm1 = ads->AR_TxEVM1;
278 ts->evm2 = ads->AR_TxEVM2;
279
280 return 0;
281 }
282
ar9002_hw_set11n_txdesc(struct ath_hw * ah,void * ds,u32 pktLen,enum ath9k_pkt_type type,u32 txPower,u32 keyIx,enum ath9k_key_type keyType,u32 flags)283 static void ar9002_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
284 u32 pktLen, enum ath9k_pkt_type type,
285 u32 txPower, u32 keyIx,
286 enum ath9k_key_type keyType, u32 flags)
287 {
288 struct ar5416_desc *ads = AR5416DESC(ds);
289
290 if (txPower > 63)
291 txPower = 63;
292
293 ads->ds_ctl0 = (pktLen & AR_FrameLen)
294 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
295 | SM(txPower, AR_XmitPower)
296 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
297 | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
298 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
299
300 ads->ds_ctl1 =
301 (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
302 | SM(type, AR_FrameType)
303 | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
304 | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
305 | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
306
307 ads->ds_ctl6 = SM(keyType, AR_EncrType);
308
309 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
310 ads->ds_ctl8 = 0;
311 ads->ds_ctl9 = 0;
312 ads->ds_ctl10 = 0;
313 ads->ds_ctl11 = 0;
314 }
315 }
316
ar9002_hw_set_clrdmask(struct ath_hw * ah __unused,void * ds,int val)317 static void ar9002_hw_set_clrdmask(struct ath_hw *ah __unused, void *ds, int val)
318 {
319 struct ar5416_desc *ads = AR5416DESC(ds);
320
321 if (val)
322 ads->ds_ctl0 |= AR_ClrDestMask;
323 else
324 ads->ds_ctl0 &= ~AR_ClrDestMask;
325 }
326
ar9002_hw_set11n_ratescenario(struct ath_hw * ah __unused,void * ds,void * lastds,u32 durUpdateEn,u32 rtsctsRate,u32 rtsctsDuration __unused,struct ath9k_11n_rate_series series[],u32 nseries __unused,u32 flags)327 static void ar9002_hw_set11n_ratescenario(struct ath_hw *ah __unused, void *ds,
328 void *lastds,
329 u32 durUpdateEn, u32 rtsctsRate,
330 u32 rtsctsDuration __unused,
331 struct ath9k_11n_rate_series series[],
332 u32 nseries __unused, u32 flags)
333 {
334 struct ar5416_desc *ads = AR5416DESC(ds);
335 struct ar5416_desc *last_ads = AR5416DESC(lastds);
336 u32 ds_ctl0;
337
338 if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
339 ds_ctl0 = ads->ds_ctl0;
340
341 if (flags & ATH9K_TXDESC_RTSENA) {
342 ds_ctl0 &= ~AR_CTSEnable;
343 ds_ctl0 |= AR_RTSEnable;
344 } else {
345 ds_ctl0 &= ~AR_RTSEnable;
346 ds_ctl0 |= AR_CTSEnable;
347 }
348
349 ads->ds_ctl0 = ds_ctl0;
350 } else {
351 ads->ds_ctl0 =
352 (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
353 }
354
355 ads->ds_ctl2 = set11nTries(series, 0)
356 | set11nTries(series, 1)
357 | set11nTries(series, 2)
358 | set11nTries(series, 3)
359 | (durUpdateEn ? AR_DurUpdateEna : 0)
360 | SM(0, AR_BurstDur);
361
362 ads->ds_ctl3 = set11nRate(series, 0)
363 | set11nRate(series, 1)
364 | set11nRate(series, 2)
365 | set11nRate(series, 3);
366
367 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
368 | set11nPktDurRTSCTS(series, 1);
369
370 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
371 | set11nPktDurRTSCTS(series, 3);
372
373 ads->ds_ctl7 = set11nRateFlags(series, 0)
374 | set11nRateFlags(series, 1)
375 | set11nRateFlags(series, 2)
376 | set11nRateFlags(series, 3)
377 | SM(rtsctsRate, AR_RTSCTSRate);
378 last_ads->ds_ctl2 = ads->ds_ctl2;
379 last_ads->ds_ctl3 = ads->ds_ctl3;
380 }
381
ar9002_hw_set11n_aggr_first(struct ath_hw * ah __unused,void * ds,u32 aggrLen)382 static void ar9002_hw_set11n_aggr_first(struct ath_hw *ah __unused, void *ds,
383 u32 aggrLen)
384 {
385 struct ar5416_desc *ads = AR5416DESC(ds);
386
387 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
388 ads->ds_ctl6 &= ~AR_AggrLen;
389 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
390 }
391
ar9002_hw_set11n_aggr_middle(struct ath_hw * ah __unused,void * ds,u32 numDelims)392 static void ar9002_hw_set11n_aggr_middle(struct ath_hw *ah __unused, void *ds,
393 u32 numDelims)
394 {
395 struct ar5416_desc *ads = AR5416DESC(ds);
396 unsigned int ctl6;
397
398 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
399
400 ctl6 = ads->ds_ctl6;
401 ctl6 &= ~AR_PadDelim;
402 ctl6 |= SM(numDelims, AR_PadDelim);
403 ads->ds_ctl6 = ctl6;
404 }
405
ar9002_hw_set11n_aggr_last(struct ath_hw * ah __unused,void * ds)406 static void ar9002_hw_set11n_aggr_last(struct ath_hw *ah __unused, void *ds)
407 {
408 struct ar5416_desc *ads = AR5416DESC(ds);
409
410 ads->ds_ctl1 |= AR_IsAggr;
411 ads->ds_ctl1 &= ~AR_MoreAggr;
412 ads->ds_ctl6 &= ~AR_PadDelim;
413 }
414
ar9002_hw_clr11n_aggr(struct ath_hw * ah __unused,void * ds)415 static void ar9002_hw_clr11n_aggr(struct ath_hw *ah __unused, void *ds)
416 {
417 struct ar5416_desc *ads = AR5416DESC(ds);
418
419 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
420 }
421
ath9k_hw_setuprxdesc(struct ath_hw * ah,struct ath_desc * ds,u32 size,u32 flags)422 void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
423 u32 size, u32 flags)
424 {
425 struct ar5416_desc *ads = AR5416DESC(ds);
426 struct ath9k_hw_capabilities *pCap = &ah->caps;
427
428 ads->ds_ctl1 = size & AR_BufLen;
429 if (flags & ATH9K_RXDESC_INTREQ)
430 ads->ds_ctl1 |= AR_RxIntrReq;
431
432 ads->ds_rxstatus8 &= ~AR_RxDone;
433 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
434 memset(&(ads->u), 0, sizeof(ads->u));
435 }
436
ar9002_hw_attach_mac_ops(struct ath_hw * ah)437 void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
438 {
439 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
440
441 ops->rx_enable = ar9002_hw_rx_enable;
442 ops->set_desc_link = ar9002_hw_set_desc_link;
443 ops->get_desc_link = ar9002_hw_get_desc_link;
444 ops->get_isr = ar9002_hw_get_isr;
445 ops->fill_txdesc = ar9002_hw_fill_txdesc;
446 ops->proc_txdesc = ar9002_hw_proc_txdesc;
447 ops->set11n_txdesc = ar9002_hw_set11n_txdesc;
448 ops->set11n_ratescenario = ar9002_hw_set11n_ratescenario;
449 ops->set11n_aggr_first = ar9002_hw_set11n_aggr_first;
450 ops->set11n_aggr_middle = ar9002_hw_set11n_aggr_middle;
451 ops->set11n_aggr_last = ar9002_hw_set11n_aggr_last;
452 ops->clr11n_aggr = ar9002_hw_clr11n_aggr;
453 ops->set_clrdmask = ar9002_hw_set_clrdmask;
454 }
455