1 /* Copyright 2013-2014 IBM Corp.
2 *
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
12 * implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16 #include <skiboot.h>
17 #include <io.h>
18 #include <timebase.h>
19 #include <pci-cfg.h>
20 #include <pci.h>
21 #include <pci-slot.h>
22 #include <vpd.h>
23 #include <interrupts.h>
24 #include <opal.h>
25 #include <cpu.h>
26 #include <device.h>
27 #include <ccan/str/str.h>
28 #include <ccan/array_size/array_size.h>
29 #include <xscom.h>
30 #include <affinity.h>
31 #include <phb3.h>
32 #include <phb3-regs.h>
33 #include <phb3-capp.h>
34 #include <capp.h>
35 #include <fsp.h>
36 #include <chip.h>
37 #include <chiptod.h>
38
39 /* Enable this to disable error interrupts for debug purposes */
40 #undef DISABLE_ERR_INTS
41
42 static void phb3_init_hw(struct phb3 *p, bool first_init);
43
44 #define PHBDBG(p, fmt, a...) prlog(PR_DEBUG, "PHB#%04x: " fmt, \
45 (p)->phb.opal_id, ## a)
46 #define PHBINF(p, fmt, a...) prlog(PR_INFO, "PHB#%04x: " fmt, \
47 (p)->phb.opal_id, ## a)
48 #define PHBERR(p, fmt, a...) prlog(PR_ERR, "PHB#%04x: " fmt, \
49 (p)->phb.opal_id, ## a)
50
51 #define PE_CAPP_EN 0x9013c03
52
53 #define PE_REG_OFFSET(p) \
54 ((PHB3_IS_NAPLES(p) && (p)->index) ? 0x40 : 0x0)
55
56 /* Helper to select an IODA table entry */
phb3_ioda_sel(struct phb3 * p,uint32_t table,uint32_t addr,bool autoinc)57 static inline void phb3_ioda_sel(struct phb3 *p, uint32_t table,
58 uint32_t addr, bool autoinc)
59 {
60 out_be64(p->regs + PHB_IODA_ADDR,
61 (autoinc ? PHB_IODA_AD_AUTOINC : 0) |
62 SETFIELD(PHB_IODA_AD_TSEL, 0ul, table) |
63 SETFIELD(PHB_IODA_AD_TADR, 0ul, addr));
64 }
65
66 static void phb3_eeh_dump_regs(struct phb3 *p,
67 struct OpalIoPhb3ErrorData *regs);
68
69 /* Check if AIB is fenced via PBCQ NFIR */
phb3_fenced(struct phb3 * p)70 static bool phb3_fenced(struct phb3 *p)
71 {
72 uint64_t nfir;
73
74 /* We still probably has crazy xscom */
75 xscom_read(p->chip_id, p->pe_xscom + 0x0, &nfir);
76 if (nfir & PPC_BIT(16)) {
77 p->flags |= PHB3_AIB_FENCED;
78
79 phb3_eeh_dump_regs(p, NULL);
80 return true;
81 }
82 return false;
83 }
84
phb3_pcicfg_rc_pref_window(void * dev __unused,struct pci_cfg_reg_filter * pcrf,uint32_t offset,uint32_t len,uint32_t * data,bool write)85 static int64_t phb3_pcicfg_rc_pref_window(void *dev __unused,
86 struct pci_cfg_reg_filter *pcrf,
87 uint32_t offset, uint32_t len,
88 uint32_t *data, bool write)
89 {
90 uint8_t *pdata;
91 uint32_t i;
92
93 /* Cache whatever we received */
94 if (write) {
95 pdata = &pcrf->data[offset - pcrf->start];
96 for (i = 0; i < len; i++, pdata++)
97 *pdata = (uint8_t)(*data >> (8 * i));
98 return OPAL_SUCCESS;
99 }
100
101 /* Return whatever we cached */
102 *data = 0;
103 pdata = &pcrf->data[offset - pcrf->start + len - 1];
104 for (i = len; i > 0; i--, pdata--) {
105 *data = (*data) << 8;
106 if (offset + i == PCI_CFG_PREF_MEM_BASE) {
107 *data |= ((*pdata & 0xf0) | 0x1);
108 continue;
109 }
110
111 *data |= *pdata;
112 }
113
114 return OPAL_SUCCESS;
115 }
116
117 /*
118 * Configuration space access
119 *
120 * The PHB lock is assumed to be already held
121 */
phb3_pcicfg_check(struct phb3 * p,uint32_t bdfn,uint32_t offset,uint32_t size,uint8_t * pe)122 static int64_t phb3_pcicfg_check(struct phb3 *p, uint32_t bdfn,
123 uint32_t offset, uint32_t size,
124 uint8_t *pe)
125 {
126 uint32_t sm = size - 1;
127
128 if (offset > 0xfff || bdfn > 0xffff)
129 return OPAL_PARAMETER;
130 if (offset & sm)
131 return OPAL_PARAMETER;
132
133 /* The root bus only has a device at 0 and we get into an
134 * error state if we try to probe beyond that, so let's
135 * avoid that and just return an error to Linux
136 */
137 if ((bdfn >> 8) == 0 && (bdfn & 0xff))
138 return OPAL_HARDWARE;
139
140 /* Check PHB state */
141 if (p->broken)
142 return OPAL_HARDWARE;
143
144 /* Fetch the PE# from cache */
145 *pe = p->rte_cache[bdfn];
146
147 return OPAL_SUCCESS;
148 }
149
phb3_link_update(struct phb * phb,uint16_t data)150 static void phb3_link_update(struct phb *phb, uint16_t data)
151 {
152 struct phb3 *p = phb_to_phb3(phb);
153 uint32_t new_spd, new_wid;
154 uint32_t old_spd, old_wid;
155 uint16_t old_data;
156 uint64_t lreg;
157 int i;
158
159 /* Read the old speed and width */
160 pci_cfg_read16(phb, 0, 0x5a, &old_data);
161
162 /* Decode the register values */
163 new_spd = data & PCICAP_EXP_LSTAT_SPEED;
164 new_wid = (data & PCICAP_EXP_LSTAT_WIDTH) >> 4;
165 old_spd = old_data & PCICAP_EXP_LSTAT_SPEED;
166 old_wid = (old_data & PCICAP_EXP_LSTAT_WIDTH) >> 4;
167
168 /* Apply maximums */
169 if (new_wid > 16)
170 new_wid = 16;
171 if (new_wid < 1)
172 new_wid = 1;
173 if (new_spd > 3)
174 new_spd = 3;
175 if (new_spd < 1)
176 new_spd = 1;
177
178 PHBINF(p, "Link change request: speed %d->%d, width %d->%d\n",
179 old_spd, new_spd, old_wid, new_wid);
180
181 /* Check if width needs to be changed */
182 if (old_wid != new_wid) {
183 PHBINF(p, "Changing width...\n");
184 lreg = in_be64(p->regs + PHB_PCIE_LINK_MANAGEMENT);
185 lreg = SETFIELD(PHB_PCIE_LM_TGT_LINK_WIDTH, lreg, new_wid);
186 lreg |= PHB_PCIE_LM_CHG_LINK_WIDTH;
187 out_be64(p->regs + PHB_PCIE_LINK_MANAGEMENT, lreg);
188 for (i=0; i<10;i++) {
189 lreg = in_be64(p->regs + PHB_PCIE_LINK_MANAGEMENT);
190 if (lreg & PHB_PCIE_LM_DL_WCHG_PENDING)
191 break;
192 time_wait_ms_nopoll(1);
193 }
194 if (!(lreg & PHB_PCIE_LM_DL_WCHG_PENDING))
195 PHBINF(p, "Timeout waiting for speed change start\n");
196 for (i=0; i<100;i++) {
197 lreg = in_be64(p->regs + PHB_PCIE_LINK_MANAGEMENT);
198 if (!(lreg & PHB_PCIE_LM_DL_WCHG_PENDING))
199 break;
200 time_wait_ms_nopoll(1);
201 }
202 if (lreg & PHB_PCIE_LM_DL_WCHG_PENDING)
203 PHBINF(p, "Timeout waiting for speed change end\n");
204 }
205 /* Check if speed needs to be changed */
206 if (old_spd != new_spd) {
207 PHBINF(p, "Changing speed...\n");
208 lreg = in_be64(p->regs + PHB_PCIE_LINK_MANAGEMENT);
209 if (lreg & PPC_BIT(19)) {
210 uint16_t lctl2;
211 PHBINF(p, " Bit19 set ! working around...\n");
212 pci_cfg_read16(phb, 0, 0x78, &lctl2);
213 PHBINF(p, " LCTL2=%04x\n", lctl2);
214 lctl2 &= ~PCICAP_EXP_LCTL2_HWAUTSPDIS;
215 pci_cfg_write16(phb, 0, 0x78, lctl2);
216 }
217 lreg = in_be64(p->regs + PHB_PCIE_LINK_MANAGEMENT);
218 lreg = SETFIELD(PHB_PCIE_LM_TGT_SPEED, lreg, new_spd);
219 lreg |= PHB_PCIE_LM_CHG_SPEED;
220 out_be64(p->regs + PHB_PCIE_LINK_MANAGEMENT, lreg);
221 }
222 }
223
phb3_pcicfg_rc_link_speed(void * dev,struct pci_cfg_reg_filter * pcrf __unused,uint32_t offset,uint32_t len,uint32_t * data,bool write)224 static int64_t phb3_pcicfg_rc_link_speed(void *dev,
225 struct pci_cfg_reg_filter *pcrf __unused,
226 uint32_t offset, uint32_t len,
227 uint32_t *data, bool write)
228 {
229 struct pci_device *pd = dev;
230
231 /* Hack for link speed changes. We intercept attempts at writing
232 * the link control/status register
233 */
234 if (write && len == 4 && offset == 0x58) {
235 phb3_link_update(pd->phb, (*data) >> 16);
236 return OPAL_SUCCESS;
237 }
238 if (write && len == 2 && offset == 0x5a) {
239 phb3_link_update(pd->phb, *(uint16_t *)data);
240 return OPAL_SUCCESS;
241 }
242
243 return OPAL_PARTIAL;
244 }
245
246 #define PHB3_PCI_CFG_READ(size, type) \
247 static int64_t phb3_pcicfg_read##size(struct phb *phb, uint32_t bdfn, \
248 uint32_t offset, type *data) \
249 { \
250 struct phb3 *p = phb_to_phb3(phb); \
251 uint64_t addr, val64; \
252 int64_t rc; \
253 uint8_t pe; \
254 bool use_asb = false; \
255 \
256 /* Initialize data in case of error */ \
257 *data = (type)0xffffffff; \
258 \
259 rc = phb3_pcicfg_check(p, bdfn, offset, sizeof(type), &pe); \
260 if (rc) \
261 return rc; \
262 \
263 if (p->flags & PHB3_AIB_FENCED) { \
264 if (!(p->flags & PHB3_CFG_USE_ASB)) \
265 return OPAL_HARDWARE; \
266 use_asb = true; \
267 } else if ((p->flags & PHB3_CFG_BLOCKED) && bdfn != 0) { \
268 return OPAL_HARDWARE; \
269 } \
270 \
271 rc = pci_handle_cfg_filters(phb, bdfn, offset, sizeof(type), \
272 (uint32_t *)data, false); \
273 if (rc != OPAL_PARTIAL) \
274 return rc; \
275 \
276 addr = PHB_CA_ENABLE; \
277 addr = SETFIELD(PHB_CA_BDFN, addr, bdfn); \
278 addr = SETFIELD(PHB_CA_REG, addr, offset); \
279 addr = SETFIELD(PHB_CA_PE, addr, pe); \
280 if (use_asb) { \
281 phb3_write_reg_asb(p, PHB_CONFIG_ADDRESS, addr); \
282 sync(); \
283 val64 = bswap_64(phb3_read_reg_asb(p, PHB_CONFIG_DATA)); \
284 *data = (type)(val64 >> (8 * (offset & (4 - sizeof(type))))); \
285 } else { \
286 out_be64(p->regs + PHB_CONFIG_ADDRESS, addr); \
287 *data = in_le##size(p->regs + PHB_CONFIG_DATA + \
288 (offset & (4 - sizeof(type)))); \
289 } \
290 \
291 return OPAL_SUCCESS; \
292 }
293
294 #define PHB3_PCI_CFG_WRITE(size, type) \
295 static int64_t phb3_pcicfg_write##size(struct phb *phb, uint32_t bdfn, \
296 uint32_t offset, type data) \
297 { \
298 struct phb3 *p = phb_to_phb3(phb); \
299 uint64_t addr, val64 = 0; \
300 int64_t rc; \
301 uint8_t pe; \
302 bool use_asb = false; \
303 \
304 rc = phb3_pcicfg_check(p, bdfn, offset, sizeof(type), &pe); \
305 if (rc) \
306 return rc; \
307 \
308 if (p->flags & PHB3_AIB_FENCED) { \
309 if (!(p->flags & PHB3_CFG_USE_ASB)) \
310 return OPAL_HARDWARE; \
311 use_asb = true; \
312 } else if ((p->flags & PHB3_CFG_BLOCKED) && bdfn != 0) { \
313 return OPAL_HARDWARE; \
314 } \
315 \
316 rc = pci_handle_cfg_filters(phb, bdfn, offset, sizeof(type), \
317 (uint32_t *)&data, true); \
318 if (rc != OPAL_PARTIAL) \
319 return rc; \
320 \
321 addr = PHB_CA_ENABLE; \
322 addr = SETFIELD(PHB_CA_BDFN, addr, bdfn); \
323 addr = SETFIELD(PHB_CA_REG, addr, offset); \
324 addr = SETFIELD(PHB_CA_PE, addr, pe); \
325 if (use_asb) { \
326 val64 = data; \
327 val64 = bswap_64(val64 << 8 * (offset & (4 - sizeof(type)))); \
328 phb3_write_reg_asb(p, PHB_CONFIG_ADDRESS, addr); \
329 sync(); \
330 phb3_write_reg_asb(p, PHB_CONFIG_DATA, val64); \
331 } else { \
332 out_be64(p->regs + PHB_CONFIG_ADDRESS, addr); \
333 out_le##size(p->regs + PHB_CONFIG_DATA + \
334 (offset & (4 - sizeof(type))), data); \
335 } \
336 \
337 return OPAL_SUCCESS; \
338 }
339
340 PHB3_PCI_CFG_READ(8, u8)
341 PHB3_PCI_CFG_READ(16, u16)
342 PHB3_PCI_CFG_READ(32, u32)
343 PHB3_PCI_CFG_WRITE(8, u8)
344 PHB3_PCI_CFG_WRITE(16, u16)
345 PHB3_PCI_CFG_WRITE(32, u32)
346
phb3_choose_bus(struct phb * phb __unused,struct pci_device * bridge __unused,uint8_t candidate,uint8_t * max_bus __unused,bool * use_max)347 static uint8_t phb3_choose_bus(struct phb *phb __unused,
348 struct pci_device *bridge __unused,
349 uint8_t candidate, uint8_t *max_bus __unused,
350 bool *use_max)
351 {
352 /* Use standard bus number selection */
353 *use_max = false;
354 return candidate;
355 }
356
phb3_get_reserved_pe_number(struct phb * phb __unused)357 static int64_t phb3_get_reserved_pe_number(struct phb *phb __unused)
358 {
359 return PHB3_RESERVED_PE_NUM;
360 }
361
phb3_enable_ecrc(struct phb * phb,bool enable)362 static inline void phb3_enable_ecrc(struct phb *phb, bool enable)
363 {
364 struct phb3 *p = phb_to_phb3(phb);
365 uint32_t ctl;
366
367 if (p->aercap <= 0)
368 return;
369
370 pci_cfg_read32(phb, 0, p->aercap + PCIECAP_AER_CAPCTL, &ctl);
371 if (enable) {
372 ctl |= (PCIECAP_AER_CAPCTL_ECRCG_EN |
373 PCIECAP_AER_CAPCTL_ECRCC_EN);
374 } else {
375 ctl &= ~(PCIECAP_AER_CAPCTL_ECRCG_EN |
376 PCIECAP_AER_CAPCTL_ECRCC_EN);
377 }
378
379 pci_cfg_write32(phb, 0, p->aercap + PCIECAP_AER_CAPCTL, ctl);
380 }
381
phb3_root_port_init(struct phb * phb,struct pci_device * dev,int ecap,int aercap)382 static void phb3_root_port_init(struct phb *phb, struct pci_device *dev,
383 int ecap, int aercap)
384 {
385 struct phb3 *p = phb_to_phb3(phb);
386 uint16_t bdfn = dev->bdfn;
387 uint16_t val16;
388 uint32_t val32;
389
390 /* Use PHB's callback so that the UTL events will be masked
391 * or unmasked when the link is down or up.
392 */
393 if (dev->slot && dev->slot->ops.prepare_link_change &&
394 phb->slot && phb->slot->ops.prepare_link_change)
395 dev->slot->ops.prepare_link_change =
396 phb->slot->ops.prepare_link_change;
397
398 /* Mask UTL link down event if root slot supports surprise
399 * hotplug as the event should be handled by hotplug driver
400 * instead of EEH subsystem.
401 */
402 if (dev->slot && dev->slot->surprise_pluggable)
403 out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0xad42800000000000UL);
404
405 /* Enable SERR and parity checking */
406 pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16);
407 val16 |= (PCI_CFG_CMD_SERR_EN | PCI_CFG_CMD_PERR_RESP);
408 pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16);
409
410 /* Enable reporting various errors */
411 if (!ecap) return;
412 pci_cfg_read16(phb, bdfn, ecap + PCICAP_EXP_DEVCTL, &val16);
413 val16 |= (PCICAP_EXP_DEVCTL_CE_REPORT |
414 PCICAP_EXP_DEVCTL_NFE_REPORT |
415 PCICAP_EXP_DEVCTL_FE_REPORT |
416 PCICAP_EXP_DEVCTL_UR_REPORT);
417 pci_cfg_write16(phb, bdfn, ecap + PCICAP_EXP_DEVCTL, val16);
418
419 if (!aercap) return;
420
421 /* Mask various unrecoverable errors. The link surprise down
422 * event should be masked when its PCI slot support surprise
423 * hotplug. The link surprise down event should be handled by
424 * PCI hotplug driver instead of EEH subsystem.
425 */
426 pci_cfg_read32(phb, bdfn, aercap + PCIECAP_AER_UE_MASK, &val32);
427 val32 |= (PCIECAP_AER_UE_MASK_POISON_TLP |
428 PCIECAP_AER_UE_MASK_COMPL_TIMEOUT |
429 PCIECAP_AER_UE_MASK_COMPL_ABORT |
430 PCIECAP_AER_UE_MASK_ECRC);
431 if (dev->slot && dev->slot->surprise_pluggable)
432 val32 |= PCIECAP_AER_UE_MASK_SURPRISE_DOWN;
433 pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_UE_MASK, val32);
434
435 /* Report various unrecoverable errors as fatal errors */
436 pci_cfg_read32(phb, bdfn, aercap + PCIECAP_AER_UE_SEVERITY, &val32);
437 val32 |= (PCIECAP_AER_UE_SEVERITY_DLLP |
438 PCIECAP_AER_UE_SEVERITY_SURPRISE_DOWN |
439 PCIECAP_AER_UE_SEVERITY_FLOW_CTL_PROT |
440 PCIECAP_AER_UE_SEVERITY_UNEXP_COMPL |
441 PCIECAP_AER_UE_SEVERITY_RECV_OVFLOW |
442 PCIECAP_AER_UE_SEVERITY_MALFORMED_TLP);
443 pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_UE_SEVERITY, val32);
444
445 /* Mask various recoverable errors */
446 pci_cfg_read32(phb, bdfn, aercap + PCIECAP_AER_CE_MASK, &val32);
447 val32 |= PCIECAP_AER_CE_MASK_ADV_NONFATAL;
448 pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_CE_MASK, val32);
449
450 /* Enable ECRC check */
451 phb3_enable_ecrc(phb, true);
452
453 /* Enable all error reporting */
454 pci_cfg_read32(phb, bdfn, aercap + PCIECAP_AER_RERR_CMD, &val32);
455 val32 |= (PCIECAP_AER_RERR_CMD_FE |
456 PCIECAP_AER_RERR_CMD_NFE |
457 PCIECAP_AER_RERR_CMD_CE);
458 pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_RERR_CMD, val32);
459 }
460
phb3_switch_port_init(struct phb * phb,struct pci_device * dev,int ecap,int aercap)461 static void phb3_switch_port_init(struct phb *phb,
462 struct pci_device *dev,
463 int ecap, int aercap)
464 {
465 struct phb3 *p = phb_to_phb3(phb);
466 uint16_t bdfn = dev->bdfn;
467 uint16_t val16;
468 uint32_t val32;
469
470 /* Enable SERR and parity checking and disable INTx */
471 pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16);
472 val16 |= (PCI_CFG_CMD_PERR_RESP |
473 PCI_CFG_CMD_SERR_EN |
474 PCI_CFG_CMD_INTx_DIS);
475 pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16);
476
477 /* Disable partity error and enable system error */
478 pci_cfg_read16(phb, bdfn, PCI_CFG_BRCTL, &val16);
479 val16 &= ~PCI_CFG_BRCTL_PERR_RESP_EN;
480 val16 |= PCI_CFG_BRCTL_SERR_EN;
481 pci_cfg_write16(phb, bdfn, PCI_CFG_BRCTL, val16);
482
483 /* Enable reporting various errors */
484 if (!ecap) return;
485 pci_cfg_read16(phb, bdfn, ecap + PCICAP_EXP_DEVCTL, &val16);
486 val16 |= (PCICAP_EXP_DEVCTL_CE_REPORT |
487 PCICAP_EXP_DEVCTL_NFE_REPORT |
488 PCICAP_EXP_DEVCTL_FE_REPORT);
489 /* HW279570 - Disable reporting of correctable errors */
490 val16 &= ~PCICAP_EXP_DEVCTL_CE_REPORT;
491 pci_cfg_write16(phb, bdfn, ecap + PCICAP_EXP_DEVCTL, val16);
492
493 /* Unmask all unrecoverable errors for upstream port. For
494 * downstream port, the surprise link down is masked because
495 * it should be handled by hotplug driver instead of EEH
496 * subsystem.
497 */
498 if (!aercap) return;
499 if (dev->dev_type == PCIE_TYPE_SWITCH_DNPORT &&
500 dev->slot && dev->slot->surprise_pluggable)
501 pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_UE_MASK,
502 PCIECAP_AER_UE_MASK_SURPRISE_DOWN);
503 else
504 pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_UE_MASK, 0x0);
505
506 /* Severity of unrecoverable errors */
507 if (dev->dev_type == PCIE_TYPE_SWITCH_UPPORT)
508 val32 = (PCIECAP_AER_UE_SEVERITY_DLLP |
509 PCIECAP_AER_UE_SEVERITY_SURPRISE_DOWN |
510 PCIECAP_AER_UE_SEVERITY_FLOW_CTL_PROT |
511 PCIECAP_AER_UE_SEVERITY_RECV_OVFLOW |
512 PCIECAP_AER_UE_SEVERITY_MALFORMED_TLP |
513 PCIECAP_AER_UE_SEVERITY_INTERNAL);
514 else
515 val32 = (PCIECAP_AER_UE_SEVERITY_FLOW_CTL_PROT |
516 PCIECAP_AER_UE_SEVERITY_INTERNAL);
517 pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_UE_SEVERITY, val32);
518
519 /*
520 * Mask various correctable errors
521 *
522 * On Murano and Venice DD1.0 we disable emission of corrected
523 * error messages to the PHB completely to workaround errata
524 * HW257476 causing the loss of tags.
525 */
526 if (p->rev < PHB3_REV_MURANO_DD20)
527 val32 = 0xffffffff;
528 else
529 val32 = PCIECAP_AER_CE_MASK_ADV_NONFATAL;
530 pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_CE_MASK, val32);
531
532 /* Enable ECRC generation and disable ECRC check */
533 pci_cfg_read32(phb, bdfn, aercap + PCIECAP_AER_CAPCTL, &val32);
534 val32 |= PCIECAP_AER_CAPCTL_ECRCG_EN;
535 val32 &= ~PCIECAP_AER_CAPCTL_ECRCC_EN;
536 pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_CAPCTL, val32);
537 }
538
phb3_endpoint_init(struct phb * phb,struct pci_device * dev,int ecap,int aercap)539 static void phb3_endpoint_init(struct phb *phb,
540 struct pci_device *dev,
541 int ecap, int aercap)
542 {
543 struct phb3 *p = phb_to_phb3(phb);
544 uint16_t bdfn = dev->bdfn;
545 uint16_t val16;
546 uint32_t val32;
547
548 /* Enable SERR and parity checking */
549 pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16);
550 val16 |= (PCI_CFG_CMD_PERR_RESP |
551 PCI_CFG_CMD_SERR_EN);
552 pci_cfg_write16(phb, bdfn, PCI_CFG_CMD, val16);
553
554 /* Enable reporting various errors */
555 if (!ecap) return;
556 pci_cfg_read16(phb, bdfn, ecap + PCICAP_EXP_DEVCTL, &val16);
557 val16 &= ~PCICAP_EXP_DEVCTL_CE_REPORT;
558 val16 |= (PCICAP_EXP_DEVCTL_NFE_REPORT |
559 PCICAP_EXP_DEVCTL_FE_REPORT |
560 PCICAP_EXP_DEVCTL_UR_REPORT);
561 /* HW279570 - Disable reporting of correctable errors */
562 val16 &= ~PCICAP_EXP_DEVCTL_CE_REPORT;
563 pci_cfg_write16(phb, bdfn, ecap + PCICAP_EXP_DEVCTL, val16);
564
565 /*
566 * On Murano and Venice DD1.0 we disable emission of corrected
567 * error messages to the PHB completely to workaround errata
568 * HW257476 causing the loss of tags.
569 */
570 if (p->rev < PHB3_REV_MURANO_DD20)
571 pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_CE_MASK,
572 0xffffffff);
573
574 /* Enable ECRC generation and check */
575 pci_cfg_read32(phb, bdfn, aercap + PCIECAP_AER_CAPCTL, &val32);
576 val32 |= (PCIECAP_AER_CAPCTL_ECRCG_EN |
577 PCIECAP_AER_CAPCTL_ECRCC_EN);
578 pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_CAPCTL, val32);
579 }
580
phb3_pcicfg_no_dstate(void * dev __unused,struct pci_cfg_reg_filter * pcrf,uint32_t offset,uint32_t len __unused,uint32_t * data __unused,bool write)581 static int64_t phb3_pcicfg_no_dstate(void *dev __unused,
582 struct pci_cfg_reg_filter *pcrf,
583 uint32_t offset, uint32_t len __unused,
584 uint32_t *data __unused, bool write)
585 {
586 uint32_t loff = offset - pcrf->start;
587
588 /* Disable D-state change on children of the PHB. For now we
589 * simply block all writes to the PM control/status
590 */
591 if (write && loff >= 4 && loff < 6)
592 return OPAL_SUCCESS;
593
594 return OPAL_PARTIAL;
595 }
596
phb3_check_device_quirks(struct phb * phb,struct pci_device * dev)597 static void phb3_check_device_quirks(struct phb *phb, struct pci_device *dev)
598 {
599 struct phb3 *p = phb_to_phb3(phb);
600
601 if (dev->primary_bus != 0 &&
602 dev->primary_bus != 1)
603 return;
604
605 if (dev->primary_bus == 1) {
606 u64 modectl;
607
608 /*
609 * For these adapters, if they are directly under the PHB, we
610 * adjust the disable_wr_scope_group bit for performances
611 *
612 * 15b3:1003 Mellanox Travis3-EN (CX3)
613 * 15b3:1011 Mellanox HydePark (ConnectIB)
614 * 15b3:1013 Mellanox GlacierPark (CX4)
615 */
616 xscom_read(p->chip_id, p->pe_xscom + 0x0b, &modectl);
617 if (PCI_VENDOR_ID(dev->vdid) == 0x15b3 &&
618 (PCI_DEVICE_ID(dev->vdid) == 0x1003 ||
619 PCI_DEVICE_ID(dev->vdid) == 0x1011 ||
620 PCI_DEVICE_ID(dev->vdid) == 0x1013))
621 modectl |= PPC_BIT(14);
622 else
623 modectl &= ~PPC_BIT(14);
624 xscom_write(p->chip_id, p->pe_xscom + 0x0b, modectl);
625
626 /*
627 * Naples has a problem with D-states at least on Mellanox CX4,
628 * disable changing D-state on Naples like we do it for PHB4.
629 */
630 if (PHB3_IS_NAPLES(p) &&
631 pci_has_cap(dev, PCI_CFG_CAP_ID_PM, false)) {
632 pci_add_cfg_reg_filter(dev,
633 pci_cap(dev, PCI_CFG_CAP_ID_PM, false),
634 8,
635 PCI_REG_FLAG_WRITE,
636 phb3_pcicfg_no_dstate);
637 }
638 } else if (dev->primary_bus == 0) {
639 /*
640 * Emulate the prefetchable window of the root port
641 * when the corresponding HW registers are readonly.
642 *
643 * 1014:03dc Root port on P8/P8E/P8NVL
644 */
645 if (PCI_VENDOR_ID(dev->vdid) == 0x1014 &&
646 PCI_DEVICE_ID(dev->vdid) == 0x03dc) {
647 uint32_t pref_hi, tmp;
648
649 pci_cfg_read32(phb, dev->bdfn,
650 PCI_CFG_PREF_MEM_BASE_U32, &pref_hi);
651 pci_cfg_write32(phb, dev->bdfn,
652 PCI_CFG_PREF_MEM_BASE_U32, ~pref_hi);
653 pci_cfg_read32(phb, dev->bdfn,
654 PCI_CFG_PREF_MEM_BASE_U32, &tmp);
655 pci_cfg_write32(phb, dev->bdfn,
656 PCI_CFG_PREF_MEM_BASE_U32, pref_hi);
657 if (tmp == pref_hi)
658 pci_add_cfg_reg_filter(dev,
659 PCI_CFG_PREF_MEM_BASE_U32, 12,
660 PCI_REG_FLAG_READ | PCI_REG_FLAG_WRITE,
661 phb3_pcicfg_rc_pref_window);
662 /* Add filter to control link speed */
663 pci_add_cfg_reg_filter(dev,
664 0x58, 4,
665 PCI_REG_FLAG_WRITE,
666 phb3_pcicfg_rc_link_speed);
667 }
668 }
669 }
670
phb3_should_disable_ecrc(struct pci_device * pd)671 static inline int phb3_should_disable_ecrc(struct pci_device *pd)
672 {
673 /*
674 * When we have PMC PCIe switch, we need disable ECRC on root port.
675 * Otherwise, the adapters behind the switch downstream ports might
676 * not probed successfully.
677 */
678 if (pd->vdid == 0x854611f8)
679 return true;
680
681 return false;
682 }
683
phb3_device_init(struct phb * phb,struct pci_device * dev,void * data)684 static int phb3_device_init(struct phb *phb,
685 struct pci_device *dev,
686 void *data)
687 {
688 struct phb3 *p = phb_to_phb3(phb);
689 int ecap, aercap;
690
691 /* Some special adapter tweaks for devices directly under the PHB */
692 phb3_check_device_quirks(phb, dev);
693
694 /* Common initialization for the device */
695 pci_device_init(phb, dev);
696
697 ecap = pci_cap(dev, PCI_CFG_CAP_ID_EXP, false);
698 aercap = pci_cap(dev, PCIECAP_ID_AER, true);
699 if (dev->dev_type == PCIE_TYPE_ROOT_PORT)
700 phb3_root_port_init(phb, dev, ecap, aercap);
701 else if (dev->dev_type == PCIE_TYPE_SWITCH_UPPORT ||
702 dev->dev_type == PCIE_TYPE_SWITCH_DNPORT)
703 phb3_switch_port_init(phb, dev, ecap, aercap);
704 else
705 phb3_endpoint_init(phb, dev, ecap, aercap);
706
707 /*
708 * Check if we need disable ECRC functionality on root port. It
709 * only happens when PCI topology changes, meaning it's skipped
710 * when reinitializing PCI device after EEH reset.
711 */
712 if (!data && phb3_should_disable_ecrc(dev)) {
713 if (p->no_ecrc_devs++ == 0)
714 phb3_enable_ecrc(phb, false);
715 }
716
717 return 0;
718 }
719
phb3_device_remove(struct phb * phb,struct pci_device * pd)720 static void phb3_device_remove(struct phb *phb, struct pci_device *pd)
721 {
722 struct phb3 *p = phb_to_phb3(phb);
723
724 if (!phb3_should_disable_ecrc(pd) || p->no_ecrc_devs == 0)
725 return;
726
727 if (--p->no_ecrc_devs == 0)
728 phb3_enable_ecrc(phb, true);
729 }
730
phb3_pci_reinit(struct phb * phb,uint64_t scope,uint64_t data)731 static int64_t phb3_pci_reinit(struct phb *phb, uint64_t scope, uint64_t data)
732 {
733 struct pci_device *pd;
734 uint16_t bdfn = data;
735 int ret;
736
737 if (scope != OPAL_REINIT_PCI_DEV)
738 return OPAL_PARAMETER;
739
740 pd = pci_find_dev(phb, bdfn);
741 if (!pd)
742 return OPAL_PARAMETER;
743
744 ret = phb3_device_init(phb, pd, pd);
745 if (ret)
746 return OPAL_HARDWARE;
747
748 return OPAL_SUCCESS;
749 }
750
751 /* Clear IODA cache tables */
phb3_init_ioda_cache(struct phb3 * p)752 static void phb3_init_ioda_cache(struct phb3 *p)
753 {
754 uint32_t i;
755 uint64_t *data64;
756
757 /*
758 * RTT and PELTV. RTE should be 0xFF's to indicate
759 * invalid PE# for the corresponding RID.
760 *
761 * Note: Instead we set all RTE entries to 0x00 to
762 * work around a problem where PE lookups might be
763 * done before Linux has established valid PE's
764 * (during PCI probing). We can revisit that once/if
765 * Linux has been fixed to always setup valid PEs.
766 *
767 * The value 0x00 corresponds to the default PE# Linux
768 * uses to check for config space freezes before it
769 * has assigned PE# to busses.
770 *
771 * WARNING: Additionally, we need to be careful, there's
772 * a HW issue, if we get an MSI on an RTT entry that is
773 * FF, things will go bad. We need to ensure we don't
774 * ever let a live FF RTT even temporarily when resetting
775 * for EEH etc... (HW278969).
776 */
777 for (i = 0; i < ARRAY_SIZE(p->rte_cache); i++)
778 p->rte_cache[i] = PHB3_RESERVED_PE_NUM;
779 memset(p->peltv_cache, 0x0, sizeof(p->peltv_cache));
780
781 /* Disable all LSI */
782 for (i = 0; i < ARRAY_SIZE(p->lxive_cache); i++) {
783 data64 = &p->lxive_cache[i];
784 *data64 = SETFIELD(IODA2_LXIVT_PRIORITY, 0ul, 0xff);
785 *data64 = SETFIELD(IODA2_LXIVT_SERVER, *data64, 0x0);
786 }
787
788 /* Diable all MSI */
789 for (i = 0; i < ARRAY_SIZE(p->ive_cache); i++) {
790 data64 = &p->ive_cache[i];
791 *data64 = SETFIELD(IODA2_IVT_PRIORITY, 0ul, 0xff);
792 *data64 = SETFIELD(IODA2_IVT_SERVER, *data64, 0x0);
793 }
794
795 /* Clear TVT */
796 memset(p->tve_cache, 0x0, sizeof(p->tve_cache));
797 /* Clear M32 domain */
798 memset(p->m32d_cache, 0x0, sizeof(p->m32d_cache));
799 /* Clear M64 domain */
800 memset(p->m64b_cache, 0x0, sizeof(p->m64b_cache));
801 }
802
803 /* phb3_ioda_reset - Reset the IODA tables
804 *
805 * @purge: If true, the cache is cleared and the cleared values
806 * are applied to HW. If false, the cached values are
807 * applied to HW
808 *
809 * This reset the IODA tables in the PHB. It is called at
810 * initialization time, on PHB reset, and can be called
811 * explicitly from OPAL
812 */
phb3_ioda_reset(struct phb * phb,bool purge)813 static int64_t phb3_ioda_reset(struct phb *phb, bool purge)
814 {
815 struct phb3 *p = phb_to_phb3(phb);
816 uint64_t server, prio;
817 uint64_t *pdata64, data64;
818 uint32_t i;
819
820 if (purge) {
821 prlog(PR_DEBUG, "PHB%x: Purging all IODA tables...\n",
822 p->phb.opal_id);
823 phb3_init_ioda_cache(p);
824 }
825
826 /* Init_27..28 - LIXVT */
827 phb3_ioda_sel(p, IODA2_TBL_LXIVT, 0, true);
828 for (i = 0; i < ARRAY_SIZE(p->lxive_cache); i++) {
829 data64 = p->lxive_cache[i];
830 server = GETFIELD(IODA2_LXIVT_SERVER, data64);
831 prio = GETFIELD(IODA2_LXIVT_PRIORITY, data64);
832 data64 = SETFIELD(IODA2_LXIVT_SERVER, data64, server);
833 data64 = SETFIELD(IODA2_LXIVT_PRIORITY, data64, prio);
834 out_be64(p->regs + PHB_IODA_DATA0, data64);
835 }
836
837 /* Init_29..30 - MRT */
838 phb3_ioda_sel(p, IODA2_TBL_MRT, 0, true);
839 for (i = 0; i < 8; i++)
840 out_be64(p->regs + PHB_IODA_DATA0, 0);
841
842 /* Init_31..32 - TVT */
843 phb3_ioda_sel(p, IODA2_TBL_TVT, 0, true);
844 for (i = 0; i < ARRAY_SIZE(p->tve_cache); i++)
845 out_be64(p->regs + PHB_IODA_DATA0, p->tve_cache[i]);
846
847 /* Init_33..34 - M64BT */
848 phb3_ioda_sel(p, IODA2_TBL_M64BT, 0, true);
849 for (i = 0; i < ARRAY_SIZE(p->m64b_cache); i++)
850 out_be64(p->regs + PHB_IODA_DATA0, p->m64b_cache[i]);
851
852 /* Init_35..36 - M32DT */
853 phb3_ioda_sel(p, IODA2_TBL_M32DT, 0, true);
854 for (i = 0; i < ARRAY_SIZE(p->m32d_cache); i++)
855 out_be64(p->regs + PHB_IODA_DATA0, p->m32d_cache[i]);
856
857 /* Load RTE, PELTV */
858 if (p->tbl_rtt)
859 memcpy((void *)p->tbl_rtt, p->rte_cache, RTT_TABLE_SIZE);
860 if (p->tbl_peltv)
861 memcpy((void *)p->tbl_peltv, p->peltv_cache, PELTV_TABLE_SIZE);
862
863 /* Load IVT */
864 if (p->tbl_ivt) {
865 pdata64 = (uint64_t *)p->tbl_ivt;
866 for (i = 0; i < IVT_TABLE_ENTRIES; i++)
867 pdata64[i * IVT_TABLE_STRIDE] = p->ive_cache[i];
868 }
869
870 /* Invalidate RTE, IVE, TCE cache */
871 out_be64(p->regs + PHB_RTC_INVALIDATE, PHB_RTC_INVALIDATE_ALL);
872 out_be64(p->regs + PHB_IVC_INVALIDATE, PHB_IVC_INVALIDATE_ALL);
873 out_be64(p->regs + PHB_TCE_KILL, PHB_TCE_KILL_ALL);
874
875 /* Clear RBA */
876 if (p->rev >= PHB3_REV_MURANO_DD20) {
877 phb3_ioda_sel(p, IODA2_TBL_RBA, 0, true);
878 for (i = 0; i < 32; i++)
879 out_be64(p->regs + PHB_IODA_DATA0, 0x0ul);
880 }
881
882 /* Clear PEST & PEEV */
883 for (i = 0; i < PHB3_MAX_PE_NUM; i++) {
884 uint64_t pesta, pestb;
885
886 phb3_ioda_sel(p, IODA2_TBL_PESTA, i, false);
887 pesta = in_be64(p->regs + PHB_IODA_DATA0);
888 out_be64(p->regs + PHB_IODA_DATA0, 0);
889 phb3_ioda_sel(p, IODA2_TBL_PESTB, i, false);
890 pestb = in_be64(p->regs + PHB_IODA_DATA0);
891 out_be64(p->regs + PHB_IODA_DATA0, 0);
892
893 if ((pesta & IODA2_PESTA_MMIO_FROZEN) ||
894 (pestb & IODA2_PESTB_DMA_STOPPED))
895 PHBDBG(p, "Frozen PE#%x (%s - %s)\n",
896 i, (pesta & IODA2_PESTA_MMIO_FROZEN) ? "DMA" : "",
897 (pestb & IODA2_PESTB_DMA_STOPPED) ? "MMIO" : "");
898 }
899
900 phb3_ioda_sel(p, IODA2_TBL_PEEV, 0, true);
901 for (i = 0; i < 4; i++)
902 out_be64(p->regs + PHB_IODA_DATA0, 0);
903
904 return OPAL_SUCCESS;
905 }
906
907 /*
908 * Clear anything we have in PAPR Error Injection registers. Though
909 * the spec says the PAPR error injection should be one-shot without
910 * the "sticky" bit. However, that's false according to the experiments
911 * I had. So we have to clear it at appropriate point in kernel to
912 * avoid endless frozen PE.
913 */
phb3_papr_errinjct_reset(struct phb * phb)914 static int64_t phb3_papr_errinjct_reset(struct phb *phb)
915 {
916 struct phb3 *p = phb_to_phb3(phb);
917
918 out_be64(p->regs + PHB_PAPR_ERR_INJ_CTL, 0x0ul);
919 out_be64(p->regs + PHB_PAPR_ERR_INJ_ADDR, 0x0ul);
920 out_be64(p->regs + PHB_PAPR_ERR_INJ_MASK, 0x0ul);
921
922 return OPAL_SUCCESS;
923 }
924
phb3_set_phb_mem_window(struct phb * phb,uint16_t window_type,uint16_t window_num,uint64_t addr,uint64_t __unused pci_addr,uint64_t size)925 static int64_t phb3_set_phb_mem_window(struct phb *phb,
926 uint16_t window_type,
927 uint16_t window_num,
928 uint64_t addr,
929 uint64_t __unused pci_addr,
930 uint64_t size)
931 {
932 struct phb3 *p = phb_to_phb3(phb);
933 uint64_t data64;
934
935 /*
936 * By design, PHB3 doesn't support IODT any more.
937 * Besides, we can't enable M32 BAR as well. So
938 * the function is used to do M64 mapping and each
939 * BAR is supposed to be shared by all PEs.
940 */
941 switch (window_type) {
942 case OPAL_IO_WINDOW_TYPE:
943 case OPAL_M32_WINDOW_TYPE:
944 return OPAL_UNSUPPORTED;
945 case OPAL_M64_WINDOW_TYPE:
946 if (window_num >= 16)
947 return OPAL_PARAMETER;
948
949 data64 = p->m64b_cache[window_num];
950 if (data64 & IODA2_M64BT_SINGLE_PE) {
951 if ((addr & 0x1FFFFFFul) ||
952 (size & 0x1FFFFFFul))
953 return OPAL_PARAMETER;
954 } else {
955 if ((addr & 0xFFFFFul) ||
956 (size & 0xFFFFFul))
957 return OPAL_PARAMETER;
958 }
959
960 /* size should be 2^N */
961 if (!size || size & (size-1))
962 return OPAL_PARAMETER;
963
964 /* address should be size aligned */
965 if (addr & (size - 1))
966 return OPAL_PARAMETER;
967
968 break;
969 default:
970 return OPAL_PARAMETER;
971 }
972
973 if (data64 & IODA2_M64BT_SINGLE_PE) {
974 data64 = SETFIELD(IODA2_M64BT_SINGLE_BASE, data64,
975 addr >> 25);
976 data64 = SETFIELD(IODA2_M64BT_SINGLE_MASK, data64,
977 0x20000000 - (size >> 25));
978 } else {
979 data64 = SETFIELD(IODA2_M64BT_BASE, data64,
980 addr >> 20);
981 data64 = SETFIELD(IODA2_M64BT_MASK, data64,
982 0x40000000 - (size >> 20));
983 }
984 p->m64b_cache[window_num] = data64;
985
986 return OPAL_SUCCESS;
987 }
988
989 /*
990 * For one specific M64 BAR, it can be shared by all PEs,
991 * or owned by single PE exclusively.
992 */
phb3_phb_mmio_enable(struct phb * phb,uint16_t window_type,uint16_t window_num,uint16_t enable)993 static int64_t phb3_phb_mmio_enable(struct phb *phb,
994 uint16_t window_type,
995 uint16_t window_num,
996 uint16_t enable)
997 {
998 struct phb3 *p = phb_to_phb3(phb);
999 uint64_t data64, base, mask;
1000
1001 /*
1002 * By design, PHB3 doesn't support IODT any more.
1003 * Besides, we can't enable M32 BAR as well. So
1004 * the function is used to do M64 mapping and each
1005 * BAR is supposed to be shared by all PEs.
1006 */
1007 switch (window_type) {
1008 case OPAL_IO_WINDOW_TYPE:
1009 case OPAL_M32_WINDOW_TYPE:
1010 return OPAL_UNSUPPORTED;
1011 case OPAL_M64_WINDOW_TYPE:
1012 if (window_num >= 16 ||
1013 enable > OPAL_ENABLE_M64_NON_SPLIT)
1014 return OPAL_PARAMETER;
1015 break;
1016 default:
1017 return OPAL_PARAMETER;
1018 }
1019
1020 /*
1021 * We need check the base/mask while enabling
1022 * the M64 BAR. Otherwise, invalid base/mask
1023 * might cause fenced AIB unintentionally
1024 */
1025 data64 = p->m64b_cache[window_num];
1026 switch (enable) {
1027 case OPAL_DISABLE_M64:
1028 data64 &= ~IODA2_M64BT_SINGLE_PE;
1029 data64 &= ~IODA2_M64BT_ENABLE;
1030 break;
1031 case OPAL_ENABLE_M64_SPLIT:
1032 if (data64 & IODA2_M64BT_SINGLE_PE)
1033 return OPAL_PARAMETER;
1034 base = GETFIELD(IODA2_M64BT_BASE, data64);
1035 base = (base << 20);
1036 mask = GETFIELD(IODA2_M64BT_MASK, data64);
1037 if (base < p->mm0_base || !mask)
1038 return OPAL_PARTIAL;
1039
1040 data64 |= IODA2_M64BT_ENABLE;
1041 break;
1042 case OPAL_ENABLE_M64_NON_SPLIT:
1043 if (!(data64 & IODA2_M64BT_SINGLE_PE))
1044 return OPAL_PARAMETER;
1045 base = GETFIELD(IODA2_M64BT_SINGLE_BASE, data64);
1046 base = (base << 25);
1047 mask = GETFIELD(IODA2_M64BT_SINGLE_MASK, data64);
1048 if (base < p->mm0_base || !mask)
1049 return OPAL_PARTIAL;
1050
1051 data64 |= IODA2_M64BT_SINGLE_PE;
1052 data64 |= IODA2_M64BT_ENABLE;
1053 break;
1054 }
1055
1056 /* Update HW and cache */
1057 phb3_ioda_sel(p, IODA2_TBL_M64BT, window_num, false);
1058 out_be64(p->regs + PHB_IODA_DATA0, data64);
1059 p->m64b_cache[window_num] = data64;
1060 return OPAL_SUCCESS;
1061 }
1062
phb3_map_pe_mmio_window(struct phb * phb,uint64_t pe_number,uint16_t window_type,uint16_t window_num,uint16_t segment_num)1063 static int64_t phb3_map_pe_mmio_window(struct phb *phb,
1064 uint64_t pe_number,
1065 uint16_t window_type,
1066 uint16_t window_num,
1067 uint16_t segment_num)
1068 {
1069 struct phb3 *p = phb_to_phb3(phb);
1070 uint64_t data64, *cache;
1071
1072 if (pe_number >= PHB3_MAX_PE_NUM)
1073 return OPAL_PARAMETER;
1074
1075 /*
1076 * PHB3 doesn't support IODT any more. On the other
1077 * hand, PHB3 support M64DT with much more flexibility.
1078 * we need figure it out later. At least, we never use
1079 * M64DT in kernel.
1080 */
1081 switch(window_type) {
1082 case OPAL_IO_WINDOW_TYPE:
1083 return OPAL_UNSUPPORTED;
1084 case OPAL_M32_WINDOW_TYPE:
1085 if (window_num != 0 || segment_num >= PHB3_MAX_PE_NUM)
1086 return OPAL_PARAMETER;
1087
1088 cache = &p->m32d_cache[segment_num];
1089 phb3_ioda_sel(p, IODA2_TBL_M32DT, segment_num, false);
1090 out_be64(p->regs + PHB_IODA_DATA0,
1091 SETFIELD(IODA2_M32DT_PE, 0ull, pe_number));
1092 *cache = SETFIELD(IODA2_M32DT_PE, 0ull, pe_number);
1093
1094 break;
1095 case OPAL_M64_WINDOW_TYPE:
1096 if (window_num >= 16)
1097 return OPAL_PARAMETER;
1098 cache = &p->m64b_cache[window_num];
1099 data64 = *cache;
1100
1101 /* The BAR shouldn't be enabled yet */
1102 if (data64 & IODA2_M64BT_ENABLE)
1103 return OPAL_PARTIAL;
1104
1105 data64 |= IODA2_M64BT_SINGLE_PE;
1106 data64 = SETFIELD(IODA2_M64BT_PE_HI, data64, pe_number >> 5);
1107 data64 = SETFIELD(IODA2_M64BT_PE_LOW, data64, pe_number);
1108 *cache = data64;
1109
1110 break;
1111 default:
1112 return OPAL_PARAMETER;
1113 }
1114
1115 return OPAL_SUCCESS;
1116 }
1117
phb3_map_pe_dma_window(struct phb * phb,uint64_t pe_number,uint16_t window_id,uint16_t tce_levels,uint64_t tce_table_addr,uint64_t tce_table_size,uint64_t tce_page_size)1118 static int64_t phb3_map_pe_dma_window(struct phb *phb,
1119 uint64_t pe_number,
1120 uint16_t window_id,
1121 uint16_t tce_levels,
1122 uint64_t tce_table_addr,
1123 uint64_t tce_table_size,
1124 uint64_t tce_page_size)
1125 {
1126 struct phb3 *p = phb_to_phb3(phb);
1127 uint64_t tts_encoded;
1128 uint64_t data64 = 0;
1129
1130 /*
1131 * Sanity check. We currently only support "2 window per PE" mode
1132 * ie, only bit 59 of the PCI address is used to select the window
1133 */
1134 if (pe_number >= PHB3_MAX_PE_NUM ||
1135 (window_id >> 1) != pe_number)
1136 return OPAL_PARAMETER;
1137
1138 /*
1139 * tce_table_size == 0 is used to disable an entry, in this case
1140 * we ignore other arguments
1141 */
1142 if (tce_table_size == 0) {
1143 phb3_ioda_sel(p, IODA2_TBL_TVT, window_id, false);
1144 out_be64(p->regs + PHB_IODA_DATA0, 0);
1145 p->tve_cache[window_id] = 0;
1146 return OPAL_SUCCESS;
1147 }
1148
1149 /* Additional arguments validation */
1150 if (tce_levels < 1 || tce_levels > 5 ||
1151 !is_pow2(tce_table_size) ||
1152 tce_table_size < 0x1000)
1153 return OPAL_PARAMETER;
1154
1155 /* Encode TCE table size */
1156 data64 = SETFIELD(IODA2_TVT_TABLE_ADDR, 0ul, tce_table_addr >> 12);
1157 tts_encoded = ilog2(tce_table_size) - 11;
1158 if (tts_encoded > 31)
1159 return OPAL_PARAMETER;
1160 data64 = SETFIELD(IODA2_TVT_TCE_TABLE_SIZE, data64, tts_encoded);
1161
1162 /* Encode TCE page size */
1163 switch (tce_page_size) {
1164 case 0x1000: /* 4K */
1165 data64 = SETFIELD(IODA2_TVT_IO_PSIZE, data64, 1);
1166 break;
1167 case 0x10000: /* 64K */
1168 data64 = SETFIELD(IODA2_TVT_IO_PSIZE, data64, 5);
1169 break;
1170 case 0x1000000: /* 16M */
1171 data64 = SETFIELD(IODA2_TVT_IO_PSIZE, data64, 13);
1172 break;
1173 case 0x10000000: /* 256M */
1174 data64 = SETFIELD(IODA2_TVT_IO_PSIZE, data64, 17);
1175 break;
1176 default:
1177 return OPAL_PARAMETER;
1178 }
1179
1180 /* Encode number of levels */
1181 data64 = SETFIELD(IODA2_TVT_NUM_LEVELS, data64, tce_levels - 1);
1182
1183 phb3_ioda_sel(p, IODA2_TBL_TVT, window_id, false);
1184 out_be64(p->regs + PHB_IODA_DATA0, data64);
1185 p->tve_cache[window_id] = data64;
1186
1187 return OPAL_SUCCESS;
1188 }
1189
phb3_map_pe_dma_window_real(struct phb * phb,uint64_t pe_number,uint16_t window_id,uint64_t pci_start_addr,uint64_t pci_mem_size)1190 static int64_t phb3_map_pe_dma_window_real(struct phb *phb,
1191 uint64_t pe_number,
1192 uint16_t window_id,
1193 uint64_t pci_start_addr,
1194 uint64_t pci_mem_size)
1195 {
1196 struct phb3 *p = phb_to_phb3(phb);
1197 uint64_t end;
1198 uint64_t tve;
1199
1200 if (pe_number >= PHB3_MAX_PE_NUM ||
1201 (window_id >> 1) != pe_number)
1202 return OPAL_PARAMETER;
1203
1204 if (pci_mem_size) {
1205 /* Enable */
1206
1207 /*
1208 * Check that the start address has the right TVE index,
1209 * we only support the 1 bit mode where each PE has 2
1210 * TVEs
1211 */
1212 if ((pci_start_addr >> 59) != (window_id & 1))
1213 return OPAL_PARAMETER;
1214 pci_start_addr &= ((1ull << 59) - 1);
1215 end = pci_start_addr + pci_mem_size;
1216
1217 /* We have to be 16M aligned */
1218 if ((pci_start_addr & 0x00ffffff) ||
1219 (pci_mem_size & 0x00ffffff))
1220 return OPAL_PARAMETER;
1221
1222 /*
1223 * It *looks* like this is the max we can support (we need
1224 * to verify this. Also we are not checking for rollover,
1225 * but then we aren't trying too hard to protect ourselves
1226 * againt a completely broken OS.
1227 */
1228 if (end > 0x0003ffffffffffffull)
1229 return OPAL_PARAMETER;
1230
1231 /*
1232 * Put start address bits 49:24 into TVE[52:53]||[0:23]
1233 * and end address bits 49:24 into TVE[54:55]||[24:47]
1234 * and set TVE[51]
1235 */
1236 tve = (pci_start_addr << 16) & (0xffffffull << 48);
1237 tve |= (pci_start_addr >> 38) & (3ull << 10);
1238 tve |= (end >> 8) & (0xfffffful << 16);
1239 tve |= (end >> 40) & (3ull << 8);
1240 tve |= PPC_BIT(51);
1241 } else {
1242 /* Disable */
1243 tve = 0;
1244 }
1245
1246 phb3_ioda_sel(p, IODA2_TBL_TVT, window_id, false);
1247 out_be64(p->regs + PHB_IODA_DATA0, tve);
1248 p->tve_cache[window_id] = tve;
1249
1250 return OPAL_SUCCESS;
1251 }
1252
phb3_pci_msi_check_q(struct phb3 * p,uint32_t ive_num)1253 static bool phb3_pci_msi_check_q(struct phb3 *p, uint32_t ive_num)
1254 {
1255 uint64_t ive, ivc, ffi, state;
1256 uint8_t *q_byte;
1257
1258 /* Each IVE has 16-bytes or 128-bytes */
1259 ive = p->tbl_ivt + (ive_num * IVT_TABLE_STRIDE * 8);
1260 q_byte = (uint8_t *)(ive + 5);
1261
1262 /*
1263 * Handle Q bit. If the Q bit doesn't show up,
1264 * we would have CI load to make that.
1265 */
1266 if (!(*q_byte & 0x1)) {
1267 /* Read from random PHB reg to force flush */
1268 in_be64(p->regs + PHB_IVC_UPDATE);
1269
1270 /* Order with subsequent read of Q */
1271 sync();
1272
1273 /* Q still not set, bail out */
1274 if (!(*q_byte & 0x1))
1275 return false;
1276 }
1277
1278 /* Lock FFI and send interrupt */
1279 while (1) {
1280 state = in_be64(p->regs + PHB_FFI_LOCK);
1281 if (!state)
1282 break;
1283 if (state == ~0ULL) /* PHB Fenced */
1284 return false;
1285 }
1286
1287 /* Clear Q bit and update IVC */
1288 *q_byte = 0;
1289 ivc = SETFIELD(PHB_IVC_UPDATE_SID, 0ul, ive_num) |
1290 PHB_IVC_UPDATE_ENABLE_Q;
1291 out_be64(p->regs + PHB_IVC_UPDATE, ivc);
1292
1293 /*
1294 * Resend interrupt. Note the lock clear bit isn't documented in
1295 * the PHB3 spec and thus is probably unnecessary but it's in
1296 * IODA2 so let's be safe here, it won't hurt to set it
1297 */
1298 ffi = SETFIELD(PHB_FFI_REQUEST_ISN, 0ul, ive_num) | PHB_FFI_LOCK_CLEAR;
1299 out_be64(p->regs + PHB_FFI_REQUEST, ffi);
1300
1301 return true;
1302 }
1303
phb3_pci_msi_flush_ive(struct phb3 * p,uint32_t ive_num)1304 static void phb3_pci_msi_flush_ive(struct phb3 *p, uint32_t ive_num)
1305 {
1306 asm volatile("dcbf %0,%1"
1307 :
1308 : "b" (p->tbl_ivt), "r" (ive_num * IVT_TABLE_STRIDE * 8)
1309 : "memory");
1310 }
1311
phb3_pci_msi_eoi(struct phb * phb,uint32_t hwirq)1312 static int64_t phb3_pci_msi_eoi(struct phb *phb,
1313 uint32_t hwirq)
1314 {
1315 struct phb3 *p = phb_to_phb3(phb);
1316 uint32_t ive_num = PHB3_IRQ_NUM(hwirq);
1317 uint64_t ive, ivc;
1318 uint8_t *p_byte, gp, gen, newgen;
1319
1320 /* OS might not configure IVT yet */
1321 if (!p->tbl_ivt)
1322 return OPAL_HARDWARE;
1323
1324 /* Each IVE has 16-bytes or 128-bytes */
1325 ive = p->tbl_ivt + (ive_num * IVT_TABLE_STRIDE * 8);
1326 p_byte = (uint8_t *)(ive + 4);
1327
1328 /* Read generation and P */
1329 gp = *p_byte;
1330 gen = (gp >> 1) & 3;
1331 newgen = (gen + 1) & 3;
1332
1333 /* Increment generation count and clear P */
1334 *p_byte = newgen << 1;
1335
1336 /* If at this point:
1337 * - the IVC is invalid (due to high IRQ load) and
1338 * - we get a new interrupt on this hwirq.
1339 * Due to the new interrupt, the IVC will fetch from the IVT.
1340 * This IVC reload will result in P set and gen=n+1. This
1341 * interrupt may not actually be delievered at this point
1342 * though.
1343 *
1344 * Software will then try to clear P in the IVC (out_be64
1345 * below). This could cause an interrupt to be lost because P
1346 * is cleared in the IVC without the new interrupt being
1347 * delivered.
1348 *
1349 * To avoid this race, we increment the generation count in
1350 * the IVT when we clear P. When software writes the IVC with
1351 * P cleared but with gen=n, the IVC won't actually clear P
1352 * because gen doesn't match what it just cached from the IVT.
1353 * Hence we don't lose P being set.
1354 */
1355
1356 /* Update the P bit in the IVC is gen count matches */
1357 ivc = SETFIELD(PHB_IVC_UPDATE_SID, 0ul, ive_num) |
1358 PHB_IVC_UPDATE_ENABLE_P |
1359 PHB_IVC_UPDATE_ENABLE_GEN |
1360 PHB_IVC_UPDATE_ENABLE_CON |
1361 SETFIELD(PHB_IVC_UPDATE_GEN_MATCH, 0ul, gen) |
1362 SETFIELD(PHB_IVC_UPDATE_GEN, 0ul, newgen);
1363 /* out_be64 has a sync to order with the IVT update above */
1364 out_be64(p->regs + PHB_IVC_UPDATE, ivc);
1365
1366 /* Handle Q bit */
1367 phb3_pci_msi_check_q(p, ive_num);
1368
1369 phb3_pci_msi_flush_ive(p, ive_num);
1370
1371 return OPAL_SUCCESS;
1372 }
1373
phb3_set_ive_pe(struct phb * phb,uint64_t pe_number,uint32_t ive_num)1374 static int64_t phb3_set_ive_pe(struct phb *phb,
1375 uint64_t pe_number,
1376 uint32_t ive_num)
1377 {
1378 struct phb3 *p = phb_to_phb3(phb);
1379 uint64_t *cache, ivep, data64;
1380 uint16_t *pe_word;
1381
1382 /* OS should enable the BAR in advance */
1383 if (!p->tbl_ivt)
1384 return OPAL_HARDWARE;
1385
1386 /* Each IVE reserves 128 bytes */
1387 if (pe_number >= PHB3_MAX_PE_NUM ||
1388 ive_num >= IVT_TABLE_ENTRIES)
1389 return OPAL_PARAMETER;
1390
1391 /* Update IVE cache */
1392 cache = &p->ive_cache[ive_num];
1393 *cache = SETFIELD(IODA2_IVT_PE, *cache, pe_number);
1394
1395 /* Update in-memory IVE without clobbering P and Q */
1396 ivep = p->tbl_ivt + (ive_num * IVT_TABLE_STRIDE * 8);
1397 pe_word = (uint16_t *)(ivep + 6);
1398 *pe_word = pe_number;
1399
1400 /* Invalidate IVC */
1401 data64 = SETFIELD(PHB_IVC_INVALIDATE_SID, 0ul, ive_num);
1402 out_be64(p->regs + PHB_IVC_INVALIDATE, data64);
1403
1404 return OPAL_SUCCESS;
1405 }
1406
phb3_get_msi_32(struct phb * phb __unused,uint64_t pe_number,uint32_t ive_num,uint8_t msi_range,uint32_t * msi_address,uint32_t * message_data)1407 static int64_t phb3_get_msi_32(struct phb *phb __unused,
1408 uint64_t pe_number,
1409 uint32_t ive_num,
1410 uint8_t msi_range,
1411 uint32_t *msi_address,
1412 uint32_t *message_data)
1413 {
1414 /*
1415 * Sanity check. We needn't check on mve_number (PE#)
1416 * on PHB3 since the interrupt source is purely determined
1417 * by its DMA address and data, but the check isn't
1418 * harmful.
1419 */
1420 if (pe_number >= PHB3_MAX_PE_NUM ||
1421 ive_num >= IVT_TABLE_ENTRIES ||
1422 msi_range != 1 || !msi_address|| !message_data)
1423 return OPAL_PARAMETER;
1424
1425 /*
1426 * DMA address and data will form the IVE index.
1427 * For more details, please refer to IODA2 spec.
1428 */
1429 *msi_address = 0xFFFF0000 | ((ive_num << 4) & 0xFFFFFE0F);
1430 *message_data = ive_num & 0x1F;
1431
1432 return OPAL_SUCCESS;
1433 }
1434
phb3_get_msi_64(struct phb * phb __unused,uint64_t pe_number,uint32_t ive_num,uint8_t msi_range,uint64_t * msi_address,uint32_t * message_data)1435 static int64_t phb3_get_msi_64(struct phb *phb __unused,
1436 uint64_t pe_number,
1437 uint32_t ive_num,
1438 uint8_t msi_range,
1439 uint64_t *msi_address,
1440 uint32_t *message_data)
1441 {
1442 /* Sanity check */
1443 if (pe_number >= PHB3_MAX_PE_NUM ||
1444 ive_num >= IVT_TABLE_ENTRIES ||
1445 msi_range != 1 || !msi_address || !message_data)
1446 return OPAL_PARAMETER;
1447
1448 /*
1449 * DMA address and data will form the IVE index.
1450 * For more details, please refer to IODA2 spec.
1451 */
1452 *msi_address = (0x1ul << 60) | ((ive_num << 4) & 0xFFFFFFFFFFFFFE0Ful);
1453 *message_data = ive_num & 0x1F;
1454
1455 return OPAL_SUCCESS;
1456 }
1457
phb3_err_check_pbcq(struct phb3 * p)1458 static bool phb3_err_check_pbcq(struct phb3 *p)
1459 {
1460 uint64_t nfir, mask, wof, val64;
1461 int32_t class, bit;
1462 uint64_t severity[PHB3_ERR_CLASS_LAST] = {
1463 0x0000000000000000UL, /* NONE */
1464 0x018000F800000000UL, /* DEAD */
1465 0x7E7DC70000000000UL, /* FENCED */
1466 0x0000000000000000UL, /* ER */
1467 0x0000000000000000UL /* INF */
1468 };
1469
1470 /*
1471 * Read on NFIR to see if XSCOM is working properly.
1472 * If XSCOM doesn't work well, we need take the PHB
1473 * into account any more.
1474 */
1475 xscom_read(p->chip_id, p->pe_xscom + 0x0, &nfir);
1476 if (nfir == 0xffffffffffffffffUL) {
1477 p->err.err_src = PHB3_ERR_SRC_NONE;
1478 p->err.err_class = PHB3_ERR_CLASS_DEAD;
1479 phb3_set_err_pending(p, true);
1480 return true;
1481 }
1482
1483 /*
1484 * Check WOF. We need handle unmasked errors firstly.
1485 * We probably run into the situation (on simulator)
1486 * where we have asserted FIR bits, but WOF has nothing.
1487 * For that case, we should check FIR as well.
1488 */
1489 xscom_read(p->chip_id, p->pe_xscom + 0x3, &mask);
1490 xscom_read(p->chip_id, p->pe_xscom + 0x8, &wof);
1491 if (wof & ~mask)
1492 wof &= ~mask;
1493 if (!wof) {
1494 if (nfir & ~mask)
1495 nfir &= ~mask;
1496 if (!nfir)
1497 return false;
1498 wof = nfir;
1499 }
1500
1501 /* We shouldn't hit class PHB3_ERR_CLASS_NONE */
1502 for (class = PHB3_ERR_CLASS_NONE;
1503 class < PHB3_ERR_CLASS_LAST;
1504 class++) {
1505 val64 = wof & severity[class];
1506 if (!val64)
1507 continue;
1508
1509 for (bit = 0; bit < 64; bit++) {
1510 if (val64 & PPC_BIT(bit)) {
1511 p->err.err_src = PHB3_ERR_SRC_PBCQ;
1512 p->err.err_class = class;
1513 p->err.err_bit = 63 - bit;
1514 phb3_set_err_pending(p, true);
1515 return true;
1516 }
1517 }
1518 }
1519
1520 return false;
1521 }
1522
phb3_err_check_lem(struct phb3 * p)1523 static bool phb3_err_check_lem(struct phb3 *p)
1524 {
1525 uint64_t fir, wof, mask, val64;
1526 int32_t class, bit;
1527 uint64_t severity[PHB3_ERR_CLASS_LAST] = {
1528 0x0000000000000000UL, /* NONE */
1529 0x0000000000000000UL, /* DEAD */
1530 0xADB670C980ADD151UL, /* FENCED */
1531 0x000800107F500A2CUL, /* ER */
1532 0x42018E2200002482UL /* INF */
1533 };
1534
1535 /*
1536 * Read FIR. If XSCOM or ASB is frozen, we needn't
1537 * go forward and just mark the PHB with dead state
1538 */
1539 fir = phb3_read_reg_asb(p, PHB_LEM_FIR_ACCUM);
1540 if (fir == 0xffffffffffffffffUL) {
1541 p->err.err_src = PHB3_ERR_SRC_PHB;
1542 p->err.err_class = PHB3_ERR_CLASS_DEAD;
1543 phb3_set_err_pending(p, true);
1544 return true;
1545 }
1546
1547 /*
1548 * Check on WOF for the unmasked errors firstly. Under
1549 * some situation where we run skiboot on simulator,
1550 * we already had FIR bits asserted, but WOF is still zero.
1551 * For that case, we check FIR directly.
1552 */
1553 wof = phb3_read_reg_asb(p, PHB_LEM_WOF);
1554 mask = phb3_read_reg_asb(p, PHB_LEM_ERROR_MASK);
1555 if (wof & ~mask)
1556 wof &= ~mask;
1557 if (!wof) {
1558 if (fir & ~mask)
1559 fir &= ~mask;
1560 if (!fir)
1561 return false;
1562 wof = fir;
1563 }
1564
1565 /* We shouldn't hit PHB3_ERR_CLASS_NONE */
1566 for (class = PHB3_ERR_CLASS_NONE;
1567 class < PHB3_ERR_CLASS_LAST;
1568 class++) {
1569 val64 = wof & severity[class];
1570 if (!val64)
1571 continue;
1572
1573 for (bit = 0; bit < 64; bit++) {
1574 if (val64 & PPC_BIT(bit)) {
1575 p->err.err_src = PHB3_ERR_SRC_PHB;
1576 p->err.err_class = class;
1577 p->err.err_bit = 63 - bit;
1578 phb3_set_err_pending(p, true);
1579 return true;
1580 }
1581 }
1582 }
1583
1584 return false;
1585 }
1586
1587 /*
1588 * The function can be called during error recovery for INF
1589 * and ER class. For INF case, it's expected to be called
1590 * when grabbing the error log. We will call it explicitly
1591 * when clearing frozen PE state for ER case.
1592 */
phb3_err_ER_clear(struct phb3 * p)1593 static void phb3_err_ER_clear(struct phb3 *p)
1594 {
1595 uint32_t val32;
1596 uint64_t val64;
1597 uint64_t fir = in_be64(p->regs + PHB_LEM_FIR_ACCUM);
1598
1599 /* Rec 1: Grab the PCI config lock */
1600 /* Removed... unnecessary. We have our own lock here */
1601
1602 /* Rec 2/3/4: Take all inbound transactions */
1603 out_be64(p->regs + PHB_CONFIG_ADDRESS, 0x8000001c00000000ul);
1604 out_be32(p->regs + PHB_CONFIG_DATA, 0x10000000);
1605
1606 /* Rec 5/6/7: Clear pending non-fatal errors */
1607 out_be64(p->regs + PHB_CONFIG_ADDRESS, 0x8000005000000000ul);
1608 val32 = in_be32(p->regs + PHB_CONFIG_DATA);
1609 out_be32(p->regs + PHB_CONFIG_DATA, (val32 & 0xe0700000) | 0x0f000f00);
1610
1611 /* Rec 8/9/10: Clear pending fatal errors for AER */
1612 out_be64(p->regs + PHB_CONFIG_ADDRESS, 0x8000010400000000ul);
1613 out_be32(p->regs + PHB_CONFIG_DATA, 0xffffffff);
1614
1615 /* Rec 11/12/13: Clear pending non-fatal errors for AER */
1616 out_be64(p->regs + PHB_CONFIG_ADDRESS, 0x8000011000000000ul);
1617 out_be32(p->regs + PHB_CONFIG_DATA, 0xffffffff);
1618
1619 /* Rec 22/23/24: Clear root port errors */
1620 out_be64(p->regs + PHB_CONFIG_ADDRESS, 0x8000013000000000ul);
1621 out_be32(p->regs + PHB_CONFIG_DATA, 0xffffffff);
1622
1623 /* Rec 25/26/27: Enable IO and MMIO bar */
1624 out_be64(p->regs + PHB_CONFIG_ADDRESS, 0x8000004000000000ul);
1625 out_be32(p->regs + PHB_CONFIG_DATA, 0x470100f8);
1626
1627 /* Rec 28: Release the PCI config lock */
1628 /* Removed... unnecessary. We have our own lock here */
1629
1630 /* Rec 29...34: Clear UTL errors */
1631 val64 = in_be64(p->regs + UTL_SYS_BUS_AGENT_STATUS);
1632 out_be64(p->regs + UTL_SYS_BUS_AGENT_STATUS, val64);
1633 val64 = in_be64(p->regs + UTL_PCIE_PORT_STATUS);
1634 out_be64(p->regs + UTL_PCIE_PORT_STATUS, val64);
1635 val64 = in_be64(p->regs + UTL_RC_STATUS);
1636 out_be64(p->regs + UTL_RC_STATUS, val64);
1637
1638 /* Rec 39...66: Clear PHB error trap */
1639 val64 = in_be64(p->regs + PHB_ERR_STATUS);
1640 out_be64(p->regs + PHB_ERR_STATUS, val64);
1641 out_be64(p->regs + PHB_ERR1_STATUS, 0x0ul);
1642 out_be64(p->regs + PHB_ERR_LOG_0, 0x0ul);
1643 out_be64(p->regs + PHB_ERR_LOG_1, 0x0ul);
1644
1645 val64 = in_be64(p->regs + PHB_OUT_ERR_STATUS);
1646 out_be64(p->regs + PHB_OUT_ERR_STATUS, val64);
1647 out_be64(p->regs + PHB_OUT_ERR1_STATUS, 0x0ul);
1648 out_be64(p->regs + PHB_OUT_ERR_LOG_0, 0x0ul);
1649 out_be64(p->regs + PHB_OUT_ERR_LOG_1, 0x0ul);
1650
1651 val64 = in_be64(p->regs + PHB_INA_ERR_STATUS);
1652 out_be64(p->regs + PHB_INA_ERR_STATUS, val64);
1653 out_be64(p->regs + PHB_INA_ERR1_STATUS, 0x0ul);
1654 out_be64(p->regs + PHB_INA_ERR_LOG_0, 0x0ul);
1655 out_be64(p->regs + PHB_INA_ERR_LOG_1, 0x0ul);
1656
1657 val64 = in_be64(p->regs + PHB_INB_ERR_STATUS);
1658 out_be64(p->regs + PHB_INB_ERR_STATUS, val64);
1659 out_be64(p->regs + PHB_INB_ERR1_STATUS, 0x0ul);
1660 out_be64(p->regs + PHB_INB_ERR_LOG_0, 0x0ul);
1661 out_be64(p->regs + PHB_INB_ERR_LOG_1, 0x0ul);
1662
1663 /* Rec 67/68: Clear FIR/WOF */
1664 out_be64(p->regs + PHB_LEM_FIR_AND_MASK, ~fir);
1665 out_be64(p->regs + PHB_LEM_WOF, 0x0ul);
1666 }
1667
phb3_read_phb_status(struct phb3 * p,struct OpalIoPhb3ErrorData * stat)1668 static void phb3_read_phb_status(struct phb3 *p,
1669 struct OpalIoPhb3ErrorData *stat)
1670 {
1671 uint16_t val;
1672 uint64_t *pPEST;
1673 uint64_t val64 = 0;
1674 uint32_t i;
1675
1676 memset(stat, 0, sizeof(struct OpalIoPhb3ErrorData));
1677
1678 /* Error data common part */
1679 stat->common.version = OPAL_PHB_ERROR_DATA_VERSION_1;
1680 stat->common.ioType = OPAL_PHB_ERROR_DATA_TYPE_PHB3;
1681 stat->common.len = sizeof(struct OpalIoPhb3ErrorData);
1682
1683 /*
1684 * We read some registers using config space through AIB.
1685 *
1686 * Get to other registers using ASB when possible to get to them
1687 * through a fence if one is present.
1688 */
1689
1690 /* Use ASB to access PCICFG if the PHB has been fenced */
1691 p->flags |= PHB3_CFG_USE_ASB;
1692
1693 /* Grab RC bridge control, make it 32-bit */
1694 phb3_pcicfg_read16(&p->phb, 0, PCI_CFG_BRCTL, &val);
1695 stat->brdgCtl = val;
1696
1697 /* Grab UTL status registers */
1698 stat->portStatusReg = hi32(phb3_read_reg_asb(p, UTL_PCIE_PORT_STATUS));
1699 stat->rootCmplxStatus = hi32(phb3_read_reg_asb(p, UTL_RC_STATUS));
1700 stat->busAgentStatus = hi32(phb3_read_reg_asb(p, UTL_SYS_BUS_AGENT_STATUS));
1701
1702 /*
1703 * Grab various RC PCIe capability registers. All device, slot
1704 * and link status are 16-bit, so we grab the pair control+status
1705 * for each of them
1706 */
1707 phb3_pcicfg_read32(&p->phb, 0, p->ecap + PCICAP_EXP_DEVCTL,
1708 &stat->deviceStatus);
1709 phb3_pcicfg_read32(&p->phb, 0, p->ecap + PCICAP_EXP_SLOTCTL,
1710 &stat->slotStatus);
1711 phb3_pcicfg_read32(&p->phb, 0, p->ecap + PCICAP_EXP_LCTL,
1712 &stat->linkStatus);
1713
1714 /*
1715 * I assume those are the standard config space header, cmd & status
1716 * together makes 32-bit. Secondary status is 16-bit so I'll clear
1717 * the top on that one
1718 */
1719 phb3_pcicfg_read32(&p->phb, 0, PCI_CFG_CMD, &stat->devCmdStatus);
1720 phb3_pcicfg_read16(&p->phb, 0, PCI_CFG_SECONDARY_STATUS, &val);
1721 stat->devSecStatus = val;
1722
1723 /* Grab a bunch of AER regs */
1724 phb3_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_RERR_STA,
1725 &stat->rootErrorStatus);
1726 phb3_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_UE_STATUS,
1727 &stat->uncorrErrorStatus);
1728 phb3_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_CE_STATUS,
1729 &stat->corrErrorStatus);
1730 phb3_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG0,
1731 &stat->tlpHdr1);
1732 phb3_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG1,
1733 &stat->tlpHdr2);
1734 phb3_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG2,
1735 &stat->tlpHdr3);
1736 phb3_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG3,
1737 &stat->tlpHdr4);
1738 phb3_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_SRCID,
1739 &stat->sourceId);
1740
1741 /* Restore to AIB */
1742 p->flags &= ~PHB3_CFG_USE_ASB;
1743
1744 /* PEC NFIR */
1745 xscom_read(p->chip_id, p->pe_xscom + 0x0, &stat->nFir);
1746 xscom_read(p->chip_id, p->pe_xscom + 0x3, &stat->nFirMask);
1747 xscom_read(p->chip_id, p->pe_xscom + 0x8, &stat->nFirWOF);
1748
1749 /* PHB3 inbound and outbound error Regs */
1750 stat->phbPlssr = phb3_read_reg_asb(p, PHB_CPU_LOADSTORE_STATUS);
1751 stat->phbCsr = phb3_read_reg_asb(p, PHB_DMA_CHAN_STATUS);
1752 stat->lemFir = phb3_read_reg_asb(p, PHB_LEM_FIR_ACCUM);
1753 stat->lemErrorMask = phb3_read_reg_asb(p, PHB_LEM_ERROR_MASK);
1754 stat->lemWOF = phb3_read_reg_asb(p, PHB_LEM_WOF);
1755 stat->phbErrorStatus = phb3_read_reg_asb(p, PHB_ERR_STATUS);
1756 stat->phbFirstErrorStatus = phb3_read_reg_asb(p, PHB_ERR1_STATUS);
1757 stat->phbErrorLog0 = phb3_read_reg_asb(p, PHB_ERR_LOG_0);
1758 stat->phbErrorLog1 = phb3_read_reg_asb(p, PHB_ERR_LOG_1);
1759 stat->mmioErrorStatus = phb3_read_reg_asb(p, PHB_OUT_ERR_STATUS);
1760 stat->mmioFirstErrorStatus = phb3_read_reg_asb(p, PHB_OUT_ERR1_STATUS);
1761 stat->mmioErrorLog0 = phb3_read_reg_asb(p, PHB_OUT_ERR_LOG_0);
1762 stat->mmioErrorLog1 = phb3_read_reg_asb(p, PHB_OUT_ERR_LOG_1);
1763 stat->dma0ErrorStatus = phb3_read_reg_asb(p, PHB_INA_ERR_STATUS);
1764 stat->dma0FirstErrorStatus = phb3_read_reg_asb(p, PHB_INA_ERR1_STATUS);
1765 stat->dma0ErrorLog0 = phb3_read_reg_asb(p, PHB_INA_ERR_LOG_0);
1766 stat->dma0ErrorLog1 = phb3_read_reg_asb(p, PHB_INA_ERR_LOG_1);
1767 stat->dma1ErrorStatus = phb3_read_reg_asb(p, PHB_INB_ERR_STATUS);
1768 stat->dma1FirstErrorStatus = phb3_read_reg_asb(p, PHB_INB_ERR1_STATUS);
1769 stat->dma1ErrorLog0 = phb3_read_reg_asb(p, PHB_INB_ERR_LOG_0);
1770 stat->dma1ErrorLog1 = phb3_read_reg_asb(p, PHB_INB_ERR_LOG_1);
1771
1772 /*
1773 * Grab PESTA & B content. The error bit (bit#0) should
1774 * be fetched from IODA and the left content from memory
1775 * resident tables.
1776 */
1777 pPEST = (uint64_t *)p->tbl_pest;
1778 val64 = PHB_IODA_AD_AUTOINC;
1779 val64 = SETFIELD(PHB_IODA_AD_TSEL, val64, IODA2_TBL_PESTA);
1780 phb3_write_reg_asb(p, PHB_IODA_ADDR, val64);
1781 for (i = 0; i < OPAL_PHB3_NUM_PEST_REGS; i++) {
1782 stat->pestA[i] = phb3_read_reg_asb(p, PHB_IODA_DATA0);
1783 stat->pestA[i] |= pPEST[2 * i];
1784 }
1785
1786 val64 = PHB_IODA_AD_AUTOINC;
1787 val64 = SETFIELD(PHB_IODA_AD_TSEL, val64, IODA2_TBL_PESTB);
1788 phb3_write_reg_asb(p, PHB_IODA_ADDR, val64);
1789 for (i = 0; i < OPAL_PHB3_NUM_PEST_REGS; i++) {
1790 stat->pestB[i] = phb3_read_reg_asb(p, PHB_IODA_DATA0);
1791 stat->pestB[i] |= pPEST[2 * i + 1];
1792 }
1793 }
1794
phb3_eeh_dump_regs(struct phb3 * p,struct OpalIoPhb3ErrorData * regs)1795 static void phb3_eeh_dump_regs(struct phb3 *p, struct OpalIoPhb3ErrorData *regs)
1796 {
1797 struct OpalIoPhb3ErrorData *s;
1798 unsigned int i;
1799
1800 if (!verbose_eeh)
1801 return;
1802
1803 if (!regs) {
1804 s = zalloc(sizeof(struct OpalIoPhb3ErrorData));
1805 if (!s) {
1806 PHBERR(p, "Failed to allocate error info !\n");
1807 return;
1808 }
1809
1810 phb3_read_phb_status(p, s);
1811 } else {
1812 s = regs;
1813 }
1814
1815 PHBERR(p, "Error detected!\n");
1816
1817 PHBERR(p, " portStatusReg = %08x\n", s->portStatusReg);
1818 PHBERR(p, " rootCmplxStatus = %08x\n", s->rootCmplxStatus);
1819 PHBERR(p, " busAgentStatus = %08x\n", s->busAgentStatus);
1820
1821 PHBERR(p, " errorClass = %016llx\n", s->errorClass);
1822 PHBERR(p, " correlator = %016llx\n", s->correlator);
1823
1824 PHBERR(p, " brdgCtl = %08x\n", s->brdgCtl);
1825 PHBERR(p, " deviceStatus = %08x\n", s->deviceStatus);
1826 PHBERR(p, " slotStatus = %08x\n", s->slotStatus);
1827 PHBERR(p, " linkStatus = %08x\n", s->linkStatus);
1828 PHBERR(p, " devCmdStatus = %08x\n", s->devCmdStatus);
1829 PHBERR(p, " devSecStatus = %08x\n", s->devSecStatus);
1830 PHBERR(p, " rootErrorStatus = %08x\n", s->rootErrorStatus);
1831 PHBERR(p, " corrErrorStatus = %08x\n", s->corrErrorStatus);
1832 PHBERR(p, " uncorrErrorStatus = %08x\n", s->uncorrErrorStatus);
1833
1834 /* Byte swap TLP headers so they are the same as the PCIe spec */
1835 PHBERR(p, " tlpHdr1 = %08x\n", bswap_32(s->tlpHdr1));
1836 PHBERR(p, " tlpHdr2 = %08x\n", bswap_32(s->tlpHdr2));
1837 PHBERR(p, " tlpHdr3 = %08x\n", bswap_32(s->tlpHdr3));
1838 PHBERR(p, " tlpHdr4 = %08x\n", bswap_32(s->tlpHdr4));
1839 PHBERR(p, " sourceId = %08x\n", s->sourceId);
1840
1841 PHBERR(p, " nFir = %016llx\n", s->nFir);
1842 PHBERR(p, " nFirMask = %016llx\n", s->nFirMask);
1843 PHBERR(p, " nFirWOF = %016llx\n", s->nFirWOF);
1844 PHBERR(p, " phbPlssr = %016llx\n", s->phbPlssr);
1845 PHBERR(p, " phbCsr = %016llx\n", s->phbCsr);
1846 PHBERR(p, " lemFir = %016llx\n", s->lemFir);
1847 PHBERR(p, " lemErrorMask = %016llx\n", s->lemErrorMask);
1848 PHBERR(p, " lemWOF = %016llx\n", s->lemWOF);
1849
1850 PHBERR(p, " phbErrorStatus = %016llx\n", s->phbErrorStatus);
1851 PHBERR(p, " phbFirstErrorStatus = %016llx\n", s->phbFirstErrorStatus);
1852 PHBERR(p, " phbErrorLog0 = %016llx\n", s->phbErrorLog0);
1853 PHBERR(p, " phbErrorLog1 = %016llx\n", s->phbErrorLog1);
1854
1855 PHBERR(p, " mmioErrorStatus = %016llx\n", s->mmioErrorStatus);
1856 PHBERR(p, "mmioFirstErrorStatus = %016llx\n", s->mmioFirstErrorStatus);
1857 PHBERR(p, " mmioErrorLog0 = %016llx\n", s->mmioErrorLog0);
1858 PHBERR(p, " mmioErrorLog1 = %016llx\n", s->mmioErrorLog1);
1859
1860 PHBERR(p, " dma0ErrorStatus = %016llx\n", s->dma0ErrorStatus);
1861 PHBERR(p, "dma0FirstErrorStatus = %016llx\n", s->dma0FirstErrorStatus);
1862 PHBERR(p, " dma0ErrorLog0 = %016llx\n", s->dma0ErrorLog0);
1863 PHBERR(p, " dma0ErrorLog1 = %016llx\n", s->dma0ErrorLog1);
1864
1865 PHBERR(p, " dma1ErrorStatus = %016llx\n", s->dma1ErrorStatus);
1866 PHBERR(p, "dma1FirstErrorStatus = %016llx\n", s->dma1FirstErrorStatus);
1867 PHBERR(p, " dma1ErrorLog0 = %016llx\n", s->dma1ErrorLog0);
1868 PHBERR(p, " dma1ErrorLog1 = %016llx\n", s->dma1ErrorLog1);
1869
1870 for (i = 0; i < OPAL_PHB3_NUM_PEST_REGS; i++) {
1871 if (!s->pestA[i] && !s->pestB[i])
1872 continue;
1873 PHBERR(p, " PEST[%03x] = %016llx %016llx\n",
1874 i, s->pestA[i], s->pestB[i]);
1875 }
1876
1877 if (s != regs)
1878 free(s);
1879 }
1880
phb3_msi_get_xive(struct irq_source * is,uint32_t isn,uint16_t * server,uint8_t * prio)1881 static int64_t phb3_msi_get_xive(struct irq_source *is, uint32_t isn,
1882 uint16_t *server, uint8_t *prio)
1883 {
1884 struct phb3 *p = is->data;
1885 uint32_t chip, index, irq;
1886 uint64_t ive;
1887
1888 chip = p8_irq_to_chip(isn);
1889 index = p8_irq_to_phb(isn);
1890 irq = PHB3_IRQ_NUM(isn);
1891
1892 if (chip != p->chip_id ||
1893 index != p->index ||
1894 irq > PHB3_MSI_IRQ_MAX)
1895 return OPAL_PARAMETER;
1896
1897 /*
1898 * Each IVE has 16 bytes in cache. Note that the kernel
1899 * should strip the link bits from server field.
1900 */
1901 ive = p->ive_cache[irq];
1902 *server = GETFIELD(IODA2_IVT_SERVER, ive);
1903 *prio = GETFIELD(IODA2_IVT_PRIORITY, ive);
1904
1905 return OPAL_SUCCESS;
1906 }
1907
phb3_msi_set_xive(struct irq_source * is,uint32_t isn,uint16_t server,uint8_t prio)1908 static int64_t phb3_msi_set_xive(struct irq_source *is, uint32_t isn,
1909 uint16_t server, uint8_t prio)
1910 {
1911 struct phb3 *p = is->data;
1912 uint32_t chip, index;
1913 uint64_t *cache, ive_num, data64, m_server, m_prio, ivc;
1914 uint32_t *ive;
1915
1916 chip = p8_irq_to_chip(isn);
1917 index = p8_irq_to_phb(isn);
1918 ive_num = PHB3_IRQ_NUM(isn);
1919
1920 if (p->broken || !p->tbl_rtt)
1921 return OPAL_HARDWARE;
1922 if (chip != p->chip_id ||
1923 index != p->index ||
1924 ive_num > PHB3_MSI_IRQ_MAX)
1925 return OPAL_PARAMETER;
1926
1927 phb_lock(&p->phb);
1928
1929 /*
1930 * We need strip the link from server. As Milton told
1931 * me, the server is assigned as follows and the left
1932 * bits unused: node/chip/core/thread/link = 2/3/4/3/2
1933 *
1934 * Note: the server has added the link bits to server.
1935 */
1936 m_server = server;
1937 m_prio = prio;
1938
1939 cache = &p->ive_cache[ive_num];
1940 *cache = SETFIELD(IODA2_IVT_SERVER, *cache, m_server);
1941 *cache = SETFIELD(IODA2_IVT_PRIORITY, *cache, m_prio);
1942
1943 /*
1944 * Update IVT and IVC. We need use IVC update register
1945 * to do that. Each IVE in the table has 128 bytes
1946 */
1947 ive = (uint32_t *)(p->tbl_ivt + ive_num * IVT_TABLE_STRIDE * 8);
1948 data64 = PHB_IVC_UPDATE_ENABLE_SERVER | PHB_IVC_UPDATE_ENABLE_PRI;
1949 data64 = SETFIELD(PHB_IVC_UPDATE_SID, data64, ive_num);
1950 data64 = SETFIELD(PHB_IVC_UPDATE_SERVER, data64, m_server);
1951 data64 = SETFIELD(PHB_IVC_UPDATE_PRI, data64, m_prio);
1952
1953 /*
1954 * We don't use SETFIELD because we are doing a 32-bit access
1955 * in order to avoid touching the P and Q bits
1956 */
1957 *ive = (m_server << 8) | m_prio;
1958 out_be64(p->regs + PHB_IVC_UPDATE, data64);
1959
1960 if (prio != 0xff) {
1961 /*
1962 * Handle Q bit if we're going to enable the
1963 * interrupt. The OS should make sure the interrupt
1964 * handler has been installed already.
1965 */
1966 if (phb3_pci_msi_check_q(p, ive_num))
1967 phb3_pci_msi_flush_ive(p, ive_num);
1968 } else {
1969 /* Read from random PHB reg to force flush */
1970 in_be64(p->regs + PHB_IVC_UPDATE);
1971
1972 /* Order with subsequent read of Q */
1973 sync();
1974
1975 /* Clear P, Q and Gen, preserve PE# */
1976 ive[1] &= 0x0000ffff;
1977
1978 /*
1979 * Update the IVC with a match against the old gen
1980 * count. No need to worry about racing with P being
1981 * set in the cache since IRQ is masked at this point.
1982 */
1983 ivc = SETFIELD(PHB_IVC_UPDATE_SID, 0ul, ive_num) |
1984 PHB_IVC_UPDATE_ENABLE_P |
1985 PHB_IVC_UPDATE_ENABLE_Q |
1986 PHB_IVC_UPDATE_ENABLE_GEN;
1987 out_be64(p->regs + PHB_IVC_UPDATE, ivc);
1988 }
1989
1990 phb_unlock(&p->phb);
1991
1992 return OPAL_SUCCESS;
1993 }
1994
phb3_lsi_get_xive(struct irq_source * is,uint32_t isn,uint16_t * server,uint8_t * prio)1995 static int64_t phb3_lsi_get_xive(struct irq_source *is, uint32_t isn,
1996 uint16_t *server, uint8_t *prio)
1997 {
1998 struct phb3 *p = is->data;
1999 uint32_t chip, index, irq;
2000 uint64_t lxive;
2001
2002 chip = p8_irq_to_chip(isn);
2003 index = p8_irq_to_phb(isn);
2004 irq = PHB3_IRQ_NUM(isn);
2005
2006 if (chip != p->chip_id ||
2007 index != p->index ||
2008 irq < PHB3_LSI_IRQ_MIN ||
2009 irq > PHB3_LSI_IRQ_MAX)
2010 return OPAL_PARAMETER;
2011
2012 lxive = p->lxive_cache[irq - PHB3_LSI_IRQ_MIN];
2013 *server = GETFIELD(IODA2_LXIVT_SERVER, lxive);
2014 *prio = GETFIELD(IODA2_LXIVT_PRIORITY, lxive);
2015
2016 return OPAL_SUCCESS;
2017 }
2018
phb3_lsi_set_xive(struct irq_source * is,uint32_t isn,uint16_t server,uint8_t prio)2019 static int64_t phb3_lsi_set_xive(struct irq_source *is, uint32_t isn,
2020 uint16_t server, uint8_t prio)
2021 {
2022 struct phb3 *p = is->data;
2023 uint32_t chip, index, irq, entry;
2024 uint64_t lxive;
2025
2026 chip = p8_irq_to_chip(isn);
2027 index = p8_irq_to_phb(isn);
2028 irq = PHB3_IRQ_NUM(isn);
2029
2030 if (p->broken)
2031 return OPAL_HARDWARE;
2032
2033 if (chip != p->chip_id ||
2034 index != p->index ||
2035 irq < PHB3_LSI_IRQ_MIN ||
2036 irq > PHB3_LSI_IRQ_MAX)
2037 return OPAL_PARAMETER;
2038
2039 lxive = SETFIELD(IODA2_LXIVT_SERVER, 0ul, server);
2040 lxive = SETFIELD(IODA2_LXIVT_PRIORITY, lxive, prio);
2041
2042 phb_lock(&p->phb);
2043
2044 /*
2045 * We cache the arguments because we have to mangle
2046 * it in order to hijack 3 bits of priority to extend
2047 * the server number
2048 */
2049 entry = irq - PHB3_LSI_IRQ_MIN;
2050 p->lxive_cache[entry] = lxive;
2051
2052 /* We use HRT entry 0 always for now */
2053 phb3_ioda_sel(p, IODA2_TBL_LXIVT, entry, false);
2054 lxive = in_be64(p->regs + PHB_IODA_DATA0);
2055 lxive = SETFIELD(IODA2_LXIVT_SERVER, lxive, server);
2056 lxive = SETFIELD(IODA2_LXIVT_PRIORITY, lxive, prio);
2057 out_be64(p->regs + PHB_IODA_DATA0, lxive);
2058
2059 phb_unlock(&p->phb);
2060
2061 return OPAL_SUCCESS;
2062 }
2063
phb3_err_interrupt(struct irq_source * is,uint32_t isn)2064 static void phb3_err_interrupt(struct irq_source *is, uint32_t isn)
2065 {
2066 struct phb3 *p = is->data;
2067
2068 PHBDBG(p, "Got interrupt 0x%08x\n", isn);
2069
2070 /* Update pending event */
2071 opal_update_pending_evt(OPAL_EVENT_PCI_ERROR,
2072 OPAL_EVENT_PCI_ERROR);
2073
2074 /* If the PHB is broken, go away */
2075 if (p->broken)
2076 return;
2077
2078 /*
2079 * Mark the PHB has pending error so that the OS
2080 * can handle it at late point.
2081 */
2082 phb3_set_err_pending(p, true);
2083 }
2084
phb3_lsi_attributes(struct irq_source * is,uint32_t isn)2085 static uint64_t phb3_lsi_attributes(struct irq_source *is, uint32_t isn)
2086 {
2087 #ifndef DISABLE_ERR_INTS
2088 struct phb3 *p = is->data;
2089 uint32_t idx = isn - p->base_lsi;
2090
2091 if (idx == PHB3_LSI_PCIE_INF || idx == PHB3_LSI_PCIE_ER)
2092 return IRQ_ATTR_TARGET_OPAL | IRQ_ATTR_TARGET_RARE | IRQ_ATTR_TYPE_LSI;
2093 #endif
2094 return IRQ_ATTR_TARGET_LINUX;
2095 }
2096
2097 /* MSIs (OS owned) */
2098 static const struct irq_source_ops phb3_msi_irq_ops = {
2099 .get_xive = phb3_msi_get_xive,
2100 .set_xive = phb3_msi_set_xive,
2101 };
2102
2103 /* LSIs (OS owned) */
2104 static const struct irq_source_ops phb3_lsi_irq_ops = {
2105 .get_xive = phb3_lsi_get_xive,
2106 .set_xive = phb3_lsi_set_xive,
2107 .attributes = phb3_lsi_attributes,
2108 .interrupt = phb3_err_interrupt,
2109 };
2110
phb3_set_pe(struct phb * phb,uint64_t pe_number,uint64_t bdfn,uint8_t bcompare,uint8_t dcompare,uint8_t fcompare,uint8_t action)2111 static int64_t phb3_set_pe(struct phb *phb,
2112 uint64_t pe_number,
2113 uint64_t bdfn,
2114 uint8_t bcompare,
2115 uint8_t dcompare,
2116 uint8_t fcompare,
2117 uint8_t action)
2118 {
2119 struct phb3 *p = phb_to_phb3(phb);
2120 uint64_t mask, val, tmp, idx;
2121 int32_t all = 0;
2122 uint16_t *rte;
2123
2124 /* Sanity check */
2125 if (!p->tbl_rtt)
2126 return OPAL_HARDWARE;
2127 if (action != OPAL_MAP_PE && action != OPAL_UNMAP_PE)
2128 return OPAL_PARAMETER;
2129 if (pe_number >= PHB3_MAX_PE_NUM || bdfn > 0xffff ||
2130 bcompare > OpalPciBusAll ||
2131 dcompare > OPAL_COMPARE_RID_DEVICE_NUMBER ||
2132 fcompare > OPAL_COMPARE_RID_FUNCTION_NUMBER)
2133 return OPAL_PARAMETER;
2134
2135 /* Figure out the RID range */
2136 if (bcompare == OpalPciBusAny) {
2137 mask = 0x0;
2138 val = 0x0;
2139 all = 0x1;
2140 } else {
2141 tmp = ((0x1 << (bcompare + 1)) - 1) << (15 - bcompare);
2142 mask = tmp;
2143 val = bdfn & tmp;
2144 }
2145
2146 if (dcompare == OPAL_IGNORE_RID_DEVICE_NUMBER)
2147 all = (all << 1) | 0x1;
2148 else {
2149 mask |= 0xf8;
2150 val |= (bdfn & 0xf8);
2151 }
2152
2153 if (fcompare == OPAL_IGNORE_RID_FUNCTION_NUMBER)
2154 all = (all << 1) | 0x1;
2155 else {
2156 mask |= 0x7;
2157 val |= (bdfn & 0x7);
2158 }
2159
2160 /* Map or unmap the RTT range */
2161 if (all == 0x7) {
2162 if (action == OPAL_MAP_PE) {
2163 for (idx = 0; idx < RTT_TABLE_ENTRIES; idx++)
2164 p->rte_cache[idx] = pe_number;
2165 } else {
2166 for ( idx = 0; idx < ARRAY_SIZE(p->rte_cache); idx++)
2167 p->rte_cache[idx] = PHB3_RESERVED_PE_NUM;
2168 }
2169 memcpy((void *)p->tbl_rtt, p->rte_cache, RTT_TABLE_SIZE);
2170 } else {
2171 rte = (uint16_t *)p->tbl_rtt;
2172 for (idx = 0; idx < RTT_TABLE_ENTRIES; idx++, rte++) {
2173 if ((idx & mask) != val)
2174 continue;
2175 if (action == OPAL_MAP_PE)
2176 p->rte_cache[idx] = pe_number;
2177 else
2178 p->rte_cache[idx] = PHB3_RESERVED_PE_NUM;
2179 *rte = p->rte_cache[idx];
2180 }
2181 }
2182
2183 /* Invalidate the entire RTC */
2184 out_be64(p->regs + PHB_RTC_INVALIDATE, PHB_RTC_INVALIDATE_ALL);
2185
2186 return OPAL_SUCCESS;
2187 }
2188
phb3_set_peltv(struct phb * phb,uint32_t parent_pe,uint32_t child_pe,uint8_t state)2189 static int64_t phb3_set_peltv(struct phb *phb,
2190 uint32_t parent_pe,
2191 uint32_t child_pe,
2192 uint8_t state)
2193 {
2194 struct phb3 *p = phb_to_phb3(phb);
2195 uint8_t *peltv;
2196 uint32_t idx, mask;
2197
2198 /* Sanity check */
2199 if (!p->tbl_peltv)
2200 return OPAL_HARDWARE;
2201 if (parent_pe >= PHB3_MAX_PE_NUM || child_pe >= PHB3_MAX_PE_NUM)
2202 return OPAL_PARAMETER;
2203
2204 /* Find index for parent PE */
2205 idx = parent_pe * (PHB3_MAX_PE_NUM / 8);
2206 idx += (child_pe / 8);
2207 mask = 0x1 << (7 - (child_pe % 8));
2208
2209 peltv = (uint8_t *)p->tbl_peltv;
2210 peltv += idx;
2211 if (state) {
2212 *peltv |= mask;
2213 p->peltv_cache[idx] |= mask;
2214 } else {
2215 *peltv &= ~mask;
2216 p->peltv_cache[idx] &= ~mask;
2217 }
2218
2219 return OPAL_SUCCESS;
2220 }
2221
phb3_prepare_link_change(struct pci_slot * slot,bool is_up)2222 static void phb3_prepare_link_change(struct pci_slot *slot,
2223 bool is_up)
2224 {
2225 struct phb3 *p = phb_to_phb3(slot->phb);
2226 struct pci_device *pd = slot->pd;
2227 uint32_t reg32;
2228
2229 p->has_link = is_up;
2230 if (!is_up) {
2231 if (!pd || !pd->slot || !pd->slot->surprise_pluggable) {
2232 /* Mask PCIE port interrupts */
2233 out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN,
2234 0xad42800000000000UL);
2235
2236 pci_cfg_read32(&p->phb, 0,
2237 p->aercap + PCIECAP_AER_UE_MASK, ®32);
2238 reg32 |= PCIECAP_AER_UE_MASK_SURPRISE_DOWN;
2239 pci_cfg_write32(&p->phb, 0,
2240 p->aercap + PCIECAP_AER_UE_MASK, reg32);
2241 }
2242
2243 /* Mask AER receiver error */
2244 phb3_pcicfg_read32(&p->phb, 0,
2245 p->aercap + PCIECAP_AER_CE_MASK, ®32);
2246 reg32 |= PCIECAP_AER_CE_RECVR_ERR;
2247 phb3_pcicfg_write32(&p->phb, 0,
2248 p->aercap + PCIECAP_AER_CE_MASK, reg32);
2249
2250 /* Block PCI-CFG access */
2251 p->flags |= PHB3_CFG_BLOCKED;
2252 } else {
2253 /* Clear AER receiver error status */
2254 phb3_pcicfg_write32(&p->phb, 0,
2255 p->aercap + PCIECAP_AER_CE_STATUS,
2256 PCIECAP_AER_CE_RECVR_ERR);
2257
2258 /* Unmask receiver error status in AER */
2259 phb3_pcicfg_read32(&p->phb, 0,
2260 p->aercap + PCIECAP_AER_CE_MASK, ®32);
2261 reg32 &= ~PCIECAP_AER_CE_RECVR_ERR;
2262 phb3_pcicfg_write32(&p->phb, 0,
2263 p->aercap + PCIECAP_AER_CE_MASK, reg32);
2264
2265 /* Clear spurrious errors and enable PCIE port interrupts */
2266 out_be64(p->regs + UTL_PCIE_PORT_STATUS,
2267 0xffdfffffffffffffUL);
2268
2269 if (!pd || !pd->slot || !pd->slot->surprise_pluggable) {
2270 out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN,
2271 0xad52800000000000UL);
2272
2273 pci_cfg_read32(&p->phb, 0,
2274 p->aercap + PCIECAP_AER_UE_MASK, ®32);
2275 reg32 &= ~PCIECAP_AER_UE_MASK_SURPRISE_DOWN;
2276 pci_cfg_write32(&p->phb, 0,
2277 p->aercap + PCIECAP_AER_UE_MASK, reg32);
2278 }
2279
2280 /* Don't block PCI-CFG */
2281 p->flags &= ~PHB3_CFG_BLOCKED;
2282
2283 /*
2284 * We might lose the bus numbers during the reset operation
2285 * and we need to restore them. Otherwise, some adapters (e.g.
2286 * IPR) can't be probed properly by the kernel. We don't need
2287 * to restore bus numbers for every kind of reset, however,
2288 * it's not harmful to always restore the bus numbers, which
2289 * simplifies the logic.
2290 */
2291 pci_restore_bridge_buses(slot->phb, slot->pd);
2292 if (slot->phb->ops->device_init)
2293 pci_walk_dev(slot->phb, slot->pd,
2294 slot->phb->ops->device_init, NULL);
2295 }
2296 }
2297
phb3_get_presence_state(struct pci_slot * slot,uint8_t * val)2298 static int64_t phb3_get_presence_state(struct pci_slot *slot, uint8_t *val)
2299 {
2300 struct phb3 *p = phb_to_phb3(slot->phb);
2301 uint64_t hp_override;
2302
2303 if (p->broken)
2304 return OPAL_HARDWARE;
2305
2306 /*
2307 * On P8, the slot status isn't wired up properly, we have
2308 * to use the hotplug override A/B bits.
2309 */
2310 hp_override = in_be64(p->regs + PHB_HOTPLUG_OVERRIDE);
2311 if ((hp_override & PHB_HPOVR_PRESENCE_A) &&
2312 (hp_override & PHB_HPOVR_PRESENCE_B))
2313 *val = OPAL_PCI_SLOT_EMPTY;
2314 else
2315 *val = OPAL_PCI_SLOT_PRESENT;
2316
2317 return OPAL_SUCCESS;
2318 }
2319
phb3_get_link_state(struct pci_slot * slot,uint8_t * val)2320 static int64_t phb3_get_link_state(struct pci_slot *slot, uint8_t *val)
2321 {
2322 struct phb3 *p = phb_to_phb3(slot->phb);
2323 uint64_t reg;
2324 uint16_t state;
2325 int64_t rc;
2326
2327 /* Link is up, let's find the actual speed */
2328 reg = in_be64(p->regs + PHB_PCIE_DLP_TRAIN_CTL);
2329 if (!(reg & PHB_PCIE_DLP_TC_DL_LINKACT)) {
2330 *val = 0;
2331 return OPAL_SUCCESS;
2332 }
2333
2334 rc = phb3_pcicfg_read16(&p->phb, 0,
2335 p->ecap + PCICAP_EXP_LSTAT, &state);
2336 if (rc != OPAL_SUCCESS) {
2337 PHBERR(p, "%s: Error %lld getting link state\n", __func__, rc);
2338 return OPAL_HARDWARE;
2339 }
2340
2341 if (state & PCICAP_EXP_LSTAT_DLLL_ACT)
2342 *val = ((state & PCICAP_EXP_LSTAT_WIDTH) >> 4);
2343 else
2344 *val = 0;
2345
2346 return OPAL_SUCCESS;
2347 }
2348
phb3_retry_state(struct pci_slot * slot)2349 static int64_t phb3_retry_state(struct pci_slot *slot)
2350 {
2351 struct phb3 *p = phb_to_phb3(slot->phb);
2352
2353 if (slot->retry_state == PCI_SLOT_STATE_NORMAL)
2354 return OPAL_WRONG_STATE;
2355
2356 PHBDBG(p, "Retry state %08x\n", slot->retry_state);
2357 slot->delay_tgt_tb = 0;
2358 pci_slot_set_state(slot, slot->retry_state);
2359 slot->retry_state = PCI_SLOT_STATE_NORMAL;
2360 return slot->ops.run_sm(slot);
2361 }
2362
phb3_poll_link(struct pci_slot * slot)2363 static int64_t phb3_poll_link(struct pci_slot *slot)
2364 {
2365 struct phb3 *p = phb_to_phb3(slot->phb);
2366 uint64_t reg;
2367 int64_t rc;
2368
2369 switch (slot->state) {
2370 case PHB3_SLOT_NORMAL:
2371 case PHB3_SLOT_LINK_START:
2372 PHBDBG(p, "LINK: Start polling\n");
2373 slot->retries = PHB3_LINK_ELECTRICAL_RETRIES;
2374 pci_slot_set_state(slot, PHB3_SLOT_LINK_WAIT_ELECTRICAL);
2375 return pci_slot_set_sm_timeout(slot, msecs_to_tb(100));
2376 case PHB3_SLOT_LINK_WAIT_ELECTRICAL:
2377 /*
2378 * Wait for the link electrical connection to be
2379 * established (shorter timeout). This allows us to
2380 * workaround spurrious presence detect on some machines
2381 * without waiting 10s each time
2382 *
2383 * Note: We *also* check for the full link up bit here
2384 * because simics doesn't seem to implement the electrical
2385 * link bit at all
2386 */
2387 reg = in_be64(p->regs + PHB_PCIE_DLP_TRAIN_CTL);
2388 if (reg & (PHB_PCIE_DLP_INBAND_PRESENCE |
2389 PHB_PCIE_DLP_TC_DL_LINKACT)) {
2390 PHBDBG(p, "LINK: Electrical link detected\n");
2391 pci_slot_set_state(slot, PHB3_SLOT_LINK_WAIT);
2392 slot->retries = PHB3_LINK_WAIT_RETRIES;
2393 return pci_slot_set_sm_timeout(slot, msecs_to_tb(100));
2394 }
2395
2396 if (slot->retries-- == 0) {
2397 PHBDBG(p, "LINK: Timeout waiting for electrical link\n");
2398 PHBDBG(p, "LINK: DLP train control: 0x%016llx\n", reg);
2399 rc = phb3_retry_state(slot);
2400 if (rc >= OPAL_SUCCESS)
2401 return rc;
2402
2403 pci_slot_set_state(slot, PHB3_SLOT_NORMAL);
2404 return OPAL_SUCCESS;
2405 }
2406 return pci_slot_set_sm_timeout(slot, msecs_to_tb(100));
2407 case PHB3_SLOT_LINK_WAIT:
2408 reg = in_be64(p->regs + PHB_PCIE_DLP_TRAIN_CTL);
2409 if (reg & PHB_PCIE_DLP_TC_DL_LINKACT) {
2410 PHBDBG(p, "LINK: Link is up\n");
2411 if (slot->ops.prepare_link_change)
2412 slot->ops.prepare_link_change(slot, true);
2413 pci_slot_set_state(slot, PHB3_SLOT_NORMAL);
2414 return OPAL_SUCCESS;
2415 }
2416
2417 if (slot->retries-- == 0) {
2418 PHBDBG(p, "LINK: Timeout waiting for link up\n");
2419 PHBDBG(p, "LINK: DLP train control: 0x%016llx\n", reg);
2420 rc = phb3_retry_state(slot);
2421 if (rc >= OPAL_SUCCESS)
2422 return rc;
2423
2424 pci_slot_set_state(slot, PHB3_SLOT_NORMAL);
2425 return OPAL_SUCCESS;
2426 }
2427 return pci_slot_set_sm_timeout(slot, msecs_to_tb(100));
2428 default:
2429 PHBERR(p, "LINK: Unexpected slot state %08x\n",
2430 slot->state);
2431 }
2432
2433 pci_slot_set_state(slot, PHB3_SLOT_NORMAL);
2434 return OPAL_HARDWARE;
2435 }
2436
phb3_hreset(struct pci_slot * slot)2437 static int64_t phb3_hreset(struct pci_slot *slot)
2438 {
2439 struct phb3 *p = phb_to_phb3(slot->phb);
2440 uint16_t brctl;
2441 uint8_t presence = 1;
2442
2443 switch (slot->state) {
2444 case PHB3_SLOT_NORMAL:
2445 PHBDBG(p, "HRESET: Starts\n");
2446 if (slot->ops.get_presence_state)
2447 slot->ops.get_presence_state(slot, &presence);
2448 if (!presence) {
2449 PHBDBG(p, "HRESET: No device\n");
2450 return OPAL_SUCCESS;
2451 }
2452
2453 PHBDBG(p, "HRESET: Prepare for link down\n");
2454 if (slot->ops.prepare_link_change)
2455 slot->ops.prepare_link_change(slot, false);
2456 /* fall through */
2457 case PHB3_SLOT_HRESET_START:
2458 PHBDBG(p, "HRESET: Assert\n");
2459
2460 phb3_pcicfg_read16(&p->phb, 0, PCI_CFG_BRCTL, &brctl);
2461 brctl |= PCI_CFG_BRCTL_SECONDARY_RESET;
2462 phb3_pcicfg_write16(&p->phb, 0, PCI_CFG_BRCTL, brctl);
2463 pci_slot_set_state(slot, PHB3_SLOT_HRESET_DELAY);
2464
2465 return pci_slot_set_sm_timeout(slot, secs_to_tb(1));
2466 case PHB3_SLOT_HRESET_DELAY:
2467 PHBDBG(p, "HRESET: Deassert\n");
2468
2469 phb3_pcicfg_read16(&p->phb, 0, PCI_CFG_BRCTL, &brctl);
2470 brctl &= ~PCI_CFG_BRCTL_SECONDARY_RESET;
2471 phb3_pcicfg_write16(&p->phb, 0, PCI_CFG_BRCTL, brctl);
2472
2473 /*
2474 * Due to some oddball adapters bouncing the link
2475 * training a couple of times, we wait for a full second
2476 * before we start checking the link status, otherwise
2477 * we can get a spurrious link down interrupt which
2478 * causes us to EEH immediately.
2479 */
2480 pci_slot_set_state(slot, PHB3_SLOT_HRESET_DELAY2);
2481 return pci_slot_set_sm_timeout(slot, secs_to_tb(1));
2482 case PHB3_SLOT_HRESET_DELAY2:
2483 pci_slot_set_state(slot, PHB3_SLOT_LINK_START);
2484 return slot->ops.poll_link(slot);
2485 default:
2486 PHBERR(p, "Unexpected slot state %08x\n", slot->state);
2487 }
2488
2489 pci_slot_set_state(slot, PHB3_SLOT_NORMAL);
2490 return OPAL_HARDWARE;
2491 }
2492
phb3_freset(struct pci_slot * slot)2493 static int64_t phb3_freset(struct pci_slot *slot)
2494 {
2495 struct phb3 *p = phb_to_phb3(slot->phb);
2496 uint8_t presence = 1;
2497 uint64_t reg;
2498
2499 switch(slot->state) {
2500 case PHB3_SLOT_NORMAL:
2501 PHBDBG(p, "FRESET: Starts\n");
2502
2503 /* Nothing to do without adapter connected */
2504 if (slot->ops.get_presence_state)
2505 slot->ops.get_presence_state(slot, &presence);
2506 if (!presence) {
2507 PHBDBG(p, "FRESET: No device\n");
2508 return OPAL_SUCCESS;
2509 }
2510
2511 PHBDBG(p, "FRESET: Prepare for link down\n");
2512 slot->retry_state = PHB3_SLOT_FRESET_START;
2513 if (slot->ops.prepare_link_change)
2514 slot->ops.prepare_link_change(slot, false);
2515 /* fall through */
2516 case PHB3_SLOT_FRESET_START:
2517 if (!p->skip_perst) {
2518 PHBDBG(p, "FRESET: Assert\n");
2519 reg = in_be64(p->regs + PHB_RESET);
2520 reg &= ~0x2000000000000000ul;
2521 out_be64(p->regs + PHB_RESET, reg);
2522 pci_slot_set_state(slot,
2523 PHB3_SLOT_FRESET_ASSERT_DELAY);
2524 return pci_slot_set_sm_timeout(slot, secs_to_tb(1));
2525 }
2526
2527 /* To skip the assert during boot time */
2528 PHBDBG(p, "FRESET: Assert skipped\n");
2529 pci_slot_set_state(slot, PHB3_SLOT_FRESET_ASSERT_DELAY);
2530 p->skip_perst = false;
2531 /* fall through */
2532 case PHB3_SLOT_FRESET_ASSERT_DELAY:
2533 PHBDBG(p, "FRESET: Deassert\n");
2534 reg = in_be64(p->regs + PHB_RESET);
2535 reg |= 0x2000000000000000ul;
2536 out_be64(p->regs + PHB_RESET, reg);
2537 pci_slot_set_state(slot,
2538 PHB3_SLOT_FRESET_DEASSERT_DELAY);
2539
2540 /* CAPP FPGA requires 1s to flash before polling link */
2541 return pci_slot_set_sm_timeout(slot, secs_to_tb(1));
2542 case PHB3_SLOT_FRESET_DEASSERT_DELAY:
2543 pci_slot_set_state(slot, PHB3_SLOT_LINK_START);
2544 return slot->ops.poll_link(slot);
2545 default:
2546 PHBERR(p, "Unexpected slot state %08x\n", slot->state);
2547 }
2548
2549 pci_slot_set_state(slot, PHB3_SLOT_NORMAL);
2550 return OPAL_HARDWARE;
2551 }
2552
load_capp_ucode(struct phb3 * p)2553 static int64_t load_capp_ucode(struct phb3 *p)
2554 {
2555 int64_t rc;
2556
2557 if (p->index > PHB3_CAPP_MAX_PHB_INDEX(p))
2558 return OPAL_HARDWARE;
2559
2560 /* 0x434150504c494448 = 'CAPPLIDH' in ASCII */
2561 rc = capp_load_ucode(p->chip_id, p->phb.opal_id, p->index,
2562 0x434150504c494448UL, PHB3_CAPP_REG_OFFSET(p),
2563 CAPP_APC_MASTER_ARRAY_ADDR_REG,
2564 CAPP_APC_MASTER_ARRAY_WRITE_REG,
2565 CAPP_SNP_ARRAY_ADDR_REG,
2566 CAPP_SNP_ARRAY_WRITE_REG);
2567 return rc;
2568 }
2569
do_capp_recovery_scoms(struct phb3 * p)2570 static void do_capp_recovery_scoms(struct phb3 *p)
2571 {
2572 uint64_t reg;
2573 uint32_t offset;
2574
2575 PHBDBG(p, "Doing CAPP recovery scoms\n");
2576
2577 offset = PHB3_CAPP_REG_OFFSET(p);
2578 /* disable snoops */
2579 xscom_write(p->chip_id, SNOOP_CAPI_CONFIG + offset, 0);
2580 load_capp_ucode(p);
2581 /* clear err rpt reg*/
2582 xscom_write(p->chip_id, CAPP_ERR_RPT_CLR + offset, 0);
2583 /* clear capp fir */
2584 xscom_write(p->chip_id, CAPP_FIR + offset, 0);
2585
2586 xscom_read(p->chip_id, CAPP_ERR_STATUS_CTRL + offset, ®);
2587 reg &= ~(PPC_BIT(0) | PPC_BIT(1));
2588 xscom_write(p->chip_id, CAPP_ERR_STATUS_CTRL + offset, reg);
2589 }
2590
2591 /*
2592 * Disable CAPI mode on a PHB.
2593 *
2594 * Must be done while PHB is fenced and in recovery. Leaves CAPP in recovery -
2595 * we can't come out of recovery until the PHB has been reinitialised.
2596 *
2597 * We don't reset generic error registers here - we rely on phb3_init_hw() to
2598 * do that.
2599 *
2600 * Sets PHB3_CAPP_DISABLING flag when complete.
2601 */
disable_capi_mode(struct phb3 * p)2602 static void disable_capi_mode(struct phb3 *p)
2603 {
2604 struct proc_chip *chip = get_chip(p->chip_id);
2605 uint64_t reg;
2606 uint32_t offset = PHB3_CAPP_REG_OFFSET(p);
2607
2608 lock(&capi_lock);
2609
2610 xscom_read(p->chip_id, PE_CAPP_EN + PE_REG_OFFSET(p), ®);
2611 if (!(reg & PPC_BIT(0))) {
2612 /* Not in CAPI mode, no action required */
2613 goto out;
2614 }
2615
2616 PHBDBG(p, "CAPP: Disabling CAPI mode\n");
2617 if (!(chip->capp_phb3_attached_mask & (1 << p->index)))
2618 PHBERR(p, "CAPP: CAPP attached mask not set!\n");
2619
2620 xscom_read(p->chip_id, CAPP_ERR_STATUS_CTRL + offset, ®);
2621 if (!(reg & PPC_BIT(0))) {
2622 PHBERR(p, "CAPP: not in recovery, can't disable CAPI mode!\n");
2623 goto out;
2624 }
2625
2626 /* Snoop CAPI Configuration Register - disable snooping */
2627 xscom_write(p->chip_id, SNOOP_CAPI_CONFIG + offset, 0ull);
2628
2629 /* APC Master PB Control Register - disable examining cResps */
2630 xscom_read(p->chip_id, APC_MASTER_PB_CTRL + offset, ®);
2631 reg &= ~PPC_BIT(3);
2632 xscom_write(p->chip_id, APC_MASTER_PB_CTRL + offset, reg);
2633
2634 /* APC Master Config Register - de-select PHBs */
2635 xscom_read(p->chip_id, APC_MASTER_CAPI_CTRL + offset, ®);
2636 reg &= ~PPC_BITMASK(1, 3);
2637 xscom_write(p->chip_id, APC_MASTER_CAPI_CTRL + offset, reg);
2638
2639 /* PE Bus AIB Mode Bits */
2640 xscom_read(p->chip_id, p->pci_xscom + 0xf, ®);
2641 reg |= PPC_BITMASK(7, 8); /* Ch2 command credit */
2642 reg &= ~PPC_BITMASK(40, 42); /* Disable HOL blocking */
2643 xscom_write(p->chip_id, p->pci_xscom + 0xf, reg);
2644
2645 /* PCI Hardware Configuration 0 Register - all store queues free */
2646 xscom_read(p->chip_id, p->pe_xscom + 0x18, ®);
2647 reg &= ~PPC_BIT(14);
2648 reg |= PPC_BIT(15);
2649 xscom_write(p->chip_id, p->pe_xscom + 0x18, reg);
2650
2651 /*
2652 * PCI Hardware Configuration 1 Register - enable read response
2653 * arrival/address request ordering
2654 */
2655 xscom_read(p->chip_id, p->pe_xscom + 0x19, ®);
2656 reg |= PPC_BITMASK(17,18);
2657 xscom_write(p->chip_id, p->pe_xscom + 0x19, reg);
2658
2659 /*
2660 * AIB TX Command Credit Register - set AIB credit values back to
2661 * normal
2662 */
2663 xscom_read(p->chip_id, p->pci_xscom + 0xd, ®);
2664 reg |= PPC_BIT(42);
2665 reg &= ~PPC_BITMASK(43, 47);
2666 xscom_write(p->chip_id, p->pci_xscom + 0xd, reg);
2667
2668 /* AIB TX Credit Init Timer - reset timer */
2669 xscom_write(p->chip_id, p->pci_xscom + 0xc, 0xff00000000000000UL);
2670
2671 /*
2672 * PBCQ Mode Control Register - set dcache handling to normal, not CAPP
2673 * mode
2674 */
2675 xscom_read(p->chip_id, p->pe_xscom + 0xb, ®);
2676 reg &= ~PPC_BIT(25);
2677 xscom_write(p->chip_id, p->pe_xscom + 0xb, reg);
2678
2679 /* Registers touched by phb3_init_capp_regs() */
2680
2681 /* CAPP Transport Control Register */
2682 xscom_write(p->chip_id, TRANSPORT_CONTROL + offset, 0x0001000000000000UL);
2683
2684 /* Canned pResp Map Register 0/1/2 */
2685 xscom_write(p->chip_id, CANNED_PRESP_MAP0 + offset, 0);
2686 xscom_write(p->chip_id, CANNED_PRESP_MAP1 + offset, 0);
2687 xscom_write(p->chip_id, CANNED_PRESP_MAP2 + offset, 0);
2688
2689 /* Flush SUE State Map Register */
2690 xscom_write(p->chip_id, FLUSH_SUE_STATE_MAP + offset, 0);
2691
2692 /* CAPP Epoch and Recovery Timers Control Register */
2693 xscom_write(p->chip_id, CAPP_EPOCH_TIMER_CTRL + offset, 0);
2694
2695 /* PE Secure CAPP Enable Register - we're all done! Disable CAPP mode! */
2696 xscom_write(p->chip_id, PE_CAPP_EN + PE_REG_OFFSET(p), 0ull);
2697
2698 /* Trigger CAPP recovery scoms after reinit */
2699 p->flags |= PHB3_CAPP_DISABLING;
2700
2701 chip->capp_phb3_attached_mask &= ~(1 << p->index);
2702
2703 out:
2704 unlock(&capi_lock);
2705 }
2706
phb3_creset(struct pci_slot * slot)2707 static int64_t phb3_creset(struct pci_slot *slot)
2708 {
2709 struct phb3 *p = phb_to_phb3(slot->phb);
2710 uint64_t cqsts, val;
2711
2712 switch (slot->state) {
2713 case PHB3_SLOT_NORMAL:
2714 case PHB3_SLOT_CRESET_START:
2715 PHBDBG(p, "CRESET: Starts\n");
2716
2717 /* do steps 3-5 of capp recovery procedure */
2718 if (p->flags & PHB3_CAPP_RECOVERY)
2719 do_capp_recovery_scoms(p);
2720
2721 /*
2722 * The users might be doing error injection through PBCQ
2723 * Error Inject Control Register. Without clearing that,
2724 * we will get recrusive error during recovery and it will
2725 * fail eventually.
2726 */
2727 xscom_write(p->chip_id, p->pe_xscom + 0xa, 0x0ul);
2728
2729 /*
2730 * We might have escalated frozen state on non-existing PE
2731 * to fenced PHB. For the case, the PHB isn't fenced in the
2732 * hardware level and it's not safe to do ETU reset. So we
2733 * have to force fenced PHB prior to ETU reset.
2734 */
2735 if (!phb3_fenced(p))
2736 xscom_write(p->chip_id, p->pe_xscom + 0x2, 0x000000f000000000ull);
2737
2738 /* Now that we're guaranteed to be fenced, disable CAPI mode */
2739 if (!(p->flags & PHB3_CAPP_RECOVERY))
2740 disable_capi_mode(p);
2741
2742 /* Clear errors in NFIR and raise ETU reset */
2743 xscom_read(p->chip_id, p->pe_xscom + 0x0, &p->nfir_cache);
2744
2745 xscom_read(p->chip_id, p->spci_xscom + 1, &val);/* HW275117 */
2746 xscom_write(p->chip_id, p->pci_xscom + 0xa,
2747 0x8000000000000000UL);
2748 pci_slot_set_state(slot, PHB3_SLOT_CRESET_WAIT_CQ);
2749 slot->retries = 500;
2750 return pci_slot_set_sm_timeout(slot, msecs_to_tb(10));
2751 case PHB3_SLOT_CRESET_WAIT_CQ:
2752 xscom_read(p->chip_id, p->pe_xscom + 0x1c, &val);
2753 xscom_read(p->chip_id, p->pe_xscom + 0x1d, &val);
2754 xscom_read(p->chip_id, p->pe_xscom + 0x1e, &val);
2755 xscom_read(p->chip_id, p->pe_xscom + 0xf, &cqsts);
2756 if (!(cqsts & 0xC000000000000000UL)) {
2757 PHBDBG(p, "CRESET: No pending transactions\n");
2758 xscom_write(p->chip_id, p->pe_xscom + 0x1, ~p->nfir_cache);
2759
2760 pci_slot_set_state(slot, PHB3_SLOT_CRESET_REINIT);
2761 return pci_slot_set_sm_timeout(slot, msecs_to_tb(100));
2762 }
2763
2764 if (slot->retries-- == 0) {
2765 PHBERR(p, "Timeout waiting for pending transaction\n");
2766 goto error;
2767 }
2768 return pci_slot_set_sm_timeout(slot, msecs_to_tb(10));
2769 case PHB3_SLOT_CRESET_REINIT:
2770 PHBDBG(p, "CRESET: Reinitialization\n");
2771
2772 /*
2773 * Clear AIB fenced state. Otherwise, we can't access the
2774 * PCI config space of root complex when reinitializing
2775 * the PHB.
2776 */
2777 p->flags &= ~PHB3_AIB_FENCED;
2778 p->flags &= ~PHB3_CAPP_RECOVERY;
2779 phb3_init_hw(p, false);
2780
2781 if (p->flags & PHB3_CAPP_DISABLING) {
2782 do_capp_recovery_scoms(p);
2783 p->flags &= ~PHB3_CAPP_DISABLING;
2784 }
2785
2786 pci_slot_set_state(slot, PHB3_SLOT_CRESET_FRESET);
2787 return pci_slot_set_sm_timeout(slot, msecs_to_tb(100));
2788 case PHB3_SLOT_CRESET_FRESET:
2789 pci_slot_set_state(slot, PHB3_SLOT_NORMAL);
2790 return slot->ops.freset(slot);
2791 default:
2792 PHBERR(p, "CRESET: Unexpected slot state %08x\n",
2793 slot->state);
2794 }
2795
2796 error:
2797 return OPAL_HARDWARE;
2798 }
2799
2800 /*
2801 * Initialize root complex slot, which is mainly used to
2802 * do fundamental reset before PCI enumeration in PCI core.
2803 * When probing root complex and building its real slot,
2804 * the operations will be copied over.
2805 */
phb3_slot_create(struct phb * phb)2806 static struct pci_slot *phb3_slot_create(struct phb *phb)
2807 {
2808 struct pci_slot *slot;
2809
2810 slot = pci_slot_alloc(phb, NULL);
2811 if (!slot)
2812 return slot;
2813
2814 /* Elementary functions */
2815 slot->ops.get_presence_state = phb3_get_presence_state;
2816 slot->ops.get_link_state = phb3_get_link_state;
2817 slot->ops.get_power_state = NULL;
2818 slot->ops.get_attention_state = NULL;
2819 slot->ops.get_latch_state = NULL;
2820 slot->ops.set_power_state = NULL;
2821 slot->ops.set_attention_state = NULL;
2822
2823 /*
2824 * For PHB slots, we have to split the fundamental reset
2825 * into 2 steps. We might not have the first step which
2826 * is to power off/on the slot, or it's controlled by
2827 * individual platforms.
2828 */
2829 slot->ops.prepare_link_change = phb3_prepare_link_change;
2830 slot->ops.poll_link = phb3_poll_link;
2831 slot->ops.hreset = phb3_hreset;
2832 slot->ops.freset = phb3_freset;
2833 slot->ops.creset = phb3_creset;
2834
2835 return slot;
2836 }
2837
phb3_eeh_freeze_status(struct phb * phb,uint64_t pe_number,uint8_t * freeze_state,uint16_t * pci_error_type,uint16_t * severity)2838 static int64_t phb3_eeh_freeze_status(struct phb *phb, uint64_t pe_number,
2839 uint8_t *freeze_state,
2840 uint16_t *pci_error_type,
2841 uint16_t *severity)
2842 {
2843 struct phb3 *p = phb_to_phb3(phb);
2844 uint64_t peev_bit = PPC_BIT(pe_number & 0x3f);
2845 uint64_t peev, pesta, pestb;
2846
2847 /* Defaults: not frozen */
2848 *freeze_state = OPAL_EEH_STOPPED_NOT_FROZEN;
2849 *pci_error_type = OPAL_EEH_NO_ERROR;
2850
2851 /* Check dead */
2852 if (p->broken) {
2853 *freeze_state = OPAL_EEH_STOPPED_MMIO_DMA_FREEZE;
2854 *pci_error_type = OPAL_EEH_PHB_ERROR;
2855 if (severity)
2856 *severity = OPAL_EEH_SEV_PHB_DEAD;
2857 return OPAL_HARDWARE;
2858 }
2859
2860 /* Check fence and CAPP recovery */
2861 if (phb3_fenced(p) || (p->flags & PHB3_CAPP_RECOVERY)) {
2862 *freeze_state = OPAL_EEH_STOPPED_MMIO_DMA_FREEZE;
2863 *pci_error_type = OPAL_EEH_PHB_ERROR;
2864 if (severity)
2865 *severity = OPAL_EEH_SEV_PHB_FENCED;
2866 return OPAL_SUCCESS;
2867 }
2868
2869 /* Check the PEEV */
2870 phb3_ioda_sel(p, IODA2_TBL_PEEV, pe_number / 64, false);
2871 peev = in_be64(p->regs + PHB_IODA_DATA0);
2872 if (!(peev & peev_bit))
2873 return OPAL_SUCCESS;
2874
2875 /* Indicate that we have an ER pending */
2876 phb3_set_err_pending(p, true);
2877 if (severity)
2878 *severity = OPAL_EEH_SEV_PE_ER;
2879
2880 /* Read the PESTA & PESTB */
2881 phb3_ioda_sel(p, IODA2_TBL_PESTA, pe_number, false);
2882 pesta = in_be64(p->regs + PHB_IODA_DATA0);
2883 phb3_ioda_sel(p, IODA2_TBL_PESTB, pe_number, false);
2884 pestb = in_be64(p->regs + PHB_IODA_DATA0);
2885
2886 /* Convert them */
2887 if (pesta & IODA2_PESTA_MMIO_FROZEN)
2888 *freeze_state |= OPAL_EEH_STOPPED_MMIO_FREEZE;
2889 if (pestb & IODA2_PESTB_DMA_STOPPED)
2890 *freeze_state |= OPAL_EEH_STOPPED_DMA_FREEZE;
2891
2892 return OPAL_SUCCESS;
2893 }
2894
phb3_eeh_freeze_clear(struct phb * phb,uint64_t pe_number,uint64_t eeh_action_token)2895 static int64_t phb3_eeh_freeze_clear(struct phb *phb, uint64_t pe_number,
2896 uint64_t eeh_action_token)
2897 {
2898 struct phb3 *p = phb_to_phb3(phb);
2899 uint64_t err, peev[4];
2900 int32_t i;
2901 bool frozen_pe = false;
2902
2903 if (p->broken)
2904 return OPAL_HARDWARE;
2905
2906 /* Summary. If nothing, move to clearing the PESTs which can
2907 * contain a freeze state from a previous error or simply set
2908 * explicitely by the user
2909 */
2910 err = in_be64(p->regs + PHB_ETU_ERR_SUMMARY);
2911 if (err == 0xffffffffffffffffUL) {
2912 if (phb3_fenced(p)) {
2913 PHBERR(p, "eeh_freeze_clear on fenced PHB\n");
2914 return OPAL_HARDWARE;
2915 }
2916 }
2917 if (err != 0)
2918 phb3_err_ER_clear(p);
2919
2920 /*
2921 * We have PEEV in system memory. It would give more performance
2922 * to access that directly.
2923 */
2924 if (eeh_action_token & OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO) {
2925 phb3_ioda_sel(p, IODA2_TBL_PESTA, pe_number, false);
2926 out_be64(p->regs + PHB_IODA_DATA0, 0);
2927 }
2928 if (eeh_action_token & OPAL_EEH_ACTION_CLEAR_FREEZE_DMA) {
2929 phb3_ioda_sel(p, IODA2_TBL_PESTB, pe_number, false);
2930 out_be64(p->regs + PHB_IODA_DATA0, 0);
2931 }
2932
2933
2934 /* Update ER pending indication */
2935 phb3_ioda_sel(p, IODA2_TBL_PEEV, 0, true);
2936 for (i = 0; i < ARRAY_SIZE(peev); i++) {
2937 peev[i] = in_be64(p->regs + PHB_IODA_DATA0);
2938 if (peev[i]) {
2939 frozen_pe = true;
2940 break;
2941 }
2942 }
2943 if (frozen_pe) {
2944 p->err.err_src = PHB3_ERR_SRC_PHB;
2945 p->err.err_class = PHB3_ERR_CLASS_ER;
2946 p->err.err_bit = -1;
2947 phb3_set_err_pending(p, true);
2948 } else
2949 phb3_set_err_pending(p, false);
2950
2951 return OPAL_SUCCESS;
2952 }
2953
phb3_eeh_freeze_set(struct phb * phb,uint64_t pe_number,uint64_t eeh_action_token)2954 static int64_t phb3_eeh_freeze_set(struct phb *phb, uint64_t pe_number,
2955 uint64_t eeh_action_token)
2956 {
2957 struct phb3 *p = phb_to_phb3(phb);
2958 uint64_t data;
2959
2960 if (p->broken)
2961 return OPAL_HARDWARE;
2962
2963 if (pe_number >= PHB3_MAX_PE_NUM)
2964 return OPAL_PARAMETER;
2965
2966 if (eeh_action_token != OPAL_EEH_ACTION_SET_FREEZE_MMIO &&
2967 eeh_action_token != OPAL_EEH_ACTION_SET_FREEZE_DMA &&
2968 eeh_action_token != OPAL_EEH_ACTION_SET_FREEZE_ALL)
2969 return OPAL_PARAMETER;
2970
2971 if (eeh_action_token & OPAL_EEH_ACTION_SET_FREEZE_MMIO) {
2972 phb3_ioda_sel(p, IODA2_TBL_PESTA, pe_number, false);
2973 data = in_be64(p->regs + PHB_IODA_DATA0);
2974 data |= IODA2_PESTA_MMIO_FROZEN;
2975 out_be64(p->regs + PHB_IODA_DATA0, data);
2976 }
2977
2978 if (eeh_action_token & OPAL_EEH_ACTION_SET_FREEZE_DMA) {
2979 phb3_ioda_sel(p, IODA2_TBL_PESTB, pe_number, false);
2980 data = in_be64(p->regs + PHB_IODA_DATA0);
2981 data |= IODA2_PESTB_DMA_STOPPED;
2982 out_be64(p->regs + PHB_IODA_DATA0, data);
2983 }
2984
2985 return OPAL_SUCCESS;
2986 }
2987
phb3_eeh_next_error(struct phb * phb,uint64_t * first_frozen_pe,uint16_t * pci_error_type,uint16_t * severity)2988 static int64_t phb3_eeh_next_error(struct phb *phb,
2989 uint64_t *first_frozen_pe,
2990 uint16_t *pci_error_type,
2991 uint16_t *severity)
2992 {
2993 struct phb3 *p = phb_to_phb3(phb);
2994 uint64_t fir, peev[4];
2995 uint32_t cfg32;
2996 int32_t i, j;
2997
2998 /* If the PHB is broken, we needn't go forward */
2999 if (p->broken) {
3000 *pci_error_type = OPAL_EEH_PHB_ERROR;
3001 *severity = OPAL_EEH_SEV_PHB_DEAD;
3002 return OPAL_SUCCESS;
3003 }
3004
3005 if ((p->flags & PHB3_CAPP_RECOVERY)) {
3006 *pci_error_type = OPAL_EEH_PHB_ERROR;
3007 *severity = OPAL_EEH_SEV_PHB_FENCED;
3008 return OPAL_SUCCESS;
3009 }
3010
3011 /*
3012 * Check if we already have pending errors. If that's
3013 * the case, then to get more information about the
3014 * pending errors. Here we try PBCQ prior to PHB.
3015 */
3016 if (phb3_err_pending(p) &&
3017 !phb3_err_check_pbcq(p) &&
3018 !phb3_err_check_lem(p))
3019 phb3_set_err_pending(p, false);
3020
3021 /* Clear result */
3022 *pci_error_type = OPAL_EEH_NO_ERROR;
3023 *severity = OPAL_EEH_SEV_NO_ERROR;
3024 *first_frozen_pe = (uint64_t)-1;
3025
3026 /* Check frozen PEs */
3027 if (!phb3_err_pending(p)) {
3028 phb3_ioda_sel(p, IODA2_TBL_PEEV, 0, true);
3029 for (i = 0; i < ARRAY_SIZE(peev); i++) {
3030 peev[i] = in_be64(p->regs + PHB_IODA_DATA0);
3031 if (peev[i]) {
3032 p->err.err_src = PHB3_ERR_SRC_PHB;
3033 p->err.err_class = PHB3_ERR_CLASS_ER;
3034 p->err.err_bit = -1;
3035 phb3_set_err_pending(p, true);
3036 break;
3037 }
3038 }
3039 }
3040
3041 /* Mapping errors */
3042 if (phb3_err_pending(p)) {
3043 /*
3044 * If the frozen PE is caused by a malfunctioning TLP, we
3045 * need reset the PHB. So convert ER to PHB-fatal error
3046 * for the case.
3047 */
3048 if (p->err.err_class == PHB3_ERR_CLASS_ER) {
3049 fir = phb3_read_reg_asb(p, PHB_LEM_FIR_ACCUM);
3050 if (fir & PPC_BIT(60)) {
3051 phb3_pcicfg_read32(&p->phb, 0,
3052 p->aercap + PCIECAP_AER_UE_STATUS, &cfg32);
3053 if (cfg32 & PCIECAP_AER_UE_MALFORMED_TLP)
3054 p->err.err_class = PHB3_ERR_CLASS_FENCED;
3055 }
3056 }
3057
3058 switch (p->err.err_class) {
3059 case PHB3_ERR_CLASS_DEAD:
3060 *pci_error_type = OPAL_EEH_PHB_ERROR;
3061 *severity = OPAL_EEH_SEV_PHB_DEAD;
3062 break;
3063 case PHB3_ERR_CLASS_FENCED:
3064 *pci_error_type = OPAL_EEH_PHB_ERROR;
3065 *severity = OPAL_EEH_SEV_PHB_FENCED;
3066 break;
3067 case PHB3_ERR_CLASS_ER:
3068 *pci_error_type = OPAL_EEH_PE_ERROR;
3069 *severity = OPAL_EEH_SEV_PE_ER;
3070
3071 phb3_ioda_sel(p, IODA2_TBL_PEEV, 0, true);
3072 for (i = 0; i < ARRAY_SIZE(peev); i++)
3073 peev[i] = in_be64(p->regs + PHB_IODA_DATA0);
3074 for (i = ARRAY_SIZE(peev) - 1; i >= 0; i--) {
3075 for (j = 0; j < 64; j++) {
3076 if (peev[i] & PPC_BIT(j)) {
3077 *first_frozen_pe = i * 64 + j;
3078 break;
3079 }
3080 }
3081
3082 if (*first_frozen_pe != (uint64_t)(-1))
3083 break;
3084 }
3085
3086 /* No frozen PE ? */
3087 if (*first_frozen_pe == (uint64_t)-1) {
3088 *pci_error_type = OPAL_EEH_NO_ERROR;
3089 *severity = OPAL_EEH_SEV_NO_ERROR;
3090 phb3_set_err_pending(p, false);
3091 }
3092
3093 break;
3094 case PHB3_ERR_CLASS_INF:
3095 *pci_error_type = OPAL_EEH_PHB_ERROR;
3096 *severity = OPAL_EEH_SEV_INF;
3097 break;
3098 default:
3099 *pci_error_type = OPAL_EEH_NO_ERROR;
3100 *severity = OPAL_EEH_SEV_NO_ERROR;
3101 phb3_set_err_pending(p, false);
3102 }
3103 }
3104
3105 return OPAL_SUCCESS;
3106 }
3107
phb3_err_inject_finalize(struct phb3 * p,uint64_t addr,uint64_t mask,uint64_t ctrl,bool is_write)3108 static int64_t phb3_err_inject_finalize(struct phb3 *p, uint64_t addr,
3109 uint64_t mask, uint64_t ctrl,
3110 bool is_write)
3111 {
3112 if (is_write)
3113 ctrl |= PHB_PAPR_ERR_INJ_CTL_WR;
3114 else
3115 ctrl |= PHB_PAPR_ERR_INJ_CTL_RD;
3116
3117 out_be64(p->regs + PHB_PAPR_ERR_INJ_ADDR, addr);
3118 out_be64(p->regs + PHB_PAPR_ERR_INJ_MASK, mask);
3119 out_be64(p->regs + PHB_PAPR_ERR_INJ_CTL, ctrl);
3120
3121 return OPAL_SUCCESS;
3122 }
3123
phb3_err_inject_mem32(struct phb3 * p,uint64_t pe_number,uint64_t addr,uint64_t mask,bool is_write)3124 static int64_t phb3_err_inject_mem32(struct phb3 *p, uint64_t pe_number,
3125 uint64_t addr, uint64_t mask,
3126 bool is_write)
3127 {
3128 uint64_t base, len, segstart, segsize;
3129 uint64_t a, m;
3130 uint64_t ctrl = PHB_PAPR_ERR_INJ_CTL_OUTB;
3131 uint32_t index;
3132
3133 segsize = (M32_PCI_SIZE / PHB3_MAX_PE_NUM);
3134 a = base = len = 0x0ull;
3135
3136 for (index = 0; index < PHB3_MAX_PE_NUM; index++) {
3137 if (GETFIELD(IODA2_M32DT_PE, p->m32d_cache[index]) != pe_number)
3138 continue;
3139
3140 /* Obviously, we can't support discontiguous segments.
3141 * We have to pick the first batch of contiguous segments
3142 * for that case
3143 */
3144 segstart = p->mm1_base + segsize * index;
3145 if (!len) {
3146 base = segstart;
3147 len = segsize;
3148 } else if ((base + len) == segstart) {
3149 len += segsize;
3150 }
3151
3152 /* Check the specified address is valid one */
3153 if (addr >= segstart && addr < (segstart + segsize)) {
3154 a = addr;
3155 break;
3156 }
3157 }
3158
3159 /* No MM32 segments assigned to the PE */
3160 if (!len)
3161 return OPAL_PARAMETER;
3162
3163 /* Specified address is out of range */
3164 if (!a) {
3165 a = base;
3166 len = len & ~(len - 1);
3167 m = ~(len - 1);
3168 } else {
3169 m = mask;
3170 }
3171
3172 a = SETFIELD(PHB_PAPR_ERR_INJ_ADDR_MMIO, 0x0ull, a);
3173 m = SETFIELD(PHB_PAPR_ERR_INJ_MASK_MMIO, 0x0ull, m);
3174
3175 return phb3_err_inject_finalize(p, a, m, ctrl, is_write);
3176 }
3177
phb3_err_inject_mem64(struct phb3 * p,uint64_t pe_number,uint64_t addr,uint64_t mask,bool is_write)3178 static int64_t phb3_err_inject_mem64(struct phb3 *p, uint64_t pe_number,
3179 uint64_t addr, uint64_t mask,
3180 bool is_write)
3181 {
3182 uint64_t base, len, segstart, segsize;
3183 uint64_t cache, a, m;
3184 uint64_t ctrl = PHB_PAPR_ERR_INJ_CTL_OUTB;
3185 uint32_t index, s_index, e_index;
3186
3187 /* By default, the PE is PCI device dependent one */
3188 s_index = 0;
3189 e_index = ARRAY_SIZE(p->m64b_cache) - 2;
3190 for (index = 0; index < RTT_TABLE_ENTRIES; index++) {
3191 if (p->rte_cache[index] != pe_number)
3192 continue;
3193
3194 if (index + 8 >= RTT_TABLE_ENTRIES)
3195 break;
3196
3197 /* PCI bus dependent PE */
3198 if (p->rte_cache[index + 8] == pe_number) {
3199 s_index = e_index = ARRAY_SIZE(p->m64b_cache) - 1;
3200 break;
3201 }
3202 }
3203
3204 a = base = len = 0x0ull;
3205 for (index = s_index; !len && index <= e_index; index++) {
3206 cache = p->m64b_cache[index];
3207 if (!(cache & IODA2_M64BT_ENABLE))
3208 continue;
3209
3210 if (cache & IODA2_M64BT_SINGLE_PE) {
3211 if (GETFIELD(IODA2_M64BT_PE_HI, cache) != (pe_number >> 5) ||
3212 GETFIELD(IODA2_M64BT_PE_LOW, cache) != (pe_number & 0x1f))
3213 continue;
3214
3215 segstart = GETFIELD(IODA2_M64BT_SINGLE_BASE, cache);
3216 segstart <<= 25; /* 32MB aligned */
3217 segsize = GETFIELD(IODA2_M64BT_SINGLE_MASK, cache);
3218 segsize = (0x2000000ull - segsize) << 25;
3219 } else {
3220 segstart = GETFIELD(IODA2_M64BT_BASE, cache);
3221 segstart <<= 20; /* 1MB aligned */
3222 segsize = GETFIELD(IODA2_M64BT_MASK, cache);
3223 segsize = (0x40000000ull - segsize) << 20;
3224
3225 segsize /= PHB3_MAX_PE_NUM;
3226 segstart = segstart + segsize * pe_number;
3227 }
3228
3229 /* First window always wins based on the ascending
3230 * searching priority the 16 BARs have. We're using
3231 * the feature to assign resource for SRIOV VFs.
3232 */
3233 if (!len) {
3234 base = segstart;
3235 len = segsize;
3236 }
3237
3238 /* Specified address is valid one */
3239 if (addr >= segstart && addr < (segstart + segsize)) {
3240 a = addr;
3241 }
3242 }
3243
3244 /* No MM64 segments assigned to the PE */
3245 if (!len)
3246 return OPAL_PARAMETER;
3247
3248 /* Address specified or calculated */
3249 if (!a) {
3250 a = base;
3251 len = len & ~(len - 1);
3252 m = ~(len - 1);
3253 } else {
3254 m = mask;
3255 }
3256
3257 a = SETFIELD(PHB_PAPR_ERR_INJ_ADDR_MMIO, 0x0ull, a);
3258 m = SETFIELD(PHB_PAPR_ERR_INJ_MASK_MMIO, 0x0ull, m);
3259
3260 return phb3_err_inject_finalize(p, a, m, ctrl, is_write);
3261 }
3262
phb3_err_inject_cfg(struct phb3 * p,uint64_t pe_number,uint64_t addr,uint64_t mask,bool is_write)3263 static int64_t phb3_err_inject_cfg(struct phb3 *p, uint64_t pe_number,
3264 uint64_t addr, uint64_t mask,
3265 bool is_write)
3266 {
3267 uint64_t a, m, prefer;
3268 uint64_t ctrl = PHB_PAPR_ERR_INJ_CTL_CFG;
3269 int bdfn;
3270 bool is_bus_pe;
3271
3272 a = 0xffffull;
3273 prefer = 0xffffull;
3274 m = PHB_PAPR_ERR_INJ_MASK_CFG_ALL;
3275 for (bdfn = 0; bdfn < RTT_TABLE_ENTRIES; bdfn++) {
3276 if (p->rte_cache[bdfn] != pe_number)
3277 continue;
3278
3279 /* The PE can be associated with PCI bus or device */
3280 is_bus_pe = false;
3281 if ((bdfn + 8) < RTT_TABLE_ENTRIES &&
3282 p->rte_cache[bdfn + 8] == pe_number)
3283 is_bus_pe = true;
3284
3285 /* Figure out the PCI config address */
3286 if (prefer == 0xffffull) {
3287 if (is_bus_pe) {
3288 m = PHB_PAPR_ERR_INJ_MASK_CFG;
3289 prefer = SETFIELD(m, 0x0ull, (bdfn >> 8));
3290 } else {
3291 m = PHB_PAPR_ERR_INJ_MASK_CFG_ALL;
3292 prefer = SETFIELD(m, 0x0ull, bdfn);
3293 }
3294 }
3295
3296 /* Check the input address is valid or not */
3297 if (!is_bus_pe &&
3298 GETFIELD(PHB_PAPR_ERR_INJ_MASK_CFG_ALL, addr) == bdfn) {
3299 a = addr;
3300 break;
3301 }
3302
3303 if (is_bus_pe &&
3304 GETFIELD(PHB_PAPR_ERR_INJ_MASK_CFG, addr) == (bdfn >> 8)) {
3305 a = addr;
3306 break;
3307 }
3308 }
3309
3310 /* Invalid PE number */
3311 if (prefer == 0xffffull)
3312 return OPAL_PARAMETER;
3313
3314 /* Specified address is out of range */
3315 if (a == 0xffffull)
3316 a = prefer;
3317 else
3318 m = mask;
3319
3320 return phb3_err_inject_finalize(p, a, m, ctrl, is_write);
3321 }
3322
phb3_err_inject_dma(struct phb3 * p,uint64_t pe_number,uint64_t addr,uint64_t mask,bool is_write,bool is_64bits)3323 static int64_t phb3_err_inject_dma(struct phb3 *p, uint64_t pe_number,
3324 uint64_t addr, uint64_t mask,
3325 bool is_write, bool is_64bits)
3326 {
3327 uint32_t index, page_size;
3328 uint64_t tve, table_entries;
3329 uint64_t base, start, end, len, a, m;
3330 uint64_t ctrl = PHB_PAPR_ERR_INJ_CTL_INB;
3331
3332 /* TVE index and base address */
3333 if (!is_64bits) {
3334 index = (pe_number << 1);
3335 base = 0x0ull;
3336 } else {
3337 index = ((pe_number << 1) + 1);
3338 base = (0x1ull << 59);
3339 }
3340
3341 /* Raw data of table entries and page size */
3342 tve = p->tve_cache[index];
3343 table_entries = GETFIELD(IODA2_TVT_TCE_TABLE_SIZE, tve);
3344 table_entries = (0x1ull << (table_entries + 8));
3345 page_size = GETFIELD(IODA2_TVT_IO_PSIZE, tve);
3346 if (!page_size && !(tve & PPC_BIT(51)))
3347 return OPAL_UNSUPPORTED;
3348
3349 /* Check the page size */
3350 switch (page_size) {
3351 case 0: /* bypass */
3352 start = ((tve & (0x3ull << 10)) << 14) |
3353 ((tve & (0xffffffull << 40)) >> 40);
3354 end = ((tve & (0x3ull << 8)) << 16) |
3355 ((tve & (0xffffffull << 16)) >> 16);
3356
3357 /* 16MB aligned size */
3358 len = (end - start) << 24;
3359 break;
3360 case 5: /* 64KB */
3361 len = table_entries * 0x10000ull;
3362 break;
3363 case 13: /* 16MB */
3364 len = table_entries * 0x1000000ull;
3365 break;
3366 case 17: /* 256MB */
3367 len = table_entries * 0x10000000ull;
3368 break;
3369 case 1: /* 4KB */
3370 default:
3371 len = table_entries * 0x1000ull;
3372 }
3373
3374 /* The specified address is in range */
3375 if (addr && addr >= base && addr < (base + len)) {
3376 a = addr;
3377 m = mask;
3378 } else {
3379 a = base;
3380 len = len & ~(len - 1);
3381 m = ~(len - 1);
3382 }
3383
3384 return phb3_err_inject_finalize(p, a, m, ctrl, is_write);
3385 }
3386
phb3_err_inject_dma32(struct phb3 * p,uint64_t pe_number,uint64_t addr,uint64_t mask,bool is_write)3387 static int64_t phb3_err_inject_dma32(struct phb3 *p, uint64_t pe_number,
3388 uint64_t addr, uint64_t mask,
3389 bool is_write)
3390 {
3391 return phb3_err_inject_dma(p, pe_number, addr, mask, is_write, false);
3392 }
3393
phb3_err_inject_dma64(struct phb3 * p,uint64_t pe_number,uint64_t addr,uint64_t mask,bool is_write)3394 static int64_t phb3_err_inject_dma64(struct phb3 *p, uint64_t pe_number,
3395 uint64_t addr, uint64_t mask,
3396 bool is_write)
3397 {
3398 return phb3_err_inject_dma(p, pe_number, addr, mask, is_write, true);
3399 }
3400
phb3_err_inject(struct phb * phb,uint64_t pe_number,uint32_t type,uint32_t func,uint64_t addr,uint64_t mask)3401 static int64_t phb3_err_inject(struct phb *phb, uint64_t pe_number,
3402 uint32_t type, uint32_t func,
3403 uint64_t addr, uint64_t mask)
3404 {
3405 struct phb3 *p = phb_to_phb3(phb);
3406 int64_t (*handler)(struct phb3 *p, uint64_t pe_number,
3407 uint64_t addr, uint64_t mask, bool is_write);
3408 bool is_write;
3409
3410 /* How could we get here without valid RTT? */
3411 if (!p->tbl_rtt)
3412 return OPAL_HARDWARE;
3413
3414 /* We can't inject error to the reserved PE */
3415 if (pe_number == PHB3_RESERVED_PE_NUM || pe_number >= PHB3_MAX_PE_NUM)
3416 return OPAL_PARAMETER;
3417
3418 /* Clear leftover from last time */
3419 out_be64(p->regs + PHB_PAPR_ERR_INJ_CTL, 0x0ul);
3420
3421 switch (func) {
3422 case OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR:
3423 case OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA:
3424 is_write = false;
3425 if (type == OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64)
3426 handler = phb3_err_inject_mem64;
3427 else
3428 handler = phb3_err_inject_mem32;
3429 break;
3430 case OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR:
3431 case OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA:
3432 is_write = true;
3433 if (type == OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64)
3434 handler = phb3_err_inject_mem64;
3435 else
3436 handler = phb3_err_inject_mem32;
3437 break;
3438 case OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR:
3439 case OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA:
3440 is_write = false;
3441 handler = phb3_err_inject_cfg;
3442 break;
3443 case OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR:
3444 case OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA:
3445 is_write = true;
3446 handler = phb3_err_inject_cfg;
3447 break;
3448 case OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR:
3449 case OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA:
3450 case OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER:
3451 case OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET:
3452 is_write = false;
3453 if (type == OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64)
3454 handler = phb3_err_inject_dma64;
3455 else
3456 handler = phb3_err_inject_dma32;
3457 break;
3458 case OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR:
3459 case OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA:
3460 case OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER:
3461 case OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET:
3462 is_write = true;
3463 if (type == OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64)
3464 handler = phb3_err_inject_dma64;
3465 else
3466 handler = phb3_err_inject_dma32;
3467 break;
3468 default:
3469 return OPAL_PARAMETER;
3470 }
3471
3472 return handler(p, pe_number, addr, mask, is_write);
3473 }
3474
phb3_get_diag_data(struct phb * phb,void * diag_buffer,uint64_t diag_buffer_len)3475 static int64_t phb3_get_diag_data(struct phb *phb,
3476 void *diag_buffer,
3477 uint64_t diag_buffer_len)
3478 {
3479 struct phb3 *p = phb_to_phb3(phb);
3480 struct OpalIoPhb3ErrorData *data = diag_buffer;
3481 bool fenced;
3482
3483 if (diag_buffer_len < sizeof(struct OpalIoPhb3ErrorData))
3484 return OPAL_PARAMETER;
3485 if (p->broken)
3486 return OPAL_HARDWARE;
3487
3488 /*
3489 * Dummy check for fence so that phb3_read_phb_status knows
3490 * whether to use ASB or AIB
3491 */
3492 fenced = phb3_fenced(p);
3493 phb3_read_phb_status(p, data);
3494
3495 if (!fenced)
3496 phb3_eeh_dump_regs(p, data);
3497
3498 /*
3499 * We're running to here probably because of errors
3500 * (INF class). For that case, we need clear the error
3501 * explicitly.
3502 */
3503 if (phb3_err_pending(p) &&
3504 p->err.err_class == PHB3_ERR_CLASS_INF &&
3505 p->err.err_src == PHB3_ERR_SRC_PHB) {
3506 phb3_err_ER_clear(p);
3507 phb3_set_err_pending(p, false);
3508 }
3509
3510 return OPAL_SUCCESS;
3511 }
3512
phb3_get_capp_info(int chip_id,struct phb * phb,struct capp_info * info)3513 static int64_t phb3_get_capp_info(int chip_id, struct phb *phb,
3514 struct capp_info *info)
3515 {
3516 struct phb3 *p = phb_to_phb3(phb);
3517 struct proc_chip *chip = get_chip(p->chip_id);
3518 uint32_t offset;
3519
3520 if (chip_id != p->chip_id)
3521 return OPAL_PARAMETER;
3522
3523 if (!((1 << p->index) & chip->capp_phb3_attached_mask))
3524 return OPAL_PARAMETER;
3525
3526 offset = PHB3_CAPP_REG_OFFSET(p);
3527
3528 if (PHB3_IS_NAPLES(p)) {
3529 if (p->index == 0)
3530 info->capp_index = 0;
3531 else
3532 info->capp_index = 1;
3533 } else
3534 info->capp_index = 0;
3535 info->phb_index = p->index;
3536 info->capp_fir_reg = CAPP_FIR + offset;
3537 info->capp_fir_mask_reg = CAPP_FIR_MASK + offset;
3538 info->capp_fir_action0_reg = CAPP_FIR_ACTION0 + offset;
3539 info->capp_fir_action1_reg = CAPP_FIR_ACTION1 + offset;
3540 info->capp_err_status_ctrl_reg = CAPP_ERR_STATUS_CTRL + offset;
3541
3542 return OPAL_SUCCESS;
3543 }
3544
phb3_init_capp_regs(struct phb3 * p,bool dma_mode)3545 static void phb3_init_capp_regs(struct phb3 *p, bool dma_mode)
3546 {
3547 uint64_t reg;
3548 uint32_t offset;
3549 uint64_t read_buffers = 0;
3550
3551 offset = PHB3_CAPP_REG_OFFSET(p);
3552 xscom_read(p->chip_id, APC_MASTER_PB_CTRL + offset, ®);
3553 reg &= ~PPC_BITMASK(10, 11);
3554 reg |= PPC_BIT(3);
3555 if (dma_mode) {
3556 /* In DMA mode, the CAPP only owns some of the PHB read buffers */
3557 read_buffers = 0x1;
3558
3559 /*
3560 * HW301991 - XSL sends PTE updates with nodal scope instead of
3561 * group scope. The workaround is to force all commands to
3562 * unlimited scope by setting bit 4. This may have a slight
3563 * performance impact, but it would be negligible on the XSL.
3564 * To avoid the possibility it might impact other cards, key it
3565 * off DMA mode since the XSL based Mellanox CX4 is the only
3566 * card to use this mode in P8 timeframe:
3567 */
3568 reg |= PPC_BIT(4);
3569 }
3570 reg |= read_buffers << PPC_BITLSHIFT(11);
3571 xscom_write(p->chip_id, APC_MASTER_PB_CTRL + offset, reg);
3572
3573 /* Dynamically workout which PHB to connect to port 0 of the CAPP.
3574 * Here is the table from the CAPP workbook:
3575 * APC_MASTER CAPP CAPP
3576 * bits 1:3 port0 port1
3577 * 000 disabled disabled
3578 * * 001 PHB2 disabled
3579 * * 010 PHB1 disabled
3580 * 011 PHB1 PHB2
3581 * * 100 PHB0 disabled
3582 * 101 PHB0 PHB2
3583 * 110 PHB0 PHB1
3584 *
3585 * We don't use port1 so only those starred above are used.
3586 * Hence reduce table to:
3587 * PHB0 -> APC MASTER(bits 1:3) = 0b100
3588 * PHB1 -> APC MASTER(bits 1:3) = 0b010
3589 * PHB2 -> APC MASTER(bits 1:3) = 0b001
3590 *
3591 * Note: Naples has two CAPP units, statically mapped:
3592 * CAPP0/PHB0 -> APC MASTER(bits 1:3) = 0b100
3593 * CAPP1/PHB1 -> APC MASTER(bits 1:3) = 0b010
3594 */
3595 reg = 0x4000000000000000ULL >> p->index;
3596 reg |= 0x0070000000000000UL;
3597 xscom_write(p->chip_id, APC_MASTER_CAPI_CTRL + offset, reg);
3598 PHBINF(p, "CAPP: port attached\n");
3599
3600 /* tlb and mmio */
3601 xscom_write(p->chip_id, TRANSPORT_CONTROL + offset, 0x4028000104000000UL);
3602
3603 xscom_write(p->chip_id, CANNED_PRESP_MAP0 + offset, 0);
3604 xscom_write(p->chip_id, CANNED_PRESP_MAP1 + offset, 0xFFFFFFFF00000000UL);
3605 xscom_write(p->chip_id, CANNED_PRESP_MAP2 + offset, 0);
3606
3607 /* error recovery */
3608 xscom_write(p->chip_id, CAPP_ERR_STATUS_CTRL + offset, 0);
3609
3610 xscom_write(p->chip_id, FLUSH_SUE_STATE_MAP + offset,
3611 0x1DC20B6600000000UL);
3612 xscom_write(p->chip_id, CAPP_EPOCH_TIMER_CTRL + offset,
3613 0xC0000000FFF0FFE0UL);
3614 xscom_write(p->chip_id, FLUSH_UOP_CONFIG1 + offset,
3615 0xB188280728000000UL);
3616 xscom_write(p->chip_id, FLUSH_UOP_CONFIG2 + offset, 0xB188400F00000000UL);
3617
3618 reg = 0xA1F0000000000000UL;
3619 reg |= read_buffers << PPC_BITLSHIFT(39);
3620 xscom_write(p->chip_id, SNOOP_CAPI_CONFIG + offset, reg);
3621 }
3622
3623 /* override some inits with CAPI defaults */
phb3_init_capp_errors(struct phb3 * p)3624 static void phb3_init_capp_errors(struct phb3 *p)
3625 {
3626 out_be64(p->regs + PHB_ERR_AIB_FENCE_ENABLE, 0xffffffdd8c80ffc0UL);
3627 out_be64(p->regs + PHB_OUT_ERR_AIB_FENCE_ENABLE, 0x9cf3fe08f8dc700fUL);
3628 out_be64(p->regs + PHB_INA_ERR_AIB_FENCE_ENABLE, 0xffff57fbff01ffdeUL);
3629 out_be64(p->regs + PHB_INB_ERR_AIB_FENCE_ENABLE, 0xfcffe0fbff7ff0ecUL);
3630 out_be64(p->regs + PHB_LEM_ERROR_MASK, 0x40018e2400022482UL);
3631 }
3632
3633 /*
3634 * Enable CAPI mode on a PHB
3635 *
3636 * Changes to this init sequence may require updating disable_capi_mode().
3637 */
enable_capi_mode(struct phb3 * p,uint64_t pe_number,bool dma_mode)3638 static int64_t enable_capi_mode(struct phb3 *p, uint64_t pe_number, bool dma_mode)
3639 {
3640 uint64_t reg;
3641 int i;
3642
3643 xscom_read(p->chip_id, PE_CAPP_EN + PE_REG_OFFSET(p), ®);
3644 if (reg & PPC_BIT(0)) {
3645 PHBDBG(p, "Already in CAPP mode\n");
3646 }
3647
3648 /* poll cqstat */
3649 for (i = 0; i < 500000; i++) {
3650 xscom_read(p->chip_id, p->pe_xscom + 0xf, ®);
3651 if (!(reg & 0xC000000000000000UL))
3652 break;
3653 time_wait_us(10);
3654 }
3655 if (reg & 0xC000000000000000UL) {
3656 PHBERR(p, "CAPP: Timeout waiting for pending transaction\n");
3657 return OPAL_HARDWARE;
3658 }
3659
3660 /* pb aib capp enable */
3661 reg = PPC_BIT(0); /* capp enable */
3662 if (dma_mode)
3663 reg |= PPC_BIT(1); /* capp dma mode */
3664 xscom_write(p->chip_id, p->spci_xscom + 0x3, reg);
3665
3666 /* FIXME security timer bar
3667 xscom_write(p->chip_id, p->spci_xscom + 0x4, 0x8000000000000000ull);
3668 */
3669
3670 /* aib mode */
3671 xscom_read(p->chip_id, p->pci_xscom + 0xf, ®);
3672 reg &= ~PPC_BITMASK(6,7);
3673 reg |= PPC_BIT(8);
3674 reg |= PPC_BITMASK(40, 41);
3675 reg &= ~PPC_BIT(42);
3676 xscom_write(p->chip_id, p->pci_xscom + 0xf, reg);
3677
3678 /* pci hwconf0 */
3679 xscom_read(p->chip_id, p->pe_xscom + 0x18, ®);
3680 reg |= PPC_BIT(14);
3681 reg &= ~PPC_BIT(15);
3682 xscom_write(p->chip_id, p->pe_xscom + 0x18, reg);
3683
3684 /* pci hwconf1 */
3685 xscom_read(p->chip_id, p->pe_xscom + 0x19, ®);
3686 reg &= ~PPC_BITMASK(17,18);
3687 xscom_write(p->chip_id, p->pe_xscom + 0x19, reg);
3688
3689 /* aib tx cmd cred */
3690 xscom_read(p->chip_id, p->pci_xscom + 0xd, ®);
3691 if (dma_mode) {
3692 /*
3693 * In DMA mode, increase AIB credit value for ch 2 (DMA read)
3694 * for performance reasons
3695 */
3696 reg &= ~PPC_BITMASK(42, 47);
3697 reg |= PPC_BITMASK(43, 45);
3698 } else {
3699 reg &= ~PPC_BITMASK(42, 46);
3700 reg |= PPC_BIT(47);
3701 }
3702 xscom_write(p->chip_id, p->pci_xscom + 0xd, reg);
3703
3704 xscom_write(p->chip_id, p->pci_xscom + 0xc, 0xff00000000000000ull);
3705
3706 /* pci mode ctl */
3707 xscom_read(p->chip_id, p->pe_xscom + 0xb, ®);
3708 reg |= PPC_BIT(25);
3709 xscom_write(p->chip_id, p->pe_xscom + 0xb, reg);
3710
3711 /* set tve no translate mode allow mmio window */
3712 memset(p->tve_cache, 0x0, sizeof(p->tve_cache));
3713 if (dma_mode) {
3714 /*
3715 * CAPP DMA mode needs access to all of memory, set address
3716 * range to 0x0000000000000000: 0x0002FFFFFFFFFFF
3717 */
3718 p->tve_cache[pe_number * 2] = 0x000000FFFFFF0200ULL;
3719 } else {
3720 /* Allow address range 0x0002000000000000: 0x0002FFFFFFFFFFF */
3721 p->tve_cache[pe_number * 2] = 0x000000FFFFFF0a00ULL;
3722 }
3723
3724 phb3_ioda_sel(p, IODA2_TBL_TVT, 0, true);
3725 for (i = 0; i < ARRAY_SIZE(p->tve_cache); i++)
3726 out_be64(p->regs + PHB_IODA_DATA0, p->tve_cache[i]);
3727
3728 /* set m64 bar to pass mmio window */
3729 memset(p->m64b_cache, 0x0, sizeof(p->m64b_cache));
3730 p->m64b_cache[0] = PPC_BIT(0); /*enable*/
3731 p->m64b_cache[0] |= PPC_BIT(1); /*single pe*/
3732 p->m64b_cache[0] |= (p->mm0_base << 12) | ((pe_number & 0x3e0) << 27); /*base and upper pe*/
3733 p->m64b_cache[0] |= 0x3fffc000 | (pe_number & 0x1f); /*mask and lower pe*/
3734
3735 p->m64b_cache[1] = PPC_BIT(0); /*enable*/
3736 p->m64b_cache[1] |= PPC_BIT(1); /*single pe*/
3737 p->m64b_cache[1] |= (0x0002000000000000ULL << 12) | ((pe_number & 0x3e0) << 27); /*base and upper pe*/
3738 p->m64b_cache[1] |= 0x3f000000 | (pe_number & 0x1f); /*mask and lower pe*/
3739
3740 phb3_ioda_sel(p, IODA2_TBL_M64BT, 0, true);
3741 for (i = 0; i < ARRAY_SIZE(p->m64b_cache); i++)
3742 out_be64(p->regs + PHB_IODA_DATA0, p->m64b_cache[i]);
3743
3744 out_be64(p->regs + PHB_PHB3_CONFIG, PHB_PHB3C_64B_TCE_EN);
3745 out_be64(p->regs + PHB_PHB3_CONFIG, PHB_PHB3C_64BIT_MSI_EN);
3746
3747 phb3_init_capp_errors(p);
3748
3749 phb3_init_capp_regs(p, dma_mode);
3750
3751 if (!chiptod_capp_timebase_sync(p->chip_id, CAPP_TFMR, CAPP_TB,
3752 PHB3_CAPP_REG_OFFSET(p))) {
3753 PHBERR(p, "CAPP: Failed to sync timebase\n");
3754 return OPAL_HARDWARE;
3755 }
3756
3757 /* set callbacks to handle HMI events */
3758 capi_ops.get_capp_info = &phb3_get_capp_info;
3759
3760 return OPAL_SUCCESS;
3761 }
3762
phb3_set_capi_mode(struct phb * phb,uint64_t mode,uint64_t pe_number)3763 static int64_t phb3_set_capi_mode(struct phb *phb, uint64_t mode,
3764 uint64_t pe_number)
3765 {
3766 struct phb3 *p = phb_to_phb3(phb);
3767 struct proc_chip *chip = get_chip(p->chip_id);
3768 uint64_t reg;
3769 uint64_t read_buffers;
3770 uint32_t offset;
3771 u8 mask;
3772
3773 if (!capp_ucode_loaded(chip, p->index)) {
3774 PHBERR(p, "CAPP: ucode not loaded\n");
3775 return OPAL_RESOURCE;
3776 }
3777
3778 lock(&capi_lock);
3779 if (PHB3_IS_NAPLES(p)) {
3780 /* Naples has two CAPP units, statically mapped. */
3781 chip->capp_phb3_attached_mask |= 1 << p->index;
3782 } else {
3783 /*
3784 * Check if CAPP port is being used by any another PHB.
3785 * Check and set chip->capp_phb3_attached_mask atomically
3786 * incase two phb3_set_capi_mode() calls race.
3787 */
3788 mask = ~(1 << p->index);
3789 if (chip->capp_phb3_attached_mask & mask) {
3790 PHBERR(p,
3791 "CAPP: port already in use by another PHB:%x\n",
3792 chip->capp_phb3_attached_mask);
3793 unlock(&capi_lock);
3794 return false;
3795 }
3796 chip->capp_phb3_attached_mask = 1 << p->index;
3797 }
3798 unlock(&capi_lock);
3799
3800 offset = PHB3_CAPP_REG_OFFSET(p);
3801 xscom_read(p->chip_id, CAPP_ERR_STATUS_CTRL + offset, ®);
3802 if ((reg & PPC_BIT(5))) {
3803 PHBERR(p, "CAPP: recovery failed (%016llx)\n", reg);
3804 return OPAL_HARDWARE;
3805 } else if ((reg & PPC_BIT(0)) && (!(reg & PPC_BIT(1)))) {
3806 PHBDBG(p, "CAPP: recovery in progress\n");
3807 return OPAL_BUSY;
3808 }
3809
3810 switch (mode) {
3811 case OPAL_PHB_CAPI_MODE_PCIE:
3812 /* Switching back to PCIe mode requires a creset */
3813 return OPAL_UNSUPPORTED;
3814
3815 case OPAL_PHB_CAPI_MODE_CAPI:
3816 return enable_capi_mode(p, pe_number, false);
3817
3818 case OPAL_PHB_CAPI_MODE_DMA:
3819 return enable_capi_mode(p, pe_number, true);
3820
3821 case OPAL_PHB_CAPI_MODE_SNOOP_OFF:
3822 xscom_write(p->chip_id, SNOOP_CAPI_CONFIG + offset,
3823 0x0000000000000000);
3824 return OPAL_SUCCESS;
3825
3826 case OPAL_PHB_CAPI_MODE_SNOOP_ON:
3827 xscom_write(p->chip_id, CAPP_ERR_STATUS_CTRL + offset,
3828 0x0000000000000000);
3829 /*
3830 * Make sure the PHB read buffers being snooped match those
3831 * being used so we don't need another mode to set SNOOP+DMA
3832 */
3833 xscom_read(p->chip_id, APC_MASTER_PB_CTRL + offset, ®);
3834 read_buffers = (reg >> PPC_BITLSHIFT(11)) & 0x3;
3835 reg = 0xA1F0000000000000UL;
3836 reg |= read_buffers << PPC_BITLSHIFT(39);
3837 xscom_write(p->chip_id, SNOOP_CAPI_CONFIG + offset, reg);
3838
3839 return OPAL_SUCCESS;
3840 }
3841
3842 return OPAL_UNSUPPORTED;
3843 }
3844
phb3_set_capp_recovery(struct phb * phb)3845 static int64_t phb3_set_capp_recovery(struct phb *phb)
3846 {
3847 struct phb3 *p = phb_to_phb3(phb);
3848
3849 if (p->flags & PHB3_CAPP_RECOVERY)
3850 return 0;
3851
3852 /* set opal event flag to indicate eeh condition */
3853 opal_update_pending_evt(OPAL_EVENT_PCI_ERROR,
3854 OPAL_EVENT_PCI_ERROR);
3855
3856 p->flags |= PHB3_CAPP_RECOVERY;
3857
3858 return 0;
3859 }
3860
3861 static const struct phb_ops phb3_ops = {
3862 .cfg_read8 = phb3_pcicfg_read8,
3863 .cfg_read16 = phb3_pcicfg_read16,
3864 .cfg_read32 = phb3_pcicfg_read32,
3865 .cfg_write8 = phb3_pcicfg_write8,
3866 .cfg_write16 = phb3_pcicfg_write16,
3867 .cfg_write32 = phb3_pcicfg_write32,
3868 .choose_bus = phb3_choose_bus,
3869 .get_reserved_pe_number = phb3_get_reserved_pe_number,
3870 .device_init = phb3_device_init,
3871 .device_remove = phb3_device_remove,
3872 .ioda_reset = phb3_ioda_reset,
3873 .papr_errinjct_reset = phb3_papr_errinjct_reset,
3874 .pci_reinit = phb3_pci_reinit,
3875 .set_phb_mem_window = phb3_set_phb_mem_window,
3876 .phb_mmio_enable = phb3_phb_mmio_enable,
3877 .map_pe_mmio_window = phb3_map_pe_mmio_window,
3878 .map_pe_dma_window = phb3_map_pe_dma_window,
3879 .map_pe_dma_window_real = phb3_map_pe_dma_window_real,
3880 .pci_msi_eoi = phb3_pci_msi_eoi,
3881 .set_xive_pe = phb3_set_ive_pe,
3882 .get_msi_32 = phb3_get_msi_32,
3883 .get_msi_64 = phb3_get_msi_64,
3884 .set_pe = phb3_set_pe,
3885 .set_peltv = phb3_set_peltv,
3886 .eeh_freeze_status = phb3_eeh_freeze_status,
3887 .eeh_freeze_clear = phb3_eeh_freeze_clear,
3888 .eeh_freeze_set = phb3_eeh_freeze_set,
3889 .next_error = phb3_eeh_next_error,
3890 .err_inject = phb3_err_inject,
3891 .get_diag_data2 = phb3_get_diag_data,
3892 .set_capi_mode = phb3_set_capi_mode,
3893 .set_capp_recovery = phb3_set_capp_recovery,
3894 };
3895
3896 /*
3897 * We should access those registers at the stage since the
3898 * AIB isn't ready yet.
3899 */
phb3_setup_aib(struct phb3 * p)3900 static void phb3_setup_aib(struct phb3 *p)
3901 {
3902 /* Init_2 - AIB TX Channel Mapping Register */
3903 phb3_write_reg_asb(p, PHB_AIB_TX_CHAN_MAPPING, 0x0211230000000000UL);
3904
3905 /* Init_3 - AIB RX command credit register */
3906 if (p->rev >= PHB3_REV_VENICE_DD20)
3907 phb3_write_reg_asb(p, PHB_AIB_RX_CMD_CRED, 0x0020000100020001UL);
3908 else
3909 phb3_write_reg_asb(p, PHB_AIB_RX_CMD_CRED, 0x0020000100010001UL);
3910
3911 /* Init_4 - AIB rx data credit register */
3912 if (p->rev >= PHB3_REV_VENICE_DD20)
3913 phb3_write_reg_asb(p, PHB_AIB_RX_DATA_CRED, 0x0020002000010001UL);
3914 else
3915 phb3_write_reg_asb(p, PHB_AIB_RX_DATA_CRED, 0x0020002000000001UL);
3916
3917 /* Init_5 - AIB rx credit init timer register */
3918 phb3_write_reg_asb(p, PHB_AIB_RX_CRED_INIT_TIMER, 0x0f00000000000000UL);
3919
3920 /* Init_6 - AIB Tag Enable register */
3921 phb3_write_reg_asb(p, PHB_AIB_TAG_ENABLE, 0xffffffff00000000UL);
3922
3923 /* Init_7 - TCE Tag Enable register */
3924 phb3_write_reg_asb(p, PHB_TCE_TAG_ENABLE, 0xffffffff00000000UL);
3925 }
3926
phb3_init_ioda2(struct phb3 * p)3927 static void phb3_init_ioda2(struct phb3 *p)
3928 {
3929 /* Init_14 - LSI Source ID */
3930 out_be64(p->regs + PHB_LSI_SOURCE_ID,
3931 SETFIELD(PHB_LSI_SRC_ID, 0ul, 0xff));
3932
3933 /* Init_15 - IVT BAR / Length
3934 * Init_16 - RBA BAR
3935 * - RTT BAR
3936 * Init_17 - PELT-V BAR
3937 */
3938 out_be64(p->regs + PHB_RTT_BAR,
3939 p->tbl_rtt | PHB_RTT_BAR_ENABLE);
3940 out_be64(p->regs + PHB_PELTV_BAR,
3941 p->tbl_peltv | PHB_PELTV_BAR_ENABLE);
3942 out_be64(p->regs + PHB_IVT_BAR,
3943 p->tbl_ivt | 0x800 | PHB_IVT_BAR_ENABLE);
3944
3945 /* DD2.0 or the subsequent chips don't have memory
3946 * resident RBA.
3947 */
3948 if (p->rev >= PHB3_REV_MURANO_DD20)
3949 out_be64(p->regs + PHB_RBA_BAR, 0x0ul);
3950 else
3951 out_be64(p->regs + PHB_RBA_BAR,
3952 p->tbl_rba | PHB_RBA_BAR_ENABLE);
3953
3954 /* Init_18..21 - Setup M32 */
3955 out_be64(p->regs + PHB_M32_BASE_ADDR, p->mm1_base);
3956 out_be64(p->regs + PHB_M32_BASE_MASK, ~(M32_PCI_SIZE - 1));
3957 out_be64(p->regs + PHB_M32_START_ADDR, M32_PCI_START);
3958
3959 /* Init_22 - Setup PEST BAR */
3960 out_be64(p->regs + PHB_PEST_BAR,
3961 p->tbl_pest | PHB_PEST_BAR_ENABLE);
3962
3963 /* Init_23 - PCIE Outbound upper address */
3964 out_be64(p->regs + PHB_M64_UPPER_BITS, 0);
3965
3966 /* Init_24 - Interrupt represent timers
3967 * The register doesn't take effect on Murano DD1.0
3968 */
3969 if (p->rev >= PHB3_REV_NAPLES_DD10)
3970 out_be64(p->regs + PHB_INTREP_TIMER, 0x0014000000000000UL);
3971 else if (p->rev >= PHB3_REV_MURANO_DD20)
3972 out_be64(p->regs + PHB_INTREP_TIMER, 0x0004000000000000UL);
3973 else
3974 out_be64(p->regs + PHB_INTREP_TIMER, 0);
3975
3976 /* Init_25 - PHB3 Configuration Register. Clear TCE cache then
3977 * configure the PHB
3978 */
3979 out_be64(p->regs + PHB_PHB3_CONFIG, PHB_PHB3C_64B_TCE_EN);
3980 out_be64(p->regs + PHB_PHB3_CONFIG,
3981 PHB_PHB3C_M32_EN | PHB_PHB3C_32BIT_MSI_EN |
3982 PHB_PHB3C_64BIT_MSI_EN);
3983
3984 /* Init_26 - At least 512ns delay according to spec */
3985 time_wait_us(2);
3986
3987 /* Init_27..36 - On-chip IODA tables init */
3988 phb3_ioda_reset(&p->phb, false);
3989 }
3990
phb3_wait_dlp_reset(struct phb3 * p)3991 static bool phb3_wait_dlp_reset(struct phb3 *p)
3992 {
3993 unsigned int i;
3994 uint64_t val;
3995
3996 /*
3997 * Firmware cannot access the UTL core regs or PCI config space
3998 * until the cores are out of DL_PGRESET.
3999 * DL_PGRESET should be polled until it is inactive with a value
4000 * of '0'. The recommended polling frequency is once every 1ms.
4001 * Firmware should poll at least 200 attempts before giving up.
4002 * MMIO Stores to the link are silently dropped by the UTL core if
4003 * the link is down.
4004 * MMIO Loads to the link will be dropped by the UTL core and will
4005 * eventually time-out and will return an all ones response if the
4006 * link is down.
4007 */
4008 #define DLP_RESET_ATTEMPTS 40000
4009
4010 PHBDBG(p, "Waiting for DLP PG reset to complete...\n");
4011 for (i = 0; i < DLP_RESET_ATTEMPTS; i++) {
4012 val = in_be64(p->regs + PHB_PCIE_DLP_TRAIN_CTL);
4013 if (!(val & PHB_PCIE_DLP_TC_DL_PGRESET))
4014 break;
4015 time_wait_us(10);
4016 }
4017 if (val & PHB_PCIE_DLP_TC_DL_PGRESET) {
4018 PHBERR(p, "Timeout waiting for DLP PG reset !\n");
4019 return false;
4020 }
4021 return true;
4022 }
4023
4024 /* phb3_init_rc - Initialize the Root Complex config space
4025 */
phb3_init_rc_cfg(struct phb3 * p)4026 static bool phb3_init_rc_cfg(struct phb3 *p)
4027 {
4028 int64_t ecap, aercap;
4029
4030 /* XXX Handle errors ? */
4031
4032 /* Init_45..46:
4033 *
4034 * Set primary bus to 0, secondary to 1 and subordinate to 0xff
4035 */
4036 phb3_pcicfg_write32(&p->phb, 0, PCI_CFG_PRIMARY_BUS, 0x00ff0100);
4037
4038 /* Init_47..52
4039 *
4040 * IO and Memory base & limits are set to base > limit, which
4041 * allows all inbounds.
4042 *
4043 * XXX This has the potential of confusing the OS which might
4044 * think that nothing is forwarded downstream. We probably need
4045 * to fix this to match the IO and M32 PHB windows
4046 */
4047 phb3_pcicfg_write16(&p->phb, 0, PCI_CFG_IO_BASE, 0x0010);
4048 phb3_pcicfg_write32(&p->phb, 0, PCI_CFG_MEM_BASE, 0x00000010);
4049 phb3_pcicfg_write32(&p->phb, 0, PCI_CFG_PREF_MEM_BASE, 0x00000010);
4050
4051 /* Init_53..54 - Setup bridge control enable forwarding of CORR, FATAL,
4052 * and NONFATAL errors
4053 */
4054 phb3_pcicfg_write16(&p->phb, 0, PCI_CFG_BRCTL, PCI_CFG_BRCTL_SERR_EN);
4055
4056 /* Init_55..56
4057 *
4058 * PCIE Device control/status, enable error reporting, disable relaxed
4059 * ordering, set MPS to 128 (see note), clear errors.
4060 *
4061 * Note: The doc recommends to set MPS to 4K. This has proved to have
4062 * some issues as it requires specific claming of MRSS on devices and
4063 * we've found devices in the field that misbehave when doing that.
4064 *
4065 * We currently leave it all to 128 bytes (minimum setting) at init
4066 * time. The generic PCIe probing later on might apply a different
4067 * value, or the kernel will, but we play it safe at early init
4068 */
4069 if (p->ecap <= 0) {
4070 ecap = pci_find_cap(&p->phb, 0, PCI_CFG_CAP_ID_EXP);
4071 if (ecap < 0) {
4072 PHBERR(p, "Can't locate PCI-E capability\n");
4073 return false;
4074 }
4075 p->ecap = ecap;
4076 } else {
4077 ecap = p->ecap;
4078 }
4079
4080 phb3_pcicfg_write16(&p->phb, 0, ecap + PCICAP_EXP_DEVSTAT,
4081 PCICAP_EXP_DEVSTAT_CE |
4082 PCICAP_EXP_DEVSTAT_NFE |
4083 PCICAP_EXP_DEVSTAT_FE |
4084 PCICAP_EXP_DEVSTAT_UE);
4085
4086 phb3_pcicfg_write16(&p->phb, 0, ecap + PCICAP_EXP_DEVCTL,
4087 PCICAP_EXP_DEVCTL_CE_REPORT |
4088 PCICAP_EXP_DEVCTL_NFE_REPORT |
4089 PCICAP_EXP_DEVCTL_FE_REPORT |
4090 PCICAP_EXP_DEVCTL_UR_REPORT |
4091 SETFIELD(PCICAP_EXP_DEVCTL_MPS, 0, PCIE_MPS_128B));
4092
4093 /* Init_57..58
4094 *
4095 * Root Control Register. Enable error reporting
4096 *
4097 * Note: Added CRS visibility.
4098 */
4099 phb3_pcicfg_write16(&p->phb, 0, ecap + PCICAP_EXP_RC,
4100 PCICAP_EXP_RC_SYSERR_ON_CE |
4101 PCICAP_EXP_RC_SYSERR_ON_NFE |
4102 PCICAP_EXP_RC_SYSERR_ON_FE |
4103 PCICAP_EXP_RC_CRS_VISIBLE);
4104
4105 /* Init_59..60
4106 *
4107 * Device Control 2. Enable ARI fwd, set timer to RTOS timer
4108 */
4109 phb3_pcicfg_write16(&p->phb, 0, ecap + PCICAP_EXP_DCTL2,
4110 SETFIELD(PCICAP_EXP_DCTL2_CMPTOUT, 0, 0xf) |
4111 PCICAP_EXP_DCTL2_ARI_FWD);
4112
4113 /* Init_61..76
4114 *
4115 * AER inits
4116 */
4117 if (p->aercap <= 0) {
4118 aercap = pci_find_ecap(&p->phb, 0, PCIECAP_ID_AER, NULL);
4119 if (aercap < 0) {
4120 PHBERR(p, "Can't locate AER capability\n");
4121 return false;
4122 }
4123 p->aercap = aercap;
4124 } else {
4125 aercap = p->aercap;
4126 }
4127
4128 /* Clear all UE status */
4129 phb3_pcicfg_write32(&p->phb, 0, aercap + PCIECAP_AER_UE_STATUS,
4130 0xffffffff);
4131 /* Disable some error reporting as per the PHB3 spec */
4132 phb3_pcicfg_write32(&p->phb, 0, aercap + PCIECAP_AER_UE_MASK,
4133 PCIECAP_AER_UE_POISON_TLP |
4134 PCIECAP_AER_UE_COMPL_TIMEOUT |
4135 PCIECAP_AER_UE_COMPL_ABORT |
4136 PCIECAP_AER_UE_ECRC);
4137 /* Report some errors as fatal */
4138 phb3_pcicfg_write32(&p->phb, 0, aercap + PCIECAP_AER_UE_SEVERITY,
4139 PCIECAP_AER_UE_DLP |
4140 PCIECAP_AER_UE_SURPRISE_DOWN |
4141 PCIECAP_AER_UE_FLOW_CTL_PROT |
4142 PCIECAP_AER_UE_UNEXP_COMPL |
4143 PCIECAP_AER_UE_RECV_OVFLOW |
4144 PCIECAP_AER_UE_MALFORMED_TLP);
4145 /* Clear all CE status */
4146 phb3_pcicfg_write32(&p->phb, 0, aercap + PCIECAP_AER_CE_STATUS,
4147 0xffffffff);
4148 /* Disable some error reporting as per the PHB3 spec */
4149 /* Note: When link down, also disable rcvr errors */
4150 phb3_pcicfg_write32(&p->phb, 0, aercap + PCIECAP_AER_CE_MASK,
4151 PCIECAP_AER_CE_ADV_NONFATAL |
4152 (p->has_link ? 0 : PCIECAP_AER_CE_RECVR_ERR));
4153
4154 /* Enable or disable ECRC generation & checking */
4155 phb3_enable_ecrc(&p->phb, !p->no_ecrc_devs);
4156
4157 /* Enable reporting in root error control */
4158 phb3_pcicfg_write32(&p->phb, 0, aercap + PCIECAP_AER_RERR_CMD,
4159 PCIECAP_AER_RERR_CMD_FE |
4160 PCIECAP_AER_RERR_CMD_NFE |
4161 PCIECAP_AER_RERR_CMD_CE);
4162 /* Clear root error status */
4163 phb3_pcicfg_write32(&p->phb, 0, aercap + PCIECAP_AER_RERR_STA,
4164 0xffffffff);
4165
4166 return true;
4167 }
4168
phb3_init_utl(struct phb3 * p)4169 static void phb3_init_utl(struct phb3 *p)
4170 {
4171 /* Init_77..79: Clear spurrious errors and assign errors to the
4172 * right "interrupt" signal
4173 */
4174 out_be64(p->regs + UTL_SYS_BUS_AGENT_STATUS, 0xffffffffffffffffUL);
4175 out_be64(p->regs + UTL_SYS_BUS_AGENT_ERR_SEVERITY, 0x5000000000000000UL);
4176 out_be64(p->regs + UTL_SYS_BUS_AGENT_IRQ_EN, 0xfcc0000000000000UL);
4177
4178 /* Init_80..81: Setup tag allocations
4179 *
4180 * Stick to HW defaults. May differs between PHB implementations
4181 */
4182
4183 /* Init_82: PCI Express port control
4184 * SW283991: Set Outbound Non-Posted request timeout to 16ms (RTOS).
4185 */
4186 out_be64(p->regs + UTL_PCIE_PORT_CONTROL, 0x8588007000000000UL);
4187
4188 /* Init_83..85: Clean & setup port errors */
4189 out_be64(p->regs + UTL_PCIE_PORT_STATUS, 0xffdfffffffffffffUL);
4190 out_be64(p->regs + UTL_PCIE_PORT_ERROR_SEV, 0x5039000000000000UL);
4191
4192 if (p->has_link)
4193 out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0xad52800000000000UL);
4194 else
4195 out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0xad42800000000000UL);
4196
4197 /* Init_86 : Cleanup RC errors */
4198 out_be64(p->regs + UTL_RC_STATUS, 0xffffffffffffffffUL);
4199 }
4200
phb3_init_errors(struct phb3 * p)4201 static void phb3_init_errors(struct phb3 *p)
4202 {
4203 /* Init_88: LEM Error Mask : Temporarily disable error interrupts */
4204 out_be64(p->regs + PHB_LEM_ERROR_MASK, 0xffffffffffffffffUL);
4205
4206 /* Init_89..97: Disable all error interrupts until end of init */
4207 out_be64(p->regs + PHB_ERR_STATUS, 0xffffffffffffffffUL);
4208 out_be64(p->regs + PHB_ERR1_STATUS, 0x0000000000000000UL);
4209 out_be64(p->regs + PHB_ERR_LEM_ENABLE, 0xffffffffffffffffUL);
4210 out_be64(p->regs + PHB_ERR_FREEZE_ENABLE, 0x0000000080800000UL);
4211 out_be64(p->regs + PHB_ERR_AIB_FENCE_ENABLE, 0xffffffdd0c00ffc0UL);
4212 out_be64(p->regs + PHB_ERR_LOG_0, 0x0000000000000000UL);
4213 out_be64(p->regs + PHB_ERR_LOG_1, 0x0000000000000000UL);
4214 out_be64(p->regs + PHB_ERR_STATUS_MASK, 0x0000000000000000UL);
4215 out_be64(p->regs + PHB_ERR1_STATUS_MASK, 0x0000000000000000UL);
4216
4217 /* Init_98_106: Configure MMIO error traps & clear old state
4218 *
4219 * Don't enable BAR multi-hit detection in bit 41.
4220 */
4221 out_be64(p->regs + PHB_OUT_ERR_STATUS, 0xffffffffffffffffUL);
4222 out_be64(p->regs + PHB_OUT_ERR1_STATUS, 0x0000000000000000UL);
4223 out_be64(p->regs + PHB_OUT_ERR_LEM_ENABLE, 0xfdffffffffbfffffUL);
4224 out_be64(p->regs + PHB_OUT_ERR_FREEZE_ENABLE, 0x0000420800000000UL);
4225 out_be64(p->regs + PHB_OUT_ERR_AIB_FENCE_ENABLE, 0x9cf3bc00f89c700fUL);
4226 out_be64(p->regs + PHB_OUT_ERR_LOG_0, 0x0000000000000000UL);
4227 out_be64(p->regs + PHB_OUT_ERR_LOG_1, 0x0000000000000000UL);
4228 out_be64(p->regs + PHB_OUT_ERR_STATUS_MASK, 0x0000000000400000UL);
4229 out_be64(p->regs + PHB_OUT_ERR1_STATUS_MASK, 0x0000000000400000UL);
4230
4231 /* Init_107_115: Configure DMA_A error traps & clear old state */
4232 out_be64(p->regs + PHB_INA_ERR_STATUS, 0xffffffffffffffffUL);
4233 out_be64(p->regs + PHB_INA_ERR1_STATUS, 0x0000000000000000UL);
4234 out_be64(p->regs + PHB_INA_ERR_LEM_ENABLE, 0xffffffffffffffffUL);
4235 out_be64(p->regs + PHB_INA_ERR_FREEZE_ENABLE, 0xc00003a901006000UL);
4236 out_be64(p->regs + PHB_INA_ERR_AIB_FENCE_ENABLE, 0x3fff5452fe019fdeUL);
4237 out_be64(p->regs + PHB_INA_ERR_LOG_0, 0x0000000000000000UL);
4238 out_be64(p->regs + PHB_INA_ERR_LOG_1, 0x0000000000000000UL);
4239 out_be64(p->regs + PHB_INA_ERR_STATUS_MASK, 0x0000000000000000UL);
4240 out_be64(p->regs + PHB_INA_ERR1_STATUS_MASK, 0x0000000000000000UL);
4241
4242 /* Init_116_124: Configure DMA_B error traps & clear old state */
4243 out_be64(p->regs + PHB_INB_ERR_STATUS, 0xffffffffffffffffUL);
4244 out_be64(p->regs + PHB_INB_ERR1_STATUS, 0x0000000000000000UL);
4245 out_be64(p->regs + PHB_INB_ERR_LEM_ENABLE, 0xffffffffffffffffUL);
4246
4247 /*
4248 * Workaround for errata HW257476, turn correctable messages into
4249 * ER freezes on Murano and Venice DD1.0
4250 */
4251 if (p->rev < PHB3_REV_MURANO_DD20)
4252 out_be64(p->regs + PHB_INB_ERR_FREEZE_ENABLE,
4253 0x0000600000000070UL);
4254 else
4255 out_be64(p->regs + PHB_INB_ERR_FREEZE_ENABLE,
4256 0x0000600000000060UL);
4257
4258 out_be64(p->regs + PHB_INB_ERR_AIB_FENCE_ENABLE, 0xfcff80fbff7ff08cUL);
4259 out_be64(p->regs + PHB_INB_ERR_LOG_0, 0x0000000000000000UL);
4260 out_be64(p->regs + PHB_INB_ERR_LOG_1, 0x0000000000000000UL);
4261 out_be64(p->regs + PHB_INB_ERR_STATUS_MASK, 0x0000000000000000UL);
4262 out_be64(p->regs + PHB_INB_ERR1_STATUS_MASK, 0x0000000000000000UL);
4263
4264 /* Init_125..128: Cleanup & configure LEM */
4265 out_be64(p->regs + PHB_LEM_FIR_ACCUM, 0x0000000000000000UL);
4266 out_be64(p->regs + PHB_LEM_ACTION0, 0xffffffffffffffffUL);
4267 out_be64(p->regs + PHB_LEM_ACTION1, 0xffffffffffffffffUL);
4268 out_be64(p->regs + PHB_LEM_WOF, 0x0000000000000000UL);
4269 }
4270
phb3_fixup_pec_inits(struct phb3 * p)4271 static int64_t phb3_fixup_pec_inits(struct phb3 *p)
4272 {
4273 int64_t rc;
4274 uint64_t val;
4275
4276 /* These fixups handle some timer updates that HB doesn't yet do
4277 * to work around problems with some adapters or external drawers
4278 * (SW283991)
4279 */
4280
4281 /* PCI Hardware Configuration 0 Register */
4282 rc = xscom_read(p->chip_id, p->pe_xscom + 0x18, &val);
4283 if (rc) {
4284 PHBERR(p, "Can't read CS0 !\n");
4285 return rc;
4286 }
4287 val = val & 0x0f0fffffffffffffull;
4288 val = val | 0x1010000000000000ull;
4289 rc = xscom_write(p->chip_id, p->pe_xscom + 0x18, val);
4290 if (rc) {
4291 PHBERR(p, "Can't write CS0 !\n");
4292 return rc;
4293 }
4294 return 0;
4295 }
4296
phb3_init_hw(struct phb3 * p,bool first_init)4297 static void phb3_init_hw(struct phb3 *p, bool first_init)
4298 {
4299 uint64_t val;
4300
4301 PHBDBG(p, "Initializing PHB...\n");
4302
4303 /* Fixups for PEC inits */
4304 if (phb3_fixup_pec_inits(p)) {
4305 PHBERR(p, "Failed to init PEC, PHB appears broken\n");
4306 goto failed;
4307 }
4308
4309 /* Lift reset */
4310 xscom_read(p->chip_id, p->spci_xscom + 1, &val);/* HW275117 */
4311 xscom_write(p->chip_id, p->pci_xscom + 0xa, 0);
4312
4313 /* XXX FIXME, turn that into a state machine or a worker thread */
4314 time_wait_ms(100);
4315
4316 /* Grab version and fit it in an int */
4317 val = phb3_read_reg_asb(p, PHB_VERSION);
4318 if (val == 0 || val == 0xffffffffffffffffUL) {
4319 PHBERR(p, "Failed to read version, PHB appears broken\n");
4320 goto failed;
4321 }
4322
4323 p->rev = ((val >> 16) & 0x00ff0000) | (val & 0xffff);
4324 PHBDBG(p, "Core revision 0x%x\n", p->rev);
4325
4326 /* Setup AIB credits etc... */
4327 phb3_setup_aib(p);
4328
4329 /* Init_8 - PCIE System Configuration Register
4330 *
4331 * Use default values, clear bit 15 (SYS_EC00_SLOT) to avoid incorrect
4332 * slot power limit message and adjust max speed based on system
4333 * config. Don't hard wire default value as some bits are different
4334 * between implementations.
4335 */
4336 val = in_be64(p->regs + PHB_PCIE_SYSTEM_CONFIG);
4337 PHBDBG(p, "Default system config: 0x%016llx\n", val);
4338 val = SETFIELD(PHB_PCIE_SCONF_SLOT, val, 0);
4339 val = SETFIELD(PHB_PCIE_SCONF_MAXLINKSPEED, val, p->max_link_speed);
4340 out_be64(p->regs + PHB_PCIE_SYSTEM_CONFIG, val);
4341 PHBDBG(p, "New system config : 0x%016llx\n",
4342 in_be64(p->regs + PHB_PCIE_SYSTEM_CONFIG));
4343
4344 /* Init_9..12 - PCIE DLP Lane EQ control */
4345 if (p->lane_eq) {
4346 out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL0,
4347 be64_to_cpu(p->lane_eq[0]));
4348 out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL1,
4349 be64_to_cpu(p->lane_eq[1]));
4350 out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL2,
4351 be64_to_cpu(p->lane_eq[2]));
4352 out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL3,
4353 be64_to_cpu(p->lane_eq[3]));
4354 }
4355
4356 /* Init_XX - (PHB2 errata)
4357 *
4358 * Set proper credits, needs adjustment due to wrong defaults
4359 * on PHB2 before we lift the reset. This only applies to Murano
4360 * and Venice
4361 */
4362 if (p->index == 2 && p->rev < PHB3_REV_NAPLES_DD10)
4363 out_be64(p->regs + PHB_PCIE_SYS_LINK_INIT, 0x9008133332120000UL);
4364
4365 /* Init_13 - PCIE Reset */
4366 /*
4367 * Lift the PHB resets but not PERST, this will be lifted
4368 * later by the initial PERST state machine
4369 */
4370 PHBDBG(p, "PHB_RESET is 0x%016llx\n", in_be64(p->regs + PHB_RESET));
4371 out_be64(p->regs + PHB_RESET, 0xd000000000000000UL);
4372
4373 /* Architected IODA2 inits */
4374 phb3_init_ioda2(p);
4375
4376 /* Init_37..42 - Clear UTL & DLP error logs */
4377 out_be64(p->regs + PHB_PCIE_UTL_ERRLOG1, 0xffffffffffffffffUL);
4378 out_be64(p->regs + PHB_PCIE_UTL_ERRLOG2, 0xffffffffffffffffUL);
4379 out_be64(p->regs + PHB_PCIE_UTL_ERRLOG3, 0xffffffffffffffffUL);
4380 out_be64(p->regs + PHB_PCIE_UTL_ERRLOG4, 0xffffffffffffffffUL);
4381 out_be64(p->regs + PHB_PCIE_DLP_ERRLOG1, 0xffffffffffffffffUL);
4382 out_be64(p->regs + PHB_PCIE_DLP_ERRLOG2, 0xffffffffffffffffUL);
4383
4384 /* Init_43 - Wait for UTL core to come out of reset */
4385 if (!phb3_wait_dlp_reset(p))
4386 goto failed;
4387
4388 /* Init_44 - Clear port status */
4389 out_be64(p->regs + UTL_PCIE_PORT_STATUS, 0xffffffffffffffffUL);
4390
4391 /* Init_45..76: Init root complex config space */
4392 if (!phb3_init_rc_cfg(p))
4393 goto failed;
4394
4395 /* Init_77..86 : Init UTL */
4396 phb3_init_utl(p);
4397
4398 /*
4399 * Init_87: PHB Control register. Various PHB settings
4400 * Enable IVC for Murano DD2.0 or later one
4401 */
4402 #ifdef IVT_TABLE_IVE_16B
4403 val = 0xf3a80e4b00000000UL;
4404 #else
4405 val = 0xf3a80ecb00000000UL;
4406 #endif
4407 if (p->rev >= PHB3_REV_MURANO_DD20)
4408 val |= 0x0000010000000000UL;
4409 if (first_init && p->rev >= PHB3_REV_NAPLES_DD10) {
4410 /* Enable 32-bit bypass support on Naples and tell the OS
4411 * about it
4412 */
4413 val |= 0x0010000000000000UL;
4414 dt_add_property(p->phb.dt_node,
4415 "ibm,32-bit-bypass-supported", NULL, 0);
4416 }
4417 out_be64(p->regs + PHB_CONTROL, val);
4418
4419 /* Init_88..128 : Setup error registers */
4420 phb3_init_errors(p);
4421
4422 /* Init_129: Read error summary */
4423 val = in_be64(p->regs + PHB_ETU_ERR_SUMMARY);
4424 if (val) {
4425 PHBERR(p, "Errors detected during PHB init: 0x%16llx\n", val);
4426 goto failed;
4427 }
4428
4429 /* NOTE: At this point the spec waits for the link to come up. We
4430 * don't bother as we are doing a PERST soon.
4431 */
4432
4433 /* XXX I don't know why the spec does this now and not earlier, so
4434 * to be sure to get it right we might want to move it to the freset
4435 * state machine, though the generic PCI layer will probably do
4436 * this anyway (ie, enable MEM, etc... in the RC)
4437 *
4438 * Note:The spec enables IO but PHB3 doesn't do IO space .... so we
4439 * leave that clear.
4440 */
4441 phb3_pcicfg_write16(&p->phb, 0, PCI_CFG_CMD,
4442 PCI_CFG_CMD_MEM_EN |
4443 PCI_CFG_CMD_BUS_MASTER_EN |
4444 PCI_CFG_CMD_PERR_RESP |
4445 PCI_CFG_CMD_SERR_EN);
4446
4447 /* Clear errors */
4448 phb3_pcicfg_write16(&p->phb, 0, PCI_CFG_STAT,
4449 PCI_CFG_STAT_SENT_TABORT |
4450 PCI_CFG_STAT_RECV_TABORT |
4451 PCI_CFG_STAT_RECV_MABORT |
4452 PCI_CFG_STAT_SENT_SERR |
4453 PCI_CFG_STAT_RECV_PERR);
4454
4455 /* Init_136 - Re-enable error interrupts */
4456
4457 /* TBD: Should we mask any of these for PERST ? */
4458 out_be64(p->regs + PHB_ERR_IRQ_ENABLE, 0x0000002280b80000UL);
4459 out_be64(p->regs + PHB_OUT_ERR_IRQ_ENABLE, 0x600c42fc042080f0UL);
4460 out_be64(p->regs + PHB_INA_ERR_IRQ_ENABLE, 0xc000a3a901826020UL);
4461 out_be64(p->regs + PHB_INB_ERR_IRQ_ENABLE, 0x0000600000800070UL);
4462 out_be64(p->regs + PHB_LEM_ERROR_MASK, 0x42498e367f502eaeUL);
4463
4464 /*
4465 * Init_141 - Enable DMA address speculation
4466 *
4467 * Errata#20131017: Disable speculation until Murano DD2.0
4468 *
4469 * Note: We keep IVT speculation disabled (bit 4). It should work with
4470 * Murano DD2.0 and later but lacks sufficient testing. We will re-enable
4471 * it once that has been done.
4472 */
4473 if (p->rev >= PHB3_REV_MURANO_DD20)
4474 out_be64(p->regs + PHB_TCE_SPEC_CTL, 0xf000000000000000UL);
4475 else
4476 out_be64(p->regs + PHB_TCE_SPEC_CTL, 0x0ul);
4477
4478 /* Errata#20131017: avoid TCE queue overflow */
4479 if (p->rev == PHB3_REV_MURANO_DD20)
4480 phb3_write_reg_asb(p, PHB_TCE_WATERMARK, 0x0003000000030302UL);
4481
4482 /* Init_142 - PHB3 - Timeout Control Register 1
4483 * SW283991: Increase timeouts
4484 */
4485 out_be64(p->regs + PHB_TIMEOUT_CTRL1, 0x1715152016200000UL);
4486
4487 /* Init_143 - PHB3 - Timeout Control Register 2 */
4488 out_be64(p->regs + PHB_TIMEOUT_CTRL2, 0x2320d71600000000UL);
4489
4490 /* Mark the PHB as functional which enables all the various sequences */
4491 p->broken = false;
4492
4493 PHBDBG(p, "Initialization complete\n");
4494
4495 return;
4496
4497 failed:
4498 PHBERR(p, "Initialization failed\n");
4499 p->broken = true;
4500 }
4501
phb3_allocate_tables(struct phb3 * p)4502 static void phb3_allocate_tables(struct phb3 *p)
4503 {
4504 uint16_t *rte;
4505 uint32_t i;
4506
4507 /* XXX Our current memalign implementation sucks,
4508 *
4509 * It will do the job, however it doesn't support freeing
4510 * the memory and wastes space by always allocating twice
4511 * as much as requested (size + alignment)
4512 */
4513 p->tbl_rtt = (uint64_t)local_alloc(p->chip_id, RTT_TABLE_SIZE, RTT_TABLE_SIZE);
4514 assert(p->tbl_rtt);
4515 rte = (uint16_t *)(p->tbl_rtt);
4516 for (i = 0; i < RTT_TABLE_ENTRIES; i++, rte++)
4517 *rte = PHB3_RESERVED_PE_NUM;
4518
4519 p->tbl_peltv = (uint64_t)local_alloc(p->chip_id, PELTV_TABLE_SIZE, PELTV_TABLE_SIZE);
4520 assert(p->tbl_peltv);
4521 memset((void *)p->tbl_peltv, 0, PELTV_TABLE_SIZE);
4522
4523 p->tbl_pest = (uint64_t)local_alloc(p->chip_id, PEST_TABLE_SIZE, PEST_TABLE_SIZE);
4524 assert(p->tbl_pest);
4525 memset((void *)p->tbl_pest, 0, PEST_TABLE_SIZE);
4526
4527 p->tbl_ivt = (uint64_t)local_alloc(p->chip_id, IVT_TABLE_SIZE, IVT_TABLE_SIZE);
4528 assert(p->tbl_ivt);
4529 memset((void *)p->tbl_ivt, 0, IVT_TABLE_SIZE);
4530
4531 p->tbl_rba = (uint64_t)local_alloc(p->chip_id, RBA_TABLE_SIZE, RBA_TABLE_SIZE);
4532 assert(p->tbl_rba);
4533 memset((void *)p->tbl_rba, 0, RBA_TABLE_SIZE);
4534 }
4535
phb3_add_properties(struct phb3 * p)4536 static void phb3_add_properties(struct phb3 *p)
4537 {
4538 struct dt_node *np = p->phb.dt_node;
4539 uint32_t lsibase, icsp = get_ics_phandle();
4540 uint64_t m32b, m64b, m64s, reg, tkill;
4541
4542 reg = cleanup_addr((uint64_t)p->regs);
4543
4544 /* Add various properties that HB doesn't have to
4545 * add, some of them simply because they result from
4546 * policy decisions made in skiboot rather than in HB
4547 * such as the MMIO windows going to PCI, interrupts,
4548 * etc...
4549 */
4550 dt_add_property_cells(np, "#address-cells", 3);
4551 dt_add_property_cells(np, "#size-cells", 2);
4552 dt_add_property_cells(np, "#interrupt-cells", 1);
4553 dt_add_property_cells(np, "bus-range", 0, 0xff);
4554 dt_add_property_cells(np, "clock-frequency", 0x200, 0); /* ??? */
4555
4556 dt_add_property_cells(np, "interrupt-parent", icsp);
4557
4558 /* XXX FIXME: add slot-name */
4559 //dt_property_cell("bus-width", 8); /* Figure it out from VPD ? */
4560
4561 /* "ranges", we only expose M32 (PHB3 doesn't do IO)
4562 *
4563 * Note: The kernel expects us to have chopped of 64k from the
4564 * M32 size (for the 32-bit MSIs). If we don't do that, it will
4565 * get confused (OPAL does it)
4566 */
4567 m32b = cleanup_addr(p->mm1_base);
4568 m64b = cleanup_addr(p->mm0_base);
4569 m64s = p->mm0_size;
4570 dt_add_property_cells(np, "ranges",
4571 /* M32 space */
4572 0x02000000, 0x00000000, M32_PCI_START,
4573 hi32(m32b), lo32(m32b), 0, M32_PCI_SIZE - 0x10000);
4574
4575 /* XXX FIXME: add opal-memwin32, dmawins, etc... */
4576 dt_add_property_u64s(np, "ibm,opal-m64-window", m64b, m64b, m64s);
4577 dt_add_property(np, "ibm,opal-single-pe", NULL, 0);
4578 //dt_add_property_cells(np, "ibm,opal-msi-ports", 2048);
4579 dt_add_property_cells(np, "ibm,opal-num-pes", 256);
4580 dt_add_property_cells(np, "ibm,opal-reserved-pe",
4581 PHB3_RESERVED_PE_NUM);
4582 dt_add_property_cells(np, "ibm,opal-msi-ranges",
4583 p->base_msi, PHB3_MSI_IRQ_COUNT);
4584 tkill = reg + PHB_TCE_KILL;
4585 dt_add_property_cells(np, "ibm,opal-tce-kill",
4586 hi32(tkill), lo32(tkill));
4587 dt_add_property_cells(np, "ibm,supported-tce-sizes",
4588 12, // 4K
4589 16, // 64K
4590 24, // 16M
4591 28); // 256M
4592
4593 /*
4594 * Indicate to Linux that the architected IODA2 MSI EOI method
4595 * is supported
4596 */
4597 dt_add_property_string(np, "ibm,msi-eoi-method", "ioda2");
4598
4599 /* Indicate to Linux that CAPP timebase sync is supported */
4600 dt_add_property_string(np, "ibm,capp-timebase-sync", NULL);
4601
4602 /* The interrupt maps will be generated in the RC node by the
4603 * PCI code based on the content of this structure:
4604 */
4605 lsibase = p->base_lsi;
4606 p->phb.lstate.int_size = 2;
4607 p->phb.lstate.int_val[0][0] = lsibase + PHB3_LSI_PCIE_INTA;
4608 p->phb.lstate.int_val[0][1] = 1;
4609 p->phb.lstate.int_val[1][0] = lsibase + PHB3_LSI_PCIE_INTB;
4610 p->phb.lstate.int_val[1][1] = 1;
4611 p->phb.lstate.int_val[2][0] = lsibase + PHB3_LSI_PCIE_INTC;
4612 p->phb.lstate.int_val[2][1] = 1;
4613 p->phb.lstate.int_val[3][0] = lsibase + PHB3_LSI_PCIE_INTD;
4614 p->phb.lstate.int_val[3][1] = 1;
4615 p->phb.lstate.int_parent[0] = icsp;
4616 p->phb.lstate.int_parent[1] = icsp;
4617 p->phb.lstate.int_parent[2] = icsp;
4618 p->phb.lstate.int_parent[3] = icsp;
4619
4620 /* Indicators for variable tables */
4621 dt_add_property_cells(np, "ibm,opal-rtt-table",
4622 hi32(p->tbl_rtt), lo32(p->tbl_rtt), RTT_TABLE_SIZE);
4623 dt_add_property_cells(np, "ibm,opal-peltv-table",
4624 hi32(p->tbl_peltv), lo32(p->tbl_peltv), PELTV_TABLE_SIZE);
4625 dt_add_property_cells(np, "ibm,opal-pest-table",
4626 hi32(p->tbl_pest), lo32(p->tbl_pest), PEST_TABLE_SIZE);
4627 dt_add_property_cells(np, "ibm,opal-ivt-table",
4628 hi32(p->tbl_ivt), lo32(p->tbl_ivt), IVT_TABLE_SIZE);
4629 dt_add_property_cells(np, "ibm,opal-ive-stride",
4630 IVT_TABLE_STRIDE);
4631 dt_add_property_cells(np, "ibm,opal-rba-table",
4632 hi32(p->tbl_rba), lo32(p->tbl_rba), RBA_TABLE_SIZE);
4633
4634 dt_add_property_cells(np, "ibm,phb-diag-data-size",
4635 sizeof(struct OpalIoPhb3ErrorData));
4636 }
4637
phb3_calculate_windows(struct phb3 * p)4638 static bool phb3_calculate_windows(struct phb3 *p)
4639 {
4640 const struct dt_property *prop;
4641
4642 /* Get PBCQ MMIO windows from device-tree */
4643 prop = dt_require_property(p->phb.dt_node,
4644 "ibm,mmio-window", -1);
4645 assert(prop->len >= (2 * sizeof(uint64_t)));
4646
4647 p->mm0_base = ((const uint64_t *)prop->prop)[0];
4648 p->mm0_size = ((const uint64_t *)prop->prop)[1];
4649 if (prop->len > 16) {
4650 p->mm1_base = ((const uint64_t *)prop->prop)[2];
4651 p->mm1_size = ((const uint64_t *)prop->prop)[3];
4652 }
4653
4654 /* Sort them so that 0 is big and 1 is small */
4655 if (p->mm1_size && p->mm1_size > p->mm0_size) {
4656 uint64_t b = p->mm0_base;
4657 uint64_t s = p->mm0_size;
4658 p->mm0_base = p->mm1_base;
4659 p->mm0_size = p->mm1_size;
4660 p->mm1_base = b;
4661 p->mm1_size = s;
4662 }
4663
4664 /* If 1 is too small, ditch it */
4665 if (p->mm1_size < M32_PCI_SIZE)
4666 p->mm1_size = 0;
4667
4668 /* If 1 doesn't exist, carve it out of 0 */
4669 if (p->mm1_size == 0) {
4670 p->mm0_size /= 2;
4671 p->mm1_base = p->mm0_base + p->mm0_size;
4672 p->mm1_size = p->mm0_size;
4673 }
4674
4675 /* Crop mm1 to our desired size */
4676 if (p->mm1_size > M32_PCI_SIZE)
4677 p->mm1_size = M32_PCI_SIZE;
4678
4679 return true;
4680 }
4681
4682 /*
4683 * Trigger a creset to disable CAPI mode on kernel shutdown.
4684 *
4685 * This helper is called repeatedly by the host sync notifier mechanism, which
4686 * relies on the kernel to regularly poll the OPAL_SYNC_HOST_REBOOT call as it
4687 * shuts down.
4688 *
4689 * This is a somewhat hacky abuse of the host sync notifier mechanism, but the
4690 * alternatives require a new API call which won't work for older kernels.
4691 */
phb3_host_sync_reset(void * data)4692 static bool phb3_host_sync_reset(void *data)
4693 {
4694 struct phb3 *p = (struct phb3 *)data;
4695 struct pci_slot *slot = p->phb.slot;
4696 struct proc_chip *chip = get_chip(p->chip_id);
4697 int64_t rc;
4698
4699 switch (slot->state) {
4700 case PHB3_SLOT_NORMAL:
4701 lock(&capi_lock);
4702 rc = (chip->capp_phb3_attached_mask & (1 << p->index)) ?
4703 OPAL_PHB_CAPI_MODE_CAPI :
4704 OPAL_PHB_CAPI_MODE_PCIE;
4705 unlock(&capi_lock);
4706
4707 if (rc == OPAL_PHB_CAPI_MODE_PCIE)
4708 return true;
4709
4710 PHBINF(p, "PHB in CAPI mode, resetting\n");
4711 p->flags &= ~PHB3_CAPP_RECOVERY;
4712 phb3_creset(slot);
4713 return false;
4714 default:
4715 rc = slot->ops.run_sm(slot);
4716 return rc <= OPAL_SUCCESS;
4717 }
4718 }
4719
phb3_create(struct dt_node * np)4720 static void phb3_create(struct dt_node *np)
4721 {
4722 const struct dt_property *prop;
4723 struct phb3 *p = zalloc(sizeof(struct phb3));
4724 struct pci_slot *slot;
4725 size_t lane_eq_len;
4726 struct dt_node *iplp;
4727 struct proc_chip *chip;
4728 int opal_id;
4729 char *path;
4730
4731 assert(p);
4732
4733 /* Populate base stuff */
4734 p->index = dt_prop_get_u32(np, "ibm,phb-index");
4735 p->chip_id = dt_prop_get_u32(np, "ibm,chip-id");
4736 p->regs = (void *)dt_get_address(np, 0, NULL);
4737 p->base_msi = PHB3_MSI_IRQ_BASE(p->chip_id, p->index);
4738 p->base_lsi = PHB3_LSI_IRQ_BASE(p->chip_id, p->index);
4739 p->phb.dt_node = np;
4740 p->phb.ops = &phb3_ops;
4741 p->phb.phb_type = phb_type_pcie_v3;
4742 p->phb.scan_map = 0x1; /* Only device 0 to scan */
4743
4744 if (!phb3_calculate_windows(p))
4745 return;
4746
4747 /* Get the various XSCOM register bases from the device-tree */
4748 prop = dt_require_property(np, "ibm,xscom-bases", 3 * sizeof(uint32_t));
4749 p->pe_xscom = ((const uint32_t *)prop->prop)[0];
4750 p->spci_xscom = ((const uint32_t *)prop->prop)[1];
4751 p->pci_xscom = ((const uint32_t *)prop->prop)[2];
4752
4753 /*
4754 * We skip the initial PERST assertion requested by the generic code
4755 * when doing a cold boot because we are coming out of cold boot already
4756 * so we save boot time that way. The PERST state machine will still
4757 * handle waiting for the link to come up, it will just avoid actually
4758 * asserting & deasserting the PERST output
4759 *
4760 * For a hot IPL, we still do a PERST
4761 *
4762 * Note: In absence of property (ie, FSP-less), we stick to the old
4763 * behaviour and set skip_perst to true
4764 */
4765 p->skip_perst = true; /* Default */
4766
4767 iplp = dt_find_by_path(dt_root, "ipl-params/ipl-params");
4768 if (iplp) {
4769 const char *ipl_type = dt_prop_get_def(iplp, "cec-major-type", NULL);
4770 if (ipl_type && (!strcmp(ipl_type, "hot")))
4771 p->skip_perst = false;
4772 }
4773
4774 /* By default link is assumed down */
4775 p->has_link = false;
4776
4777 /* We register the PHB before we initialize it so we
4778 * get a useful OPAL ID for it. We use a different numbering here
4779 * between Naples and Venice/Murano in order to leave room for the
4780 * NPU on Naples.
4781 */
4782 chip = next_chip(NULL); /* Just need any chip */
4783 if (chip && chip->type == PROC_CHIP_P8_NAPLES)
4784 opal_id = p->chip_id * 8 + p->index;
4785 else
4786 opal_id = p->chip_id * 4 + p->index;
4787 pci_register_phb(&p->phb, opal_id);
4788 slot = phb3_slot_create(&p->phb);
4789 if (!slot)
4790 PHBERR(p, "Cannot create PHB slot\n");
4791
4792 /* Hello ! */
4793 path = dt_get_path(np);
4794 PHBINF(p, "Found %s @[%d:%d]\n", path, p->chip_id, p->index);
4795 PHBINF(p, " M32 [0x%016llx..0x%016llx]\n",
4796 p->mm1_base, p->mm1_base + p->mm1_size - 1);
4797 PHBINF(p, " M64 [0x%016llx..0x%016llx]\n",
4798 p->mm0_base, p->mm0_base + p->mm0_size - 1);
4799 free(path);
4800
4801 /* Find base location code from root node */
4802 p->phb.base_loc_code = dt_prop_get_def(dt_root,
4803 "ibm,io-base-loc-code", NULL);
4804 if (!p->phb.base_loc_code)
4805 PHBDBG(p, "Base location code not found !\n");
4806
4807 /* Priority order: NVRAM -> dt -> GEN3 */
4808 p->max_link_speed = 3;
4809 if (dt_has_node_property(np, "ibm,max-link-speed", NULL))
4810 p->max_link_speed = dt_prop_get_u32(np, "ibm,max-link-speed");
4811 if (pcie_max_link_speed)
4812 p->max_link_speed = pcie_max_link_speed;
4813 if (p->max_link_speed > 3) /* clamp to 3 */
4814 p->max_link_speed = 3;
4815 PHBINF(p, "Max link speed: GEN%i\n", p->max_link_speed);
4816
4817 /* Check for lane equalization values from HB or HDAT */
4818 p->lane_eq = dt_prop_get_def_size(np, "ibm,lane-eq", NULL, &lane_eq_len);
4819 if (p->lane_eq && lane_eq_len != (8 * 4)) {
4820 PHBERR(p, "Device-tree has ibm,lane-eq with wrong len %ld\n",
4821 lane_eq_len);
4822 p->lane_eq = NULL;
4823 }
4824 if (p->lane_eq) {
4825 PHBDBG(p, "Override lane equalization settings:\n");
4826 PHBDBG(p, " 0x%016llx 0x%016llx\n",
4827 be64_to_cpu(p->lane_eq[0]), be64_to_cpu(p->lane_eq[1]));
4828 PHBDBG(p, " 0x%016llx 0x%016llx\n",
4829 be64_to_cpu(p->lane_eq[2]), be64_to_cpu(p->lane_eq[3]));
4830 }
4831
4832 /*
4833 * Grab CEC IO VPD load info from the root of the device-tree,
4834 * on P8 there's a single such VPD for the whole machine
4835 */
4836 prop = dt_find_property(dt_root, "ibm,io-vpd");
4837 if (!prop) {
4838 /* LX VPD Lid not already loaded */
4839 if (platform.vpd_iohub_load)
4840 platform.vpd_iohub_load(dt_root);
4841 }
4842
4843 /* Allocate the SkiBoot internal in-memory tables for the PHB */
4844 phb3_allocate_tables(p);
4845
4846 phb3_add_properties(p);
4847
4848 /* Clear IODA2 cache */
4849 phb3_init_ioda_cache(p);
4850
4851 /* Register interrupt sources */
4852 register_irq_source(&phb3_msi_irq_ops, p, p->base_msi,
4853 PHB3_MSI_IRQ_COUNT);
4854 register_irq_source(&phb3_lsi_irq_ops, p, p->base_lsi, 8);
4855
4856 /* Get the HW up and running */
4857 phb3_init_hw(p, true);
4858
4859 /* Load capp microcode into capp unit */
4860 load_capp_ucode(p);
4861
4862 opal_add_host_sync_notifier(phb3_host_sync_reset, p);
4863
4864 /* Platform additional setup */
4865 if (platform.pci_setup_phb)
4866 platform.pci_setup_phb(&p->phb, p->index);
4867 }
4868
phb3_probe_pbcq(struct dt_node * pbcq)4869 static void phb3_probe_pbcq(struct dt_node *pbcq)
4870 {
4871 uint32_t spci_xscom, pci_xscom, pe_xscom, gcid, pno;
4872 uint64_t val, phb_bar, bar_en;
4873 uint64_t mmio0_bar, mmio0_bmask, mmio0_sz;
4874 uint64_t mmio1_bar, mmio1_bmask, mmio1_sz;
4875 uint64_t reg[2];
4876 uint64_t mmio_win[4];
4877 unsigned int mmio_win_sz;
4878 struct dt_node *np;
4879 char *path;
4880 uint64_t capp_ucode_base;
4881 unsigned int max_link_speed;
4882
4883 gcid = dt_get_chip_id(pbcq);
4884 pno = dt_prop_get_u32(pbcq, "ibm,phb-index");
4885 path = dt_get_path(pbcq);
4886 prlog(PR_NOTICE, "Chip %d Found PBCQ%d at %s\n", gcid, pno, path);
4887 free(path);
4888
4889 pe_xscom = dt_get_address(pbcq, 0, NULL);
4890 pci_xscom = dt_get_address(pbcq, 1, NULL);
4891 spci_xscom = dt_get_address(pbcq, 2, NULL);
4892 prlog(PR_DEBUG, "PHB3[%x:%x]: X[PE]=0x%08x X[PCI]=0x%08x"
4893 " X[SPCI]=0x%08x\n",
4894 gcid, pno, pe_xscom, pci_xscom, spci_xscom);
4895
4896 /* Check if CAPP mode */
4897 if (xscom_read(gcid, spci_xscom + 0x03, &val)) {
4898 prerror("PHB3[%x:%x]: Cannot read AIB CAPP ENABLE\n",
4899 gcid, pno);
4900 return;
4901 }
4902 if (val >> 63) {
4903 prerror("PHB3[%x:%x]: Ignoring bridge in CAPP mode\n",
4904 gcid, pno);
4905 return;
4906 }
4907
4908 /* Get PE BARs, assume only 0 and 2 are used for now */
4909 xscom_read(gcid, pe_xscom + 0x42, &phb_bar);
4910 phb_bar >>= 14;
4911 prlog(PR_DEBUG, "PHB3[%x:%x] REGS = 0x%016llx [4k]\n",
4912 gcid, pno, phb_bar);
4913 if (phb_bar == 0) {
4914 prerror("PHB3[%x:%x]: No PHB BAR set !\n", gcid, pno);
4915 return;
4916 }
4917
4918 /* Dbl check PHB BAR */
4919 xscom_read(gcid, spci_xscom + 1, &val);/* HW275117 */
4920 xscom_read(gcid, pci_xscom + 0x0b, &val);
4921 val >>= 14;
4922 prlog(PR_DEBUG, "PHB3[%x:%x] PCIBAR = 0x%016llx\n", gcid, pno, val);
4923 if (phb_bar != val) {
4924 prerror("PHB3[%x:%x] PCIBAR invalid, fixing up...\n",
4925 gcid, pno);
4926 xscom_read(gcid, spci_xscom + 1, &val);/* HW275117 */
4927 xscom_write(gcid, pci_xscom + 0x0b, phb_bar << 14);
4928 }
4929
4930 /* Check MMIO BARs */
4931 xscom_read(gcid, pe_xscom + 0x40, &mmio0_bar);
4932 xscom_read(gcid, pe_xscom + 0x43, &mmio0_bmask);
4933 mmio0_bmask &= 0xffffffffc0000000ull;
4934 mmio0_sz = ((~mmio0_bmask) >> 14) + 1;
4935 mmio0_bar >>= 14;
4936 prlog(PR_DEBUG, "PHB3[%x:%x] MMIO0 = 0x%016llx [0x%016llx]\n",
4937 gcid, pno, mmio0_bar, mmio0_sz);
4938 xscom_read(gcid, pe_xscom + 0x41, &mmio1_bar);
4939 xscom_read(gcid, pe_xscom + 0x44, &mmio1_bmask);
4940 mmio1_bmask &= 0xffffffffc0000000ull;
4941 mmio1_sz = ((~mmio1_bmask) >> 14) + 1;
4942 mmio1_bar >>= 14;
4943 prlog(PR_DEBUG, "PHB3[%x:%x] MMIO1 = 0x%016llx [0x%016llx]\n",
4944 gcid, pno, mmio1_bar, mmio1_sz);
4945
4946 /* Check BAR enable
4947 *
4948 * XXX BAR aren't always enabled by HB, we'll make assumptions
4949 * that BARs are valid if they value is non-0
4950 */
4951 xscom_read(gcid, pe_xscom + 0x45, &bar_en);
4952 prlog(PR_DEBUG, "PHB3[%x:%x] BAREN = 0x%016llx\n",
4953 gcid, pno, bar_en);
4954
4955 /* Always enable PHB BAR */
4956 bar_en |= 0x2000000000000000ull;
4957
4958 /* Build MMIO windows list */
4959 mmio_win_sz = 0;
4960 if (mmio0_bar) {
4961 mmio_win[mmio_win_sz++] = mmio0_bar;
4962 mmio_win[mmio_win_sz++] = mmio0_sz;
4963 bar_en |= 0x8000000000000000ul;
4964 }
4965 if (mmio1_bar) {
4966 mmio_win[mmio_win_sz++] = mmio1_bar;
4967 mmio_win[mmio_win_sz++] = mmio1_sz;
4968 bar_en |= 0x4000000000000000ul;
4969 }
4970
4971 /* No MMIO windows ? Barf ! */
4972 if (mmio_win_sz == 0) {
4973 prerror("PHB3[%x:%x]: No MMIO windows enabled !\n",
4974 gcid, pno);
4975 return;
4976 }
4977
4978 /* Set the interrupt routing stuff, 8 relevant bits in mask
4979 * (11 bits per PHB)
4980 */
4981 val = p8_chip_irq_phb_base(gcid, pno);
4982 val = (val << 45);
4983 xscom_write(gcid, pe_xscom + 0x1a, val);
4984 xscom_write(gcid, pe_xscom + 0x1b, 0xff00000000000000ul);
4985
4986 /* Configure LSI location to the top of the map */
4987 xscom_write(gcid, pe_xscom + 0x1f, 0xff00000000000000ul);
4988
4989 /* Now add IRSN message bits to BAR enable and write it */
4990 bar_en |= 0x1800000000000000ul;
4991 xscom_write(gcid, pe_xscom + 0x45, bar_en);
4992
4993 prlog(PR_DEBUG, "PHB3[%x:%x] NEWBAREN = 0x%016llx\n",
4994 gcid, pno, bar_en);
4995
4996 xscom_read(gcid, pe_xscom + 0x1a, &val);
4997 prlog(PR_DEBUG, "PHB3[%x:%x] IRSNC = 0x%016llx\n",
4998 gcid, pno, val);
4999 xscom_read(gcid, pe_xscom + 0x1b, &val);
5000 prlog(PR_DEBUG, "PHB3[%x:%x] IRSNM = 0x%016llx\n",
5001 gcid, pno, val);
5002 prlog(PR_DEBUG, "PHB3[%x:%x] LSI = 0x%016llx\n",
5003 gcid, pno, val);
5004
5005 /* Create PHB node */
5006 reg[0] = phb_bar;
5007 reg[1] = 0x1000;
5008
5009 np = dt_new_addr(dt_root, "pciex", reg[0]);
5010 if (!np)
5011 return;
5012
5013 dt_add_property_strings(np, "compatible", "ibm,power8-pciex",
5014 "ibm,ioda2-phb");
5015 dt_add_property_strings(np, "device_type", "pciex");
5016 dt_add_property(np, "reg", reg, sizeof(reg));
5017
5018 /* Everything else is handled later by skiboot, we just
5019 * stick a few hints here
5020 */
5021 dt_add_property_cells(np, "ibm,xscom-bases",
5022 pe_xscom, spci_xscom, pci_xscom);
5023 dt_add_property(np, "ibm,mmio-window", mmio_win, 8 * mmio_win_sz);
5024 dt_add_property_cells(np, "ibm,phb-index", pno);
5025 dt_add_property_cells(np, "ibm,pbcq", pbcq->phandle);
5026 dt_add_property_cells(np, "ibm,chip-id", gcid);
5027 if (dt_has_node_property(pbcq, "ibm,use-ab-detect", NULL))
5028 dt_add_property(np, "ibm,use-ab-detect", NULL, 0);
5029 if (dt_has_node_property(pbcq, "ibm,hub-id", NULL))
5030 dt_add_property_cells(np, "ibm,hub-id",
5031 dt_prop_get_u32(pbcq, "ibm,hub-id"));
5032 if (dt_has_node_property(pbcq, "ibm,loc-code", NULL)) {
5033 const char *lc = dt_prop_get(pbcq, "ibm,loc-code");
5034 dt_add_property_string(np, "ibm,loc-code", lc);
5035 }
5036 if (dt_has_node_property(pbcq, "ibm,lane-eq", NULL)) {
5037 size_t leq_size;
5038 const void *leq = dt_prop_get_def_size(pbcq, "ibm,lane-eq",
5039 NULL, &leq_size);
5040 if (leq != NULL && leq_size == 4 * 8)
5041 dt_add_property(np, "ibm,lane-eq", leq, leq_size);
5042 }
5043 if (dt_has_node_property(pbcq, "ibm,capp-ucode", NULL)) {
5044 capp_ucode_base = dt_prop_get_u32(pbcq, "ibm,capp-ucode");
5045 dt_add_property_cells(np, "ibm,capp-ucode", capp_ucode_base);
5046 }
5047 if (dt_has_node_property(pbcq, "ibm,max-link-speed", NULL)) {
5048 max_link_speed = dt_prop_get_u32(pbcq, "ibm,max-link-speed");
5049 dt_add_property_cells(np, "ibm,max-link-speed", max_link_speed);
5050 }
5051 dt_add_property_cells(np, "ibm,capi-flags",
5052 OPAL_PHB_CAPI_FLAG_SNOOP_CONTROL);
5053
5054 add_chip_dev_associativity(np);
5055 }
5056
5057
probe_phb3(void)5058 void probe_phb3(void)
5059 {
5060 struct dt_node *np;
5061
5062 /* Look for PBCQ XSCOM nodes */
5063 dt_for_each_compatible(dt_root, np, "ibm,power8-pbcq")
5064 phb3_probe_pbcq(np);
5065
5066 /* Look for newly created PHB nodes */
5067 dt_for_each_compatible(dt_root, np, "ibm,power8-pciex")
5068 phb3_create(np);
5069 }
5070
5071
5072