1 /* 2 * Driver for Blackfin on-chip ATAPI controller. 3 * 4 * Enter bugs at http://blackfin.uclinux.org/ 5 * 6 * Copyright (c) 2008 Analog Devices Inc. 7 * 8 * Licensed under the GPL-2 or later. 9 */ 10 11 #ifndef PATA_BFIN_H 12 #define PATA_BFIN_H 13 14 #include <asm/blackfin_local.h> 15 16 struct ata_ioports { 17 unsigned long cmd_addr; 18 unsigned long data_addr; 19 unsigned long error_addr; 20 unsigned long feature_addr; 21 unsigned long nsect_addr; 22 unsigned long lbal_addr; 23 unsigned long lbam_addr; 24 unsigned long lbah_addr; 25 unsigned long device_addr; 26 unsigned long status_addr; 27 unsigned long command_addr; 28 unsigned long altstatus_addr; 29 unsigned long ctl_addr; 30 unsigned long bmdma_addr; 31 unsigned long scr_addr; 32 }; 33 34 struct ata_port { 35 unsigned int port_no; /* primary=0, secondary=1 */ 36 struct ata_ioports ioaddr; /* ATA cmd/ctl/dma reg blks */ 37 unsigned long flag; 38 unsigned int ata_mode; 39 unsigned char ctl_reg; 40 unsigned char last_ctl; 41 unsigned char dev_mask; 42 }; 43 44 extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE]; 45 46 #define DRV_NAME "pata-bfin" 47 #define DRV_VERSION "0.9" 48 #define __iomem 49 50 #define ATA_REG_CTRL 0x0E 51 #define ATA_REG_ALTSTATUS ATA_REG_CTRL 52 #define ATA_TMOUT_BOOT 30000 53 #define ATA_TMOUT_BOOT_QUICK 7000 54 55 #define PATA_BFIN_WAIT_TIMEOUT 10000 56 #define PATA_DEV_NUM_PER_PORT 2 57 58 /* These are the offset of the controller's registers */ 59 #define ATAPI_OFFSET_CONTROL 0x00 60 #define ATAPI_OFFSET_STATUS 0x04 61 #define ATAPI_OFFSET_DEV_ADDR 0x08 62 #define ATAPI_OFFSET_DEV_TXBUF 0x0c 63 #define ATAPI_OFFSET_DEV_RXBUF 0x10 64 #define ATAPI_OFFSET_INT_MASK 0x14 65 #define ATAPI_OFFSET_INT_STATUS 0x18 66 #define ATAPI_OFFSET_XFER_LEN 0x1c 67 #define ATAPI_OFFSET_LINE_STATUS 0x20 68 #define ATAPI_OFFSET_SM_STATE 0x24 69 #define ATAPI_OFFSET_TERMINATE 0x28 70 #define ATAPI_OFFSET_PIO_TFRCNT 0x2c 71 #define ATAPI_OFFSET_DMA_TFRCNT 0x30 72 #define ATAPI_OFFSET_UMAIN_TFRCNT 0x34 73 #define ATAPI_OFFSET_UDMAOUT_TFRCNT 0x38 74 #define ATAPI_OFFSET_REG_TIM_0 0x40 75 #define ATAPI_OFFSET_PIO_TIM_0 0x44 76 #define ATAPI_OFFSET_PIO_TIM_1 0x48 77 #define ATAPI_OFFSET_MULTI_TIM_0 0x50 78 #define ATAPI_OFFSET_MULTI_TIM_1 0x54 79 #define ATAPI_OFFSET_MULTI_TIM_2 0x58 80 #define ATAPI_OFFSET_ULTRA_TIM_0 0x60 81 #define ATAPI_OFFSET_ULTRA_TIM_1 0x64 82 #define ATAPI_OFFSET_ULTRA_TIM_2 0x68 83 #define ATAPI_OFFSET_ULTRA_TIM_3 0x6c 84 85 86 #define ATAPI_GET_CONTROL(base)\ 87 bfin_read16(base + ATAPI_OFFSET_CONTROL) 88 #define ATAPI_SET_CONTROL(base, val)\ 89 bfin_write16(base + ATAPI_OFFSET_CONTROL, val) 90 #define ATAPI_GET_STATUS(base)\ 91 bfin_read16(base + ATAPI_OFFSET_STATUS) 92 #define ATAPI_GET_DEV_ADDR(base)\ 93 bfin_read16(base + ATAPI_OFFSET_DEV_ADDR) 94 #define ATAPI_SET_DEV_ADDR(base, val)\ 95 bfin_write16(base + ATAPI_OFFSET_DEV_ADDR, val) 96 #define ATAPI_GET_DEV_TXBUF(base)\ 97 bfin_read16(base + ATAPI_OFFSET_DEV_TXBUF) 98 #define ATAPI_SET_DEV_TXBUF(base, val)\ 99 bfin_write16(base + ATAPI_OFFSET_DEV_TXBUF, val) 100 #define ATAPI_GET_DEV_RXBUF(base)\ 101 bfin_read16(base + ATAPI_OFFSET_DEV_RXBUF) 102 #define ATAPI_SET_DEV_RXBUF(base, val)\ 103 bfin_write16(base + ATAPI_OFFSET_DEV_RXBUF, val) 104 #define ATAPI_GET_INT_MASK(base)\ 105 bfin_read16(base + ATAPI_OFFSET_INT_MASK) 106 #define ATAPI_SET_INT_MASK(base, val)\ 107 bfin_write16(base + ATAPI_OFFSET_INT_MASK, val) 108 #define ATAPI_GET_INT_STATUS(base)\ 109 bfin_read16(base + ATAPI_OFFSET_INT_STATUS) 110 #define ATAPI_SET_INT_STATUS(base, val)\ 111 bfin_write16(base + ATAPI_OFFSET_INT_STATUS, val) 112 #define ATAPI_GET_XFER_LEN(base)\ 113 bfin_read16(base + ATAPI_OFFSET_XFER_LEN) 114 #define ATAPI_SET_XFER_LEN(base, val)\ 115 bfin_write16(base + ATAPI_OFFSET_XFER_LEN, val) 116 #define ATAPI_GET_LINE_STATUS(base)\ 117 bfin_read16(base + ATAPI_OFFSET_LINE_STATUS) 118 #define ATAPI_GET_SM_STATE(base)\ 119 bfin_read16(base + ATAPI_OFFSET_SM_STATE) 120 #define ATAPI_GET_TERMINATE(base)\ 121 bfin_read16(base + ATAPI_OFFSET_TERMINATE) 122 #define ATAPI_SET_TERMINATE(base, val)\ 123 bfin_write16(base + ATAPI_OFFSET_TERMINATE, val) 124 #define ATAPI_GET_PIO_TFRCNT(base)\ 125 bfin_read16(base + ATAPI_OFFSET_PIO_TFRCNT) 126 #define ATAPI_GET_DMA_TFRCNT(base)\ 127 bfin_read16(base + ATAPI_OFFSET_DMA_TFRCNT) 128 #define ATAPI_GET_UMAIN_TFRCNT(base)\ 129 bfin_read16(base + ATAPI_OFFSET_UMAIN_TFRCNT) 130 #define ATAPI_GET_UDMAOUT_TFRCNT(base)\ 131 bfin_read16(base + ATAPI_OFFSET_UDMAOUT_TFRCNT) 132 #define ATAPI_GET_REG_TIM_0(base)\ 133 bfin_read16(base + ATAPI_OFFSET_REG_TIM_0) 134 #define ATAPI_SET_REG_TIM_0(base, val)\ 135 bfin_write16(base + ATAPI_OFFSET_REG_TIM_0, val) 136 #define ATAPI_GET_PIO_TIM_0(base)\ 137 bfin_read16(base + ATAPI_OFFSET_PIO_TIM_0) 138 #define ATAPI_SET_PIO_TIM_0(base, val)\ 139 bfin_write16(base + ATAPI_OFFSET_PIO_TIM_0, val) 140 #define ATAPI_GET_PIO_TIM_1(base)\ 141 bfin_read16(base + ATAPI_OFFSET_PIO_TIM_1) 142 #define ATAPI_SET_PIO_TIM_1(base, val)\ 143 bfin_write16(base + ATAPI_OFFSET_PIO_TIM_1, val) 144 #define ATAPI_GET_MULTI_TIM_0(base)\ 145 bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_0) 146 #define ATAPI_SET_MULTI_TIM_0(base, val)\ 147 bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_0, val) 148 #define ATAPI_GET_MULTI_TIM_1(base)\ 149 bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_1) 150 #define ATAPI_SET_MULTI_TIM_1(base, val)\ 151 bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_1, val) 152 #define ATAPI_GET_MULTI_TIM_2(base)\ 153 bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_2) 154 #define ATAPI_SET_MULTI_TIM_2(base, val)\ 155 bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_2, val) 156 #define ATAPI_GET_ULTRA_TIM_0(base)\ 157 bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_0) 158 #define ATAPI_SET_ULTRA_TIM_0(base, val)\ 159 bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_0, val) 160 #define ATAPI_GET_ULTRA_TIM_1(base)\ 161 bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_1) 162 #define ATAPI_SET_ULTRA_TIM_1(base, val)\ 163 bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_1, val) 164 #define ATAPI_GET_ULTRA_TIM_2(base)\ 165 bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_2) 166 #define ATAPI_SET_ULTRA_TIM_2(base, val)\ 167 bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_2, val) 168 #define ATAPI_GET_ULTRA_TIM_3(base)\ 169 bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_3) 170 #define ATAPI_SET_ULTRA_TIM_3(base, val)\ 171 bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_3, val) 172 173 #endif 174