1 /*
2 * (C) Copyright 2003-2010
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * Derived from the MPC8xx FEC driver.
6 * Adapted for MPC512x by Grzegorz Bernacki <gjb@semihalf.com>
7 */
8
9 #include <common.h>
10 #include <malloc.h>
11 #include <net.h>
12 #include <netdev.h>
13 #include <miiphy.h>
14 #include <asm/io.h>
15 #include "mpc512x_fec.h"
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 #define DEBUG 0
20
21 #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
22 defined(CONFIG_MPC512x_FEC)
23
24 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
25 #error "CONFIG_MII has to be defined!"
26 #endif
27
28 int fec512x_miiphy_read(char *devname, u8 phyAddr, u8 regAddr, u16 * retVal);
29 int fec512x_miiphy_write(char *devname, u8 phyAddr, u8 regAddr, u16 data);
30 int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis);
31
32 static uchar rx_buff[FEC_BUFFER_SIZE];
33 static int rx_buff_idx = 0;
34
35 /********************************************************************/
36 #if (DEBUG & 0x2)
mpc512x_fec_phydump(char * devname)37 static void mpc512x_fec_phydump (char *devname)
38 {
39 u16 phyStatus, i;
40 u8 phyAddr = CONFIG_PHY_ADDR;
41 u8 reg_mask[] = {
42 /* regs to print: 0...8, 21,27,31 */
43 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
44 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1,
45 };
46
47 for (i = 0; i < 32; i++) {
48 if (reg_mask[i]) {
49 miiphy_read (devname, phyAddr, i, &phyStatus);
50 printf ("Mii reg %d: 0x%04x\n", i, phyStatus);
51 }
52 }
53 }
54 #endif
55
56 /********************************************************************/
mpc512x_fec_bd_init(mpc512x_fec_priv * fec)57 static int mpc512x_fec_bd_init (mpc512x_fec_priv *fec)
58 {
59 int ix;
60
61 /*
62 * Receive BDs init
63 */
64 for (ix = 0; ix < FEC_RBD_NUM; ix++) {
65 fec->bdBase->rbd[ix].dataPointer =
66 (u32)&fec->bdBase->recv_frames[ix];
67 fec->bdBase->rbd[ix].status = FEC_RBD_EMPTY;
68 fec->bdBase->rbd[ix].dataLength = 0;
69 }
70
71 /*
72 * have the last RBD to close the ring
73 */
74 fec->bdBase->rbd[ix - 1].status |= FEC_RBD_WRAP;
75 fec->rbdIndex = 0;
76
77 /*
78 * Trasmit BDs init
79 */
80 for (ix = 0; ix < FEC_TBD_NUM; ix++) {
81 fec->bdBase->tbd[ix].status = 0;
82 }
83
84 /*
85 * Have the last TBD to close the ring
86 */
87 fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP;
88
89 /*
90 * Initialize some indices
91 */
92 fec->tbdIndex = 0;
93 fec->usedTbdIndex = 0;
94 fec->cleanTbdNum = FEC_TBD_NUM;
95
96 return 0;
97 }
98
99 /********************************************************************/
mpc512x_fec_rbd_clean(mpc512x_fec_priv * fec,volatile FEC_RBD * pRbd)100 static void mpc512x_fec_rbd_clean (mpc512x_fec_priv *fec, volatile FEC_RBD * pRbd)
101 {
102 /*
103 * Reset buffer descriptor as empty
104 */
105 if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
106 pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
107 else
108 pRbd->status = FEC_RBD_EMPTY;
109
110 pRbd->dataLength = 0;
111
112 /*
113 * Increment BD count
114 */
115 fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
116
117 /*
118 * Now, we have an empty RxBD, notify FEC
119 * Set Descriptor polling active
120 */
121 out_be32(&fec->eth->r_des_active, 0x01000000);
122 }
123
124 /********************************************************************/
mpc512x_fec_tbd_scrub(mpc512x_fec_priv * fec)125 static void mpc512x_fec_tbd_scrub (mpc512x_fec_priv *fec)
126 {
127 volatile FEC_TBD *pUsedTbd;
128
129 #if (DEBUG & 0x1)
130 printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
131 fec->cleanTbdNum, fec->usedTbdIndex);
132 #endif
133
134 /*
135 * process all the consumed TBDs
136 */
137 while (fec->cleanTbdNum < FEC_TBD_NUM) {
138 pUsedTbd = &fec->bdBase->tbd[fec->usedTbdIndex];
139 if (pUsedTbd->status & FEC_TBD_READY) {
140 #if (DEBUG & 0x20)
141 printf ("Cannot clean TBD %d, in use\n", fec->usedTbdIndex);
142 #endif
143 return;
144 }
145
146 /*
147 * clean this buffer descriptor
148 */
149 if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
150 pUsedTbd->status = FEC_TBD_WRAP;
151 else
152 pUsedTbd->status = 0;
153
154 /*
155 * update some indeces for a correct handling of the TBD ring
156 */
157 fec->cleanTbdNum++;
158 fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
159 }
160 }
161
162 /********************************************************************/
mpc512x_fec_set_hwaddr(mpc512x_fec_priv * fec,unsigned char * mac)163 static void mpc512x_fec_set_hwaddr (mpc512x_fec_priv *fec, unsigned char *mac)
164 {
165 u8 currByte; /* byte for which to compute the CRC */
166 int byte; /* loop - counter */
167 int bit; /* loop - counter */
168 u32 crc = 0xffffffff; /* initial value */
169
170 /*
171 * The algorithm used is the following:
172 * we loop on each of the six bytes of the provided address,
173 * and we compute the CRC by left-shifting the previous
174 * value by one position, so that each bit in the current
175 * byte of the address may contribute the calculation. If
176 * the latter and the MSB in the CRC are different, then
177 * the CRC value so computed is also ex-ored with the
178 * "polynomium generator". The current byte of the address
179 * is also shifted right by one bit at each iteration.
180 * This is because the CRC generatore in hardware is implemented
181 * as a shift-register with as many ex-ores as the radixes
182 * in the polynomium. This suggests that we represent the
183 * polynomiumm itself as a 32-bit constant.
184 */
185 for (byte = 0; byte < 6; byte++) {
186 currByte = mac[byte];
187 for (bit = 0; bit < 8; bit++) {
188 if ((currByte & 0x01) ^ (crc & 0x01)) {
189 crc >>= 1;
190 crc = crc ^ 0xedb88320;
191 } else {
192 crc >>= 1;
193 }
194 currByte >>= 1;
195 }
196 }
197
198 crc = crc >> 26;
199
200 /*
201 * Set individual hash table register
202 */
203 if (crc >= 32) {
204 out_be32(&fec->eth->iaddr1, (1 << (crc - 32)));
205 out_be32(&fec->eth->iaddr2, 0);
206 } else {
207 out_be32(&fec->eth->iaddr1, 0);
208 out_be32(&fec->eth->iaddr2, (1 << crc));
209 }
210
211 /*
212 * Set physical address
213 */
214 out_be32(&fec->eth->paddr1, (mac[0] << 24) + (mac[1] << 16) +
215 (mac[2] << 8) + mac[3]);
216 out_be32(&fec->eth->paddr2, (mac[4] << 24) + (mac[5] << 16) +
217 0x8808);
218 }
219
220 /********************************************************************/
mpc512x_fec_init(struct eth_device * dev,bd_t * bis)221 static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis)
222 {
223 mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
224
225 #if (DEBUG & 0x1)
226 printf ("mpc512x_fec_init... Begin\n");
227 #endif
228
229 mpc512x_fec_set_hwaddr (fec, dev->enetaddr);
230 out_be32(&fec->eth->gaddr1, 0x00000000);
231 out_be32(&fec->eth->gaddr2, 0x00000000);
232
233 mpc512x_fec_init_phy (dev, bis);
234
235 /* Set interrupt mask register */
236 out_be32(&fec->eth->imask, 0x00000000);
237
238 /* Clear FEC-Lite interrupt event register(IEVENT) */
239 out_be32(&fec->eth->ievent, 0xffffffff);
240
241 /* Set transmit fifo watermark register(X_WMRK), default = 64 */
242 out_be32(&fec->eth->x_wmrk, 0x0);
243
244 /* Set Opcode/Pause Duration Register */
245 out_be32(&fec->eth->op_pause, 0x00010020);
246
247 /* Frame length=1522; MII mode */
248 out_be32(&fec->eth->r_cntrl, (FEC_MAX_FRAME_LEN << 16) | 0x24);
249
250 /* Half-duplex, heartbeat disabled */
251 out_be32(&fec->eth->x_cntrl, 0x00000000);
252
253 /* Enable MIB counters */
254 out_be32(&fec->eth->mib_control, 0x0);
255
256 /* Setup recv fifo start and buff size */
257 out_be32(&fec->eth->r_fstart, 0x500);
258 out_be32(&fec->eth->r_buff_size, FEC_BUFFER_SIZE);
259
260 /* Setup BD base addresses */
261 out_be32(&fec->eth->r_des_start, (u32)fec->bdBase->rbd);
262 out_be32(&fec->eth->x_des_start, (u32)fec->bdBase->tbd);
263
264 /* DMA Control */
265 out_be32(&fec->eth->dma_control, 0xc0000000);
266
267 /* Enable FEC */
268 setbits_be32(&fec->eth->ecntrl, 0x00000006);
269
270 /* Initilize addresses and status words of BDs */
271 mpc512x_fec_bd_init (fec);
272
273 /* Descriptor polling active */
274 out_be32(&fec->eth->r_des_active, 0x01000000);
275
276 #if (DEBUG & 0x1)
277 printf("mpc512x_fec_init... Done \n");
278 #endif
279 return 1;
280 }
281
282 /********************************************************************/
mpc512x_fec_init_phy(struct eth_device * dev,bd_t * bis)283 int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis)
284 {
285 mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
286 const u8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
287 int timeout = 1;
288 u16 phyStatus;
289
290 #if (DEBUG & 0x1)
291 printf ("mpc512x_fec_init_phy... Begin\n");
292 #endif
293
294 /*
295 * Clear FEC-Lite interrupt event register(IEVENT)
296 */
297 out_be32(&fec->eth->ievent, 0xffffffff);
298
299 /*
300 * Set interrupt mask register
301 */
302 out_be32(&fec->eth->imask, 0x00000000);
303
304 if (fec->xcv_type != SEVENWIRE) {
305 /*
306 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
307 * and do not drop the Preamble.
308 */
309 out_be32(&fec->eth->mii_speed,
310 (((gd->ips_clk / 1000000) / 5) + 1) << 1);
311
312 /*
313 * Reset PHY, then delay 300ns
314 */
315 miiphy_write (dev->name, phyAddr, 0x0, 0x8000);
316 udelay (1000);
317
318 if (fec->xcv_type == MII10) {
319 /*
320 * Force 10Base-T, FDX operation
321 */
322 #if (DEBUG & 0x2)
323 printf ("Forcing 10 Mbps ethernet link... ");
324 #endif
325 miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
326
327 miiphy_write (dev->name, phyAddr, 0x0, 0x0180);
328
329 timeout = 20;
330 do { /* wait for link status to go down */
331 udelay (10000);
332 if ((timeout--) == 0) {
333 #if (DEBUG & 0x2)
334 printf ("hmmm, should not have waited...");
335 #endif
336 break;
337 }
338 miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
339 #if (DEBUG & 0x2)
340 printf ("=");
341 #endif
342 } while ((phyStatus & 0x0004)); /* !link up */
343
344 timeout = 1000;
345 do { /* wait for link status to come back up */
346 udelay (10000);
347 if ((timeout--) == 0) {
348 printf ("failed. Link is down.\n");
349 break;
350 }
351 miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
352 #if (DEBUG & 0x2)
353 printf ("+");
354 #endif
355 } while (!(phyStatus & 0x0004)); /* !link up */
356
357 #if (DEBUG & 0x2)
358 printf ("done.\n");
359 #endif
360 } else { /* MII100 */
361 /*
362 * Set the auto-negotiation advertisement register bits
363 */
364 miiphy_write (dev->name, phyAddr, 0x4, 0x01e1);
365
366 /*
367 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
368 */
369 miiphy_write (dev->name, phyAddr, 0x0, 0x1200);
370
371 /*
372 * Wait for AN completion
373 */
374 timeout = 2500;
375 do {
376 udelay (1000);
377
378 if ((timeout--) == 0) {
379 #if (DEBUG & 0x2)
380 printf ("PHY auto neg 0 failed...\n");
381 #endif
382 return -1;
383 }
384
385 if (miiphy_read (dev->name, phyAddr, 0x1, &phyStatus) != 0) {
386 #if (DEBUG & 0x2)
387 printf ("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
388 #endif
389 return -1;
390 }
391 } while (!(phyStatus & 0x0004));
392
393 #if (DEBUG & 0x2)
394 printf ("PHY auto neg complete! \n");
395 #endif
396 }
397 }
398
399 #if (DEBUG & 0x2)
400 if (fec->xcv_type != SEVENWIRE)
401 mpc512x_fec_phydump (dev->name);
402 #endif
403
404 #if (DEBUG & 0x1)
405 printf ("mpc512x_fec_init_phy... Done \n");
406 #endif
407 return 1;
408 }
409
410 /********************************************************************/
mpc512x_fec_halt(struct eth_device * dev)411 static void mpc512x_fec_halt (struct eth_device *dev)
412 {
413 mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
414 int counter = 0xffff;
415
416 #if (DEBUG & 0x2)
417 if (fec->xcv_type != SEVENWIRE)
418 mpc512x_fec_phydump (dev->name);
419 #endif
420
421 /*
422 * mask FEC chip interrupts
423 */
424 out_be32(&fec->eth->imask, 0);
425
426 /*
427 * issue graceful stop command to the FEC transmitter if necessary
428 */
429 setbits_be32(&fec->eth->x_cntrl, 0x00000001);
430
431 /*
432 * wait for graceful stop to register
433 */
434 while ((counter--) && (!(in_be32(&fec->eth->ievent) & 0x10000000)))
435 ;
436
437 /*
438 * Disable the Ethernet Controller
439 */
440 clrbits_be32(&fec->eth->ecntrl, 0x00000002);
441
442 /*
443 * Issue a reset command to the FEC chip
444 */
445 setbits_be32(&fec->eth->ecntrl, 0x1);
446
447 /*
448 * wait at least 16 clock cycles
449 */
450 udelay (10);
451 #if (DEBUG & 0x3)
452 printf ("Ethernet task stopped\n");
453 #endif
454 }
455
456 /********************************************************************/
457
mpc512x_fec_send(struct eth_device * dev,volatile void * eth_data,int data_length)458 static int mpc512x_fec_send (struct eth_device *dev, volatile void *eth_data,
459 int data_length)
460 {
461 /*
462 * This routine transmits one frame. This routine only accepts
463 * 6-byte Ethernet addresses.
464 */
465 mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
466 volatile FEC_TBD *pTbd;
467
468 #if (DEBUG & 0x20)
469 printf("tbd status: 0x%04x\n", fec->tbdBase[fec->tbdIndex].status);
470 #endif
471
472 /*
473 * Clear Tx BD ring at first
474 */
475 mpc512x_fec_tbd_scrub (fec);
476
477 /*
478 * Check for valid length of data.
479 */
480 if ((data_length > 1500) || (data_length <= 0)) {
481 return -1;
482 }
483
484 /*
485 * Check the number of vacant TxBDs.
486 */
487 if (fec->cleanTbdNum < 1) {
488 #if (DEBUG & 0x20)
489 printf ("No available TxBDs ...\n");
490 #endif
491 return -1;
492 }
493
494 /*
495 * Get the first TxBD to send the mac header
496 */
497 pTbd = &fec->bdBase->tbd[fec->tbdIndex];
498 pTbd->dataLength = data_length;
499 pTbd->dataPointer = (u32)eth_data;
500 pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
501 fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
502
503 /* Activate transmit Buffer Descriptor polling */
504 out_be32(&fec->eth->x_des_active, 0x01000000);
505
506 #if (DEBUG & 0x8)
507 printf ( "+" );
508 #endif
509
510 fec->cleanTbdNum -= 1;
511
512 /*
513 * wait until frame is sent .
514 */
515 while (pTbd->status & FEC_TBD_READY) {
516 udelay (10);
517 #if (DEBUG & 0x8)
518 printf ("TDB status = %04x\n", pTbd->status);
519 #endif
520 }
521
522 return 0;
523 }
524
525
526 /********************************************************************/
mpc512x_fec_recv(struct eth_device * dev)527 static int mpc512x_fec_recv (struct eth_device *dev)
528 {
529 /*
530 * This command pulls one frame from the card
531 */
532 mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
533 volatile FEC_RBD *pRbd = &fec->bdBase->rbd[fec->rbdIndex];
534 unsigned long ievent;
535 int frame_length = 0;
536
537 #if (DEBUG & 0x1)
538 printf ("mpc512x_fec_recv %d Start...\n", fec->rbdIndex);
539 #endif
540 #if (DEBUG & 0x8)
541 printf( "-" );
542 #endif
543
544 /*
545 * Check if any critical events have happened
546 */
547 ievent = in_be32(&fec->eth->ievent);
548 out_be32(&fec->eth->ievent, ievent);
549 if (ievent & 0x20060000) {
550 /* BABT, Rx/Tx FIFO errors */
551 mpc512x_fec_halt (dev);
552 mpc512x_fec_init (dev, NULL);
553 return 0;
554 }
555 if (ievent & 0x80000000) {
556 /* Heartbeat error */
557 setbits_be32(&fec->eth->x_cntrl, 0x00000001);
558 }
559 if (ievent & 0x10000000) {
560 /* Graceful stop complete */
561 if (in_be32(&fec->eth->x_cntrl) & 0x00000001) {
562 mpc512x_fec_halt (dev);
563 clrbits_be32(&fec->eth->x_cntrl, 0x00000001);;
564 mpc512x_fec_init (dev, NULL);
565 }
566 }
567
568 if (!(pRbd->status & FEC_RBD_EMPTY)) {
569 if (!(pRbd->status & FEC_RBD_ERR) &&
570 ((pRbd->dataLength - 4) > 14)) {
571
572 /*
573 * Get buffer size
574 */
575 if (pRbd->status & FEC_RBD_LAST)
576 frame_length = pRbd->dataLength - 4;
577 else
578 frame_length = pRbd->dataLength;
579 #if (DEBUG & 0x20)
580 {
581 int i;
582 printf ("recv data length 0x%08x data hdr: ",
583 pRbd->dataLength);
584 for (i = 0; i < 14; i++)
585 printf ("%x ", *((u8*)pRbd->dataPointer + i));
586 printf("\n");
587 }
588 #endif
589 /*
590 * Fill the buffer and pass it to upper layers
591 */
592 memcpy (&rx_buff[rx_buff_idx], (void*)pRbd->dataPointer,
593 frame_length - rx_buff_idx);
594 rx_buff_idx = frame_length;
595
596 if (pRbd->status & FEC_RBD_LAST) {
597 NetReceive ((uchar*)rx_buff, frame_length);
598 rx_buff_idx = 0;
599 }
600 }
601
602 /*
603 * Reset buffer descriptor as empty
604 */
605 mpc512x_fec_rbd_clean (fec, pRbd);
606 }
607
608 /* Try to fill Buffer Descriptors */
609 out_be32(&fec->eth->r_des_active, 0x01000000);
610
611 return frame_length;
612 }
613
614 /********************************************************************/
mpc512x_fec_initialize(bd_t * bis)615 int mpc512x_fec_initialize (bd_t * bis)
616 {
617 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
618 mpc512x_fec_priv *fec;
619 struct eth_device *dev;
620 void * bd;
621
622 fec = (mpc512x_fec_priv *) malloc (sizeof(*fec));
623 dev = (struct eth_device *) malloc (sizeof(*dev));
624 memset (dev, 0, sizeof *dev);
625
626 fec->eth = &im->fec;
627
628 # ifndef CONFIG_FEC_10MBIT
629 fec->xcv_type = MII100;
630 # else
631 fec->xcv_type = MII10;
632 # endif
633 dev->priv = (void *)fec;
634 dev->iobase = (int)&im->fec;
635 dev->init = mpc512x_fec_init;
636 dev->halt = mpc512x_fec_halt;
637 dev->send = mpc512x_fec_send;
638 dev->recv = mpc512x_fec_recv;
639
640 sprintf (dev->name, "FEC ETHERNET");
641 eth_register (dev);
642
643 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
644 miiphy_register (dev->name,
645 fec512x_miiphy_read, fec512x_miiphy_write);
646 #endif
647
648 /* Clean up space FEC's MIB and FIFO RAM ...*/
649 memset ((void *)&im->fec.mib, 0x00, sizeof(im->fec.mib));
650 memset ((void *)&im->fec.fifo, 0x00, sizeof(im->fec.fifo));
651
652 /*
653 * Malloc space for BDs (must be quad word-aligned)
654 * this pointer is lost, so cannot be freed
655 */
656 bd = malloc (sizeof(mpc512x_buff_descs) + 0x1f);
657 fec->bdBase = (mpc512x_buff_descs*)((u32)bd & 0xfffffff0);
658 memset ((void *) bd, 0x00, sizeof(mpc512x_buff_descs) + 0x1f);
659
660 /*
661 * Set interrupt mask register
662 */
663 out_be32(&fec->eth->imask, 0x00000000);
664
665 /*
666 * Clear FEC-Lite interrupt event register(IEVENT)
667 */
668 out_be32(&fec->eth->ievent, 0xffffffff);
669
670 return 1;
671 }
672
673 /* MII-interface related functions */
674 /********************************************************************/
fec512x_miiphy_read(char * devname,u8 phyAddr,u8 regAddr,u16 * retVal)675 int fec512x_miiphy_read (char *devname, u8 phyAddr, u8 regAddr, u16 * retVal)
676 {
677 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
678 volatile fec512x_t *eth = &im->fec;
679 u32 reg; /* convenient holder for the PHY register */
680 u32 phy; /* convenient holder for the PHY */
681 int timeout = 0xffff;
682
683 /*
684 * reading from any PHY's register is done by properly
685 * programming the FEC's MII data register.
686 */
687 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
688 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
689
690 out_be32(ð->mii_data, FEC_MII_DATA_ST |
691 FEC_MII_DATA_OP_RD |
692 FEC_MII_DATA_TA |
693 phy | reg);
694
695 /*
696 * wait for the related interrupt
697 */
698 while ((timeout--) && (!(in_be32(ð->ievent) & 0x00800000)))
699 ;
700
701 if (timeout == 0) {
702 #if (DEBUG & 0x2)
703 printf ("Read MDIO failed...\n");
704 #endif
705 return -1;
706 }
707
708 /*
709 * clear mii interrupt bit
710 */
711 out_be32(ð->ievent, 0x00800000);
712
713 /*
714 * it's now safe to read the PHY's register
715 */
716 *retVal = (u16) in_be32(ð->mii_data);
717
718 return 0;
719 }
720
721 /********************************************************************/
fec512x_miiphy_write(char * devname,u8 phyAddr,u8 regAddr,u16 data)722 int fec512x_miiphy_write (char *devname, u8 phyAddr, u8 regAddr, u16 data)
723 {
724 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
725 volatile fec512x_t *eth = &im->fec;
726 u32 reg; /* convenient holder for the PHY register */
727 u32 phy; /* convenient holder for the PHY */
728 int timeout = 0xffff;
729
730 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
731 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
732
733 out_be32(ð->mii_data, FEC_MII_DATA_ST |
734 FEC_MII_DATA_OP_WR |
735 FEC_MII_DATA_TA |
736 phy | reg | data);
737
738 /*
739 * wait for the MII interrupt
740 */
741 while ((timeout--) && (!(in_be32(ð->ievent) & 0x00800000)))
742 ;
743
744 if (timeout == 0) {
745 #if (DEBUG & 0x2)
746 printf ("Write MDIO failed...\n");
747 #endif
748 return -1;
749 }
750
751 /*
752 * clear MII interrupt bit
753 */
754 out_be32(ð->ievent, 0x00800000);
755
756 return 0;
757 }
758
759 #endif /* CONFIG_MPC512x_FEC */
760