1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
4 * Copyright 2017 NXP
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <dm/platform_data/pfe_dm_eth.h>
10 #include <net.h>
11 #include <net/pfe_eth/pfe_eth.h>
12 #include <net/pfe_eth/pfe_mdio.h>
13
14 struct gemac_s gem_info[] = {
15 /* PORT_0 configuration */
16 {
17 /* GEMAC config */
18 .gemac_speed = PFE_MAC_SPEED_1000M,
19 .gemac_duplex = DUPLEX_FULL,
20
21 /* phy iface */
22 .phy_address = CONFIG_PFE_EMAC1_PHY_ADDR,
23 .phy_mode = PHY_INTERFACE_MODE_SGMII,
24 },
25 /* PORT_1 configuration */
26 {
27 /* GEMAC config */
28 .gemac_speed = PFE_MAC_SPEED_1000M,
29 .gemac_duplex = DUPLEX_FULL,
30
31 /* phy iface */
32 .phy_address = CONFIG_PFE_EMAC2_PHY_ADDR,
33 .phy_mode = PHY_INTERFACE_MODE_RGMII_TXID,
34 },
35 };
36
pfe_gemac_enable(void * gemac_base)37 static inline void pfe_gemac_enable(void *gemac_base)
38 {
39 writel(readl(gemac_base + EMAC_ECNTRL_REG) |
40 EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
41 }
42
pfe_gemac_disable(void * gemac_base)43 static inline void pfe_gemac_disable(void *gemac_base)
44 {
45 writel(readl(gemac_base + EMAC_ECNTRL_REG) &
46 ~EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
47 }
48
pfe_gemac_set_speed(void * gemac_base,u32 speed)49 static inline void pfe_gemac_set_speed(void *gemac_base, u32 speed)
50 {
51 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
52 u32 ecr = readl(gemac_base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_SPEED;
53 u32 rcr = readl(gemac_base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_RMII_10T;
54 u32 rgmii_pcr = in_be32(&scfg->rgmiipcr) &
55 ~(SCFG_RGMIIPCR_SETSP_1000M | SCFG_RGMIIPCR_SETSP_10M);
56
57 if (speed == _1000BASET) {
58 ecr |= EMAC_ECNTRL_SPEED;
59 rgmii_pcr |= SCFG_RGMIIPCR_SETSP_1000M;
60 } else if (speed != _100BASET) {
61 rcr |= EMAC_RCNTRL_RMII_10T;
62 rgmii_pcr |= SCFG_RGMIIPCR_SETSP_10M;
63 }
64
65 writel(ecr, gemac_base + EMAC_ECNTRL_REG);
66 out_be32(&scfg->rgmiipcr, rgmii_pcr | SCFG_RGMIIPCR_SETFD);
67
68 /* remove loop back */
69 rcr &= ~EMAC_RCNTRL_LOOP;
70 /* enable flow control */
71 rcr |= EMAC_RCNTRL_FCE;
72
73 /* Enable MII mode */
74 rcr |= EMAC_RCNTRL_MII_MODE;
75
76 writel(rcr, gemac_base + EMAC_RCNTRL_REG);
77
78 /* Enable Tx full duplex */
79 writel(readl(gemac_base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_FDEN,
80 gemac_base + EMAC_TCNTRL_REG);
81 }
82
pfe_eth_write_hwaddr(struct udevice * dev)83 static int pfe_eth_write_hwaddr(struct udevice *dev)
84 {
85 struct pfe_eth_dev *priv = dev_get_priv(dev);
86 struct gemac_s *gem = priv->gem;
87 struct eth_pdata *pdata = dev_get_platdata(dev);
88 uchar *mac = pdata->enetaddr;
89
90 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
91 gem->gemac_base + EMAC_PHY_ADDR_LOW);
92 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, gem->gemac_base +
93 EMAC_PHY_ADDR_HIGH);
94 return 0;
95 }
96
97 /** Stops or Disables GEMAC pointing to this eth iface.
98 *
99 * @param[in] edev Pointer to eth device structure.
100 *
101 * @return none
102 */
pfe_eth_stop(struct udevice * dev)103 static inline void pfe_eth_stop(struct udevice *dev)
104 {
105 struct pfe_eth_dev *priv = dev_get_priv(dev);
106
107 pfe_gemac_disable(priv->gem->gemac_base);
108
109 gpi_disable(priv->gem->egpi_base);
110 }
111
pfe_eth_start(struct udevice * dev)112 static int pfe_eth_start(struct udevice *dev)
113 {
114 struct pfe_eth_dev *priv = dev_get_priv(dev);
115 struct gemac_s *gem = priv->gem;
116 int speed;
117
118 /* set ethernet mac address */
119 pfe_eth_write_hwaddr(dev);
120
121 writel(EMAC_TFWR, gem->gemac_base + EMAC_TFWR_STR_FWD);
122 writel(EMAC_RX_SECTION_FULL_32, gem->gemac_base + EMAC_RX_SECTIOM_FULL);
123 writel(EMAC_TRUNC_FL_16K, gem->gemac_base + EMAC_TRUNC_FL);
124 writel(EMAC_TX_SECTION_EMPTY_30, gem->gemac_base
125 + EMAC_TX_SECTION_EMPTY);
126 writel(EMAC_MIBC_NO_CLR_NO_DIS, gem->gemac_base
127 + EMAC_MIB_CTRL_STS_REG);
128
129 #ifdef CONFIG_PHYLIB
130 /* Start up the PHY */
131 if (phy_startup(priv->phydev)) {
132 printf("Could not initialize PHY %s\n",
133 priv->phydev->dev->name);
134 return -1;
135 }
136 speed = priv->phydev->speed;
137 printf("Speed detected %x\n", speed);
138 if (priv->phydev->duplex == DUPLEX_HALF) {
139 printf("Half duplex not supported\n");
140 return -1;
141 }
142 #endif
143
144 pfe_gemac_set_speed(gem->gemac_base, speed);
145
146 /* Enable GPI */
147 gpi_enable(gem->egpi_base);
148
149 /* Enable GEMAC */
150 pfe_gemac_enable(gem->gemac_base);
151
152 return 0;
153 }
154
pfe_eth_send(struct udevice * dev,void * packet,int length)155 static int pfe_eth_send(struct udevice *dev, void *packet, int length)
156 {
157 struct pfe_eth_dev *priv = (struct pfe_eth_dev *)dev->priv;
158
159 int rc;
160 int i = 0;
161
162 rc = pfe_send(priv->gemac_port, packet, length);
163
164 if (rc < 0) {
165 printf("Tx Queue full\n");
166 return rc;
167 }
168
169 while (1) {
170 rc = pfe_tx_done();
171 if (rc == 0)
172 break;
173
174 udelay(100);
175 i++;
176 if (i == 30000)
177 printf("Tx timeout, send failed\n");
178 break;
179 }
180
181 return 0;
182 }
183
pfe_eth_recv(struct udevice * dev,int flags,uchar ** packetp)184 static int pfe_eth_recv(struct udevice *dev, int flags, uchar **packetp)
185 {
186 struct pfe_eth_dev *priv = dev_get_priv(dev);
187 uchar *pkt_buf;
188 int len;
189 int phy_port;
190
191 len = pfe_recv(&pkt_buf, &phy_port);
192
193 if (len == 0)
194 return -EAGAIN; /* no packet in rx */
195 else if (len < 0)
196 return -EAGAIN;
197
198 debug("Rx pkt: pkt_buf(0x%p), phy_port(%d), len(%d)\n", pkt_buf,
199 phy_port, len);
200 if (phy_port != priv->gemac_port) {
201 printf("Rx pkt not on expected port\n");
202 return -EAGAIN;
203 }
204
205 *packetp = pkt_buf;
206
207 return len;
208 }
209
pfe_eth_probe(struct udevice * dev)210 static int pfe_eth_probe(struct udevice *dev)
211 {
212 struct pfe_eth_dev *priv = dev_get_priv(dev);
213 struct pfe_ddr_address *pfe_addr;
214 struct pfe_eth_pdata *pdata = dev_get_platdata(dev);
215 int ret = 0;
216 static int init_done;
217
218 if (!init_done) {
219 pfe_addr = (struct pfe_ddr_address *)malloc(sizeof
220 (struct pfe_ddr_address));
221 if (!pfe_addr)
222 return -ENOMEM;
223
224 pfe_addr->ddr_pfe_baseaddr =
225 (void *)pdata->pfe_ddr_addr.ddr_pfe_baseaddr;
226 pfe_addr->ddr_pfe_phys_baseaddr =
227 (unsigned long)pdata->pfe_ddr_addr.ddr_pfe_phys_baseaddr;
228
229 debug("ddr_pfe_baseaddr: %p, ddr_pfe_phys_baseaddr: %08x\n",
230 pfe_addr->ddr_pfe_baseaddr,
231 (u32)pfe_addr->ddr_pfe_phys_baseaddr);
232
233 ret = pfe_drv_init(pfe_addr);
234 if (ret)
235 return ret;
236
237 init_pfe_scfg_dcfg_regs();
238 init_done = 1;
239 }
240
241 priv->gemac_port = pdata->pfe_eth_pdata_mac.phy_interface;
242 priv->gem = &gem_info[priv->gemac_port];
243 priv->dev = dev;
244
245 switch (priv->gemac_port) {
246 case EMAC_PORT_0:
247 default:
248 priv->gem->gemac_base = EMAC1_BASE_ADDR;
249 priv->gem->egpi_base = EGPI1_BASE_ADDR;
250 break;
251 case EMAC_PORT_1:
252 priv->gem->gemac_base = EMAC2_BASE_ADDR;
253 priv->gem->egpi_base = EGPI2_BASE_ADDR;
254 break;
255 }
256
257 ret = pfe_eth_board_init(dev);
258 if (ret)
259 return ret;
260
261 #if defined(CONFIG_PHYLIB)
262 ret = pfe_phy_configure(priv, pdata->pfe_eth_pdata_mac.phy_interface,
263 gem_info[priv->gemac_port].phy_address);
264 #endif
265 return ret;
266 }
267
pfe_eth_bind(struct udevice * dev)268 static int pfe_eth_bind(struct udevice *dev)
269 {
270 struct pfe_eth_pdata *pdata = dev_get_platdata(dev);
271 char name[20];
272
273 sprintf(name, "pfe_eth%u", pdata->pfe_eth_pdata_mac.phy_interface);
274
275 return device_set_name(dev, name);
276 }
277
278 static const struct eth_ops pfe_eth_ops = {
279 .start = pfe_eth_start,
280 .send = pfe_eth_send,
281 .recv = pfe_eth_recv,
282 .free_pkt = pfe_eth_free_pkt,
283 .stop = pfe_eth_stop,
284 .write_hwaddr = pfe_eth_write_hwaddr,
285 };
286
287 U_BOOT_DRIVER(pfe_eth) = {
288 .name = "pfe_eth",
289 .id = UCLASS_ETH,
290 .bind = pfe_eth_bind,
291 .probe = pfe_eth_probe,
292 .remove = pfe_eth_remove,
293 .ops = &pfe_eth_ops,
294 .priv_auto_alloc_size = sizeof(struct pfe_eth_dev),
295 .platdata_auto_alloc_size = sizeof(struct pfe_eth_pdata)
296 };
297