1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * Author: Andy Yan <andy.yan@rock-chips.com>
5 */
6 #include <common.h>
7 #include <dm.h>
8 #include <errno.h>
9 #include <syscon.h>
10 #include <asm/io.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/grf_rv1108.h>
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/periph.h>
15 #include <dm/pinctrl.h>
16
17 struct rv1108_pinctrl_priv {
18 struct rv1108_grf *grf;
19 };
20
21 /* GRF_GPIO1B_IOMUX */
22 enum {
23 GPIO1B7_SHIFT = 14,
24 GPIO1B7_MASK = 3 << GPIO1B7_SHIFT,
25 GPIO1B7_GPIO = 0,
26 GPIO1B7_LCDC_D12,
27 GPIO1B7_I2S_SDIO2_M0,
28 GPIO1B7_GMAC_RXDV,
29
30 GPIO1B6_SHIFT = 12,
31 GPIO1B6_MASK = 3 << GPIO1B6_SHIFT,
32 GPIO1B6_GPIO = 0,
33 GPIO1B6_LCDC_D13,
34 GPIO1B6_I2S_LRCLKTX_M0,
35 GPIO1B6_GMAC_RXD1,
36
37 GPIO1B5_SHIFT = 10,
38 GPIO1B5_MASK = 3 << GPIO1B5_SHIFT,
39 GPIO1B5_GPIO = 0,
40 GPIO1B5_LCDC_D14,
41 GPIO1B5_I2S_SDIO1_M0,
42 GPIO1B5_GMAC_RXD0,
43
44 GPIO1B4_SHIFT = 8,
45 GPIO1B4_MASK = 3 << GPIO1B4_SHIFT,
46 GPIO1B4_GPIO = 0,
47 GPIO1B4_LCDC_D15,
48 GPIO1B4_I2S_MCLK_M0,
49 GPIO1B4_GMAC_TXEN,
50
51 GPIO1B3_SHIFT = 6,
52 GPIO1B3_MASK = 3 << GPIO1B3_SHIFT,
53 GPIO1B3_GPIO = 0,
54 GPIO1B3_LCDC_D16,
55 GPIO1B3_I2S_SCLK_M0,
56 GPIO1B3_GMAC_TXD1,
57
58 GPIO1B2_SHIFT = 4,
59 GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
60 GPIO1B2_GPIO = 0,
61 GPIO1B2_LCDC_D17,
62 GPIO1B2_I2S_SDIO_M0,
63 GPIO1B2_GMAC_TXD0,
64
65 GPIO1B1_SHIFT = 2,
66 GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
67 GPIO1B1_GPIO = 0,
68 GPIO1B1_LCDC_D9,
69 GPIO1B1_PWM7,
70
71 GPIO1B0_SHIFT = 0,
72 GPIO1B0_MASK = 3,
73 GPIO1B0_GPIO = 0,
74 GPIO1B0_LCDC_D8,
75 GPIO1B0_PWM6,
76 };
77
78 /* GRF_GPIO1C_IOMUX */
79 enum {
80 GPIO1C7_SHIFT = 14,
81 GPIO1C7_MASK = 3 << GPIO1C7_SHIFT,
82 GPIO1C7_GPIO = 0,
83 GPIO1C7_CIF_D5,
84 GPIO1C7_I2S_SDIO2_M1,
85
86 GPIO1C6_SHIFT = 12,
87 GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
88 GPIO1C6_GPIO = 0,
89 GPIO1C6_CIF_D4,
90 GPIO1C6_I2S_LRCLKTX_M1,
91
92 GPIO1C5_SHIFT = 10,
93 GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
94 GPIO1C5_GPIO = 0,
95 GPIO1C5_LCDC_CLK,
96 GPIO1C5_GMAC_CLK,
97
98 GPIO1C4_SHIFT = 8,
99 GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
100 GPIO1C4_GPIO = 0,
101 GPIO1C4_LCDC_HSYNC,
102 GPIO1C4_GMAC_MDC,
103
104 GPIO1C3_SHIFT = 6,
105 GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
106 GPIO1C3_GPIO = 0,
107 GPIO1C3_LCDC_VSYNC,
108 GPIO1C3_GMAC_MDIO,
109
110 GPIO1C2_SHIFT = 4,
111 GPIO1C2_MASK = 3 << GPIO1C2_SHIFT,
112 GPIO1C2_GPIO = 0,
113 GPIO1C2_LCDC_EN,
114 GPIO1C2_I2S_SDIO3_M0,
115 GPIO1C2_GMAC_RXER,
116
117 GPIO1C1_SHIFT = 2,
118 GPIO1C1_MASK = 3 << GPIO1C1_SHIFT,
119 GPIO1C1_GPIO = 0,
120 GPIO1C1_LCDC_D10,
121 GPIO1C1_I2S_SDI_M0,
122 GPIO1C1_PWM4,
123
124 GPIO1C0_SHIFT = 0,
125 GPIO1C0_MASK = 3,
126 GPIO1C0_GPIO = 0,
127 GPIO1C0_LCDC_D11,
128 GPIO1C0_I2S_LRCLKRX_M0,
129 };
130
131 /* GRF_GPIO1D_OIMUX */
132 enum {
133 GPIO1D7_SHIFT = 14,
134 GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
135 GPIO1D7_GPIO = 0,
136 GPIO1D7_HDMI_CEC,
137 GPIO1D7_DSP_RTCK,
138
139 GPIO1D6_SHIFT = 12,
140 GPIO1D6_MASK = 1 << GPIO1D6_SHIFT,
141 GPIO1D6_GPIO = 0,
142 GPIO1D6_HDMI_HPD_M0,
143
144 GPIO1D5_SHIFT = 10,
145 GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
146 GPIO1D5_GPIO = 0,
147 GPIO1D5_UART2_RTSN,
148 GPIO1D5_HDMI_SDA_M0,
149
150 GPIO1D4_SHIFT = 8,
151 GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
152 GPIO1D4_GPIO = 0,
153 GPIO1D4_UART2_CTSN,
154 GPIO1D4_HDMI_SCL_M0,
155
156 GPIO1D3_SHIFT = 6,
157 GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
158 GPIO1D3_GPIO = 0,
159 GPIO1D3_UART0_SOUT,
160 GPIO1D3_SPI_TXD_M0,
161
162 GPIO1D2_SHIFT = 4,
163 GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
164 GPIO1D2_GPIO = 0,
165 GPIO1D2_UART0_SIN,
166 GPIO1D2_SPI_RXD_M0,
167 GPIO1D2_DSP_TDI,
168
169 GPIO1D1_SHIFT = 2,
170 GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
171 GPIO1D1_GPIO = 0,
172 GPIO1D1_UART0_RTSN,
173 GPIO1D1_SPI_CSN0_M0,
174 GPIO1D1_DSP_TMS,
175
176 GPIO1D0_SHIFT = 0,
177 GPIO1D0_MASK = 3,
178 GPIO1D0_GPIO = 0,
179 GPIO1D0_UART0_CTSN,
180 GPIO1D0_SPI_CLK_M0,
181 GPIO1D0_DSP_TCK,
182 };
183
184 /* GRF_GPIO2A_IOMUX */
185 enum {
186 GPIO2A7_SHIFT = 14,
187 GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
188 GPIO2A7_GPIO = 0,
189 GPIO2A7_FLASH_D7,
190 GPIO2A7_EMMC_D7,
191
192 GPIO2A6_SHIFT = 12,
193 GPIO2A6_MASK = 3 << GPIO2A6_SHIFT,
194 GPIO2A6_GPIO = 0,
195 GPIO2A6_FLASH_D6,
196 GPIO2A6_EMMC_D6,
197
198 GPIO2A5_SHIFT = 10,
199 GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
200 GPIO2A5_GPIO = 0,
201 GPIO2A5_FLASH_D5,
202 GPIO2A5_EMMC_D5,
203
204 GPIO2A4_SHIFT = 8,
205 GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
206 GPIO2A4_GPIO = 0,
207 GPIO2A4_FLASH_D4,
208 GPIO2A4_EMMC_D4,
209
210 GPIO2A3_SHIFT = 6,
211 GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
212 GPIO2A3_GPIO = 0,
213 GPIO2A3_FLASH_D3,
214 GPIO2A3_EMMC_D3,
215 GPIO2A3_SFC_HOLD_IO3,
216
217 GPIO2A2_SHIFT = 4,
218 GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
219 GPIO2A2_GPIO = 0,
220 GPIO2A2_FLASH_D2,
221 GPIO2A2_EMMC_D2,
222 GPIO2A2_SFC_WP_IO2,
223
224 GPIO2A1_SHIFT = 2,
225 GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
226 GPIO2A1_GPIO = 0,
227 GPIO2A1_FLASH_D1,
228 GPIO2A1_EMMC_D1,
229 GPIO2A1_SFC_SO_IO1,
230
231 GPIO2A0_SHIFT = 0,
232 GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
233 GPIO2A0_GPIO = 0,
234 GPIO2A0_FLASH_D0,
235 GPIO2A0_EMMC_D0,
236 GPIO2A0_SFC_SI_IO0,
237 };
238
239 /* GRF_GPIO2D_IOMUX */
240 enum {
241 GPIO2B7_SHIFT = 14,
242 GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
243 GPIO2B7_GPIO = 0,
244 GPIO2B7_FLASH_CS1,
245 GPIO2B7_SFC_CLK,
246
247 GPIO2B6_SHIFT = 12,
248 GPIO2B6_MASK = 1 << GPIO2B6_SHIFT,
249 GPIO2B6_GPIO = 0,
250 GPIO2B6_EMMC_CLKO,
251
252 GPIO2B5_SHIFT = 10,
253 GPIO2B5_MASK = 1 << GPIO2B5_SHIFT,
254 GPIO2B5_GPIO = 0,
255 GPIO2B5_FLASH_CS0,
256
257 GPIO2B4_SHIFT = 8,
258 GPIO2B4_MASK = 3 << GPIO2B4_SHIFT,
259 GPIO2B4_GPIO = 0,
260 GPIO2B4_FLASH_RDY,
261 GPIO2B4_EMMC_CMD,
262 GPIO2B4_SFC_CSN0,
263
264 GPIO2B3_SHIFT = 6,
265 GPIO2B3_MASK = 1 << GPIO2B3_SHIFT,
266 GPIO2B3_GPIO = 0,
267 GPIO2B3_FLASH_RDN,
268
269 GPIO2B2_SHIFT = 4,
270 GPIO2B2_MASK = 1 << GPIO2B2_SHIFT,
271 GPIO2B2_GPIO = 0,
272 GPIO2B2_FLASH_WRN,
273
274 GPIO2B1_SHIFT = 2,
275 GPIO2B1_MASK = 1 << GPIO2B1_SHIFT,
276 GPIO2B1_GPIO = 0,
277 GPIO2B1_FLASH_CLE,
278
279 GPIO2B0_SHIFT = 0,
280 GPIO2B0_MASK = 1 << GPIO2B0_SHIFT,
281 GPIO2B0_GPIO = 0,
282 GPIO2B0_FLASH_ALE,
283 };
284
285 /* GRF_GPIO2D_IOMUX */
286 enum {
287 GPIO2D7_SHIFT = 14,
288 GPIO2D7_MASK = 1 << GPIO2D7_SHIFT,
289 GPIO2D7_GPIO = 0,
290 GPIO2D7_SDIO_D0,
291
292 GPIO2D6_SHIFT = 12,
293 GPIO2D6_MASK = 1 << GPIO2D6_SHIFT,
294 GPIO2D6_GPIO = 0,
295 GPIO2D6_SDIO_CMD,
296
297 GPIO2D5_SHIFT = 10,
298 GPIO2D5_MASK = 1 << GPIO2D5_SHIFT,
299 GPIO2D5_GPIO = 0,
300 GPIO2D5_SDIO_CLKO,
301
302 GPIO2D4_SHIFT = 8,
303 GPIO2D4_MASK = 1 << GPIO2D4_SHIFT,
304 GPIO2D4_GPIO = 0,
305 GPIO2D4_I2C1_SCL,
306
307 GPIO2D3_SHIFT = 6,
308 GPIO2D3_MASK = 1 << GPIO2D3_SHIFT,
309 GPIO2D3_GPIO = 0,
310 GPIO2D3_I2C1_SDA,
311
312 GPIO2D2_SHIFT = 4,
313 GPIO2D2_MASK = 3 << GPIO2D2_SHIFT,
314 GPIO2D2_GPIO = 0,
315 GPIO2D2_UART2_SOUT_M0,
316 GPIO2D2_JTAG_TCK,
317
318 GPIO2D1_SHIFT = 2,
319 GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
320 GPIO2D1_GPIO = 0,
321 GPIO2D1_UART2_SIN_M0,
322 GPIO2D1_JTAG_TMS,
323 GPIO2D1_DSP_TMS,
324
325 GPIO2D0_SHIFT = 0,
326 GPIO2D0_MASK = 3,
327 GPIO2D0_GPIO = 0,
328 GPIO2D0_UART0_CTSN,
329 GPIO2D0_SPI_CLK_M0,
330 GPIO2D0_DSP_TCK,
331 };
332
333 /* GRF_GPIO3A_IOMUX */
334 enum {
335 GPIO3A7_SHIFT = 14,
336 GPIO3A7_MASK = 1 << GPIO3A7_SHIFT,
337 GPIO3A7_GPIO = 0,
338
339 GPIO3A6_SHIFT = 12,
340 GPIO3A6_MASK = 1 << GPIO3A6_SHIFT,
341 GPIO3A6_GPIO = 0,
342 GPIO3A6_UART1_SOUT,
343
344 GPIO3A5_SHIFT = 10,
345 GPIO3A5_MASK = 1 << GPIO3A5_SHIFT,
346 GPIO3A5_GPIO = 0,
347 GPIO3A5_UART1_SIN,
348
349 GPIO3A4_SHIFT = 8,
350 GPIO3A4_MASK = 1 << GPIO3A4_SHIFT,
351 GPIO3A4_GPIO = 0,
352 GPIO3A4_UART1_CTSN,
353
354 GPIO3A3_SHIFT = 6,
355 GPIO3A3_MASK = 1 << GPIO3A3_SHIFT,
356 GPIO3A3_GPIO = 0,
357 GPIO3A3_UART1_RTSN,
358
359 GPIO3A2_SHIFT = 4,
360 GPIO3A2_MASK = 1 << GPIO3A2_SHIFT,
361 GPIO3A2_GPIO = 0,
362 GPIO3A2_SDIO_D3,
363
364 GPIO3A1_SHIFT = 2,
365 GPIO3A1_MASK = 1 << GPIO3A1_SHIFT,
366 GPIO3A1_GPIO = 0,
367 GPIO3A1_SDIO_D2,
368
369 GPIO3A0_SHIFT = 0,
370 GPIO3A0_MASK = 1,
371 GPIO3A0_GPIO = 0,
372 GPIO3A0_SDIO_D1,
373 };
374
375 /* GRF_GPIO3C_IOMUX */
376 enum {
377 GPIO3C7_SHIFT = 14,
378 GPIO3C7_MASK = 1 << GPIO3C7_SHIFT,
379 GPIO3C7_GPIO = 0,
380 GPIO3C7_CIF_CLKI,
381
382 GPIO3C6_SHIFT = 12,
383 GPIO3C6_MASK = 1 << GPIO3C6_SHIFT,
384 GPIO3C6_GPIO = 0,
385 GPIO3C6_CIF_VSYNC,
386
387 GPIO3C5_SHIFT = 10,
388 GPIO3C5_MASK = 1 << GPIO3C5_SHIFT,
389 GPIO3C5_GPIO = 0,
390 GPIO3C5_SDMMC_CMD,
391
392 GPIO3C4_SHIFT = 8,
393 GPIO3C4_MASK = 1 << GPIO3C4_SHIFT,
394 GPIO3C4_GPIO = 0,
395 GPIO3C4_SDMMC_CLKO,
396
397 GPIO3C3_SHIFT = 6,
398 GPIO3C3_MASK = 3 << GPIO3C3_SHIFT,
399 GPIO3C3_GPIO = 0,
400 GPIO3C3_SDMMC_D0,
401 GPIO3C3_UART2_SOUT_M1,
402
403 GPIO3C2_SHIFT = 4,
404 GPIO3C2_MASK = 3 << GPIO3C2_SHIFT,
405 GPIO3C2_GPIO = 0,
406 GPIO3C2_SDMMC_D1,
407 GPIO3C2_UART2_SIN_M1,
408
409 GPIOC1_SHIFT = 2,
410 GPIOC1_MASK = 1 << GPIOC1_SHIFT,
411 GPIOC1_GPIO = 0,
412 GPIOC1_SDMMC_D2,
413
414 GPIOC0_SHIFT = 0,
415 GPIOC0_MASK = 1,
416 GPIO3C0_GPIO = 0,
417 GPIO3C0_SDMMC_D3,
418 };
419
pinctrl_rv1108_uart_config(struct rv1108_grf * grf,int uart_id)420 static void pinctrl_rv1108_uart_config(struct rv1108_grf *grf, int uart_id)
421 {
422 switch (uart_id) {
423 case PERIPH_ID_UART0:
424 rk_clrsetreg(&grf->gpio3a_iomux,
425 GPIO3A6_MASK | GPIO3A5_MASK,
426 GPIO3A6_UART1_SOUT << GPIO3A6_SHIFT |
427 GPIO3A5_UART1_SIN << GPIO3A5_SHIFT);
428 break;
429 case PERIPH_ID_UART1:
430 rk_clrsetreg(&grf->gpio1d_iomux,
431 GPIO1D3_MASK | GPIO1D2_MASK | GPIO1D1_MASK |
432 GPIO1D0_MASK,
433 GPIO1D3_UART0_SOUT << GPIO1D3_SHIFT |
434 GPIO1D2_UART0_SIN << GPIO1D2_SHIFT |
435 GPIO1D1_UART0_RTSN << GPIO1D1_SHIFT |
436 GPIO1D0_UART0_CTSN << GPIO1D0_SHIFT);
437 break;
438 case PERIPH_ID_UART2:
439 rk_clrsetreg(&grf->gpio2d_iomux,
440 GPIO2D2_MASK | GPIO2D1_MASK,
441 GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT |
442 GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT);
443 break;
444 }
445 }
446
pinctrl_rv1108_gmac_config(struct rv1108_grf * grf,int func)447 static void pinctrl_rv1108_gmac_config(struct rv1108_grf *grf, int func)
448 {
449 rk_clrsetreg(&grf->gpio1b_iomux,
450 GPIO1B7_MASK | GPIO1B6_MASK | GPIO1B5_MASK |
451 GPIO1B4_MASK | GPIO1B3_MASK | GPIO1B2_MASK,
452 GPIO1B7_GMAC_RXDV << GPIO1B7_SHIFT |
453 GPIO1B6_GMAC_RXD1 << GPIO1B6_SHIFT |
454 GPIO1B5_GMAC_RXD0 << GPIO1B5_SHIFT |
455 GPIO1B4_GMAC_TXEN << GPIO1B4_SHIFT |
456 GPIO1B3_GMAC_TXD1 << GPIO1B3_SHIFT |
457 GPIO1B2_GMAC_TXD0 << GPIO1B2_SHIFT);
458 rk_clrsetreg(&grf->gpio1c_iomux,
459 GPIO1C5_MASK | GPIO1C4_MASK |
460 GPIO1C3_MASK | GPIO1C2_MASK,
461 GPIO1C5_GMAC_CLK << GPIO1C5_SHIFT |
462 GPIO1C4_GMAC_MDC << GPIO1C4_SHIFT |
463 GPIO1C3_GMAC_MDIO << GPIO1C3_SHIFT |
464 GPIO1C2_GMAC_RXER << GPIO1C2_SHIFT);
465 writel(0xffff57f5, &grf->gpio1b_drv);
466 }
467
pinctrl_rv1108_sfc_config(struct rv1108_grf * grf)468 static void pinctrl_rv1108_sfc_config(struct rv1108_grf *grf)
469 {
470 rk_clrsetreg(&grf->gpio2a_iomux, GPIO2A3_MASK | GPIO2A2_MASK |
471 GPIO2A1_MASK | GPIO2A0_MASK,
472 GPIO2A3_SFC_HOLD_IO3 << GPIO2A3_SHIFT |
473 GPIO2A2_SFC_WP_IO2 << GPIO2A2_SHIFT |
474 GPIO2A1_SFC_SO_IO1 << GPIO2A1_SHIFT |
475 GPIO2A0_SFC_SI_IO0 << GPIO2A0_SHIFT);
476 rk_clrsetreg(&grf->gpio2b_iomux, GPIO2B7_MASK | GPIO2B4_MASK,
477 GPIO2B7_SFC_CLK << GPIO2B7_SHIFT |
478 GPIO2B4_SFC_CSN0 << GPIO2B4_SHIFT);
479 }
480
rv1108_pinctrl_request(struct udevice * dev,int func,int flags)481 static int rv1108_pinctrl_request(struct udevice *dev, int func, int flags)
482 {
483 struct rv1108_pinctrl_priv *priv = dev_get_priv(dev);
484
485 switch (func) {
486 case PERIPH_ID_UART0:
487 case PERIPH_ID_UART1:
488 case PERIPH_ID_UART2:
489 pinctrl_rv1108_uart_config(priv->grf, func);
490 break;
491 case PERIPH_ID_GMAC:
492 pinctrl_rv1108_gmac_config(priv->grf, func);
493 case PERIPH_ID_SFC:
494 pinctrl_rv1108_sfc_config(priv->grf);
495 default:
496 return -EINVAL;
497 }
498
499 return 0;
500 }
501
rv1108_pinctrl_get_periph_id(struct udevice * dev,struct udevice * periph)502 static int rv1108_pinctrl_get_periph_id(struct udevice *dev,
503 struct udevice *periph)
504 {
505 u32 cell[3];
506 int ret;
507
508 ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
509 if (ret < 0)
510 return -EINVAL;
511
512 switch (cell[1]) {
513 case 11:
514 return PERIPH_ID_SDCARD;
515 case 13:
516 return PERIPH_ID_EMMC;
517 case 19:
518 return PERIPH_ID_GMAC;
519 case 30:
520 return PERIPH_ID_I2C0;
521 case 31:
522 return PERIPH_ID_I2C1;
523 case 32:
524 return PERIPH_ID_I2C2;
525 case 39:
526 return PERIPH_ID_PWM0;
527 case 44:
528 return PERIPH_ID_UART0;
529 case 45:
530 return PERIPH_ID_UART1;
531 case 46:
532 return PERIPH_ID_UART2;
533 case 56:
534 return PERIPH_ID_SFC;
535 }
536
537 return -ENOENT;
538 }
539
rv1108_pinctrl_set_state_simple(struct udevice * dev,struct udevice * periph)540 static int rv1108_pinctrl_set_state_simple(struct udevice *dev,
541 struct udevice *periph)
542 {
543 int func;
544
545 func = rv1108_pinctrl_get_periph_id(dev, periph);
546 if (func < 0)
547 return func;
548
549 return rv1108_pinctrl_request(dev, func, 0);
550 }
551
552 static struct pinctrl_ops rv1108_pinctrl_ops = {
553 .set_state_simple = rv1108_pinctrl_set_state_simple,
554 .request = rv1108_pinctrl_request,
555 .get_periph_id = rv1108_pinctrl_get_periph_id,
556 };
557
rv1108_pinctrl_probe(struct udevice * dev)558 static int rv1108_pinctrl_probe(struct udevice *dev)
559 {
560 struct rv1108_pinctrl_priv *priv = dev_get_priv(dev);
561
562 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
563
564 return 0;
565 }
566
567 static const struct udevice_id rv1108_pinctrl_ids[] = {
568 {.compatible = "rockchip,rv1108-pinctrl" },
569 { }
570 };
571
572 U_BOOT_DRIVER(pinctrl_rv1108) = {
573 .name = "pinctrl_rv1108",
574 .id = UCLASS_PINCTRL,
575 .of_match = rv1108_pinctrl_ids,
576 .priv_auto_alloc_size = sizeof(struct rv1108_pinctrl_priv),
577 .ops = &rv1108_pinctrl_ops,
578 .bind = dm_scan_fdt_dev,
579 .probe = rv1108_pinctrl_probe,
580 };
581