1# AArch32 VFP instruction descriptions (unconditional insns)
2#
3#  Copyright (c) 2019 Linaro, Ltd
4#
5# This library is free software; you can redistribute it and/or
6# modify it under the terms of the GNU Lesser General Public
7# License as published by the Free Software Foundation; either
8# version 2 of the License, or (at your option) any later version.
9#
10# This library is distributed in the hope that it will be useful,
11# but WITHOUT ANY WARRANTY; without even the implied warranty of
12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
13# Lesser General Public License for more details.
14#
15# You should have received a copy of the GNU Lesser General Public
16# License along with this library; if not, see <http://www.gnu.org/licenses/>.
17
18#
19# This file is processed by scripts/decodetree.py
20#
21# Encodings for the unconditional VFP instructions are here:
22# generally anything matching A32
23#  1111 1110 .... .... .... 101. ...0 ....
24# and T32
25#  1111 110. .... .... .... 101. .... ....
26#  1111 1110 .... .... .... 101. .... ....
27# (but those patterns might also cover some Neon instructions,
28# which do not live in this file.)
29
30# VFP registers have an odd encoding with a four-bit field
31# and a one-bit field which are assembled in different orders
32# depending on whether the register is double or single precision.
33# Each individual instruction function must do the checks for
34# "double register selected but CPU does not have double support"
35# and "double register number has bit 4 set but CPU does not
36# support D16-D31" (which should UNDEF).
37%vm_dp  5:1 0:4
38%vm_sp  0:4 5:1
39%vn_dp  7:1 16:4
40%vn_sp  16:4 7:1
41%vd_dp  22:1 12:4
42%vd_sp  12:4 22:1
43
44VSEL        1111 1110 0. cc:2 .... .... 1010 .0.0 .... \
45            vm=%vm_sp vn=%vn_sp vd=%vd_sp dp=0
46VSEL        1111 1110 0. cc:2 .... .... 1011 .0.0 .... \
47            vm=%vm_dp vn=%vn_dp vd=%vd_dp dp=1
48
49VMINMAXNM   1111 1110 1.00 .... .... 1010 . op:1 .0 .... \
50            vm=%vm_sp vn=%vn_sp vd=%vd_sp dp=0
51VMINMAXNM   1111 1110 1.00 .... .... 1011 . op:1 .0 .... \
52            vm=%vm_dp vn=%vn_dp vd=%vd_dp dp=1
53
54VRINT       1111 1110 1.11 10 rm:2 .... 1010 01.0 .... \
55            vm=%vm_sp vd=%vd_sp dp=0
56VRINT       1111 1110 1.11 10 rm:2 .... 1011 01.0 .... \
57            vm=%vm_dp vd=%vd_dp dp=1
58
59# VCVT float to int with specified rounding mode; Vd is always single-precision
60VCVT        1111 1110 1.11 11 rm:2 .... 1010 op:1 1.0 .... \
61            vm=%vm_sp vd=%vd_sp dp=0
62VCVT        1111 1110 1.11 11 rm:2 .... 1011 op:1 1.0 .... \
63            vm=%vm_dp vd=%vd_sp dp=1
64