1 /*
2 * QTest testcase for Q35 northbridge
3 *
4 * Copyright (c) 2015 Red Hat, Inc.
5 *
6 * Author: Gerd Hoffmann <kraxel@redhat.com>
7 *
8 * This work is licensed under the terms of the GNU GPL, version 2 or later.
9 * See the COPYING file in the top-level directory.
10 */
11
12 #include "qemu/osdep.h"
13 #include "libqtest.h"
14 #include "libqos/pci.h"
15 #include "libqos/pci-pc.h"
16 #include "hw/pci-host/q35.h"
17 #include "qapi/qmp/qdict.h"
18
19 #define TSEG_SIZE_TEST_GUEST_RAM_MBYTES 128
20
21 /* @esmramc_tseg_sz: ESMRAMC.TSEG_SZ bitmask for selecting the requested TSEG
22 * size. Must be a subset of
23 * MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK.
24 *
25 * @extended_tseg_mbytes: Size of the extended TSEG. Only consulted if
26 * @esmramc_tseg_sz equals
27 * MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK precisely.
28 *
29 * @expected_tseg_mbytes: Expected guest-visible TSEG size in megabytes,
30 * matching @esmramc_tseg_sz and @extended_tseg_mbytes
31 * above.
32 */
33 struct TsegSizeArgs {
34 uint8_t esmramc_tseg_sz;
35 uint16_t extended_tseg_mbytes;
36 uint16_t expected_tseg_mbytes;
37 };
38 typedef struct TsegSizeArgs TsegSizeArgs;
39
40 static const TsegSizeArgs tseg_1mb = {
41 .esmramc_tseg_sz = MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB,
42 .extended_tseg_mbytes = 0,
43 .expected_tseg_mbytes = 1,
44 };
45 static const TsegSizeArgs tseg_2mb = {
46 .esmramc_tseg_sz = MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB,
47 .extended_tseg_mbytes = 0,
48 .expected_tseg_mbytes = 2,
49 };
50 static const TsegSizeArgs tseg_8mb = {
51 .esmramc_tseg_sz = MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB,
52 .extended_tseg_mbytes = 0,
53 .expected_tseg_mbytes = 8,
54 };
55 static const TsegSizeArgs tseg_ext_16mb = {
56 .esmramc_tseg_sz = MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK,
57 .extended_tseg_mbytes = 16,
58 .expected_tseg_mbytes = 16,
59 };
60
smram_set_bit(QPCIDevice * pcidev,uint8_t mask,bool enabled)61 static void smram_set_bit(QPCIDevice *pcidev, uint8_t mask, bool enabled)
62 {
63 uint8_t smram;
64
65 smram = qpci_config_readb(pcidev, MCH_HOST_BRIDGE_SMRAM);
66 if (enabled) {
67 smram |= mask;
68 } else {
69 smram &= ~mask;
70 }
71 qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_SMRAM, smram);
72 }
73
smram_test_bit(QPCIDevice * pcidev,uint8_t mask)74 static bool smram_test_bit(QPCIDevice *pcidev, uint8_t mask)
75 {
76 uint8_t smram;
77
78 smram = qpci_config_readb(pcidev, MCH_HOST_BRIDGE_SMRAM);
79 return smram & mask;
80 }
81
test_smram_lock(void)82 static void test_smram_lock(void)
83 {
84 QPCIBus *pcibus;
85 QPCIDevice *pcidev;
86 QDict *response;
87 QTestState *qts;
88
89 qts = qtest_init("-M q35");
90
91 pcibus = qpci_new_pc(qts, NULL);
92 g_assert(pcibus != NULL);
93
94 pcidev = qpci_device_find(pcibus, 0);
95 g_assert(pcidev != NULL);
96
97 /* check open is settable */
98 smram_set_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN, false);
99 g_assert(smram_test_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN) == false);
100 smram_set_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN, true);
101 g_assert(smram_test_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN) == true);
102
103 /* lock, check open is cleared & not settable */
104 smram_set_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_LCK, true);
105 g_assert(smram_test_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN) == false);
106 smram_set_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN, true);
107 g_assert(smram_test_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN) == false);
108
109 /* reset */
110 response = qtest_qmp(qts, "{'execute': 'system_reset', 'arguments': {} }");
111 g_assert(response);
112 g_assert(!qdict_haskey(response, "error"));
113 qobject_unref(response);
114
115 /* check open is settable again */
116 smram_set_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN, false);
117 g_assert(smram_test_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN) == false);
118 smram_set_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN, true);
119 g_assert(smram_test_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN) == true);
120
121 g_free(pcidev);
122 qpci_free_pc(pcibus);
123
124 qtest_quit(qts);
125 }
126
test_tseg_size(const void * data)127 static void test_tseg_size(const void *data)
128 {
129 const TsegSizeArgs *args = data;
130 QPCIBus *pcibus;
131 QPCIDevice *pcidev;
132 uint8_t smram_val;
133 uint8_t esmramc_val;
134 uint32_t ram_offs;
135 QTestState *qts;
136
137 if (args->esmramc_tseg_sz == MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) {
138 qts = qtest_initf("-M q35 -m %uM -global mch.extended-tseg-mbytes=%u",
139 TSEG_SIZE_TEST_GUEST_RAM_MBYTES,
140 args->extended_tseg_mbytes);
141 } else {
142 qts = qtest_initf("-M q35 -m %uM", TSEG_SIZE_TEST_GUEST_RAM_MBYTES);
143 }
144
145 /* locate the DRAM controller */
146 pcibus = qpci_new_pc(qts, NULL);
147 g_assert(pcibus != NULL);
148 pcidev = qpci_device_find(pcibus, 0);
149 g_assert(pcidev != NULL);
150
151 /* Set TSEG size. Restrict TSEG visibility to SMM by setting T_EN. */
152 esmramc_val = qpci_config_readb(pcidev, MCH_HOST_BRIDGE_ESMRAMC);
153 esmramc_val &= ~MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK;
154 esmramc_val |= args->esmramc_tseg_sz;
155 esmramc_val |= MCH_HOST_BRIDGE_ESMRAMC_T_EN;
156 qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_ESMRAMC, esmramc_val);
157
158 /* Enable TSEG by setting G_SMRAME. Close TSEG by setting D_CLS. */
159 smram_val = qpci_config_readb(pcidev, MCH_HOST_BRIDGE_SMRAM);
160 smram_val &= ~(MCH_HOST_BRIDGE_SMRAM_D_OPEN |
161 MCH_HOST_BRIDGE_SMRAM_D_LCK);
162 smram_val |= (MCH_HOST_BRIDGE_SMRAM_D_CLS |
163 MCH_HOST_BRIDGE_SMRAM_G_SMRAME);
164 qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_SMRAM, smram_val);
165
166 /* lock TSEG */
167 smram_val |= MCH_HOST_BRIDGE_SMRAM_D_LCK;
168 qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_SMRAM, smram_val);
169
170 /* Now check that the byte right before the TSEG is r/w, and that the first
171 * byte in the TSEG always reads as 0xff.
172 */
173 ram_offs = (TSEG_SIZE_TEST_GUEST_RAM_MBYTES - args->expected_tseg_mbytes) *
174 1024 * 1024 - 1;
175 g_assert_cmpint(qtest_readb(qts, ram_offs), ==, 0);
176 qtest_writeb(qts, ram_offs, 1);
177 g_assert_cmpint(qtest_readb(qts, ram_offs), ==, 1);
178
179 ram_offs++;
180 g_assert_cmpint(qtest_readb(qts, ram_offs), ==, 0xff);
181 qtest_writeb(qts, ram_offs, 1);
182 g_assert_cmpint(qtest_readb(qts, ram_offs), ==, 0xff);
183
184 g_free(pcidev);
185 qpci_free_pc(pcibus);
186 qtest_quit(qts);
187 }
188
main(int argc,char ** argv)189 int main(int argc, char **argv)
190 {
191 g_test_init(&argc, &argv, NULL);
192
193 qtest_add_func("/q35/smram/lock", test_smram_lock);
194
195 qtest_add_data_func("/q35/tseg-size/1mb", &tseg_1mb, test_tseg_size);
196 qtest_add_data_func("/q35/tseg-size/2mb", &tseg_2mb, test_tseg_size);
197 qtest_add_data_func("/q35/tseg-size/8mb", &tseg_8mb, test_tseg_size);
198 qtest_add_data_func("/q35/tseg-size/ext/16mb", &tseg_ext_16mb,
199 test_tseg_size);
200 return g_test_run();
201 }
202