1
2/* Capstone Disassembly Engine, http://www.capstone-engine.org */
3/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
4
5/*===- TableGen'erated file -------------------------------------*- C++ -*-===*|*                                                                            *|
6|* Target Register Enum Values                                                 *|
7|*                                                                            *|
8|* Automatically generated file, do not edit!                                 *|
9|*                                                                            *|
10\*===----------------------------------------------------------------------===*/
11
12#ifdef GET_REGINFO_ENUM
13#undef GET_REGINFO_ENUM
14
15enum {
16  X86_NoRegister,
17  X86_AH = 1,
18  X86_AL = 2,
19  X86_AX = 3,
20  X86_BH = 4,
21  X86_BL = 5,
22  X86_BP = 6,
23  X86_BPH = 7,
24  X86_BPL = 8,
25  X86_BX = 9,
26  X86_CH = 10,
27  X86_CL = 11,
28  X86_CS = 12,
29  X86_CX = 13,
30  X86_DF = 14,
31  X86_DH = 15,
32  X86_DI = 16,
33  X86_DIH = 17,
34  X86_DIL = 18,
35  X86_DL = 19,
36  X86_DS = 20,
37  X86_DX = 21,
38  X86_EAX = 22,
39  X86_EBP = 23,
40  X86_EBX = 24,
41  X86_ECX = 25,
42  X86_EDI = 26,
43  X86_EDX = 27,
44  X86_EFLAGS = 28,
45  X86_EIP = 29,
46  X86_EIZ = 30,
47  X86_ES = 31,
48  X86_ESI = 32,
49  X86_ESP = 33,
50  X86_FPSW = 34,
51  X86_FS = 35,
52  X86_GS = 36,
53  X86_HAX = 37,
54  X86_HBP = 38,
55  X86_HBX = 39,
56  X86_HCX = 40,
57  X86_HDI = 41,
58  X86_HDX = 42,
59  X86_HIP = 43,
60  X86_HSI = 44,
61  X86_HSP = 45,
62  X86_IP = 46,
63  X86_RAX = 47,
64  X86_RBP = 48,
65  X86_RBX = 49,
66  X86_RCX = 50,
67  X86_RDI = 51,
68  X86_RDX = 52,
69  X86_RIP = 53,
70  X86_RIZ = 54,
71  X86_RSI = 55,
72  X86_RSP = 56,
73  X86_SI = 57,
74  X86_SIH = 58,
75  X86_SIL = 59,
76  X86_SP = 60,
77  X86_SPH = 61,
78  X86_SPL = 62,
79  X86_SS = 63,
80  X86_SSP = 64,
81  X86_BND0 = 65,
82  X86_BND1 = 66,
83  X86_BND2 = 67,
84  X86_BND3 = 68,
85  X86_CR0 = 69,
86  X86_CR1 = 70,
87  X86_CR2 = 71,
88  X86_CR3 = 72,
89  X86_CR4 = 73,
90  X86_CR5 = 74,
91  X86_CR6 = 75,
92  X86_CR7 = 76,
93  X86_CR8 = 77,
94  X86_CR9 = 78,
95  X86_CR10 = 79,
96  X86_CR11 = 80,
97  X86_CR12 = 81,
98  X86_CR13 = 82,
99  X86_CR14 = 83,
100  X86_CR15 = 84,
101  X86_DR0 = 85,
102  X86_DR1 = 86,
103  X86_DR2 = 87,
104  X86_DR3 = 88,
105  X86_DR4 = 89,
106  X86_DR5 = 90,
107  X86_DR6 = 91,
108  X86_DR7 = 92,
109  X86_DR8 = 93,
110  X86_DR9 = 94,
111  X86_DR10 = 95,
112  X86_DR11 = 96,
113  X86_DR12 = 97,
114  X86_DR13 = 98,
115  X86_DR14 = 99,
116  X86_DR15 = 100,
117  X86_FP0 = 101,
118  X86_FP1 = 102,
119  X86_FP2 = 103,
120  X86_FP3 = 104,
121  X86_FP4 = 105,
122  X86_FP5 = 106,
123  X86_FP6 = 107,
124  X86_FP7 = 108,
125  X86_K0 = 109,
126  X86_K1 = 110,
127  X86_K2 = 111,
128  X86_K3 = 112,
129  X86_K4 = 113,
130  X86_K5 = 114,
131  X86_K6 = 115,
132  X86_K7 = 116,
133  X86_MM0 = 117,
134  X86_MM1 = 118,
135  X86_MM2 = 119,
136  X86_MM3 = 120,
137  X86_MM4 = 121,
138  X86_MM5 = 122,
139  X86_MM6 = 123,
140  X86_MM7 = 124,
141  X86_R8 = 125,
142  X86_R9 = 126,
143  X86_R10 = 127,
144  X86_R11 = 128,
145  X86_R12 = 129,
146  X86_R13 = 130,
147  X86_R14 = 131,
148  X86_R15 = 132,
149  X86_ST0 = 133,
150  X86_ST1 = 134,
151  X86_ST2 = 135,
152  X86_ST3 = 136,
153  X86_ST4 = 137,
154  X86_ST5 = 138,
155  X86_ST6 = 139,
156  X86_ST7 = 140,
157  X86_XMM0 = 141,
158  X86_XMM1 = 142,
159  X86_XMM2 = 143,
160  X86_XMM3 = 144,
161  X86_XMM4 = 145,
162  X86_XMM5 = 146,
163  X86_XMM6 = 147,
164  X86_XMM7 = 148,
165  X86_XMM8 = 149,
166  X86_XMM9 = 150,
167  X86_XMM10 = 151,
168  X86_XMM11 = 152,
169  X86_XMM12 = 153,
170  X86_XMM13 = 154,
171  X86_XMM14 = 155,
172  X86_XMM15 = 156,
173  X86_XMM16 = 157,
174  X86_XMM17 = 158,
175  X86_XMM18 = 159,
176  X86_XMM19 = 160,
177  X86_XMM20 = 161,
178  X86_XMM21 = 162,
179  X86_XMM22 = 163,
180  X86_XMM23 = 164,
181  X86_XMM24 = 165,
182  X86_XMM25 = 166,
183  X86_XMM26 = 167,
184  X86_XMM27 = 168,
185  X86_XMM28 = 169,
186  X86_XMM29 = 170,
187  X86_XMM30 = 171,
188  X86_XMM31 = 172,
189  X86_YMM0 = 173,
190  X86_YMM1 = 174,
191  X86_YMM2 = 175,
192  X86_YMM3 = 176,
193  X86_YMM4 = 177,
194  X86_YMM5 = 178,
195  X86_YMM6 = 179,
196  X86_YMM7 = 180,
197  X86_YMM8 = 181,
198  X86_YMM9 = 182,
199  X86_YMM10 = 183,
200  X86_YMM11 = 184,
201  X86_YMM12 = 185,
202  X86_YMM13 = 186,
203  X86_YMM14 = 187,
204  X86_YMM15 = 188,
205  X86_YMM16 = 189,
206  X86_YMM17 = 190,
207  X86_YMM18 = 191,
208  X86_YMM19 = 192,
209  X86_YMM20 = 193,
210  X86_YMM21 = 194,
211  X86_YMM22 = 195,
212  X86_YMM23 = 196,
213  X86_YMM24 = 197,
214  X86_YMM25 = 198,
215  X86_YMM26 = 199,
216  X86_YMM27 = 200,
217  X86_YMM28 = 201,
218  X86_YMM29 = 202,
219  X86_YMM30 = 203,
220  X86_YMM31 = 204,
221  X86_ZMM0 = 205,
222  X86_ZMM1 = 206,
223  X86_ZMM2 = 207,
224  X86_ZMM3 = 208,
225  X86_ZMM4 = 209,
226  X86_ZMM5 = 210,
227  X86_ZMM6 = 211,
228  X86_ZMM7 = 212,
229  X86_ZMM8 = 213,
230  X86_ZMM9 = 214,
231  X86_ZMM10 = 215,
232  X86_ZMM11 = 216,
233  X86_ZMM12 = 217,
234  X86_ZMM13 = 218,
235  X86_ZMM14 = 219,
236  X86_ZMM15 = 220,
237  X86_ZMM16 = 221,
238  X86_ZMM17 = 222,
239  X86_ZMM18 = 223,
240  X86_ZMM19 = 224,
241  X86_ZMM20 = 225,
242  X86_ZMM21 = 226,
243  X86_ZMM22 = 227,
244  X86_ZMM23 = 228,
245  X86_ZMM24 = 229,
246  X86_ZMM25 = 230,
247  X86_ZMM26 = 231,
248  X86_ZMM27 = 232,
249  X86_ZMM28 = 233,
250  X86_ZMM29 = 234,
251  X86_ZMM30 = 235,
252  X86_ZMM31 = 236,
253  X86_R8B = 237,
254  X86_R9B = 238,
255  X86_R10B = 239,
256  X86_R11B = 240,
257  X86_R12B = 241,
258  X86_R13B = 242,
259  X86_R14B = 243,
260  X86_R15B = 244,
261  X86_R8BH = 245,
262  X86_R9BH = 246,
263  X86_R10BH = 247,
264  X86_R11BH = 248,
265  X86_R12BH = 249,
266  X86_R13BH = 250,
267  X86_R14BH = 251,
268  X86_R15BH = 252,
269  X86_R8D = 253,
270  X86_R9D = 254,
271  X86_R10D = 255,
272  X86_R11D = 256,
273  X86_R12D = 257,
274  X86_R13D = 258,
275  X86_R14D = 259,
276  X86_R15D = 260,
277  X86_R8W = 261,
278  X86_R9W = 262,
279  X86_R10W = 263,
280  X86_R11W = 264,
281  X86_R12W = 265,
282  X86_R13W = 266,
283  X86_R14W = 267,
284  X86_R15W = 268,
285  X86_R8WH = 269,
286  X86_R9WH = 270,
287  X86_R10WH = 271,
288  X86_R11WH = 272,
289  X86_R12WH = 273,
290  X86_R13WH = 274,
291  X86_R14WH = 275,
292  X86_R15WH = 276,
293  X86_NUM_TARGET_REGS 	// 277
294};
295
296// Register classes
297enum {
298  X86_GR8RegClassID = 0,
299  X86_GRH8RegClassID = 1,
300  X86_GR8_NOREXRegClassID = 2,
301  X86_GR8_ABCD_HRegClassID = 3,
302  X86_GR8_ABCD_LRegClassID = 4,
303  X86_GRH16RegClassID = 5,
304  X86_GR16RegClassID = 6,
305  X86_GR16_NOREXRegClassID = 7,
306  X86_VK1RegClassID = 8,
307  X86_VK16RegClassID = 9,
308  X86_VK2RegClassID = 10,
309  X86_VK4RegClassID = 11,
310  X86_VK8RegClassID = 12,
311  X86_VK16WMRegClassID = 13,
312  X86_VK1WMRegClassID = 14,
313  X86_VK2WMRegClassID = 15,
314  X86_VK4WMRegClassID = 16,
315  X86_VK8WMRegClassID = 17,
316  X86_SEGMENT_REGRegClassID = 18,
317  X86_GR16_ABCDRegClassID = 19,
318  X86_FPCCRRegClassID = 20,
319  X86_FR32XRegClassID = 21,
320  X86_LOW32_ADDR_ACCESS_RBPRegClassID = 22,
321  X86_LOW32_ADDR_ACCESSRegClassID = 23,
322  X86_LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID = 24,
323  X86_DEBUG_REGRegClassID = 25,
324  X86_FR32RegClassID = 26,
325  X86_GR32RegClassID = 27,
326  X86_GR32_NOSPRegClassID = 28,
327  X86_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID = 29,
328  X86_GR32_NOREXRegClassID = 30,
329  X86_VK32RegClassID = 31,
330  X86_GR32_NOREX_NOSPRegClassID = 32,
331  X86_RFP32RegClassID = 33,
332  X86_VK32WMRegClassID = 34,
333  X86_GR32_ABCDRegClassID = 35,
334  X86_GR32_TCRegClassID = 36,
335  X86_GR32_ADRegClassID = 37,
336  X86_LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID = 38,
337  X86_CCRRegClassID = 39,
338  X86_DFCCRRegClassID = 40,
339  X86_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID = 41,
340  X86_LOW32_ADDR_ACCESS_with_sub_32bitRegClassID = 42,
341  X86_RFP64RegClassID = 43,
342  X86_FR64XRegClassID = 44,
343  X86_GR64RegClassID = 45,
344  X86_CONTROL_REGRegClassID = 46,
345  X86_FR64RegClassID = 47,
346  X86_GR64_with_sub_8bitRegClassID = 48,
347  X86_GR64_NOSPRegClassID = 49,
348  X86_GR64_NOREXRegClassID = 50,
349  X86_GR64_TCRegClassID = 51,
350  X86_GR64_NOSP_and_GR64_TCRegClassID = 52,
351  X86_GR64_TCW64RegClassID = 53,
352  X86_GR64_with_sub_16bit_in_GR16_NOREXRegClassID = 54,
353  X86_VK64RegClassID = 55,
354  X86_VR64RegClassID = 56,
355  X86_GR64_NOREX_NOSPRegClassID = 57,
356  X86_GR64_NOSP_and_GR64_TCW64RegClassID = 58,
357  X86_GR64_TC_and_GR64_TCW64RegClassID = 59,
358  X86_VK64WMRegClassID = 60,
359  X86_GR64_NOREX_and_GR64_TCRegClassID = 61,
360  X86_GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID = 62,
361  X86_GR64_NOREX_NOSP_and_GR64_TCRegClassID = 63,
362  X86_GR64_ABCDRegClassID = 64,
363  X86_GR64_NOREX_and_GR64_TCW64RegClassID = 65,
364  X86_GR64_with_sub_32bit_in_GR32_TCRegClassID = 66,
365  X86_GR64_ADRegClassID = 67,
366  X86_GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID = 68,
367  X86_GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBPRegClassID = 69,
368  X86_GR64_and_LOW32_ADDR_ACCESSRegClassID = 70,
369  X86_RSTRegClassID = 71,
370  X86_RFP80RegClassID = 72,
371  X86_VR128XRegClassID = 73,
372  X86_VR128RegClassID = 74,
373  X86_VR128HRegClassID = 75,
374  X86_VR128LRegClassID = 76,
375  X86_BNDRRegClassID = 77,
376  X86_VR256XRegClassID = 78,
377  X86_VR256RegClassID = 79,
378  X86_VR256HRegClassID = 80,
379  X86_VR256LRegClassID = 81,
380  X86_VR512RegClassID = 82,
381  X86_VR512_with_sub_xmm_in_FR32RegClassID = 83,
382  X86_VR512_with_sub_xmm_in_VR128HRegClassID = 84,
383  X86_VR512_with_sub_xmm_in_VR128LRegClassID = 85,
384};
385#endif // GET_REGINFO_ENUM
386
387#ifdef GET_REGINFO_MC_DESC
388#define GET_REGINFO_MC_DESC
389
390
391static const MCPhysReg X86RegDiffLists[] = {
392  /* 0 */ 0, 1, 0,
393  /* 3 */ 64875, 1, 1, 0,
394  /* 7 */ 65259, 1, 1, 0,
395  /* 11 */ 65397, 1, 1, 0,
396  /* 15 */ 65466, 1, 1, 0,
397  /* 19 */ 2, 1, 0,
398  /* 22 */ 4, 1, 0,
399  /* 25 */ 6, 1, 0,
400  /* 28 */ 11, 1, 0,
401  /* 31 */ 22, 1, 0,
402  /* 34 */ 26, 1, 0,
403  /* 37 */ 29, 1, 0,
404  /* 40 */ 64851, 1, 0,
405  /* 43 */ 10, 3, 0,
406  /* 46 */ 4, 0,
407  /* 48 */ 5, 0,
408  /* 50 */ 65292, 1, 7, 0,
409  /* 54 */ 65417, 1, 7, 0,
410  /* 58 */ 10, 3, 7, 0,
411  /* 62 */ 65512, 8, 0,
412  /* 65 */ 65342, 1, 11, 0,
413  /* 69 */ 65348, 1, 11, 0,
414  /* 73 */ 65442, 1, 11, 0,
415  /* 77 */ 65448, 1, 11, 0,
416  /* 81 */ 12, 0,
417  /* 83 */ 65342, 1, 14, 0,
418  /* 87 */ 65348, 1, 14, 0,
419  /* 91 */ 65442, 1, 14, 0,
420  /* 95 */ 65448, 1, 14, 0,
421  /* 99 */ 21, 0,
422  /* 101 */ 22, 0,
423  /* 103 */ 65534, 65509, 23, 0,
424  /* 107 */ 65535, 65509, 23, 0,
425  /* 111 */ 65534, 65511, 23, 0,
426  /* 115 */ 65535, 65511, 23, 0,
427  /* 119 */ 65524, 23, 0,
428  /* 122 */ 128, 8, 65512, 8, 24, 0,
429  /* 128 */ 65519, 24, 0,
430  /* 131 */ 65522, 24, 0,
431  /* 134 */ 65511, 65526, 2, 65535, 24, 0,
432  /* 140 */ 2, 6, 25, 0,
433  /* 144 */ 6, 6, 25, 0,
434  /* 148 */ 65534, 10, 25, 0,
435  /* 152 */ 65535, 10, 25, 0,
436  /* 156 */ 2, 12, 25, 0,
437  /* 160 */ 3, 12, 25, 0,
438  /* 164 */ 4, 15, 25, 0,
439  /* 168 */ 5, 15, 25, 0,
440  /* 172 */ 65534, 17, 25, 0,
441  /* 176 */ 65535, 17, 25, 0,
442  /* 180 */ 1, 19, 25, 0,
443  /* 184 */ 2, 19, 25, 0,
444  /* 188 */ 65521, 25, 0,
445  /* 191 */ 26, 0,
446  /* 193 */ 65511, 65530, 65534, 65532, 27, 0,
447  /* 199 */ 65511, 65524, 65534, 65535, 30, 0,
448  /* 205 */ 65511, 65519, 2, 65535, 31, 0,
449  /* 211 */ 32, 32, 0,
450  /* 214 */ 65511, 65521, 65532, 65535, 35, 0,
451  /* 220 */ 65511, 65517, 65535, 65535, 36, 0,
452  /* 226 */ 64829, 0,
453  /* 228 */ 64900, 0,
454  /* 230 */ 64923, 0,
455  /* 232 */ 65131, 0,
456  /* 234 */ 65520, 65408, 0,
457  /* 237 */ 16, 65528, 65408, 0,
458  /* 241 */ 24, 65528, 65408, 0,
459  /* 245 */ 65430, 0,
460  /* 247 */ 65432, 0,
461  /* 249 */ 65461, 0,
462  /* 251 */ 65493, 0,
463  /* 253 */ 65504, 65504, 0,
464  /* 256 */ 65509, 0,
465  /* 258 */ 65511, 0,
466  /* 260 */ 65514, 0,
467  /* 262 */ 65513, 27, 2, 65535, 65520, 0,
468  /* 268 */ 65513, 25, 2, 65535, 65522, 0,
469  /* 274 */ 65525, 0,
470  /* 276 */ 65530, 0,
471  /* 278 */ 65531, 0,
472  /* 280 */ 65534, 65532, 0,
473  /* 283 */ 65512, 17, 65533, 0,
474  /* 287 */ 65534, 0,
475  /* 289 */ 2, 65535, 0,
476  /* 292 */ 65532, 65535, 0,
477  /* 295 */ 65534, 65535, 0,
478  /* 298 */ 65535, 65535, 0,
479};
480
481static const uint16_t X86SubRegIdxLists[] = {
482  /* 0 */ 1, 2, 0,
483  /* 3 */ 1, 3, 0,
484  /* 6 */ 6, 4, 1, 2, 5, 0,
485  /* 12 */ 6, 4, 1, 3, 5, 0,
486  /* 18 */ 6, 4, 5, 0,
487  /* 22 */ 8, 7, 0,
488};
489
490static const MCRegisterDesc X86RegDesc[] = {
491  { 5, 0, 0, 0, 0, 0 },
492  { 873, 2, 184, 2, 4641, 0 },
493  { 1014, 2, 180, 2, 4641, 0 },
494  { 1148, 298, 181, 0, 0, 2 },
495  { 879, 2, 168, 2, 4593, 0 },
496  { 1017, 2, 164, 2, 4593, 0 },
497  { 1043, 289, 173, 3, 352, 5 },
498  { 936, 2, 176, 2, 768, 0 },
499  { 1034, 2, 172, 2, 736, 0 },
500  { 1160, 292, 165, 0, 304, 2 },
501  { 922, 2, 160, 2, 4497, 0 },
502  { 1020, 2, 156, 2, 4497, 0 },
503  { 1082, 2, 2, 2, 4497, 0 },
504  { 1172, 295, 157, 0, 400, 2 },
505  { 870, 2, 2, 2, 4449, 0 },
506  { 925, 2, 144, 2, 4449, 0 },
507  { 991, 289, 149, 3, 448, 5 },
508  { 928, 2, 152, 2, 1296, 0 },
509  { 1026, 2, 148, 2, 4130, 0 },
510  { 1023, 2, 140, 2, 4417, 0 },
511  { 1085, 2, 2, 2, 4417, 0 },
512  { 1184, 280, 141, 0, 688, 2 },
513  { 1147, 221, 142, 7, 1524, 8 },
514  { 1042, 206, 142, 13, 1236, 12 },
515  { 1159, 215, 142, 7, 1460, 8 },
516  { 1171, 200, 142, 7, 1172, 8 },
517  { 990, 135, 142, 13, 869, 12 },
518  { 1183, 194, 142, 7, 928, 8 },
519  { 1094, 2, 2, 2, 1584, 0 },
520  { 1054, 284, 126, 19, 496, 16 },
521  { 1195, 2, 2, 2, 4417, 0 },
522  { 1088, 2, 2, 2, 4417, 0 },
523  { 1002, 269, 105, 13, 243, 12 },
524  { 1066, 263, 105, 13, 243, 12 },
525  { 1142, 2, 2, 2, 4593, 0 },
526  { 1091, 2, 2, 2, 4593, 0 },
527  { 1098, 2, 2, 2, 4593, 0 },
528  { 1151, 2, 188, 2, 4161, 0 },
529  { 1046, 2, 188, 2, 4161, 0 },
530  { 1163, 2, 188, 2, 4161, 0 },
531  { 1175, 2, 188, 2, 4161, 0 },
532  { 994, 2, 188, 2, 4161, 0 },
533  { 1187, 2, 188, 2, 4161, 0 },
534  { 1058, 2, 131, 2, 3923, 0 },
535  { 1006, 2, 119, 2, 3955, 0 },
536  { 1070, 2, 119, 2, 3955, 0 },
537  { 1055, 2, 128, 2, 1616, 0 },
538  { 1155, 220, 2, 6, 1396, 8 },
539  { 1050, 205, 2, 12, 1108, 12 },
540  { 1167, 214, 2, 6, 1332, 8 },
541  { 1179, 199, 2, 6, 1044, 8 },
542  { 998, 134, 2, 12, 805, 12 },
543  { 1191, 193, 2, 6, 928, 8 },
544  { 1062, 283, 2, 18, 496, 16 },
545  { 1199, 2, 2, 2, 3488, 0 },
546  { 1010, 268, 2, 12, 179, 12 },
547  { 1074, 262, 2, 12, 179, 12 },
548  { 1003, 289, 112, 3, 544, 5 },
549  { 932, 2, 115, 2, 3152, 0 },
550  { 1030, 2, 111, 2, 3056, 0 },
551  { 1067, 289, 104, 3, 592, 5 },
552  { 940, 2, 107, 2, 3248, 0 },
553  { 1038, 2, 103, 2, 3719, 0 },
554  { 1101, 2, 2, 2, 4097, 0 },
555  { 1078, 2, 2, 2, 4097, 0 },
556  { 64, 2, 2, 2, 4097, 0 },
557  { 167, 2, 2, 2, 4097, 0 },
558  { 252, 2, 2, 2, 4097, 0 },
559  { 337, 2, 2, 2, 4097, 0 },
560  { 91, 2, 2, 2, 4097, 0 },
561  { 194, 2, 2, 2, 4097, 0 },
562  { 279, 2, 2, 2, 4097, 0 },
563  { 364, 2, 2, 2, 4097, 0 },
564  { 444, 2, 2, 2, 4097, 0 },
565  { 524, 2, 2, 2, 4097, 0 },
566  { 594, 2, 2, 2, 4097, 0 },
567  { 664, 2, 2, 2, 4097, 0 },
568  { 727, 2, 2, 2, 4097, 0 },
569  { 786, 2, 2, 2, 4097, 0 },
570  { 18, 2, 2, 2, 4097, 0 },
571  { 121, 2, 2, 2, 4097, 0 },
572  { 224, 2, 2, 2, 4097, 0 },
573  { 309, 2, 2, 2, 4097, 0 },
574  { 394, 2, 2, 2, 4097, 0 },
575  { 474, 2, 2, 2, 4097, 0 },
576  { 95, 2, 2, 2, 4097, 0 },
577  { 198, 2, 2, 2, 4097, 0 },
578  { 283, 2, 2, 2, 4097, 0 },
579  { 368, 2, 2, 2, 4097, 0 },
580  { 448, 2, 2, 2, 4097, 0 },
581  { 528, 2, 2, 2, 4097, 0 },
582  { 598, 2, 2, 2, 4097, 0 },
583  { 668, 2, 2, 2, 4097, 0 },
584  { 731, 2, 2, 2, 4097, 0 },
585  { 790, 2, 2, 2, 4097, 0 },
586  { 23, 2, 2, 2, 4097, 0 },
587  { 126, 2, 2, 2, 4097, 0 },
588  { 229, 2, 2, 2, 4097, 0 },
589  { 314, 2, 2, 2, 4097, 0 },
590  { 399, 2, 2, 2, 4097, 0 },
591  { 479, 2, 2, 2, 4097, 0 },
592  { 87, 2, 2, 2, 4097, 0 },
593  { 190, 2, 2, 2, 4097, 0 },
594  { 275, 2, 2, 2, 4097, 0 },
595  { 360, 2, 2, 2, 4097, 0 },
596  { 440, 2, 2, 2, 4097, 0 },
597  { 520, 2, 2, 2, 4097, 0 },
598  { 590, 2, 2, 2, 4097, 0 },
599  { 660, 2, 2, 2, 4097, 0 },
600  { 69, 2, 2, 2, 4097, 0 },
601  { 172, 2, 2, 2, 4097, 0 },
602  { 257, 2, 2, 2, 4097, 0 },
603  { 342, 2, 2, 2, 4097, 0 },
604  { 422, 2, 2, 2, 4097, 0 },
605  { 502, 2, 2, 2, 4097, 0 },
606  { 572, 2, 2, 2, 4097, 0 },
607  { 642, 2, 2, 2, 4097, 0 },
608  { 73, 2, 2, 2, 4097, 0 },
609  { 176, 2, 2, 2, 4097, 0 },
610  { 261, 2, 2, 2, 4097, 0 },
611  { 346, 2, 2, 2, 4097, 0 },
612  { 426, 2, 2, 2, 4097, 0 },
613  { 506, 2, 2, 2, 4097, 0 },
614  { 576, 2, 2, 2, 4097, 0 },
615  { 646, 2, 2, 2, 4097, 0 },
616  { 728, 122, 2, 12, 115, 12 },
617  { 787, 122, 2, 12, 115, 12 },
618  { 19, 122, 2, 12, 115, 12 },
619  { 122, 122, 2, 12, 115, 12 },
620  { 225, 122, 2, 12, 115, 12 },
621  { 310, 122, 2, 12, 115, 12 },
622  { 395, 122, 2, 12, 115, 12 },
623  { 475, 122, 2, 12, 115, 12 },
624  { 99, 2, 2, 2, 4385, 0 },
625  { 202, 2, 2, 2, 4385, 0 },
626  { 287, 2, 2, 2, 4385, 0 },
627  { 372, 2, 2, 2, 4385, 0 },
628  { 452, 2, 2, 2, 4385, 0 },
629  { 532, 2, 2, 2, 4385, 0 },
630  { 602, 2, 2, 2, 4385, 0 },
631  { 672, 2, 2, 2, 4385, 0 },
632  { 72, 2, 211, 2, 4385, 0 },
633  { 175, 2, 211, 2, 4385, 0 },
634  { 260, 2, 211, 2, 4385, 0 },
635  { 345, 2, 211, 2, 4385, 0 },
636  { 425, 2, 211, 2, 4385, 0 },
637  { 505, 2, 211, 2, 4385, 0 },
638  { 575, 2, 211, 2, 4385, 0 },
639  { 645, 2, 211, 2, 4385, 0 },
640  { 712, 2, 211, 2, 4385, 0 },
641  { 771, 2, 211, 2, 4385, 0 },
642  { 0, 2, 211, 2, 4385, 0 },
643  { 103, 2, 211, 2, 4385, 0 },
644  { 206, 2, 211, 2, 4385, 0 },
645  { 291, 2, 211, 2, 4385, 0 },
646  { 376, 2, 211, 2, 4385, 0 },
647  { 456, 2, 211, 2, 4385, 0 },
648  { 536, 2, 211, 2, 4385, 0 },
649  { 606, 2, 211, 2, 4385, 0 },
650  { 676, 2, 211, 2, 4385, 0 },
651  { 735, 2, 211, 2, 4385, 0 },
652  { 28, 2, 211, 2, 4385, 0 },
653  { 131, 2, 211, 2, 4385, 0 },
654  { 234, 2, 211, 2, 4385, 0 },
655  { 319, 2, 211, 2, 4385, 0 },
656  { 404, 2, 211, 2, 4385, 0 },
657  { 484, 2, 211, 2, 4385, 0 },
658  { 554, 2, 211, 2, 4385, 0 },
659  { 624, 2, 211, 2, 4385, 0 },
660  { 694, 2, 211, 2, 4385, 0 },
661  { 753, 2, 211, 2, 4385, 0 },
662  { 46, 2, 211, 2, 4385, 0 },
663  { 149, 2, 211, 2, 4385, 0 },
664  { 77, 254, 212, 23, 4017, 19 },
665  { 180, 254, 212, 23, 4017, 19 },
666  { 265, 254, 212, 23, 4017, 19 },
667  { 350, 254, 212, 23, 4017, 19 },
668  { 430, 254, 212, 23, 4017, 19 },
669  { 510, 254, 212, 23, 4017, 19 },
670  { 580, 254, 212, 23, 4017, 19 },
671  { 650, 254, 212, 23, 4017, 19 },
672  { 717, 254, 212, 23, 4017, 19 },
673  { 776, 254, 212, 23, 4017, 19 },
674  { 6, 254, 212, 23, 4017, 19 },
675  { 109, 254, 212, 23, 4017, 19 },
676  { 212, 254, 212, 23, 4017, 19 },
677  { 297, 254, 212, 23, 4017, 19 },
678  { 382, 254, 212, 23, 4017, 19 },
679  { 462, 254, 212, 23, 4017, 19 },
680  { 542, 254, 212, 23, 4017, 19 },
681  { 612, 254, 212, 23, 4017, 19 },
682  { 682, 254, 212, 23, 4017, 19 },
683  { 741, 254, 212, 23, 4017, 19 },
684  { 34, 254, 212, 23, 4017, 19 },
685  { 137, 254, 212, 23, 4017, 19 },
686  { 240, 254, 212, 23, 4017, 19 },
687  { 325, 254, 212, 23, 4017, 19 },
688  { 410, 254, 212, 23, 4017, 19 },
689  { 490, 254, 212, 23, 4017, 19 },
690  { 560, 254, 212, 23, 4017, 19 },
691  { 630, 254, 212, 23, 4017, 19 },
692  { 700, 254, 212, 23, 4017, 19 },
693  { 759, 254, 212, 23, 4017, 19 },
694  { 52, 254, 212, 23, 4017, 19 },
695  { 155, 254, 212, 23, 4017, 19 },
696  { 82, 253, 2, 22, 3985, 19 },
697  { 185, 253, 2, 22, 3985, 19 },
698  { 270, 253, 2, 22, 3985, 19 },
699  { 355, 253, 2, 22, 3985, 19 },
700  { 435, 253, 2, 22, 3985, 19 },
701  { 515, 253, 2, 22, 3985, 19 },
702  { 585, 253, 2, 22, 3985, 19 },
703  { 655, 253, 2, 22, 3985, 19 },
704  { 722, 253, 2, 22, 3985, 19 },
705  { 781, 253, 2, 22, 3985, 19 },
706  { 12, 253, 2, 22, 3985, 19 },
707  { 115, 253, 2, 22, 3985, 19 },
708  { 218, 253, 2, 22, 3985, 19 },
709  { 303, 253, 2, 22, 3985, 19 },
710  { 388, 253, 2, 22, 3985, 19 },
711  { 468, 253, 2, 22, 3985, 19 },
712  { 548, 253, 2, 22, 3985, 19 },
713  { 618, 253, 2, 22, 3985, 19 },
714  { 688, 253, 2, 22, 3985, 19 },
715  { 747, 253, 2, 22, 3985, 19 },
716  { 40, 253, 2, 22, 3985, 19 },
717  { 143, 253, 2, 22, 3985, 19 },
718  { 246, 253, 2, 22, 3985, 19 },
719  { 331, 253, 2, 22, 3985, 19 },
720  { 416, 253, 2, 22, 3985, 19 },
721  { 496, 253, 2, 22, 3985, 19 },
722  { 566, 253, 2, 22, 3985, 19 },
723  { 636, 253, 2, 22, 3985, 19 },
724  { 706, 253, 2, 22, 3985, 19 },
725  { 765, 253, 2, 22, 3985, 19 },
726  { 58, 253, 2, 22, 3985, 19 },
727  { 161, 253, 2, 22, 3985, 19 },
728  { 824, 2, 241, 2, 3683, 0 },
729  { 828, 2, 241, 2, 3683, 0 },
730  { 794, 2, 241, 2, 3683, 0 },
731  { 799, 2, 241, 2, 3683, 0 },
732  { 804, 2, 241, 2, 3683, 0 },
733  { 809, 2, 241, 2, 3683, 0 },
734  { 814, 2, 241, 2, 3683, 0 },
735  { 819, 2, 241, 2, 3683, 0 },
736  { 912, 2, 237, 2, 3651, 0 },
737  { 917, 2, 237, 2, 3651, 0 },
738  { 876, 2, 237, 2, 3651, 0 },
739  { 882, 2, 237, 2, 3651, 0 },
740  { 888, 2, 237, 2, 3651, 0 },
741  { 894, 2, 237, 2, 3651, 0 },
742  { 900, 2, 237, 2, 3651, 0 },
743  { 906, 2, 237, 2, 3651, 0 },
744  { 862, 123, 235, 13, 51, 12 },
745  { 866, 123, 235, 13, 51, 12 },
746  { 832, 123, 235, 13, 51, 12 },
747  { 837, 123, 235, 13, 51, 12 },
748  { 842, 123, 235, 13, 51, 12 },
749  { 847, 123, 235, 13, 51, 12 },
750  { 852, 123, 235, 13, 51, 12 },
751  { 857, 123, 235, 13, 51, 12 },
752  { 1134, 62, 238, 3, 643, 5 },
753  { 1138, 62, 238, 3, 643, 5 },
754  { 1104, 62, 238, 3, 643, 5 },
755  { 1109, 62, 238, 3, 643, 5 },
756  { 1114, 62, 238, 3, 643, 5 },
757  { 1119, 62, 238, 3, 643, 5 },
758  { 1124, 62, 238, 3, 643, 5 },
759  { 1129, 62, 238, 3, 643, 5 },
760  { 980, 2, 234, 2, 3619, 0 },
761  { 985, 2, 234, 2, 3619, 0 },
762  { 944, 2, 234, 2, 3619, 0 },
763  { 950, 2, 234, 2, 3619, 0 },
764  { 956, 2, 234, 2, 3619, 0 },
765  { 962, 2, 234, 2, 3619, 0 },
766  { 968, 2, 234, 2, 3619, 0 },
767  { 974, 2, 234, 2, 3619, 0 },
768};
769
770  // GR8 Register Class...
771  static const MCPhysReg GR8[] = {
772    X86_AL, X86_CL, X86_DL, X86_AH, X86_CH, X86_DH, X86_BL, X86_BH, X86_SIL, X86_DIL, X86_BPL, X86_SPL, X86_R8B, X86_R9B, X86_R10B, X86_R11B, X86_R14B, X86_R15B, X86_R12B, X86_R13B,
773  };
774  // GR8 Bit set.
775  static const uint8_t GR8Bits[] = {
776    0x36, 0x8d, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
777  };
778  // GRH8 Register Class...
779  static const MCPhysReg GRH8[] = {
780    X86_SIH, X86_DIH, X86_BPH, X86_SPH, X86_R8BH, X86_R9BH, X86_R10BH, X86_R11BH, X86_R12BH, X86_R13BH, X86_R14BH, X86_R15BH,
781  };
782  // GRH8 Bit set.
783  static const uint8_t GRH8Bits[] = {
784    0x80, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
785  };
786  // GR8_NOREX Register Class...
787  static const MCPhysReg GR8_NOREX[] = {
788    X86_AL, X86_CL, X86_DL, X86_AH, X86_CH, X86_DH, X86_BL, X86_BH,
789  };
790  // GR8_NOREX Bit set.
791  static const uint8_t GR8_NOREXBits[] = {
792    0x36, 0x8c, 0x08,
793  };
794  // GR8_ABCD_H Register Class...
795  static const MCPhysReg GR8_ABCD_H[] = {
796    X86_AH, X86_CH, X86_DH, X86_BH,
797  };
798  // GR8_ABCD_H Bit set.
799  static const uint8_t GR8_ABCD_HBits[] = {
800    0x12, 0x84,
801  };
802  // GR8_ABCD_L Register Class...
803  static const MCPhysReg GR8_ABCD_L[] = {
804    X86_AL, X86_CL, X86_DL, X86_BL,
805  };
806  // GR8_ABCD_L Bit set.
807  static const uint8_t GR8_ABCD_LBits[] = {
808    0x24, 0x08, 0x08,
809  };
810  // GRH16 Register Class...
811  static const MCPhysReg GRH16[] = {
812    X86_HAX, X86_HCX, X86_HDX, X86_HSI, X86_HDI, X86_HBX, X86_HBP, X86_HSP, X86_HIP, X86_R8WH, X86_R9WH, X86_R10WH, X86_R11WH, X86_R12WH, X86_R13WH, X86_R14WH, X86_R15WH,
813  };
814  // GRH16 Bit set.
815  static const uint8_t GRH16Bits[] = {
816    0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
817  };
818  // GR16 Register Class...
819  static const MCPhysReg GR16[] = {
820    X86_AX, X86_CX, X86_DX, X86_SI, X86_DI, X86_BX, X86_BP, X86_SP, X86_R8W, X86_R9W, X86_R10W, X86_R11W, X86_R14W, X86_R15W, X86_R12W, X86_R13W,
821  };
822  // GR16 Bit set.
823  static const uint8_t GR16Bits[] = {
824    0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
825  };
826  // GR16_NOREX Register Class...
827  static const MCPhysReg GR16_NOREX[] = {
828    X86_AX, X86_CX, X86_DX, X86_SI, X86_DI, X86_BX, X86_BP, X86_SP,
829  };
830  // GR16_NOREX Bit set.
831  static const uint8_t GR16_NOREXBits[] = {
832    0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x12,
833  };
834  // VK1 Register Class...
835  static const MCPhysReg VK1[] = {
836    X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
837  };
838  // VK1 Bit set.
839  static const uint8_t VK1Bits[] = {
840    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
841  };
842  // VK16 Register Class...
843  static const MCPhysReg VK16[] = {
844    X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
845  };
846  // VK16 Bit set.
847  static const uint8_t VK16Bits[] = {
848    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
849  };
850  // VK2 Register Class...
851  static const MCPhysReg VK2[] = {
852    X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
853  };
854  // VK2 Bit set.
855  static const uint8_t VK2Bits[] = {
856    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
857  };
858  // VK4 Register Class...
859  static const MCPhysReg VK4[] = {
860    X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
861  };
862  // VK4 Bit set.
863  static const uint8_t VK4Bits[] = {
864    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
865  };
866  // VK8 Register Class...
867  static const MCPhysReg VK8[] = {
868    X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
869  };
870  // VK8 Bit set.
871  static const uint8_t VK8Bits[] = {
872    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
873  };
874  // VK16WM Register Class...
875  static const MCPhysReg VK16WM[] = {
876    X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
877  };
878  // VK16WM Bit set.
879  static const uint8_t VK16WMBits[] = {
880    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f,
881  };
882  // VK1WM Register Class...
883  static const MCPhysReg VK1WM[] = {
884    X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
885  };
886  // VK1WM Bit set.
887  static const uint8_t VK1WMBits[] = {
888    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f,
889  };
890  // VK2WM Register Class...
891  static const MCPhysReg VK2WM[] = {
892    X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
893  };
894  // VK2WM Bit set.
895  static const uint8_t VK2WMBits[] = {
896    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f,
897  };
898  // VK4WM Register Class...
899  static const MCPhysReg VK4WM[] = {
900    X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
901  };
902  // VK4WM Bit set.
903  static const uint8_t VK4WMBits[] = {
904    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f,
905  };
906  // VK8WM Register Class...
907  static const MCPhysReg VK8WM[] = {
908    X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
909  };
910  // VK8WM Bit set.
911  static const uint8_t VK8WMBits[] = {
912    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f,
913  };
914  // SEGMENT_REG Register Class...
915  static const MCPhysReg SEGMENT_REG[] = {
916    X86_CS, X86_DS, X86_SS, X86_ES, X86_FS, X86_GS,
917  };
918  // SEGMENT_REG Bit set.
919  static const uint8_t SEGMENT_REGBits[] = {
920    0x00, 0x10, 0x10, 0x80, 0x18, 0x00, 0x00, 0x80,
921  };
922  // GR16_ABCD Register Class...
923  static const MCPhysReg GR16_ABCD[] = {
924    X86_AX, X86_CX, X86_DX, X86_BX,
925  };
926  // GR16_ABCD Bit set.
927  static const uint8_t GR16_ABCDBits[] = {
928    0x08, 0x22, 0x20,
929  };
930  // FPCCR Register Class...
931  static const MCPhysReg FPCCR[] = {
932    X86_FPSW,
933  };
934  // FPCCR Bit set.
935  static const uint8_t FPCCRBits[] = {
936    0x00, 0x00, 0x00, 0x00, 0x04,
937  };
938  // FR32X Register Class...
939  static const MCPhysReg FR32X[] = {
940    X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15, X86_XMM16, X86_XMM17, X86_XMM18, X86_XMM19, X86_XMM20, X86_XMM21, X86_XMM22, X86_XMM23, X86_XMM24, X86_XMM25, X86_XMM26, X86_XMM27, X86_XMM28, X86_XMM29, X86_XMM30, X86_XMM31,
941  };
942  // FR32X Bit set.
943  static const uint8_t FR32XBits[] = {
944    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
945  };
946  // LOW32_ADDR_ACCESS_RBP Register Class...
947  static const MCPhysReg LOW32_ADDR_ACCESS_RBP[] = {
948    X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_ESP, X86_R8D, X86_R9D, X86_R10D, X86_R11D, X86_R14D, X86_R15D, X86_R12D, X86_R13D, X86_RIP, X86_RBP,
949  };
950  // LOW32_ADDR_ACCESS_RBP Bit set.
951  static const uint8_t LOW32_ADDR_ACCESS_RBPBits[] = {
952    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
953  };
954  // LOW32_ADDR_ACCESS Register Class...
955  static const MCPhysReg LOW32_ADDR_ACCESS[] = {
956    X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_ESP, X86_R8D, X86_R9D, X86_R10D, X86_R11D, X86_R14D, X86_R15D, X86_R12D, X86_R13D, X86_RIP,
957  };
958  // LOW32_ADDR_ACCESS Bit set.
959  static const uint8_t LOW32_ADDR_ACCESSBits[] = {
960    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
961  };
962  // LOW32_ADDR_ACCESS_RBP_with_sub_8bit Register Class...
963  static const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit[] = {
964    X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_ESP, X86_R8D, X86_R9D, X86_R10D, X86_R11D, X86_R14D, X86_R15D, X86_R12D, X86_R13D, X86_RBP,
965  };
966  // LOW32_ADDR_ACCESS_RBP_with_sub_8bit Bit set.
967  static const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits[] = {
968    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
969  };
970  // DEBUG_REG Register Class...
971  static const MCPhysReg DEBUG_REG[] = {
972    X86_DR0, X86_DR1, X86_DR2, X86_DR3, X86_DR4, X86_DR5, X86_DR6, X86_DR7, X86_DR8, X86_DR9, X86_DR10, X86_DR11, X86_DR12, X86_DR13, X86_DR14, X86_DR15,
973  };
974  // DEBUG_REG Bit set.
975  static const uint8_t DEBUG_REGBits[] = {
976    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
977  };
978  // FR32 Register Class...
979  static const MCPhysReg FR32[] = {
980    X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15,
981  };
982  // FR32 Bit set.
983  static const uint8_t FR32Bits[] = {
984    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
985  };
986  // GR32 Register Class...
987  static const MCPhysReg GR32[] = {
988    X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_ESP, X86_R8D, X86_R9D, X86_R10D, X86_R11D, X86_R14D, X86_R15D, X86_R12D, X86_R13D,
989  };
990  // GR32 Bit set.
991  static const uint8_t GR32Bits[] = {
992    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
993  };
994  // GR32_NOSP Register Class...
995  static const MCPhysReg GR32_NOSP[] = {
996    X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_R8D, X86_R9D, X86_R10D, X86_R11D, X86_R14D, X86_R15D, X86_R12D, X86_R13D,
997  };
998  // GR32_NOSP Bit set.
999  static const uint8_t GR32_NOSPBits[] = {
1000    0x00, 0x00, 0xc0, 0x0f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
1001  };
1002  // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Register Class...
1003  static const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX[] = {
1004    X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_ESP, X86_RBP,
1005  };
1006  // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Bit set.
1007  static const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits[] = {
1008    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x01,
1009  };
1010  // GR32_NOREX Register Class...
1011  static const MCPhysReg GR32_NOREX[] = {
1012    X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_ESP,
1013  };
1014  // GR32_NOREX Bit set.
1015  static const uint8_t GR32_NOREXBits[] = {
1016    0x00, 0x00, 0xc0, 0x0f, 0x03,
1017  };
1018  // VK32 Register Class...
1019  static const MCPhysReg VK32[] = {
1020    X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
1021  };
1022  // VK32 Bit set.
1023  static const uint8_t VK32Bits[] = {
1024    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
1025  };
1026  // GR32_NOREX_NOSP Register Class...
1027  static const MCPhysReg GR32_NOREX_NOSP[] = {
1028    X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP,
1029  };
1030  // GR32_NOREX_NOSP Bit set.
1031  static const uint8_t GR32_NOREX_NOSPBits[] = {
1032    0x00, 0x00, 0xc0, 0x0f, 0x01,
1033  };
1034  // RFP32 Register Class...
1035  static const MCPhysReg RFP32[] = {
1036    X86_FP0, X86_FP1, X86_FP2, X86_FP3, X86_FP4, X86_FP5, X86_FP6,
1037  };
1038  // RFP32 Bit set.
1039  static const uint8_t RFP32Bits[] = {
1040    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f,
1041  };
1042  // VK32WM Register Class...
1043  static const MCPhysReg VK32WM[] = {
1044    X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
1045  };
1046  // VK32WM Bit set.
1047  static const uint8_t VK32WMBits[] = {
1048    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f,
1049  };
1050  // GR32_ABCD Register Class...
1051  static const MCPhysReg GR32_ABCD[] = {
1052    X86_EAX, X86_ECX, X86_EDX, X86_EBX,
1053  };
1054  // GR32_ABCD Bit set.
1055  static const uint8_t GR32_ABCDBits[] = {
1056    0x00, 0x00, 0x40, 0x0b,
1057  };
1058  // GR32_TC Register Class...
1059  static const MCPhysReg GR32_TC[] = {
1060    X86_EAX, X86_ECX, X86_EDX,
1061  };
1062  // GR32_TC Bit set.
1063  static const uint8_t GR32_TCBits[] = {
1064    0x00, 0x00, 0x40, 0x0a,
1065  };
1066  // GR32_AD Register Class...
1067  static const MCPhysReg GR32_AD[] = {
1068    X86_EAX, X86_EDX,
1069  };
1070  // GR32_AD Bit set.
1071  static const uint8_t GR32_ADBits[] = {
1072    0x00, 0x00, 0x40, 0x08,
1073  };
1074  // LOW32_ADDR_ACCESS_RBP_with_sub_32bit Register Class...
1075  static const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_32bit[] = {
1076    X86_RIP, X86_RBP,
1077  };
1078  // LOW32_ADDR_ACCESS_RBP_with_sub_32bit Bit set.
1079  static const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits[] = {
1080    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21,
1081  };
1082  // CCR Register Class...
1083  static const MCPhysReg CCR[] = {
1084    X86_EFLAGS,
1085  };
1086  // CCR Bit set.
1087  static const uint8_t CCRBits[] = {
1088    0x00, 0x00, 0x00, 0x10,
1089  };
1090  // DFCCR Register Class...
1091  static const MCPhysReg DFCCR[] = {
1092    X86_DF,
1093  };
1094  // DFCCR Bit set.
1095  static const uint8_t DFCCRBits[] = {
1096    0x00, 0x40,
1097  };
1098  // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Register Class...
1099  static const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit[] = {
1100    X86_RBP,
1101  };
1102  // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Bit set.
1103  static const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits[] = {
1104    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
1105  };
1106  // LOW32_ADDR_ACCESS_with_sub_32bit Register Class...
1107  static const MCPhysReg LOW32_ADDR_ACCESS_with_sub_32bit[] = {
1108    X86_RIP,
1109  };
1110  // LOW32_ADDR_ACCESS_with_sub_32bit Bit set.
1111  static const uint8_t LOW32_ADDR_ACCESS_with_sub_32bitBits[] = {
1112    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
1113  };
1114  // RFP64 Register Class...
1115  static const MCPhysReg RFP64[] = {
1116    X86_FP0, X86_FP1, X86_FP2, X86_FP3, X86_FP4, X86_FP5, X86_FP6,
1117  };
1118  // RFP64 Bit set.
1119  static const uint8_t RFP64Bits[] = {
1120    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f,
1121  };
1122  // FR64X Register Class...
1123  static const MCPhysReg FR64X[] = {
1124    X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15, X86_XMM16, X86_XMM17, X86_XMM18, X86_XMM19, X86_XMM20, X86_XMM21, X86_XMM22, X86_XMM23, X86_XMM24, X86_XMM25, X86_XMM26, X86_XMM27, X86_XMM28, X86_XMM29, X86_XMM30, X86_XMM31,
1125  };
1126  // FR64X Bit set.
1127  static const uint8_t FR64XBits[] = {
1128    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
1129  };
1130  // GR64 Register Class...
1131  static const MCPhysReg GR64[] = {
1132    X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R10, X86_R11, X86_RBX, X86_R14, X86_R15, X86_R12, X86_R13, X86_RBP, X86_RSP, X86_RIP,
1133  };
1134  // GR64 Bit set.
1135  static const uint8_t GR64Bits[] = {
1136    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xbf, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
1137  };
1138  // CONTROL_REG Register Class...
1139  static const MCPhysReg CONTROL_REG[] = {
1140    X86_CR0, X86_CR1, X86_CR2, X86_CR3, X86_CR4, X86_CR5, X86_CR6, X86_CR7, X86_CR8, X86_CR9, X86_CR10, X86_CR11, X86_CR12, X86_CR13, X86_CR14, X86_CR15,
1141  };
1142  // CONTROL_REG Bit set.
1143  static const uint8_t CONTROL_REGBits[] = {
1144    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
1145  };
1146  // FR64 Register Class...
1147  static const MCPhysReg FR64[] = {
1148    X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15,
1149  };
1150  // FR64 Bit set.
1151  static const uint8_t FR64Bits[] = {
1152    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
1153  };
1154  // GR64_with_sub_8bit Register Class...
1155  static const MCPhysReg GR64_with_sub_8bit[] = {
1156    X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R10, X86_R11, X86_RBX, X86_R14, X86_R15, X86_R12, X86_R13, X86_RBP, X86_RSP,
1157  };
1158  // GR64_with_sub_8bit Bit set.
1159  static const uint8_t GR64_with_sub_8bitBits[] = {
1160    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
1161  };
1162  // GR64_NOSP Register Class...
1163  static const MCPhysReg GR64_NOSP[] = {
1164    X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R10, X86_R11, X86_RBX, X86_R14, X86_R15, X86_R12, X86_R13, X86_RBP,
1165  };
1166  // GR64_NOSP Bit set.
1167  static const uint8_t GR64_NOSPBits[] = {
1168    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
1169  };
1170  // GR64_NOREX Register Class...
1171  static const MCPhysReg GR64_NOREX[] = {
1172    X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_RBX, X86_RBP, X86_RSP, X86_RIP,
1173  };
1174  // GR64_NOREX Bit set.
1175  static const uint8_t GR64_NOREXBits[] = {
1176    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xbf, 0x01,
1177  };
1178  // GR64_TC Register Class...
1179  static const MCPhysReg GR64_TC[] = {
1180    X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R11, X86_RIP,
1181  };
1182  // GR64_TC Bit set.
1183  static const uint8_t GR64_TCBits[] = {
1184    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xbc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01,
1185  };
1186  // GR64_NOSP_and_GR64_TC Register Class...
1187  static const MCPhysReg GR64_NOSP_and_GR64_TC[] = {
1188    X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R11,
1189  };
1190  // GR64_NOSP_and_GR64_TC Bit set.
1191  static const uint8_t GR64_NOSP_and_GR64_TCBits[] = {
1192    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01,
1193  };
1194  // GR64_TCW64 Register Class...
1195  static const MCPhysReg GR64_TCW64[] = {
1196    X86_RAX, X86_RCX, X86_RDX, X86_R8, X86_R9, X86_R10, X86_R11, X86_RIP,
1197  };
1198  // GR64_TCW64 Bit set.
1199  static const uint8_t GR64_TCW64Bits[] = {
1200    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
1201  };
1202  // GR64_with_sub_16bit_in_GR16_NOREX Register Class...
1203  static const MCPhysReg GR64_with_sub_16bit_in_GR16_NOREX[] = {
1204    X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_RBX, X86_RBP, X86_RSP,
1205  };
1206  // GR64_with_sub_16bit_in_GR16_NOREX Bit set.
1207  static const uint8_t GR64_with_sub_16bit_in_GR16_NOREXBits[] = {
1208    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9f, 0x01,
1209  };
1210  // VK64 Register Class...
1211  static const MCPhysReg VK64[] = {
1212    X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
1213  };
1214  // VK64 Bit set.
1215  static const uint8_t VK64Bits[] = {
1216    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
1217  };
1218  // VR64 Register Class...
1219  static const MCPhysReg VR64[] = {
1220    X86_MM0, X86_MM1, X86_MM2, X86_MM3, X86_MM4, X86_MM5, X86_MM6, X86_MM7,
1221  };
1222  // VR64 Bit set.
1223  static const uint8_t VR64Bits[] = {
1224    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
1225  };
1226  // GR64_NOREX_NOSP Register Class...
1227  static const MCPhysReg GR64_NOREX_NOSP[] = {
1228    X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_RBX, X86_RBP,
1229  };
1230  // GR64_NOREX_NOSP Bit set.
1231  static const uint8_t GR64_NOREX_NOSPBits[] = {
1232    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9f,
1233  };
1234  // GR64_NOSP_and_GR64_TCW64 Register Class...
1235  static const MCPhysReg GR64_NOSP_and_GR64_TCW64[] = {
1236    X86_RAX, X86_RCX, X86_RDX, X86_R8, X86_R9, X86_R10, X86_R11,
1237  };
1238  // GR64_NOSP_and_GR64_TCW64 Bit set.
1239  static const uint8_t GR64_NOSP_and_GR64_TCW64Bits[] = {
1240    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
1241  };
1242  // GR64_TC_and_GR64_TCW64 Register Class...
1243  static const MCPhysReg GR64_TC_and_GR64_TCW64[] = {
1244    X86_RAX, X86_RCX, X86_RDX, X86_R8, X86_R9, X86_R11, X86_RIP,
1245  };
1246  // GR64_TC_and_GR64_TCW64 Bit set.
1247  static const uint8_t GR64_TC_and_GR64_TCW64Bits[] = {
1248    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01,
1249  };
1250  // VK64WM Register Class...
1251  static const MCPhysReg VK64WM[] = {
1252    X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
1253  };
1254  // VK64WM Bit set.
1255  static const uint8_t VK64WMBits[] = {
1256    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f,
1257  };
1258  // GR64_NOREX_and_GR64_TC Register Class...
1259  static const MCPhysReg GR64_NOREX_and_GR64_TC[] = {
1260    X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_RIP,
1261  };
1262  // GR64_NOREX_and_GR64_TC Bit set.
1263  static const uint8_t GR64_NOREX_and_GR64_TCBits[] = {
1264    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xbc,
1265  };
1266  // GR64_TC_and_GR64_NOSP_and_GR64_TCW64 Register Class...
1267  static const MCPhysReg GR64_TC_and_GR64_NOSP_and_GR64_TCW64[] = {
1268    X86_RAX, X86_RCX, X86_RDX, X86_R8, X86_R9, X86_R11,
1269  };
1270  // GR64_TC_and_GR64_NOSP_and_GR64_TCW64 Bit set.
1271  static const uint8_t GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits[] = {
1272    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01,
1273  };
1274  // GR64_NOREX_NOSP_and_GR64_TC Register Class...
1275  static const MCPhysReg GR64_NOREX_NOSP_and_GR64_TC[] = {
1276    X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI,
1277  };
1278  // GR64_NOREX_NOSP_and_GR64_TC Bit set.
1279  static const uint8_t GR64_NOREX_NOSP_and_GR64_TCBits[] = {
1280    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9c,
1281  };
1282  // GR64_ABCD Register Class...
1283  static const MCPhysReg GR64_ABCD[] = {
1284    X86_RAX, X86_RCX, X86_RDX, X86_RBX,
1285  };
1286  // GR64_ABCD Bit set.
1287  static const uint8_t GR64_ABCDBits[] = {
1288    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x16,
1289  };
1290  // GR64_NOREX_and_GR64_TCW64 Register Class...
1291  static const MCPhysReg GR64_NOREX_and_GR64_TCW64[] = {
1292    X86_RAX, X86_RCX, X86_RDX, X86_RIP,
1293  };
1294  // GR64_NOREX_and_GR64_TCW64 Bit set.
1295  static const uint8_t GR64_NOREX_and_GR64_TCW64Bits[] = {
1296    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x34,
1297  };
1298  // GR64_with_sub_32bit_in_GR32_TC Register Class...
1299  static const MCPhysReg GR64_with_sub_32bit_in_GR32_TC[] = {
1300    X86_RAX, X86_RCX, X86_RDX,
1301  };
1302  // GR64_with_sub_32bit_in_GR32_TC Bit set.
1303  static const uint8_t GR64_with_sub_32bit_in_GR32_TCBits[] = {
1304    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x14,
1305  };
1306  // GR64_AD Register Class...
1307  static const MCPhysReg GR64_AD[] = {
1308    X86_RAX, X86_RDX,
1309  };
1310  // GR64_AD Bit set.
1311  static const uint8_t GR64_ADBits[] = {
1312    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x10,
1313  };
1314  // GR64_and_LOW32_ADDR_ACCESS_RBP Register Class...
1315  static const MCPhysReg GR64_and_LOW32_ADDR_ACCESS_RBP[] = {
1316    X86_RBP, X86_RIP,
1317  };
1318  // GR64_and_LOW32_ADDR_ACCESS_RBP Bit set.
1319  static const uint8_t GR64_and_LOW32_ADDR_ACCESS_RBPBits[] = {
1320    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21,
1321  };
1322  // GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBP Register Class...
1323  static const MCPhysReg GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBP[] = {
1324    X86_RBP,
1325  };
1326  // GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBP Bit set.
1327  static const uint8_t GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBPBits[] = {
1328    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
1329  };
1330  // GR64_and_LOW32_ADDR_ACCESS Register Class...
1331  static const MCPhysReg GR64_and_LOW32_ADDR_ACCESS[] = {
1332    X86_RIP,
1333  };
1334  // GR64_and_LOW32_ADDR_ACCESS Bit set.
1335  static const uint8_t GR64_and_LOW32_ADDR_ACCESSBits[] = {
1336    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
1337  };
1338  // RST Register Class...
1339  static const MCPhysReg RST[] = {
1340    X86_ST0, X86_ST1, X86_ST2, X86_ST3, X86_ST4, X86_ST5, X86_ST6, X86_ST7,
1341  };
1342  // RST Bit set.
1343  static const uint8_t RSTBits[] = {
1344    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
1345  };
1346  // RFP80 Register Class...
1347  static const MCPhysReg RFP80[] = {
1348    X86_FP0, X86_FP1, X86_FP2, X86_FP3, X86_FP4, X86_FP5, X86_FP6,
1349  };
1350  // RFP80 Bit set.
1351  static const uint8_t RFP80Bits[] = {
1352    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f,
1353  };
1354  // VR128X Register Class...
1355  static const MCPhysReg VR128X[] = {
1356    X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15, X86_XMM16, X86_XMM17, X86_XMM18, X86_XMM19, X86_XMM20, X86_XMM21, X86_XMM22, X86_XMM23, X86_XMM24, X86_XMM25, X86_XMM26, X86_XMM27, X86_XMM28, X86_XMM29, X86_XMM30, X86_XMM31,
1357  };
1358  // VR128X Bit set.
1359  static const uint8_t VR128XBits[] = {
1360    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
1361  };
1362  // VR128 Register Class...
1363  static const MCPhysReg VR128[] = {
1364    X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15,
1365  };
1366  // VR128 Bit set.
1367  static const uint8_t VR128Bits[] = {
1368    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
1369  };
1370  // VR128H Register Class...
1371  static const MCPhysReg VR128H[] = {
1372    X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15,
1373  };
1374  // VR128H Bit set.
1375  static const uint8_t VR128HBits[] = {
1376    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
1377  };
1378  // VR128L Register Class...
1379  static const MCPhysReg VR128L[] = {
1380    X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7,
1381  };
1382  // VR128L Bit set.
1383  static const uint8_t VR128LBits[] = {
1384    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
1385  };
1386  // BNDR Register Class...
1387  static const MCPhysReg BNDR[] = {
1388    X86_BND0, X86_BND1, X86_BND2, X86_BND3,
1389  };
1390  // BNDR Bit set.
1391  static const uint8_t BNDRBits[] = {
1392    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e,
1393  };
1394  // VR256X Register Class...
1395  static const MCPhysReg VR256X[] = {
1396    X86_YMM0, X86_YMM1, X86_YMM2, X86_YMM3, X86_YMM4, X86_YMM5, X86_YMM6, X86_YMM7, X86_YMM8, X86_YMM9, X86_YMM10, X86_YMM11, X86_YMM12, X86_YMM13, X86_YMM14, X86_YMM15, X86_YMM16, X86_YMM17, X86_YMM18, X86_YMM19, X86_YMM20, X86_YMM21, X86_YMM22, X86_YMM23, X86_YMM24, X86_YMM25, X86_YMM26, X86_YMM27, X86_YMM28, X86_YMM29, X86_YMM30, X86_YMM31,
1397  };
1398  // VR256X Bit set.
1399  static const uint8_t VR256XBits[] = {
1400    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
1401  };
1402  // VR256 Register Class...
1403  static const MCPhysReg VR256[] = {
1404    X86_YMM0, X86_YMM1, X86_YMM2, X86_YMM3, X86_YMM4, X86_YMM5, X86_YMM6, X86_YMM7, X86_YMM8, X86_YMM9, X86_YMM10, X86_YMM11, X86_YMM12, X86_YMM13, X86_YMM14, X86_YMM15,
1405  };
1406  // VR256 Bit set.
1407  static const uint8_t VR256Bits[] = {
1408    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
1409  };
1410  // VR256H Register Class...
1411  static const MCPhysReg VR256H[] = {
1412    X86_YMM8, X86_YMM9, X86_YMM10, X86_YMM11, X86_YMM12, X86_YMM13, X86_YMM14, X86_YMM15,
1413  };
1414  // VR256H Bit set.
1415  static const uint8_t VR256HBits[] = {
1416    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
1417  };
1418  // VR256L Register Class...
1419  static const MCPhysReg VR256L[] = {
1420    X86_YMM0, X86_YMM1, X86_YMM2, X86_YMM3, X86_YMM4, X86_YMM5, X86_YMM6, X86_YMM7,
1421  };
1422  // VR256L Bit set.
1423  static const uint8_t VR256LBits[] = {
1424    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
1425  };
1426  // VR512 Register Class...
1427  static const MCPhysReg VR512[] = {
1428    X86_ZMM0, X86_ZMM1, X86_ZMM2, X86_ZMM3, X86_ZMM4, X86_ZMM5, X86_ZMM6, X86_ZMM7, X86_ZMM8, X86_ZMM9, X86_ZMM10, X86_ZMM11, X86_ZMM12, X86_ZMM13, X86_ZMM14, X86_ZMM15, X86_ZMM16, X86_ZMM17, X86_ZMM18, X86_ZMM19, X86_ZMM20, X86_ZMM21, X86_ZMM22, X86_ZMM23, X86_ZMM24, X86_ZMM25, X86_ZMM26, X86_ZMM27, X86_ZMM28, X86_ZMM29, X86_ZMM30, X86_ZMM31,
1429  };
1430  // VR512 Bit set.
1431  static const uint8_t VR512Bits[] = {
1432    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
1433  };
1434  // VR512_with_sub_xmm_in_FR32 Register Class...
1435  static const MCPhysReg VR512_with_sub_xmm_in_FR32[] = {
1436    X86_ZMM0, X86_ZMM1, X86_ZMM2, X86_ZMM3, X86_ZMM4, X86_ZMM5, X86_ZMM6, X86_ZMM7, X86_ZMM8, X86_ZMM9, X86_ZMM10, X86_ZMM11, X86_ZMM12, X86_ZMM13, X86_ZMM14, X86_ZMM15,
1437  };
1438  // VR512_with_sub_xmm_in_FR32 Bit set.
1439  static const uint8_t VR512_with_sub_xmm_in_FR32Bits[] = {
1440    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
1441  };
1442  // VR512_with_sub_xmm_in_VR128H Register Class...
1443  static const MCPhysReg VR512_with_sub_xmm_in_VR128H[] = {
1444    X86_ZMM8, X86_ZMM9, X86_ZMM10, X86_ZMM11, X86_ZMM12, X86_ZMM13, X86_ZMM14, X86_ZMM15,
1445  };
1446  // VR512_with_sub_xmm_in_VR128H Bit set.
1447  static const uint8_t VR512_with_sub_xmm_in_VR128HBits[] = {
1448    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
1449  };
1450  // VR512_with_sub_xmm_in_VR128L Register Class...
1451  static const MCPhysReg VR512_with_sub_xmm_in_VR128L[] = {
1452    X86_ZMM0, X86_ZMM1, X86_ZMM2, X86_ZMM3, X86_ZMM4, X86_ZMM5, X86_ZMM6, X86_ZMM7,
1453  };
1454  // VR512_with_sub_xmm_in_VR128L Bit set.
1455  static const uint8_t VR512_with_sub_xmm_in_VR128LBits[] = {
1456    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
1457  };
1458
1459
1460static const MCRegisterClass X86MCRegisterClasses[] = {
1461  { GR8, GR8Bits, sizeof(GR8Bits) },
1462  { GRH8, GRH8Bits, sizeof(GRH8Bits) },
1463  { GR8_NOREX, GR8_NOREXBits, sizeof(GR8_NOREXBits) },
1464  { GR8_ABCD_H, GR8_ABCD_HBits, sizeof(GR8_ABCD_HBits) },
1465  { GR8_ABCD_L, GR8_ABCD_LBits, sizeof(GR8_ABCD_LBits) },
1466  { GRH16, GRH16Bits, sizeof(GRH16Bits) },
1467  { GR16, GR16Bits, sizeof(GR16Bits) },
1468  { GR16_NOREX, GR16_NOREXBits, sizeof(GR16_NOREXBits) },
1469  { VK1, VK1Bits, sizeof(VK1Bits) },
1470  { VK16, VK16Bits, sizeof(VK16Bits) },
1471  { VK2, VK2Bits, sizeof(VK2Bits) },
1472  { VK4, VK4Bits, sizeof(VK4Bits) },
1473  { VK8, VK8Bits, sizeof(VK8Bits) },
1474  { VK16WM, VK16WMBits, sizeof(VK16WMBits) },
1475  { VK1WM, VK1WMBits, sizeof(VK1WMBits) },
1476  { VK2WM, VK2WMBits, sizeof(VK2WMBits) },
1477  { VK4WM, VK4WMBits, sizeof(VK4WMBits) },
1478  { VK8WM, VK8WMBits, sizeof(VK8WMBits) },
1479  { SEGMENT_REG, SEGMENT_REGBits, sizeof(SEGMENT_REGBits) },
1480  { GR16_ABCD, GR16_ABCDBits, sizeof(GR16_ABCDBits) },
1481  { FPCCR, FPCCRBits, sizeof(FPCCRBits) },
1482  { FR32X, FR32XBits, sizeof(FR32XBits) },
1483  { LOW32_ADDR_ACCESS_RBP, LOW32_ADDR_ACCESS_RBPBits, sizeof(LOW32_ADDR_ACCESS_RBPBits) },
1484  { LOW32_ADDR_ACCESS, LOW32_ADDR_ACCESSBits, sizeof(LOW32_ADDR_ACCESSBits) },
1485  { LOW32_ADDR_ACCESS_RBP_with_sub_8bit, LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits) },
1486  { DEBUG_REG, DEBUG_REGBits, sizeof(DEBUG_REGBits) },
1487  { FR32, FR32Bits, sizeof(FR32Bits) },
1488  { GR32, GR32Bits, sizeof(GR32Bits) },
1489  { GR32_NOSP, GR32_NOSPBits, sizeof(GR32_NOSPBits) },
1490  { LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX, LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits) },
1491  { GR32_NOREX, GR32_NOREXBits, sizeof(GR32_NOREXBits) },
1492  { VK32, VK32Bits, sizeof(VK32Bits) },
1493  { GR32_NOREX_NOSP, GR32_NOREX_NOSPBits, sizeof(GR32_NOREX_NOSPBits) },
1494  { RFP32, RFP32Bits, sizeof(RFP32Bits) },
1495  { VK32WM, VK32WMBits, sizeof(VK32WMBits) },
1496  { GR32_ABCD, GR32_ABCDBits, sizeof(GR32_ABCDBits) },
1497  { GR32_TC, GR32_TCBits, sizeof(GR32_TCBits) },
1498  { GR32_AD, GR32_ADBits, sizeof(GR32_ADBits) },
1499  { LOW32_ADDR_ACCESS_RBP_with_sub_32bit, LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits) },
1500  { CCR, CCRBits, sizeof(CCRBits) },
1501  { DFCCR, DFCCRBits, sizeof(DFCCRBits) },
1502  { LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit, LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits) },
1503  { LOW32_ADDR_ACCESS_with_sub_32bit, LOW32_ADDR_ACCESS_with_sub_32bitBits, sizeof(LOW32_ADDR_ACCESS_with_sub_32bitBits) },
1504  { RFP64, RFP64Bits, sizeof(RFP64Bits) },
1505  { FR64X, FR64XBits, sizeof(FR64XBits) },
1506  { GR64, GR64Bits, sizeof(GR64Bits) },
1507  { CONTROL_REG, CONTROL_REGBits, sizeof(CONTROL_REGBits) },
1508  { FR64, FR64Bits, sizeof(FR64Bits) },
1509  { GR64_with_sub_8bit, GR64_with_sub_8bitBits, sizeof(GR64_with_sub_8bitBits) },
1510  { GR64_NOSP, GR64_NOSPBits, sizeof(GR64_NOSPBits) },
1511  { GR64_NOREX, GR64_NOREXBits, sizeof(GR64_NOREXBits) },
1512  { GR64_TC, GR64_TCBits, sizeof(GR64_TCBits) },
1513  { GR64_NOSP_and_GR64_TC, GR64_NOSP_and_GR64_TCBits, sizeof(GR64_NOSP_and_GR64_TCBits) },
1514  { GR64_TCW64, GR64_TCW64Bits, sizeof(GR64_TCW64Bits) },
1515  { GR64_with_sub_16bit_in_GR16_NOREX, GR64_with_sub_16bit_in_GR16_NOREXBits, sizeof(GR64_with_sub_16bit_in_GR16_NOREXBits) },
1516  { VK64, VK64Bits, sizeof(VK64Bits) },
1517  { VR64, VR64Bits, sizeof(VR64Bits) },
1518  { GR64_NOREX_NOSP, GR64_NOREX_NOSPBits, sizeof(GR64_NOREX_NOSPBits) },
1519  { GR64_NOSP_and_GR64_TCW64, GR64_NOSP_and_GR64_TCW64Bits, sizeof(GR64_NOSP_and_GR64_TCW64Bits) },
1520  { GR64_TC_and_GR64_TCW64, GR64_TC_and_GR64_TCW64Bits, sizeof(GR64_TC_and_GR64_TCW64Bits) },
1521  { VK64WM, VK64WMBits, sizeof(VK64WMBits) },
1522  { GR64_NOREX_and_GR64_TC, GR64_NOREX_and_GR64_TCBits, sizeof(GR64_NOREX_and_GR64_TCBits) },
1523  { GR64_TC_and_GR64_NOSP_and_GR64_TCW64, GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits, sizeof(GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits) },
1524  { GR64_NOREX_NOSP_and_GR64_TC, GR64_NOREX_NOSP_and_GR64_TCBits, sizeof(GR64_NOREX_NOSP_and_GR64_TCBits) },
1525  { GR64_ABCD, GR64_ABCDBits, sizeof(GR64_ABCDBits) },
1526  { GR64_NOREX_and_GR64_TCW64, GR64_NOREX_and_GR64_TCW64Bits, sizeof(GR64_NOREX_and_GR64_TCW64Bits) },
1527  { GR64_with_sub_32bit_in_GR32_TC, GR64_with_sub_32bit_in_GR32_TCBits, sizeof(GR64_with_sub_32bit_in_GR32_TCBits) },
1528  { GR64_AD, GR64_ADBits, sizeof(GR64_ADBits) },
1529  { GR64_and_LOW32_ADDR_ACCESS_RBP, GR64_and_LOW32_ADDR_ACCESS_RBPBits, sizeof(GR64_and_LOW32_ADDR_ACCESS_RBPBits) },
1530  { GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBP, GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBPBits, sizeof(GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBPBits) },
1531  { GR64_and_LOW32_ADDR_ACCESS, GR64_and_LOW32_ADDR_ACCESSBits, sizeof(GR64_and_LOW32_ADDR_ACCESSBits) },
1532  { RST, RSTBits, sizeof(RSTBits) },
1533  { RFP80, RFP80Bits, sizeof(RFP80Bits) },
1534  { VR128X, VR128XBits, sizeof(VR128XBits) },
1535  { VR128, VR128Bits, sizeof(VR128Bits) },
1536  { VR128H, VR128HBits, sizeof(VR128HBits) },
1537  { VR128L, VR128LBits, sizeof(VR128LBits) },
1538  { BNDR, BNDRBits, sizeof(BNDRBits) },
1539  { VR256X, VR256XBits, sizeof(VR256XBits) },
1540  { VR256, VR256Bits, sizeof(VR256Bits) },
1541  { VR256H, VR256HBits, sizeof(VR256HBits) },
1542  { VR256L, VR256LBits, sizeof(VR256LBits) },
1543  { VR512, VR512Bits, sizeof(VR512Bits) },
1544  { VR512_with_sub_xmm_in_FR32, VR512_with_sub_xmm_in_FR32Bits, sizeof(VR512_with_sub_xmm_in_FR32Bits) },
1545  { VR512_with_sub_xmm_in_VR128H, VR512_with_sub_xmm_in_VR128HBits, sizeof(VR512_with_sub_xmm_in_VR128HBits) },
1546  { VR512_with_sub_xmm_in_VR128L, VR512_with_sub_xmm_in_VR128LBits, sizeof(VR512_with_sub_xmm_in_VR128LBits) },
1547};
1548
1549#endif // GET_REGINFO_MC_DESC
1550