1//===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the X86 instruction set, defining the instructions, and 11// properties of the instructions which are needed for code generation, machine 12// code emission, and analysis. 13// 14//===----------------------------------------------------------------------===// 15 16//===----------------------------------------------------------------------===// 17// X86 specific DAG Nodes. 18// 19 20def SDTIntShiftDOp: SDTypeProfile<1, 3, 21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 22 SDTCisInt<0>, SDTCisInt<3>]>; 23 24def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>; 25 26def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; 27//def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; 28 29def SDTX86Cmov : SDTypeProfile<1, 4, 30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; 32 33// Unary and binary operator instructions that set EFLAGS as a side-effect. 34def SDTUnaryArithWithFlags : SDTypeProfile<2, 1, 35 [SDTCisSameAs<0, 2>, 36 SDTCisInt<0>, SDTCisVT<1, i32>]>; 37 38def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 39 [SDTCisSameAs<0, 2>, 40 SDTCisSameAs<0, 3>, 41 SDTCisInt<0>, SDTCisVT<1, i32>]>; 42 43// SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS 44def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 45 [SDTCisSameAs<0, 2>, 46 SDTCisSameAs<0, 3>, 47 SDTCisInt<0>, 48 SDTCisVT<1, i32>, 49 SDTCisVT<4, i32>]>; 50// RES1, RES2, FLAGS = op LHS, RHS 51def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2, 52 [SDTCisSameAs<0, 1>, 53 SDTCisSameAs<0, 2>, 54 SDTCisSameAs<0, 3>, 55 SDTCisInt<0>, SDTCisVT<1, i32>]>; 56def SDTX86BrCond : SDTypeProfile<0, 3, 57 [SDTCisVT<0, OtherVT>, 58 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 59 60def SDTX86SetCC : SDTypeProfile<1, 2, 61 [SDTCisVT<0, i8>, 62 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 63def SDTX86SetCC_C : SDTypeProfile<1, 2, 64 [SDTCisInt<0>, 65 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 66 67def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>; 68 69def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>; 70 71def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>, 72 SDTCisVT<2, i8>]>; 73def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 74def SDTX86caspairSaveEbx8 : SDTypeProfile<1, 3, 75 [SDTCisVT<0, i32>, SDTCisPtrTy<1>, 76 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 77def SDTX86caspairSaveRbx16 : SDTypeProfile<1, 3, 78 [SDTCisVT<0, i64>, SDTCisPtrTy<1>, 79 SDTCisVT<2, i64>, SDTCisVT<3, i64>]>; 80 81def SDTLockBinaryArithWithFlags : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 82 SDTCisPtrTy<1>, 83 SDTCisInt<2>]>; 84 85def SDTLockUnaryArithWithFlags : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, 86 SDTCisPtrTy<1>]>; 87 88def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; 89 90def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>, 91 SDTCisVT<1, i32>]>; 92def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, 93 SDTCisVT<1, i32>]>; 94 95def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; 96 97def SDT_X86NtBrind : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; 98 99def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>, 100 SDTCisVT<1, iPTR>, 101 SDTCisVT<2, iPTR>]>; 102 103def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>, 104 SDTCisPtrTy<1>, 105 SDTCisVT<2, i32>, 106 SDTCisVT<3, i8>, 107 SDTCisVT<4, i32>]>; 108 109def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; 110 111def SDTX86Void : SDTypeProfile<0, 0, []>; 112 113def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 114 115def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 116 117def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 118 119def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 120 121def SDT_X86WIN_ALLOCA : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 122 123def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; 124 125def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 126 127def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; 128 129def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>; 130 131def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER, 132 [SDNPHasChain,SDNPSideEffect]>; 133def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER, 134 [SDNPHasChain]>; 135 136 137def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>; 138def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>; 139def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>; 140def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>; 141 142def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>; 143def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>; 144 145def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>; 146def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, 147 [SDNPHasChain]>; 148def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; 149def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>; 150 151def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>; 152 153def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand, 154 [SDNPHasChain, SDNPSideEffect]>; 155 156def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand, 157 [SDNPHasChain, SDNPSideEffect]>; 158 159def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas, 160 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 161 SDNPMayLoad, SDNPMemOperand]>; 162def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair, 163 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 164 SDNPMayLoad, SDNPMemOperand]>; 165def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair, 166 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 167 SDNPMayLoad, SDNPMemOperand]>; 168def X86cas8save_ebx : SDNode<"X86ISD::LCMPXCHG8_SAVE_EBX_DAG", 169 SDTX86caspairSaveEbx8, 170 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 171 SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 172def X86cas16save_rbx : SDNode<"X86ISD::LCMPXCHG16_SAVE_RBX_DAG", 173 SDTX86caspairSaveRbx16, 174 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 175 SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 176 177def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret, 178 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 179def X86iret : SDNode<"X86ISD::IRET", SDTX86Ret, 180 [SDNPHasChain, SDNPOptInGlue]>; 181 182def X86vastart_save_xmm_regs : 183 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS", 184 SDT_X86VASTART_SAVE_XMM_REGS, 185 [SDNPHasChain, SDNPVariadic]>; 186def X86vaarg64 : 187 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64, 188 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 189 SDNPMemOperand]>; 190def X86callseq_start : 191 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart, 192 [SDNPHasChain, SDNPOutGlue]>; 193def X86callseq_end : 194 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd, 195 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 196 197def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, 198 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 199 SDNPVariadic]>; 200 201def X86NoTrackCall : SDNode<"X86ISD::NT_CALL", SDT_X86Call, 202 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 203 SDNPVariadic]>; 204def X86NoTrackBrind : SDNode<"X86ISD::NT_BRIND", SDT_X86NtBrind, 205 [SDNPHasChain]>; 206 207def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, 208 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>; 209def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, 210 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 211 SDNPMayLoad]>; 212 213def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void, 214 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 215def X86rdtscp : SDNode<"X86ISD::RDTSCP_DAG", SDTX86Void, 216 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 217def X86rdpmc : SDNode<"X86ISD::RDPMC_DAG", SDTX86Void, 218 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 219 220def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>; 221def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>; 222 223def X86RecoverFrameAlloc : SDNode<"ISD::LOCAL_RECOVER", 224 SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, 225 SDTCisInt<1>]>>; 226 227def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR, 228 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 229 230def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR, 231 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 232 233def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET, 234 [SDNPHasChain]>; 235 236def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP", 237 SDTypeProfile<1, 1, [SDTCisInt<0>, 238 SDTCisPtrTy<1>]>, 239 [SDNPHasChain, SDNPSideEffect]>; 240def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP", 241 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 242 [SDNPHasChain, SDNPSideEffect]>; 243def X86eh_sjlj_setup_dispatch : SDNode<"X86ISD::EH_SJLJ_SETUP_DISPATCH", 244 SDTypeProfile<0, 0, []>, 245 [SDNPHasChain, SDNPSideEffect]>; 246 247def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, 248 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 249 250def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags, 251 [SDNPCommutative]>; 252def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>; 253def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags, 254 [SDNPCommutative]>; 255def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags, 256 [SDNPCommutative]>; 257def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>; 258def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>; 259 260def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>; 261def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>; 262def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags, 263 [SDNPCommutative]>; 264def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags, 265 [SDNPCommutative]>; 266def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags, 267 [SDNPCommutative]>; 268 269def X86lock_add : SDNode<"X86ISD::LADD", SDTLockBinaryArithWithFlags, 270 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 271 SDNPMemOperand]>; 272def X86lock_sub : SDNode<"X86ISD::LSUB", SDTLockBinaryArithWithFlags, 273 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 274 SDNPMemOperand]>; 275def X86lock_or : SDNode<"X86ISD::LOR", SDTLockBinaryArithWithFlags, 276 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 277 SDNPMemOperand]>; 278def X86lock_xor : SDNode<"X86ISD::LXOR", SDTLockBinaryArithWithFlags, 279 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 280 SDNPMemOperand]>; 281def X86lock_and : SDNode<"X86ISD::LAND", SDTLockBinaryArithWithFlags, 282 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 283 SDNPMemOperand]>; 284 285def X86lock_inc : SDNode<"X86ISD::LINC", SDTLockUnaryArithWithFlags, 286 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 287 SDNPMemOperand]>; 288def X86lock_dec : SDNode<"X86ISD::LDEC", SDTLockUnaryArithWithFlags, 289 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 290 SDNPMemOperand]>; 291 292def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>; 293 294def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; 295 296def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDT_X86WIN_ALLOCA, 297 [SDNPHasChain, SDNPOutGlue]>; 298 299def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA, 300 [SDNPHasChain]>; 301 302def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL, 303 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 304 305def X86lwpins : SDNode<"X86ISD::LWPINS", 306 SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, 307 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, 308 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPSideEffect]>; 309 310def X86umwait : SDNode<"X86ISD::UMWAIT", 311 SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, 312 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, 313 [SDNPHasChain, SDNPSideEffect]>; 314 315def X86tpause : SDNode<"X86ISD::TPAUSE", 316 SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, 317 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, 318 [SDNPHasChain, SDNPSideEffect]>; 319 320//===----------------------------------------------------------------------===// 321// X86 Operand Definitions. 322// 323 324// A version of ptr_rc which excludes SP, ESP, and RSP. This is used for 325// the index operand of an address, to conform to x86 encoding restrictions. 326def ptr_rc_nosp : PointerLikeRegClass<1>; 327 328// *mem - Operand definitions for the funky X86 addressing mode operands. 329// 330def X86MemAsmOperand : AsmOperandClass { 331 let Name = "Mem"; 332} 333let RenderMethod = "addMemOperands", SuperClasses = [X86MemAsmOperand] in { 334 def X86Mem8AsmOperand : AsmOperandClass { let Name = "Mem8"; } 335 def X86Mem16AsmOperand : AsmOperandClass { let Name = "Mem16"; } 336 def X86Mem32AsmOperand : AsmOperandClass { let Name = "Mem32"; } 337 def X86Mem64AsmOperand : AsmOperandClass { let Name = "Mem64"; } 338 def X86Mem80AsmOperand : AsmOperandClass { let Name = "Mem80"; } 339 def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; } 340 def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; } 341 def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; } 342 // Gather mem operands 343 def X86Mem64_RC128Operand : AsmOperandClass { let Name = "Mem64_RC128"; } 344 def X86Mem128_RC128Operand : AsmOperandClass { let Name = "Mem128_RC128"; } 345 def X86Mem256_RC128Operand : AsmOperandClass { let Name = "Mem256_RC128"; } 346 def X86Mem128_RC256Operand : AsmOperandClass { let Name = "Mem128_RC256"; } 347 def X86Mem256_RC256Operand : AsmOperandClass { let Name = "Mem256_RC256"; } 348 349 def X86Mem64_RC128XOperand : AsmOperandClass { let Name = "Mem64_RC128X"; } 350 def X86Mem128_RC128XOperand : AsmOperandClass { let Name = "Mem128_RC128X"; } 351 def X86Mem256_RC128XOperand : AsmOperandClass { let Name = "Mem256_RC128X"; } 352 def X86Mem128_RC256XOperand : AsmOperandClass { let Name = "Mem128_RC256X"; } 353 def X86Mem256_RC256XOperand : AsmOperandClass { let Name = "Mem256_RC256X"; } 354 def X86Mem512_RC256XOperand : AsmOperandClass { let Name = "Mem512_RC256X"; } 355 def X86Mem256_RC512Operand : AsmOperandClass { let Name = "Mem256_RC512"; } 356 def X86Mem512_RC512Operand : AsmOperandClass { let Name = "Mem512_RC512"; } 357} 358 359def X86AbsMemAsmOperand : AsmOperandClass { 360 let Name = "AbsMem"; 361 let SuperClasses = [X86MemAsmOperand]; 362} 363 364class X86MemOperand<string printMethod, 365 AsmOperandClass parserMatchClass = X86MemAsmOperand> : Operand<iPTR> { 366 let PrintMethod = printMethod; 367 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG); 368 let ParserMatchClass = parserMatchClass; 369 let OperandType = "OPERAND_MEMORY"; 370} 371 372// Gather mem operands 373class X86VMemOperand<RegisterClass RC, string printMethod, 374 AsmOperandClass parserMatchClass> 375 : X86MemOperand<printMethod, parserMatchClass> { 376 let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, SEGMENT_REG); 377} 378 379def anymem : X86MemOperand<"printanymem">; 380 381// FIXME: Right now we allow any size during parsing, but we might want to 382// restrict to only unsized memory. 383def opaquemem : X86MemOperand<"printopaquemem">; 384 385def i8mem : X86MemOperand<"printi8mem", X86Mem8AsmOperand>; 386def i16mem : X86MemOperand<"printi16mem", X86Mem16AsmOperand>; 387def i32mem : X86MemOperand<"printi32mem", X86Mem32AsmOperand>; 388def i64mem : X86MemOperand<"printi64mem", X86Mem64AsmOperand>; 389def i128mem : X86MemOperand<"printi128mem", X86Mem128AsmOperand>; 390def i256mem : X86MemOperand<"printi256mem", X86Mem256AsmOperand>; 391def i512mem : X86MemOperand<"printi512mem", X86Mem512AsmOperand>; 392def f32mem : X86MemOperand<"printf32mem", X86Mem32AsmOperand>; 393def f64mem : X86MemOperand<"printf64mem", X86Mem64AsmOperand>; 394def f80mem : X86MemOperand<"printf80mem", X86Mem80AsmOperand>; 395def f128mem : X86MemOperand<"printf128mem", X86Mem128AsmOperand>; 396def f256mem : X86MemOperand<"printf256mem", X86Mem256AsmOperand>; 397def f512mem : X86MemOperand<"printf512mem", X86Mem512AsmOperand>; 398 399def v512mem : X86VMemOperand<VR512, "printf512mem", X86Mem512AsmOperand>; 400 401// Gather mem operands 402def vx64mem : X86VMemOperand<VR128, "printi64mem", X86Mem64_RC128Operand>; 403def vx128mem : X86VMemOperand<VR128, "printi128mem", X86Mem128_RC128Operand>; 404def vx256mem : X86VMemOperand<VR128, "printi256mem", X86Mem256_RC128Operand>; 405def vy128mem : X86VMemOperand<VR256, "printi128mem", X86Mem128_RC256Operand>; 406def vy256mem : X86VMemOperand<VR256, "printi256mem", X86Mem256_RC256Operand>; 407 408def vx64xmem : X86VMemOperand<VR128X, "printi64mem", X86Mem64_RC128XOperand>; 409def vx128xmem : X86VMemOperand<VR128X, "printi128mem", X86Mem128_RC128XOperand>; 410def vx256xmem : X86VMemOperand<VR128X, "printi256mem", X86Mem256_RC128XOperand>; 411def vy128xmem : X86VMemOperand<VR256X, "printi128mem", X86Mem128_RC256XOperand>; 412def vy256xmem : X86VMemOperand<VR256X, "printi256mem", X86Mem256_RC256XOperand>; 413def vy512xmem : X86VMemOperand<VR256X, "printi512mem", X86Mem512_RC256XOperand>; 414def vz256mem : X86VMemOperand<VR512, "printi256mem", X86Mem256_RC512Operand>; 415def vz512mem : X86VMemOperand<VR512, "printi512mem", X86Mem512_RC512Operand>; 416 417// A version of i8mem for use on x86-64 and x32 that uses a NOREX GPR instead 418// of a plain GPR, so that it doesn't potentially require a REX prefix. 419def ptr_rc_norex : PointerLikeRegClass<2>; 420def ptr_rc_norex_nosp : PointerLikeRegClass<3>; 421 422def i8mem_NOREX : Operand<iPTR> { 423 let PrintMethod = "printi8mem"; 424 let MIOperandInfo = (ops ptr_rc_norex, i8imm, ptr_rc_norex_nosp, i32imm, 425 SEGMENT_REG); 426 let ParserMatchClass = X86Mem8AsmOperand; 427 let OperandType = "OPERAND_MEMORY"; 428} 429 430// GPRs available for tailcall. 431// It represents GR32_TC, GR64_TC or GR64_TCW64. 432def ptr_rc_tailcall : PointerLikeRegClass<4>; 433 434// Special i32mem for addresses of load folding tail calls. These are not 435// allowed to use callee-saved registers since they must be scheduled 436// after callee-saved register are popped. 437def i32mem_TC : Operand<i32> { 438 let PrintMethod = "printi32mem"; 439 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall, 440 i32imm, SEGMENT_REG); 441 let ParserMatchClass = X86Mem32AsmOperand; 442 let OperandType = "OPERAND_MEMORY"; 443} 444 445// Special i64mem for addresses of load folding tail calls. These are not 446// allowed to use callee-saved registers since they must be scheduled 447// after callee-saved register are popped. 448def i64mem_TC : Operand<i64> { 449 let PrintMethod = "printi64mem"; 450 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, 451 ptr_rc_tailcall, i32imm, SEGMENT_REG); 452 let ParserMatchClass = X86Mem64AsmOperand; 453 let OperandType = "OPERAND_MEMORY"; 454} 455 456let OperandType = "OPERAND_PCREL", 457 ParserMatchClass = X86AbsMemAsmOperand, 458 PrintMethod = "printPCRelImm" in { 459def i32imm_pcrel : Operand<i32>; 460def i16imm_pcrel : Operand<i16>; 461 462// Branch targets have OtherVT type and print as pc-relative values. 463def brtarget : Operand<OtherVT>; 464def brtarget8 : Operand<OtherVT>; 465 466} 467 468// Special parser to detect 16-bit mode to select 16-bit displacement. 469def X86AbsMem16AsmOperand : AsmOperandClass { 470 let Name = "AbsMem16"; 471 let RenderMethod = "addAbsMemOperands"; 472 let SuperClasses = [X86AbsMemAsmOperand]; 473} 474 475// Branch targets have OtherVT type and print as pc-relative values. 476let OperandType = "OPERAND_PCREL", 477 PrintMethod = "printPCRelImm" in { 478let ParserMatchClass = X86AbsMem16AsmOperand in 479 def brtarget16 : Operand<OtherVT>; 480let ParserMatchClass = X86AbsMemAsmOperand in 481 def brtarget32 : Operand<OtherVT>; 482} 483 484let RenderMethod = "addSrcIdxOperands" in { 485 def X86SrcIdx8Operand : AsmOperandClass { 486 let Name = "SrcIdx8"; 487 let SuperClasses = [X86Mem8AsmOperand]; 488 } 489 def X86SrcIdx16Operand : AsmOperandClass { 490 let Name = "SrcIdx16"; 491 let SuperClasses = [X86Mem16AsmOperand]; 492 } 493 def X86SrcIdx32Operand : AsmOperandClass { 494 let Name = "SrcIdx32"; 495 let SuperClasses = [X86Mem32AsmOperand]; 496 } 497 def X86SrcIdx64Operand : AsmOperandClass { 498 let Name = "SrcIdx64"; 499 let SuperClasses = [X86Mem64AsmOperand]; 500 } 501} // RenderMethod = "addSrcIdxOperands" 502 503let RenderMethod = "addDstIdxOperands" in { 504 def X86DstIdx8Operand : AsmOperandClass { 505 let Name = "DstIdx8"; 506 let SuperClasses = [X86Mem8AsmOperand]; 507 } 508 def X86DstIdx16Operand : AsmOperandClass { 509 let Name = "DstIdx16"; 510 let SuperClasses = [X86Mem16AsmOperand]; 511 } 512 def X86DstIdx32Operand : AsmOperandClass { 513 let Name = "DstIdx32"; 514 let SuperClasses = [X86Mem32AsmOperand]; 515 } 516 def X86DstIdx64Operand : AsmOperandClass { 517 let Name = "DstIdx64"; 518 let SuperClasses = [X86Mem64AsmOperand]; 519 } 520} // RenderMethod = "addDstIdxOperands" 521 522let RenderMethod = "addMemOffsOperands" in { 523 def X86MemOffs16_8AsmOperand : AsmOperandClass { 524 let Name = "MemOffs16_8"; 525 let SuperClasses = [X86Mem8AsmOperand]; 526 } 527 def X86MemOffs16_16AsmOperand : AsmOperandClass { 528 let Name = "MemOffs16_16"; 529 let SuperClasses = [X86Mem16AsmOperand]; 530 } 531 def X86MemOffs16_32AsmOperand : AsmOperandClass { 532 let Name = "MemOffs16_32"; 533 let SuperClasses = [X86Mem32AsmOperand]; 534 } 535 def X86MemOffs32_8AsmOperand : AsmOperandClass { 536 let Name = "MemOffs32_8"; 537 let SuperClasses = [X86Mem8AsmOperand]; 538 } 539 def X86MemOffs32_16AsmOperand : AsmOperandClass { 540 let Name = "MemOffs32_16"; 541 let SuperClasses = [X86Mem16AsmOperand]; 542 } 543 def X86MemOffs32_32AsmOperand : AsmOperandClass { 544 let Name = "MemOffs32_32"; 545 let SuperClasses = [X86Mem32AsmOperand]; 546 } 547 def X86MemOffs32_64AsmOperand : AsmOperandClass { 548 let Name = "MemOffs32_64"; 549 let SuperClasses = [X86Mem64AsmOperand]; 550 } 551 def X86MemOffs64_8AsmOperand : AsmOperandClass { 552 let Name = "MemOffs64_8"; 553 let SuperClasses = [X86Mem8AsmOperand]; 554 } 555 def X86MemOffs64_16AsmOperand : AsmOperandClass { 556 let Name = "MemOffs64_16"; 557 let SuperClasses = [X86Mem16AsmOperand]; 558 } 559 def X86MemOffs64_32AsmOperand : AsmOperandClass { 560 let Name = "MemOffs64_32"; 561 let SuperClasses = [X86Mem32AsmOperand]; 562 } 563 def X86MemOffs64_64AsmOperand : AsmOperandClass { 564 let Name = "MemOffs64_64"; 565 let SuperClasses = [X86Mem64AsmOperand]; 566 } 567} // RenderMethod = "addMemOffsOperands" 568 569class X86SrcIdxOperand<string printMethod, AsmOperandClass parserMatchClass> 570 : X86MemOperand<printMethod, parserMatchClass> { 571 let MIOperandInfo = (ops ptr_rc, SEGMENT_REG); 572} 573 574class X86DstIdxOperand<string printMethod, AsmOperandClass parserMatchClass> 575 : X86MemOperand<printMethod, parserMatchClass> { 576 let MIOperandInfo = (ops ptr_rc); 577} 578 579def srcidx8 : X86SrcIdxOperand<"printSrcIdx8", X86SrcIdx8Operand>; 580def srcidx16 : X86SrcIdxOperand<"printSrcIdx16", X86SrcIdx16Operand>; 581def srcidx32 : X86SrcIdxOperand<"printSrcIdx32", X86SrcIdx32Operand>; 582def srcidx64 : X86SrcIdxOperand<"printSrcIdx64", X86SrcIdx64Operand>; 583def dstidx8 : X86DstIdxOperand<"printDstIdx8", X86DstIdx8Operand>; 584def dstidx16 : X86DstIdxOperand<"printDstIdx16", X86DstIdx16Operand>; 585def dstidx32 : X86DstIdxOperand<"printDstIdx32", X86DstIdx32Operand>; 586def dstidx64 : X86DstIdxOperand<"printDstIdx64", X86DstIdx64Operand>; 587 588class X86MemOffsOperand<Operand immOperand, string printMethod, 589 AsmOperandClass parserMatchClass> 590 : X86MemOperand<printMethod, parserMatchClass> { 591 let MIOperandInfo = (ops immOperand, SEGMENT_REG); 592} 593 594def offset16_8 : X86MemOffsOperand<i16imm, "printMemOffs8", 595 X86MemOffs16_8AsmOperand>; 596def offset16_16 : X86MemOffsOperand<i16imm, "printMemOffs16", 597 X86MemOffs16_16AsmOperand>; 598def offset16_32 : X86MemOffsOperand<i16imm, "printMemOffs32", 599 X86MemOffs16_32AsmOperand>; 600def offset32_8 : X86MemOffsOperand<i32imm, "printMemOffs8", 601 X86MemOffs32_8AsmOperand>; 602def offset32_16 : X86MemOffsOperand<i32imm, "printMemOffs16", 603 X86MemOffs32_16AsmOperand>; 604def offset32_32 : X86MemOffsOperand<i32imm, "printMemOffs32", 605 X86MemOffs32_32AsmOperand>; 606def offset32_64 : X86MemOffsOperand<i32imm, "printMemOffs64", 607 X86MemOffs32_64AsmOperand>; 608def offset64_8 : X86MemOffsOperand<i64imm, "printMemOffs8", 609 X86MemOffs64_8AsmOperand>; 610def offset64_16 : X86MemOffsOperand<i64imm, "printMemOffs16", 611 X86MemOffs64_16AsmOperand>; 612def offset64_32 : X86MemOffsOperand<i64imm, "printMemOffs32", 613 X86MemOffs64_32AsmOperand>; 614def offset64_64 : X86MemOffsOperand<i64imm, "printMemOffs64", 615 X86MemOffs64_64AsmOperand>; 616 617def SSECC : Operand<i8> { 618 let PrintMethod = "printSSEAVXCC"; 619 let OperandType = "OPERAND_IMMEDIATE"; 620} 621 622def AVXCC : Operand<i8> { 623 let PrintMethod = "printSSEAVXCC"; 624 let OperandType = "OPERAND_IMMEDIATE"; 625} 626 627def AVX512ICC : Operand<i8> { 628 let PrintMethod = "printSSEAVXCC"; 629 let OperandType = "OPERAND_IMMEDIATE"; 630} 631 632def XOPCC : Operand<i8> { 633 let PrintMethod = "printXOPCC"; 634 let OperandType = "OPERAND_IMMEDIATE"; 635} 636 637class ImmSExtAsmOperandClass : AsmOperandClass { 638 let SuperClasses = [ImmAsmOperand]; 639 let RenderMethod = "addImmOperands"; 640} 641 642def X86GR32orGR64AsmOperand : AsmOperandClass { 643 let Name = "GR32orGR64"; 644} 645 646def GR32orGR64 : RegisterOperand<GR32> { 647 let ParserMatchClass = X86GR32orGR64AsmOperand; 648} 649def AVX512RCOperand : AsmOperandClass { 650 let Name = "AVX512RC"; 651} 652def AVX512RC : Operand<i32> { 653 let PrintMethod = "printRoundingControl"; 654 let OperandType = "OPERAND_IMMEDIATE"; 655 let ParserMatchClass = AVX512RCOperand; 656} 657 658// Sign-extended immediate classes. We don't need to define the full lattice 659// here because there is no instruction with an ambiguity between ImmSExti64i32 660// and ImmSExti32i8. 661// 662// The strange ranges come from the fact that the assembler always works with 663// 64-bit immediates, but for a 16-bit target value we want to accept both "-1" 664// (which will be a -1ULL), and "0xFF" (-1 in 16-bits). 665 666// [0, 0x7FFFFFFF] | 667// [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF] 668def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass { 669 let Name = "ImmSExti64i32"; 670} 671 672// [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] | 673// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 674def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass { 675 let Name = "ImmSExti16i8"; 676 let SuperClasses = [ImmSExti64i32AsmOperand]; 677} 678 679// [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] | 680// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 681def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass { 682 let Name = "ImmSExti32i8"; 683} 684 685// [0, 0x0000007F] | 686// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 687def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass { 688 let Name = "ImmSExti64i8"; 689 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand, 690 ImmSExti64i32AsmOperand]; 691} 692 693// Unsigned immediate used by SSE/AVX instructions 694// [0, 0xFF] 695// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 696def ImmUnsignedi8AsmOperand : AsmOperandClass { 697 let Name = "ImmUnsignedi8"; 698 let RenderMethod = "addImmOperands"; 699} 700 701// A couple of more descriptive operand definitions. 702// 16-bits but only 8 bits are significant. 703def i16i8imm : Operand<i16> { 704 let ParserMatchClass = ImmSExti16i8AsmOperand; 705 let OperandType = "OPERAND_IMMEDIATE"; 706} 707// 32-bits but only 8 bits are significant. 708def i32i8imm : Operand<i32> { 709 let ParserMatchClass = ImmSExti32i8AsmOperand; 710 let OperandType = "OPERAND_IMMEDIATE"; 711} 712 713// 64-bits but only 32 bits are significant. 714def i64i32imm : Operand<i64> { 715 let ParserMatchClass = ImmSExti64i32AsmOperand; 716 let OperandType = "OPERAND_IMMEDIATE"; 717} 718 719// 64-bits but only 8 bits are significant. 720def i64i8imm : Operand<i64> { 721 let ParserMatchClass = ImmSExti64i8AsmOperand; 722 let OperandType = "OPERAND_IMMEDIATE"; 723} 724 725// Unsigned 8-bit immediate used by SSE/AVX instructions. 726def u8imm : Operand<i8> { 727 let PrintMethod = "printU8Imm"; 728 let ParserMatchClass = ImmUnsignedi8AsmOperand; 729 let OperandType = "OPERAND_IMMEDIATE"; 730} 731 732// 32-bit immediate but only 8-bits are significant and they are unsigned. 733// Used by some SSE/AVX instructions that use intrinsics. 734def i32u8imm : Operand<i32> { 735 let PrintMethod = "printU8Imm"; 736 let ParserMatchClass = ImmUnsignedi8AsmOperand; 737 let OperandType = "OPERAND_IMMEDIATE"; 738} 739 740// 64-bits but only 32 bits are significant, and those bits are treated as being 741// pc relative. 742def i64i32imm_pcrel : Operand<i64> { 743 let PrintMethod = "printPCRelImm"; 744 let ParserMatchClass = X86AbsMemAsmOperand; 745 let OperandType = "OPERAND_PCREL"; 746} 747 748def lea64_32mem : Operand<i32> { 749 let PrintMethod = "printanymem"; 750 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG); 751 let ParserMatchClass = X86MemAsmOperand; 752} 753 754// Memory operands that use 64-bit pointers in both ILP32 and LP64. 755def lea64mem : Operand<i64> { 756 let PrintMethod = "printanymem"; 757 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG); 758 let ParserMatchClass = X86MemAsmOperand; 759} 760 761 762//===----------------------------------------------------------------------===// 763// X86 Complex Pattern Definitions. 764// 765 766// Define X86-specific addressing mode. 767def addr : ComplexPattern<iPTR, 5, "selectAddr", [], [SDNPWantParent]>; 768def lea32addr : ComplexPattern<i32, 5, "selectLEAAddr", 769 [add, sub, mul, X86mul_imm, shl, or, frameindex], 770 []>; 771// In 64-bit mode 32-bit LEAs can use RIP-relative addressing. 772def lea64_32addr : ComplexPattern<i32, 5, "selectLEA64_32Addr", 773 [add, sub, mul, X86mul_imm, shl, or, 774 frameindex, X86WrapperRIP], 775 []>; 776 777def tls32addr : ComplexPattern<i32, 5, "selectTLSADDRAddr", 778 [tglobaltlsaddr], []>; 779 780def tls32baseaddr : ComplexPattern<i32, 5, "selectTLSADDRAddr", 781 [tglobaltlsaddr], []>; 782 783def lea64addr : ComplexPattern<i64, 5, "selectLEAAddr", 784 [add, sub, mul, X86mul_imm, shl, or, frameindex, 785 X86WrapperRIP], []>; 786 787def tls64addr : ComplexPattern<i64, 5, "selectTLSADDRAddr", 788 [tglobaltlsaddr], []>; 789 790def tls64baseaddr : ComplexPattern<i64, 5, "selectTLSADDRAddr", 791 [tglobaltlsaddr], []>; 792 793def vectoraddr : ComplexPattern<iPTR, 5, "selectVectorAddr", [],[SDNPWantParent]>; 794 795// A relocatable immediate is either an immediate operand or an operand that can 796// be relocated by the linker to an immediate, such as a regular symbol in 797// non-PIC code. 798def relocImm : ComplexPattern<iAny, 1, "selectRelocImm", [imm, X86Wrapper], [], 799 0>; 800 801//===----------------------------------------------------------------------===// 802// X86 Instruction Predicate Definitions. 803def TruePredicate : Predicate<"true">; 804 805def HasCMov : Predicate<"Subtarget->hasCMov()">; 806def NoCMov : Predicate<"!Subtarget->hasCMov()">; 807 808def HasMMX : Predicate<"Subtarget->hasMMX()">; 809def Has3DNow : Predicate<"Subtarget->has3DNow()">; 810def Has3DNowA : Predicate<"Subtarget->has3DNowA()">; 811def HasSSE1 : Predicate<"Subtarget->hasSSE1()">; 812def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">; 813def HasSSE2 : Predicate<"Subtarget->hasSSE2()">; 814def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">; 815def HasSSE3 : Predicate<"Subtarget->hasSSE3()">; 816def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">; 817def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">; 818def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">; 819def HasSSE41 : Predicate<"Subtarget->hasSSE41()">; 820def NoSSE41 : Predicate<"!Subtarget->hasSSE41()">; 821def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">; 822def HasSSE42 : Predicate<"Subtarget->hasSSE42()">; 823def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">; 824def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">; 825def NoAVX : Predicate<"!Subtarget->hasAVX()">; 826def HasAVX : Predicate<"Subtarget->hasAVX()">; 827def HasAVX2 : Predicate<"Subtarget->hasAVX2()">; 828def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">; 829def HasAVX512 : Predicate<"Subtarget->hasAVX512()">; 830def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">; 831def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">; 832def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">; 833def HasCDI : Predicate<"Subtarget->hasCDI()">; 834def HasVPOPCNTDQ : Predicate<"Subtarget->hasVPOPCNTDQ()">; 835def HasPFI : Predicate<"Subtarget->hasPFI()">; 836def HasERI : Predicate<"Subtarget->hasERI()">; 837def HasDQI : Predicate<"Subtarget->hasDQI()">; 838def NoDQI : Predicate<"!Subtarget->hasDQI()">; 839def HasBWI : Predicate<"Subtarget->hasBWI()">; 840def NoBWI : Predicate<"!Subtarget->hasBWI()">; 841def HasVLX : Predicate<"Subtarget->hasVLX()">; 842def NoVLX : Predicate<"!Subtarget->hasVLX()">; 843def NoVLX_Or_NoBWI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasBWI()">; 844def NoVLX_Or_NoDQI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasDQI()">; 845def PKU : Predicate<"Subtarget->hasPKU()">; 846def HasVNNI : Predicate<"Subtarget->hasVNNI()">; 847 848def HasBITALG : Predicate<"Subtarget->hasBITALG()">; 849def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">; 850def HasAES : Predicate<"Subtarget->hasAES()">; 851def HasVAES : Predicate<"Subtarget->hasVAES()">; 852def NoVLX_Or_NoVAES : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasVAES()">; 853def HasFXSR : Predicate<"Subtarget->hasFXSR()">; 854def HasXSAVE : Predicate<"Subtarget->hasXSAVE()">; 855def HasXSAVEOPT : Predicate<"Subtarget->hasXSAVEOPT()">; 856def HasXSAVEC : Predicate<"Subtarget->hasXSAVEC()">; 857def HasXSAVES : Predicate<"Subtarget->hasXSAVES()">; 858def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">; 859def NoVLX_Or_NoVPCLMULQDQ : 860 Predicate<"!Subtarget->hasVLX() || !Subtarget->hasVPCLMULQDQ()">; 861def HasVPCLMULQDQ : Predicate<"Subtarget->hasVPCLMULQDQ()">; 862def HasGFNI : Predicate<"Subtarget->hasGFNI()">; 863def HasFMA : Predicate<"Subtarget->hasFMA()">; 864def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; 865def NoFMA4 : Predicate<"!Subtarget->hasFMA4()">; 866def HasXOP : Predicate<"Subtarget->hasXOP()">; 867def HasTBM : Predicate<"Subtarget->hasTBM()">; 868def NoTBM : Predicate<"!Subtarget->hasTBM()">; 869def HasLWP : Predicate<"Subtarget->hasLWP()">; 870def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">; 871def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">; 872def HasF16C : Predicate<"Subtarget->hasF16C()">; 873def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">; 874def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">; 875def HasBMI : Predicate<"Subtarget->hasBMI()">; 876def HasBMI2 : Predicate<"Subtarget->hasBMI2()">; 877def NoBMI2 : Predicate<"!Subtarget->hasBMI2()">; 878def HasVBMI : Predicate<"Subtarget->hasVBMI()">; 879def HasVBMI2 : Predicate<"Subtarget->hasVBMI2()">; 880def HasIFMA : Predicate<"Subtarget->hasIFMA()">; 881def HasRTM : Predicate<"Subtarget->hasRTM()">; 882def HasADX : Predicate<"Subtarget->hasADX()">; 883def HasSHA : Predicate<"Subtarget->hasSHA()">; 884def HasSGX : Predicate<"Subtarget->hasSGX()">; 885def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">; 886def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">; 887def HasSSEPrefetch : Predicate<"Subtarget->hasSSEPrefetch()">; 888def NoSSEPrefetch : Predicate<"!Subtarget->hasSSEPrefetch()">; 889def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">; 890def HasPREFETCHWT1 : Predicate<"Subtarget->hasPREFETCHWT1()">; 891def HasLAHFSAHF : Predicate<"Subtarget->hasLAHFSAHF()">; 892def HasMWAITX : Predicate<"Subtarget->hasMWAITX()">; 893def HasCLZERO : Predicate<"Subtarget->hasCLZERO()">; 894def HasCLDEMOTE : Predicate<"Subtarget->hasCLDEMOTE()">; 895def HasMOVDIRI : Predicate<"Subtarget->hasMOVDIRI()">; 896def HasMOVDIR64B : Predicate<"Subtarget->hasMOVDIR64B()">; 897def HasPTWRITE : Predicate<"Subtarget->hasPTWRITE()">; 898def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">; 899def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">; 900def HasMPX : Predicate<"Subtarget->hasMPX()">; 901def HasSHSTK : Predicate<"Subtarget->hasSHSTK()">; 902def HasCLFLUSHOPT : Predicate<"Subtarget->hasCLFLUSHOPT()">; 903def HasCLWB : Predicate<"Subtarget->hasCLWB()">; 904def HasWBNOINVD : Predicate<"Subtarget->hasWBNOINVD()">; 905def HasRDPID : Predicate<"Subtarget->hasRDPID()">; 906def HasWAITPKG : Predicate<"Subtarget->hasWAITPKG()">; 907def HasINVPCID : Predicate<"Subtarget->hasINVPCID()">; 908def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">; 909def HasPCONFIG : Predicate<"Subtarget->hasPCONFIG()">; 910def Not64BitMode : Predicate<"!Subtarget->is64Bit()">, 911 AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">; 912def In64BitMode : Predicate<"Subtarget->is64Bit()">, 913 AssemblerPredicate<"Mode64Bit", "64-bit mode">; 914def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">; 915def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">; 916def In16BitMode : Predicate<"Subtarget->is16Bit()">, 917 AssemblerPredicate<"Mode16Bit", "16-bit mode">; 918def Not16BitMode : Predicate<"!Subtarget->is16Bit()">, 919 AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">; 920def In32BitMode : Predicate<"Subtarget->is32Bit()">, 921 AssemblerPredicate<"Mode32Bit", "32-bit mode">; 922def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; 923def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">; 924def NotWin64WithoutFP : Predicate<"!Subtarget->isTargetWin64() ||" 925 "Subtarget->getFrameLowering()->hasFP(*MF)"> { 926 let RecomputePerFunction = 1; 927} 928def IsPS4 : Predicate<"Subtarget->isTargetPS4()">; 929def NotPS4 : Predicate<"!Subtarget->isTargetPS4()">; 930def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; 931def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; 932def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; 933def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">; 934def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||" 935 "TM.getCodeModel() == CodeModel::Kernel">; 936def IsNotPIC : Predicate<"!TM.isPositionIndependent()">; 937 938// We could compute these on a per-module basis but doing so requires accessing 939// the Function object through the <Target>Subtarget and objections were raised 940// to that (see post-commit review comments for r301750). 941let RecomputePerFunction = 1 in { 942 def OptForSize : Predicate<"MF->getFunction().optForSize()">; 943 def OptForMinSize : Predicate<"MF->getFunction().optForMinSize()">; 944 def OptForSpeed : Predicate<"!MF->getFunction().optForSize()">; 945 def UseIncDec : Predicate<"!Subtarget->slowIncDec() || " 946 "MF->getFunction().optForSize()">; 947 def NoSSE41_Or_OptForSize : Predicate<"MF->getFunction().optForSize() || " 948 "!Subtarget->hasSSE41()">; 949} 950 951def CallImmAddr : Predicate<"Subtarget->isLegalToCallImmediateAddr()">; 952def FavorMemIndirectCall : Predicate<"!Subtarget->slowTwoMemOps()">; 953def HasFastMem32 : Predicate<"!Subtarget->isUnalignedMem32Slow()">; 954def HasFastLZCNT : Predicate<"Subtarget->hasFastLZCNT()">; 955def HasFastSHLDRotate : Predicate<"Subtarget->hasFastSHLDRotate()">; 956def HasERMSB : Predicate<"Subtarget->hasERMSB()">; 957def HasMFence : Predicate<"Subtarget->hasMFence()">; 958def UseRetpoline : Predicate<"Subtarget->useRetpoline()">; 959def NotUseRetpoline : Predicate<"!Subtarget->useRetpoline()">; 960 961//===----------------------------------------------------------------------===// 962// X86 Instruction Format Definitions. 963// 964 965include "X86InstrFormats.td" 966 967//===----------------------------------------------------------------------===// 968// Pattern fragments. 969// 970 971// X86 specific condition code. These correspond to CondCode in 972// X86InstrInfo.h. They must be kept in synch. 973def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE 974def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC 975def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C 976def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA 977def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z 978def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE 979def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL 980def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE 981def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG 982def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ 983def X86_COND_NO : PatLeaf<(i8 10)>; 984def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO 985def X86_COND_NS : PatLeaf<(i8 12)>; 986def X86_COND_O : PatLeaf<(i8 13)>; 987def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE 988def X86_COND_S : PatLeaf<(i8 15)>; 989 990def i16immSExt8 : ImmLeaf<i16, [{ return isInt<8>(Imm); }]>; 991def i32immSExt8 : ImmLeaf<i32, [{ return isInt<8>(Imm); }]>; 992def i64immSExt8 : ImmLeaf<i64, [{ return isInt<8>(Imm); }]>; 993def i64immSExt32 : ImmLeaf<i64, [{ return isInt<32>(Imm); }]>; 994 995// FIXME: Ideally we would just replace the above i*immSExt* matchers with 996// relocImm-based matchers, but then FastISel would be unable to use them. 997def i64relocImmSExt8 : PatLeaf<(i64 relocImm), [{ 998 return isSExtRelocImm<8>(N); 999}]>; 1000def i64relocImmSExt32 : PatLeaf<(i64 relocImm), [{ 1001 return isSExtRelocImm<32>(N); 1002}]>; 1003 1004// If we have multiple users of an immediate, it's much smaller to reuse 1005// the register, rather than encode the immediate in every instruction. 1006// This has the risk of increasing register pressure from stretched live 1007// ranges, however, the immediates should be trivial to rematerialize by 1008// the RA in the event of high register pressure. 1009// TODO : This is currently enabled for stores and binary ops. There are more 1010// cases for which this can be enabled, though this catches the bulk of the 1011// issues. 1012// TODO2 : This should really also be enabled under O2, but there's currently 1013// an issue with RA where we don't pull the constants into their users 1014// when we rematerialize them. I'll follow-up on enabling O2 after we fix that 1015// issue. 1016// TODO3 : This is currently limited to single basic blocks (DAG creation 1017// pulls block immediates to the top and merges them if necessary). 1018// Eventually, it would be nice to allow ConstantHoisting to merge constants 1019// globally for potentially added savings. 1020// 1021def imm8_su : PatLeaf<(i8 relocImm), [{ 1022 return !shouldAvoidImmediateInstFormsForSize(N); 1023}]>; 1024def imm16_su : PatLeaf<(i16 relocImm), [{ 1025 return !shouldAvoidImmediateInstFormsForSize(N); 1026}]>; 1027def imm32_su : PatLeaf<(i32 relocImm), [{ 1028 return !shouldAvoidImmediateInstFormsForSize(N); 1029}]>; 1030def i64immSExt32_su : PatLeaf<(i64immSExt32), [{ 1031 return !shouldAvoidImmediateInstFormsForSize(N); 1032}]>; 1033 1034def i16immSExt8_su : PatLeaf<(i16immSExt8), [{ 1035 return !shouldAvoidImmediateInstFormsForSize(N); 1036}]>; 1037def i32immSExt8_su : PatLeaf<(i32immSExt8), [{ 1038 return !shouldAvoidImmediateInstFormsForSize(N); 1039}]>; 1040def i64immSExt8_su : PatLeaf<(i64immSExt8), [{ 1041 return !shouldAvoidImmediateInstFormsForSize(N); 1042}]>; 1043 1044def i64relocImmSExt8_su : PatLeaf<(i64relocImmSExt8), [{ 1045 return !shouldAvoidImmediateInstFormsForSize(N); 1046}]>; 1047def i64relocImmSExt32_su : PatLeaf<(i64relocImmSExt32), [{ 1048 return !shouldAvoidImmediateInstFormsForSize(N); 1049}]>; 1050 1051// i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit 1052// unsigned field. 1053def i64immZExt32 : ImmLeaf<i64, [{ return isUInt<32>(Imm); }]>; 1054 1055def i64immZExt32SExt8 : ImmLeaf<i64, [{ 1056 return isUInt<32>(Imm) && isInt<8>(static_cast<int32_t>(Imm)); 1057}]>; 1058 1059// Helper fragments for loads. 1060 1061// It's safe to fold a zextload/extload from i1 as a regular i8 load. The 1062// upper bits are guaranteed to be zero and we were going to emit a MOV8rm 1063// which might get folded during peephole anyway. 1064def loadi8 : PatFrag<(ops node:$ptr), (i8 (unindexedload node:$ptr)), [{ 1065 LoadSDNode *LD = cast<LoadSDNode>(N); 1066 ISD::LoadExtType ExtType = LD->getExtensionType(); 1067 return ExtType == ISD::NON_EXTLOAD || ExtType == ISD::EXTLOAD || 1068 ExtType == ISD::ZEXTLOAD; 1069}]>; 1070 1071// It's always safe to treat a anyext i16 load as a i32 load if the i16 is 1072// known to be 32-bit aligned or better. Ditto for i8 to i16. 1073def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{ 1074 LoadSDNode *LD = cast<LoadSDNode>(N); 1075 ISD::LoadExtType ExtType = LD->getExtensionType(); 1076 if (ExtType == ISD::NON_EXTLOAD) 1077 return true; 1078 if (ExtType == ISD::EXTLOAD) 1079 return LD->getAlignment() >= 2 && !LD->isVolatile(); 1080 return false; 1081}]>; 1082 1083def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ 1084 LoadSDNode *LD = cast<LoadSDNode>(N); 1085 ISD::LoadExtType ExtType = LD->getExtensionType(); 1086 if (ExtType == ISD::NON_EXTLOAD) 1087 return true; 1088 if (ExtType == ISD::EXTLOAD) 1089 return LD->getAlignment() >= 4 && !LD->isVolatile(); 1090 return false; 1091}]>; 1092 1093def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>; 1094def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; 1095def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; 1096def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>; 1097def loadf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr))>; 1098def alignedloadf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr)), [{ 1099 LoadSDNode *Ld = cast<LoadSDNode>(N); 1100 return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); 1101}]>; 1102def memopf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr)), [{ 1103 LoadSDNode *Ld = cast<LoadSDNode>(N); 1104 return Subtarget->hasSSEUnalignedMem() || 1105 Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); 1106}]>; 1107 1108def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>; 1109def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; 1110def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; 1111def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>; 1112def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>; 1113def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>; 1114 1115def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>; 1116def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>; 1117def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>; 1118def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; 1119def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; 1120def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; 1121def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>; 1122def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>; 1123def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>; 1124def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>; 1125 1126def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>; 1127def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>; 1128def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>; 1129def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>; 1130def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; 1131def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; 1132def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>; 1133def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>; 1134def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>; 1135def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>; 1136 1137 1138// An 'and' node with a single use. 1139def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 1140 return N->hasOneUse(); 1141}]>; 1142// An 'srl' node with a single use. 1143def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{ 1144 return N->hasOneUse(); 1145}]>; 1146// An 'trunc' node with a single use. 1147def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{ 1148 return N->hasOneUse(); 1149}]>; 1150 1151//===----------------------------------------------------------------------===// 1152// Instruction list. 1153// 1154 1155// Nop 1156let hasSideEffects = 0, SchedRW = [WriteNop] in { 1157 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>; 1158 def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero), 1159 "nop{w}\t$zero", []>, TB, OpSize16, NotMemoryFoldable; 1160 def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero), 1161 "nop{l}\t$zero", []>, TB, OpSize32, NotMemoryFoldable; 1162 def NOOPQ : RI<0x1f, MRMXm, (outs), (ins i64mem:$zero), 1163 "nop{q}\t$zero", []>, TB, NotMemoryFoldable, 1164 Requires<[In64BitMode]>; 1165 // Also allow register so we can assemble/disassemble 1166 def NOOPWr : I<0x1f, MRMXr, (outs), (ins GR16:$zero), 1167 "nop{w}\t$zero", []>, TB, OpSize16, NotMemoryFoldable; 1168 def NOOPLr : I<0x1f, MRMXr, (outs), (ins GR32:$zero), 1169 "nop{l}\t$zero", []>, TB, OpSize32, NotMemoryFoldable; 1170 def NOOPQr : RI<0x1f, MRMXr, (outs), (ins GR64:$zero), 1171 "nop{q}\t$zero", []>, TB, NotMemoryFoldable, 1172 Requires<[In64BitMode]>; 1173 def NOOPW_19 : I<0x19, MRMXm, (outs), (ins i16mem:$zero), 1174 "nop{w}\t$zero", []>, TB, OpSize16; 1175 def NOOPL_19 : I<0x19, MRMXm, (outs), (ins i32mem:$zero), 1176 "nop{l}\t$zero", []>, TB, OpSize32; 1177 //def NOOPW_1a : I<0x1a, MRMXm, (outs), (ins i16mem:$zero), 1178 // "nop{w}\t$zero", []>, TB, OpSize16; 1179 //def NOOPL_1a : I<0x1a, MRMXm, (outs), (ins i32mem:$zero), 1180 // "nop{l}\t$zero", []>, TB, OpSize32; 1181 //def NOOPW_1b : I<0x1b, MRMXm, (outs), (ins i16mem:$zero), 1182 // "nop{w}\t$zero", []>, TB, OpSize16; 1183 //def NOOPL_1b : I<0x1b, MRMXm, (outs), (ins i32mem:$zero), 1184 // "nop{l}\t$zero", []>, TB, OpSize32; 1185 def NOOPW_1c : I<0x1c, MRMXm, (outs), (ins i16mem:$zero), 1186 "nop{w}\t$zero", []>, TB, OpSize16; 1187 //def NOOPL_1c : I<0x1c, MRMXm, (outs), (ins i32mem:$zero), 1188 // "nop{l}\t$zero", []>, TB, OpSize32; 1189 def NOOPW_1d : I<0x1d, MRMXm, (outs), (ins i16mem:$zero), 1190 "nop{w}\t$zero", []>, TB, OpSize16; 1191 def NOOPL_1d : I<0x1d, MRMXm, (outs), (ins i32mem:$zero), 1192 "nop{l}\t$zero", []>, TB, OpSize32; 1193 def NOOPW_1e : I<0x1e, MRMXm, (outs), (ins i16mem:$zero), 1194 "nop{w}\t$zero", []>, TB, OpSize16; 1195 def NOOPL_1e : I<0x1e, MRMXm, (outs), (ins i32mem:$zero), 1196 "nop{l}\t$zero", []>, TB, OpSize32; 1197 1198 def NOOP18_16m4 : I<0x18, MRM4m, (outs), (ins i16mem:$zero), 1199 "nop{w}\t$zero", []>, TB, OpSize16; 1200 def NOOP18_m4 : I<0x18, MRM4m, (outs), (ins i32mem:$zero), 1201 "nop{l}\t$zero", []>, TB, OpSize32; 1202 1203 def NOOP18_16r4 : I<0x18, MRM4r, (outs), (ins GR16:$zero), 1204 "nop{w}\t$zero", []>, TB, OpSize16; 1205 def NOOP18_r4 : I<0x18, MRM4r, (outs), (ins GR32:$zero), 1206 "nop{l}\t$zero", []>, TB, OpSize32; 1207 1208 def NOOP18_16m5 : I<0x18, MRM5m, (outs), (ins i16mem:$zero), 1209 "nop{w}\t$zero", []>, TB, OpSize16; 1210 def NOOP18_m5 : I<0x18, MRM5m, (outs), (ins i32mem:$zero), 1211 "nop{l}\t$zero", []>, TB, OpSize32; 1212 1213 def NOOP18_16r5 : I<0x18, MRM5r, (outs), (ins GR16:$zero), 1214 "nop{w}\t$zero", []>, TB, OpSize16; 1215 def NOOP18_r5 : I<0x18, MRM5r, (outs), (ins GR32:$zero), 1216 "nop{l}\t$zero", []>, TB, OpSize32; 1217 1218 def NOOP18_16m6 : I<0x18, MRM6m, (outs), (ins i16mem:$zero), 1219 "nop{w}\t$zero", []>, TB, OpSize16; 1220 def NOOP18_m6 : I<0x18, MRM6m, (outs), (ins i32mem:$zero), 1221 "nop{l}\t$zero", []>, TB, OpSize32; 1222 1223 def NOOP18_16r6 : I<0x18, MRM6r, (outs), (ins GR16:$zero), 1224 "nop{w}\t$zero", []>, TB, OpSize16; 1225 def NOOP18_r6 : I<0x18, MRM6r, (outs), (ins GR32:$zero), 1226 "nop{l}\t$zero", []>, TB, OpSize32; 1227 1228 def NOOP18_16m7 : I<0x18, MRM7m, (outs), (ins i16mem:$zero), 1229 "nop{w}\t$zero", []>, TB, OpSize16; 1230 def NOOP18_m7 : I<0x18, MRM7m, (outs), (ins i32mem:$zero), 1231 "nop{l}\t$zero", []>, TB, OpSize32; 1232 1233 def NOOP18_16r7 : I<0x18, MRM7r, (outs), (ins GR16:$zero), 1234 "nop{w}\t$zero", []>, TB, OpSize16; 1235 def NOOP18_r7 : I<0x18, MRM7r, (outs), (ins GR32:$zero), 1236 "nop{l}\t$zero", []>, TB, OpSize32; 1237} 1238 1239 1240// Constructing a stack frame. 1241def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl), 1242 "enter\t$len, $lvl", []>, Sched<[WriteMicrocoded]>; 1243 1244let SchedRW = [WriteALU] in { 1245let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in 1246def LEAVE : I<0xC9, RawFrm, (outs), (ins), "leave", []>, 1247 Requires<[Not64BitMode]>; 1248 1249let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in 1250def LEAVE64 : I<0xC9, RawFrm, (outs), (ins), "leave", []>, 1251 Requires<[In64BitMode]>; 1252} // SchedRW 1253 1254//===----------------------------------------------------------------------===// 1255// Miscellaneous Instructions. 1256// 1257 1258/* 1259let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1, 1260 SchedRW = [WriteSystem] in 1261 def Int_eh_sjlj_setup_dispatch 1262 : PseudoI<(outs), (ins), [(X86eh_sjlj_setup_dispatch)]>; 1263*/ 1264 1265let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in { 1266let mayLoad = 1, SchedRW = [WriteLoad] in { 1267def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, 1268 OpSize16; 1269def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>, 1270 OpSize32, Requires<[Not64BitMode]>; 1271// Long form for the disassembler. 1272let isCodeGenOnly = 1, ForceDisassemble = 1 in { 1273def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, 1274 OpSize16, NotMemoryFoldable; 1275def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>, 1276 OpSize32, Requires<[Not64BitMode]>, NotMemoryFoldable; 1277} // isCodeGenOnly = 1, ForceDisassemble = 1 1278} // mayLoad, SchedRW 1279let mayStore = 1, mayLoad = 1, SchedRW = [WriteRMW] in { 1280def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", []>, 1281 OpSize16; 1282def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", []>, 1283 OpSize32, Requires<[Not64BitMode]>; 1284} // mayStore, mayLoad, WriteRMW 1285 1286let mayStore = 1, SchedRW = [WriteStore] in { 1287def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, 1288 OpSize16; 1289def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>, 1290 OpSize32, Requires<[Not64BitMode]>; 1291// Long form for the disassembler. 1292let isCodeGenOnly = 1, ForceDisassemble = 1 in { 1293def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, 1294 OpSize16, NotMemoryFoldable; 1295def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>, 1296 OpSize32, Requires<[Not64BitMode]>, NotMemoryFoldable; 1297} // isCodeGenOnly = 1, ForceDisassemble = 1 1298 1299def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm), 1300 "push{w}\t$imm", []>, OpSize16; 1301def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), 1302 "push{w}\t$imm", []>, OpSize16; 1303 1304def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm), 1305 "push{l}\t$imm", []>, OpSize32, 1306 Requires<[Not64BitMode]>; 1307def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm), 1308 "push{l}\t$imm", []>, OpSize32, 1309 Requires<[Not64BitMode]>; 1310} // mayStore, SchedRW 1311 1312let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in { 1313def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src", []>, 1314 OpSize16; 1315def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src", []>, 1316 OpSize32, Requires<[Not64BitMode]>; 1317} // mayLoad, mayStore, SchedRW 1318 1319} 1320 1321/* 1322let mayLoad = 1, mayStore = 1, usesCustomInserter = 1, 1323 SchedRW = [WriteRMW], Defs = [ESP] in { 1324 let Uses = [ESP] in 1325 def RDFLAGS32 : PseudoI<(outs GR32:$dst), (ins), 1326 [(set GR32:$dst, (int_x86_flags_read_u32))]>, 1327 Requires<[Not64BitMode]>; 1328 1329 let Uses = [RSP] in 1330 def RDFLAGS64 : PseudoI<(outs GR64:$dst), (ins), 1331 [(set GR64:$dst, (int_x86_flags_read_u64))]>, 1332 Requires<[In64BitMode]>; 1333} 1334 1335let mayLoad = 1, mayStore = 1, usesCustomInserter = 1, 1336 SchedRW = [WriteRMW] in { 1337 let Defs = [ESP, EFLAGS, DF], Uses = [ESP] in 1338 def WRFLAGS32 : PseudoI<(outs), (ins GR32:$src), 1339 [(int_x86_flags_write_u32 GR32:$src)]>, 1340 Requires<[Not64BitMode]>; 1341 1342 let Defs = [RSP, EFLAGS, DF], Uses = [RSP] in 1343 def WRFLAGS64 : PseudoI<(outs), (ins GR64:$src), 1344 [(int_x86_flags_write_u64 GR64:$src)]>, 1345 Requires<[In64BitMode]>; 1346} 1347*/ 1348 1349let Defs = [ESP, EFLAGS, DF], Uses = [ESP], mayLoad = 1, hasSideEffects=0, 1350 SchedRW = [WriteLoad] in { 1351def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize16; 1352def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>, OpSize32, 1353 Requires<[Not64BitMode]>; 1354} 1355 1356let Defs = [ESP], Uses = [ESP, EFLAGS, DF], mayStore = 1, hasSideEffects=0, 1357 SchedRW = [WriteStore] in { 1358def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize16; 1359def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>, OpSize32, 1360 Requires<[Not64BitMode]>; 1361} 1362 1363let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in { 1364let mayLoad = 1, SchedRW = [WriteLoad] in { 1365def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>, 1366 OpSize32, Requires<[In64BitMode]>; 1367// Long form for the disassembler. 1368let isCodeGenOnly = 1, ForceDisassemble = 1 in { 1369def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>, 1370 OpSize32, Requires<[In64BitMode]>, NotMemoryFoldable; 1371} // isCodeGenOnly = 1, ForceDisassemble = 1 1372} // mayLoad, SchedRW 1373let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in 1374def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", []>, 1375 OpSize32, Requires<[In64BitMode]>; 1376let mayStore = 1, SchedRW = [WriteStore] in { 1377def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", []>, 1378 OpSize32, Requires<[In64BitMode]>; 1379// Long form for the disassembler. 1380let isCodeGenOnly = 1, ForceDisassemble = 1 in { 1381def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>, 1382 OpSize32, Requires<[In64BitMode]>, NotMemoryFoldable; 1383} // isCodeGenOnly = 1, ForceDisassemble = 1 1384} // mayStore, SchedRW 1385let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in { 1386def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>, 1387 OpSize32, Requires<[In64BitMode]>; 1388} // mayLoad, mayStore, SchedRW 1389} 1390 1391let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1, 1392 SchedRW = [WriteStore] in { 1393def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm), 1394 "push{q}\t$imm", []>, OpSize32, 1395 Requires<[In64BitMode]>; 1396def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm), 1397 "push{q}\t$imm", []>, OpSize32, 1398 Requires<[In64BitMode]>; 1399} 1400 1401let Defs = [RSP, EFLAGS, DF], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in 1402def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", []>, 1403 OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>; 1404let Defs = [RSP], Uses = [RSP, EFLAGS, DF], mayStore = 1, hasSideEffects=0 in 1405def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", []>, 1406 OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>; 1407 1408let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP], 1409 mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in { 1410def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", []>, 1411 OpSize32, Requires<[Not64BitMode]>; 1412def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", []>, 1413 OpSize16, Requires<[Not64BitMode]>; 1414} 1415let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], 1416 mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in { 1417def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", []>, 1418 OpSize32, Requires<[Not64BitMode]>; 1419def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", []>, 1420 OpSize16, Requires<[Not64BitMode]>; 1421} 1422 1423let Constraints = "$src = $dst", SchedRW = [WriteBSWAP32] in { 1424// This instruction is a consequence of BSWAP32r observing operand size. The 1425// encoding is valid, but the behavior is undefined. 1426let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in 1427def BSWAP16r_BAD : I<0xC8, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), 1428 "bswap{w}\t$dst", []>, OpSize16, TB; 1429// GR32 = bswap GR32 1430def BSWAP32r : I<0xC8, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), 1431 "bswap{l}\t$dst", 1432 [(set GR32:$dst, (bswap GR32:$src))]>, OpSize32, TB; 1433 1434let SchedRW = [WriteBSWAP64] in 1435def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), 1436 "bswap{q}\t$dst", 1437 [(set GR64:$dst, (bswap GR64:$src))]>, TB; 1438} // Constraints = "$src = $dst", SchedRW 1439 1440// Bit scan instructions. 1441let Defs = [EFLAGS] in { 1442def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1443 "bsf{w}\t{$src, $dst|$dst, $src}", 1444 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, 1445 PS, OpSize16, Sched<[WriteBSF]>; 1446def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1447 "bsf{w}\t{$src, $dst|$dst, $src}", 1448 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, 1449 PS, OpSize16, Sched<[WriteBSFLd]>; 1450def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1451 "bsf{l}\t{$src, $dst|$dst, $src}", 1452 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, 1453 PS, OpSize32, Sched<[WriteBSF]>; 1454def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1455 "bsf{l}\t{$src, $dst|$dst, $src}", 1456 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, 1457 PS, OpSize32, Sched<[WriteBSFLd]>; 1458def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1459 "bsf{q}\t{$src, $dst|$dst, $src}", 1460 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, 1461 PS, Sched<[WriteBSF]>; 1462def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1463 "bsf{q}\t{$src, $dst|$dst, $src}", 1464 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, 1465 PS, Sched<[WriteBSFLd]>; 1466 1467def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1468 "bsr{w}\t{$src, $dst|$dst, $src}", 1469 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, 1470 PS, OpSize16, Sched<[WriteBSR]>; 1471def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1472 "bsr{w}\t{$src, $dst|$dst, $src}", 1473 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, 1474 PS, OpSize16, Sched<[WriteBSRLd]>; 1475def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1476 "bsr{l}\t{$src, $dst|$dst, $src}", 1477 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, 1478 PS, OpSize32, Sched<[WriteBSR]>; 1479def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1480 "bsr{l}\t{$src, $dst|$dst, $src}", 1481 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, 1482 PS, OpSize32, Sched<[WriteBSRLd]>; 1483def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1484 "bsr{q}\t{$src, $dst|$dst, $src}", 1485 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>, 1486 PS, Sched<[WriteBSR]>; 1487def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1488 "bsr{q}\t{$src, $dst|$dst, $src}", 1489 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>, 1490 PS, Sched<[WriteBSRLd]>; 1491} // Defs = [EFLAGS] 1492 1493let SchedRW = [WriteMicrocoded] in { 1494let Defs = [EDI,ESI], Uses = [EDI,ESI,DF] in { 1495def MOVSB : I<0xA4, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src), 1496 "movsb\t{$src, $dst|$dst, $src}", []>; 1497def MOVSW : I<0xA5, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src), 1498 "movsw\t{$src, $dst|$dst, $src}", []>, OpSize16; 1499def MOVSL : I<0xA5, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src), 1500 "movs{l|d}\t{$src, $dst|$dst, $src}", []>, OpSize32; 1501def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src), 1502 "movsq\t{$src, $dst|$dst, $src}", []>, 1503 Requires<[In64BitMode]>; 1504} 1505 1506let Defs = [EDI], Uses = [AL,EDI,DF] in 1507def STOSB : I<0xAA, RawFrmDst, (outs), (ins dstidx8:$dst), 1508 "stosb\t{%al, $dst|$dst, al}", []>; 1509let Defs = [EDI], Uses = [AX,EDI,DF] in 1510def STOSW : I<0xAB, RawFrmDst, (outs), (ins dstidx16:$dst), 1511 "stosw\t{%ax, $dst|$dst, ax}", []>, OpSize16; 1512let Defs = [EDI], Uses = [EAX,EDI,DF] in 1513def STOSL : I<0xAB, RawFrmDst, (outs), (ins dstidx32:$dst), 1514 "stos{l|d}\t{%eax, $dst|$dst, eax}", []>, OpSize32; 1515let Defs = [RDI], Uses = [RAX,RDI,DF] in 1516def STOSQ : RI<0xAB, RawFrmDst, (outs), (ins dstidx64:$dst), 1517 "stosq\t{%rax, $dst|$dst, rax}", []>, 1518 Requires<[In64BitMode]>; 1519 1520let Defs = [EDI,EFLAGS], Uses = [AL,EDI,DF] in 1521def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst), 1522 "scasb\t{$dst, %al|al, $dst}", []>; 1523let Defs = [EDI,EFLAGS], Uses = [AX,EDI,DF] in 1524def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst), 1525 "scasw\t{$dst, %ax|ax, $dst}", []>, OpSize16; 1526let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,DF] in 1527def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst), 1528 "scas{l|d}\t{$dst, %eax|eax, $dst}", []>, OpSize32; 1529let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,DF] in 1530def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst), 1531 "scasq\t{$dst, %rax|rax, $dst}", []>, 1532 Requires<[In64BitMode]>; 1533 1534let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,DF] in { 1535def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src), 1536 "cmpsb\t{$dst, $src|$src, $dst}", []>; 1537def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src), 1538 "cmpsw\t{$dst, $src|$src, $dst}", []>, OpSize16; 1539def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src), 1540 "cmps{l|d}\t{$dst, $src|$src, $dst}", []>, OpSize32; 1541def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src), 1542 "cmpsq\t{$dst, $src|$src, $dst}", []>, 1543 Requires<[In64BitMode]>; 1544} 1545} // SchedRW 1546 1547//===----------------------------------------------------------------------===// 1548// Move Instructions. 1549// 1550let SchedRW = [WriteMove] in { 1551let hasSideEffects = 0, isMoveReg = 1 in { 1552def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), 1553 "mov{b}\t{$src, $dst|$dst, $src}", []>; 1554def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1555 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16; 1556def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 1557 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32; 1558def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 1559 "mov{q}\t{$src, $dst|$dst, $src}", []>; 1560} 1561 1562let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 1563def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src), 1564 "mov{b}\t{$src, $dst|$dst, $src}", 1565 [(set GR8:$dst, imm:$src)]>; 1566def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src), 1567 "mov{w}\t{$src, $dst|$dst, $src}", 1568 [(set GR16:$dst, imm:$src)]>, OpSize16; 1569def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src), 1570 "mov{l}\t{$src, $dst|$dst, $src}", 1571 [(set GR32:$dst, relocImm:$src)]>, OpSize32; 1572def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src), 1573 "mov{q}\t{$src, $dst|$dst, $src}", 1574 [(set GR64:$dst, i64immSExt32:$src)]>; 1575} 1576let isReMaterializable = 1 in { 1577def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src), 1578 "movabs{q}\t{$src, $dst|$dst, $src}", 1579 [(set GR64:$dst, relocImm:$src)]>; 1580} 1581 1582// Longer forms that use a ModR/M byte. Needed for disassembler 1583let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { 1584def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src), 1585 "mov{b}\t{$src, $dst|$dst, $src}", []>, 1586 FoldGenData<"MOV8ri">; 1587def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src), 1588 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16, 1589 FoldGenData<"MOV16ri">; 1590def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src), 1591 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32, 1592 FoldGenData<"MOV32ri">; 1593} 1594} // SchedRW 1595 1596let SchedRW = [WriteStore] in { 1597def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src), 1598 "mov{b}\t{$src, $dst|$dst, $src}", 1599 [(store (i8 imm8_su:$src), addr:$dst)]>; 1600def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src), 1601 "mov{w}\t{$src, $dst|$dst, $src}", 1602 [(store (i16 imm16_su:$src), addr:$dst)]>, OpSize16; 1603def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src), 1604 "mov{l}\t{$src, $dst|$dst, $src}", 1605 [(store (i32 imm32_su:$src), addr:$dst)]>, OpSize32; 1606def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src), 1607 "mov{q}\t{$src, $dst|$dst, $src}", 1608 [(store i64immSExt32_su:$src, addr:$dst)]>, 1609 Requires<[In64BitMode]>; 1610} // SchedRW 1611 1612let hasSideEffects = 0 in { 1613 1614/// Memory offset versions of moves. The immediate is an address mode sized 1615/// offset from the segment base. 1616let SchedRW = [WriteALU] in { 1617let mayLoad = 1 in { 1618let Defs = [AL] in 1619def MOV8ao32 : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset32_8:$src), 1620 "mov{b}\t{$src, %al|al, $src}", []>, 1621 AdSize32; 1622let Defs = [AX] in 1623def MOV16ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_16:$src), 1624 "mov{w}\t{$src, %ax|ax, $src}", []>, 1625 OpSize16, AdSize32; 1626let Defs = [EAX] in 1627def MOV32ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_32:$src), 1628 "mov{l}\t{$src, %eax|eax, $src}", []>, 1629 OpSize32, AdSize32; 1630let Defs = [RAX] in 1631def MOV64ao32 : RIi32<0xA1, RawFrmMemOffs, (outs), (ins offset32_64:$src), 1632 "mov{q}\t{$src, %rax|rax, $src}", []>, 1633 AdSize32; 1634 1635let Defs = [AL] in 1636def MOV8ao16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset16_8:$src), 1637 "mov{b}\t{$src, %al|al, $src}", []>, AdSize16; 1638let Defs = [AX] in 1639def MOV16ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_16:$src), 1640 "mov{w}\t{$src, %ax|ax, $src}", []>, 1641 OpSize16, AdSize16; 1642let Defs = [EAX] in 1643def MOV32ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_32:$src), 1644 "mov{l}\t{$src, %eax|eax, $src}", []>, 1645 AdSize16, OpSize32; 1646} // mayLoad 1647let mayStore = 1 in { 1648let Uses = [AL] in 1649def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs), (ins offset32_8:$dst), 1650 "mov{b}\t{%al, $dst|$dst, al}", []>, AdSize32; 1651let Uses = [AX] in 1652def MOV16o32a : Ii32<0xA3, RawFrmMemOffs, (outs), (ins offset32_16:$dst), 1653 "mov{w}\t{%ax, $dst|$dst, ax}", []>, 1654 OpSize16, AdSize32; 1655let Uses = [EAX] in 1656def MOV32o32a : Ii32<0xA3, RawFrmMemOffs, (outs), (ins offset32_32:$dst), 1657 "mov{l}\t{%eax, $dst|$dst, eax}", []>, 1658 OpSize32, AdSize32; 1659let Uses = [RAX] in 1660def MOV64o32a : RIi32<0xA3, RawFrmMemOffs, (outs), (ins offset32_64:$dst), 1661 "mov{q}\t{%rax, $dst|$dst, rax}", []>, 1662 AdSize32; 1663 1664let Uses = [AL] in 1665def MOV8o16a : Ii16<0xA2, RawFrmMemOffs, (outs), (ins offset16_8:$dst), 1666 "mov{b}\t{%al, $dst|$dst, al}", []>, AdSize16; 1667let Uses = [AX] in 1668def MOV16o16a : Ii16<0xA3, RawFrmMemOffs, (outs), (ins offset16_16:$dst), 1669 "mov{w}\t{%ax, $dst|$dst, ax}", []>, 1670 OpSize16, AdSize16; 1671let Uses = [EAX] in 1672def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs), (ins offset16_32:$dst), 1673 "mov{l}\t{%eax, $dst|$dst, eax}", []>, 1674 OpSize32, AdSize16; 1675} // mayStore 1676 1677// These forms all have full 64-bit absolute addresses in their instructions 1678// and use the movabs mnemonic to indicate this specific form. 1679let mayLoad = 1 in { 1680let Defs = [AL] in 1681def MOV8ao64 : Ii64<0xA0, RawFrmMemOffs, (outs), (ins offset64_8:$src), 1682 "movabs{b}\t{$src, %al|al, $src}", []>, 1683 AdSize64; 1684let Defs = [AX] in 1685def MOV16ao64 : Ii64<0xA1, RawFrmMemOffs, (outs), (ins offset64_16:$src), 1686 "movabs{w}\t{$src, %ax|ax, $src}", []>, 1687 OpSize16, AdSize64; 1688let Defs = [EAX] in 1689def MOV32ao64 : Ii64<0xA1, RawFrmMemOffs, (outs), (ins offset64_32:$src), 1690 "movabs{l}\t{$src, %eax|eax, $src}", []>, 1691 OpSize32, AdSize64; 1692let Defs = [RAX] in 1693def MOV64ao64 : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64_64:$src), 1694 "movabs{q}\t{$src, %rax|rax, $src}", []>, 1695 AdSize64; 1696} // mayLoad 1697 1698let mayStore = 1 in { 1699let Uses = [AL] in 1700def MOV8o64a : Ii64<0xA2, RawFrmMemOffs, (outs), (ins offset64_8:$dst), 1701 "movabs{b}\t{%al, $dst|$dst, al}", []>, 1702 AdSize64; 1703let Uses = [AX] in 1704def MOV16o64a : Ii64<0xA3, RawFrmMemOffs, (outs), (ins offset64_16:$dst), 1705 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, 1706 OpSize16, AdSize64; 1707let Uses = [EAX] in 1708def MOV32o64a : Ii64<0xA3, RawFrmMemOffs, (outs), (ins offset64_32:$dst), 1709 "movabs{l}\t{%eax, $dst|$dst, eax}", []>, 1710 OpSize32, AdSize64; 1711let Uses = [RAX] in 1712def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs), (ins offset64_64:$dst), 1713 "movabs{q}\t{%rax, $dst|$dst, rax}", []>, 1714 AdSize64; 1715} // mayStore 1716} // SchedRW 1717} // hasSideEffects = 0 1718 1719let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, 1720 SchedRW = [WriteMove], isMoveReg = 1 in { 1721def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src), 1722 "mov{b}\t{$src, $dst|$dst, $src}", []>, 1723 FoldGenData<"MOV8rr">; 1724def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1725 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16, 1726 FoldGenData<"MOV16rr">; 1727def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1728 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32, 1729 FoldGenData<"MOV32rr">; 1730def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1731 "mov{q}\t{$src, $dst|$dst, $src}", []>, 1732 FoldGenData<"MOV64rr">; 1733} 1734 1735// Reversed version with ".s" suffix for GAS compatibility. 1736//// def : InstAlias<"mov{b}.s\t{$src, $dst|$dst, $src}", 1737// (MOV8rr_REV GR8:$dst, GR8:$src), 0>; 1738//// def : InstAlias<"mov{w}.s\t{$src, $dst|$dst, $src}", 1739// (MOV16rr_REV GR16:$dst, GR16:$src), 0>; 1740//// def : InstAlias<"mov{l}.s\t{$src, $dst|$dst, $src}", 1741// (MOV32rr_REV GR32:$dst, GR32:$src), 0>; 1742//// def : InstAlias<"mov{q}.s\t{$src, $dst|$dst, $src}", 1743// (MOV64rr_REV GR64:$dst, GR64:$src), 0>; 1744//// def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", 1745// (MOV8rr_REV GR8:$dst, GR8:$src), 0, "att">; 1746//// def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", 1747// (MOV16rr_REV GR16:$dst, GR16:$src), 0, "att">; 1748//// def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", 1749// (MOV32rr_REV GR32:$dst, GR32:$src), 0, "att">; 1750//// def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", 1751// (MOV64rr_REV GR64:$dst, GR64:$src), 0, "att">; 1752 1753let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in { 1754def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src), 1755 "mov{b}\t{$src, $dst|$dst, $src}", 1756 [(set GR8:$dst, (loadi8 addr:$src))]>; 1757def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1758 "mov{w}\t{$src, $dst|$dst, $src}", 1759 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize16; 1760def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1761 "mov{l}\t{$src, $dst|$dst, $src}", 1762 [(set GR32:$dst, (loadi32 addr:$src))]>, OpSize32; 1763def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1764 "mov{q}\t{$src, $dst|$dst, $src}", 1765 [(set GR64:$dst, (load addr:$src))]>; 1766} 1767 1768let SchedRW = [WriteStore] in { 1769def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), 1770 "mov{b}\t{$src, $dst|$dst, $src}", 1771 [(store GR8:$src, addr:$dst)]>; 1772def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1773 "mov{w}\t{$src, $dst|$dst, $src}", 1774 [(store GR16:$src, addr:$dst)]>, OpSize16; 1775def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1776 "mov{l}\t{$src, $dst|$dst, $src}", 1777 [(store GR32:$src, addr:$dst)]>, OpSize32; 1778def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1779 "mov{q}\t{$src, $dst|$dst, $src}", 1780 [(store GR64:$src, addr:$dst)]>; 1781} // SchedRW 1782 1783// Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so 1784// that they can be used for copying and storing h registers, which can't be 1785// encoded when a REX prefix is present. 1786let isCodeGenOnly = 1 in { 1787let hasSideEffects = 0, isMoveReg = 1 in 1788def MOV8rr_NOREX : I<0x88, MRMDestReg, 1789 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src), 1790 "mov{b}\t{$src, $dst|$dst, $src}", []>, 1791 Sched<[WriteMove]>; 1792let mayStore = 1, hasSideEffects = 0 in 1793def MOV8mr_NOREX : I<0x88, MRMDestMem, 1794 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src), 1795 "mov{b}\t{$src, $dst|$dst, $src}", []>, 1796 Sched<[WriteStore]>; 1797let mayLoad = 1, hasSideEffects = 0, 1798 canFoldAsLoad = 1, isReMaterializable = 1 in 1799def MOV8rm_NOREX : I<0x8A, MRMSrcMem, 1800 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src), 1801 "mov{b}\t{$src, $dst|$dst, $src}", []>, 1802 Sched<[WriteLoad]>; 1803} 1804 1805 1806// Condition code ops, incl. set if equal/not equal/... 1807let SchedRW = [WriteLAHFSAHF] in { 1808let Defs = [EFLAGS], Uses = [AH] in 1809def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", 1810 [(set EFLAGS, (X86sahf AH))]>, 1811 Requires<[HasLAHFSAHF]>; 1812let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in 1813def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>, // AH = flags 1814 Requires<[HasLAHFSAHF]>; 1815} // SchedRW 1816 1817//===----------------------------------------------------------------------===// 1818// Bit tests instructions: BT, BTS, BTR, BTC. 1819 1820let Defs = [EFLAGS] in { 1821let SchedRW = [WriteBitTest] in { 1822def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1823 "bt{w}\t{$src2, $src1|$src1, $src2}", 1824 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, 1825 OpSize16, TB, NotMemoryFoldable; 1826def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1827 "bt{l}\t{$src2, $src1|$src1, $src2}", 1828 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, 1829 OpSize32, TB, NotMemoryFoldable; 1830def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1831 "bt{q}\t{$src2, $src1|$src1, $src2}", 1832 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))]>, TB, 1833 NotMemoryFoldable; 1834} // SchedRW 1835 1836// Unlike with the register+register form, the memory+register form of the 1837// bt instruction does not ignore the high bits of the index. From ISel's 1838// perspective, this is pretty bizarre. Make these instructions disassembly 1839// only for now. These instructions are also slow on modern CPUs so that's 1840// another reason to avoid generating them. 1841 1842let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in { 1843 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1844 "bt{w}\t{$src2, $src1|$src1, $src2}", 1845 []>, OpSize16, TB, NotMemoryFoldable; 1846 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1847 "bt{l}\t{$src2, $src1|$src1, $src2}", 1848 []>, OpSize32, TB, NotMemoryFoldable; 1849 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1850 "bt{q}\t{$src2, $src1|$src1, $src2}", 1851 []>, TB, NotMemoryFoldable; 1852} 1853 1854let SchedRW = [WriteBitTest] in { 1855def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1856 "bt{w}\t{$src2, $src1|$src1, $src2}", 1857 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>, 1858 OpSize16, TB; 1859def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1860 "bt{l}\t{$src2, $src1|$src1, $src2}", 1861 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, 1862 OpSize32, TB; 1863def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1864 "bt{q}\t{$src2, $src1|$src1, $src2}", 1865 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))]>, TB; 1866} // SchedRW 1867 1868// Note that these instructions aren't slow because that only applies when the 1869// other operand is in a register. When it's an immediate, bt is still fast. 1870let SchedRW = [WriteALU] in { 1871def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1872 "bt{w}\t{$src2, $src1|$src1, $src2}", 1873 [(set EFLAGS, (X86bt (loadi16 addr:$src1), 1874 i16immSExt8:$src2))]>, 1875 OpSize16, TB; 1876def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1877 "bt{l}\t{$src2, $src1|$src1, $src2}", 1878 [(set EFLAGS, (X86bt (loadi32 addr:$src1), 1879 i32immSExt8:$src2))]>, 1880 OpSize32, TB; 1881def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1882 "bt{q}\t{$src2, $src1|$src1, $src2}", 1883 [(set EFLAGS, (X86bt (loadi64 addr:$src1), 1884 i64immSExt8:$src2))]>, TB, 1885 Requires<[In64BitMode]>; 1886} // SchedRW 1887 1888let hasSideEffects = 0 in { 1889let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { 1890def BTC16rr : I<0xBB, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 1891 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, 1892 OpSize16, TB, NotMemoryFoldable; 1893def BTC32rr : I<0xBB, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 1894 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, 1895 OpSize32, TB, NotMemoryFoldable; 1896def BTC64rr : RI<0xBB, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 1897 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 1898 NotMemoryFoldable; 1899} // SchedRW 1900 1901let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1902def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1903 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, 1904 OpSize16, TB, NotMemoryFoldable; 1905def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1906 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, 1907 OpSize32, TB, NotMemoryFoldable; 1908def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1909 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 1910 NotMemoryFoldable; 1911} 1912 1913let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { 1914def BTC16ri8 : Ii8<0xBA, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), 1915 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; 1916def BTC32ri8 : Ii8<0xBA, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), 1917 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; 1918def BTC64ri8 : RIi8<0xBA, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), 1919 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1920} // SchedRW 1921 1922let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1923def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1924 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; 1925def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1926 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; 1927def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1928 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 1929 Requires<[In64BitMode]>; 1930} 1931 1932let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { 1933def BTR16rr : I<0xB3, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 1934 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, 1935 OpSize16, TB, NotMemoryFoldable; 1936def BTR32rr : I<0xB3, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 1937 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, 1938 OpSize32, TB, NotMemoryFoldable; 1939def BTR64rr : RI<0xB3, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 1940 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 1941 NotMemoryFoldable; 1942} // SchedRW 1943 1944let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1945def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1946 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, 1947 OpSize16, TB, NotMemoryFoldable; 1948def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1949 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, 1950 OpSize32, TB, NotMemoryFoldable; 1951def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1952 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 1953 NotMemoryFoldable; 1954} 1955 1956let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { 1957def BTR16ri8 : Ii8<0xBA, MRM6r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), 1958 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, 1959 OpSize16, TB; 1960def BTR32ri8 : Ii8<0xBA, MRM6r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), 1961 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, 1962 OpSize32, TB; 1963def BTR64ri8 : RIi8<0xBA, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), 1964 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1965} // SchedRW 1966 1967let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1968def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1969 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, 1970 OpSize16, TB; 1971def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1972 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, 1973 OpSize32, TB; 1974def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1975 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 1976 Requires<[In64BitMode]>; 1977} 1978 1979let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { 1980def BTS16rr : I<0xAB, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 1981 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, 1982 OpSize16, TB, NotMemoryFoldable; 1983def BTS32rr : I<0xAB, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 1984 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, 1985 OpSize32, TB, NotMemoryFoldable; 1986def BTS64rr : RI<0xAB, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 1987 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 1988 NotMemoryFoldable; 1989} // SchedRW 1990 1991let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1992def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1993 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, 1994 OpSize16, TB, NotMemoryFoldable; 1995def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1996 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, 1997 OpSize32, TB, NotMemoryFoldable; 1998def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1999 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 2000 NotMemoryFoldable; 2001} 2002 2003let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { 2004def BTS16ri8 : Ii8<0xBA, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), 2005 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; 2006def BTS32ri8 : Ii8<0xBA, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), 2007 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; 2008def BTS64ri8 : RIi8<0xBA, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), 2009 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 2010} // SchedRW 2011 2012let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 2013def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 2014 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; 2015def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 2016 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; 2017def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 2018 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 2019 Requires<[In64BitMode]>; 2020} 2021} // hasSideEffects = 0 2022} // Defs = [EFLAGS] 2023 2024 2025//===----------------------------------------------------------------------===// 2026// Atomic support 2027// 2028 2029// Atomic swap. These are just normal xchg instructions. But since a memory 2030// operand is referenced, the atomicity is ensured. 2031multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag> { 2032 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in { 2033 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst), 2034 (ins GR8:$val, i8mem:$ptr), 2035 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"), 2036 [(set 2037 GR8:$dst, 2038 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))]>; 2039 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst), 2040 (ins GR16:$val, i16mem:$ptr), 2041 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"), 2042 [(set 2043 GR16:$dst, 2044 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))]>, 2045 OpSize16; 2046 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst), 2047 (ins GR32:$val, i32mem:$ptr), 2048 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"), 2049 [(set 2050 GR32:$dst, 2051 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))]>, 2052 OpSize32; 2053 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst), 2054 (ins GR64:$val, i64mem:$ptr), 2055 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"), 2056 [(set 2057 GR64:$dst, 2058 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))]>; 2059 } 2060} 2061 2062defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap">, NotMemoryFoldable; 2063 2064// Swap between registers. 2065let SchedRW = [WriteALU] in { 2066let Constraints = "$src1 = $dst1, $src2 = $dst2", hasSideEffects = 0 in { 2067def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst1, GR8:$dst2), 2068 (ins GR8:$src1, GR8:$src2), 2069 "xchg{b}\t{$src1, $src2|$src2, $src1}", []>, NotMemoryFoldable; 2070def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst1, GR16:$dst2), 2071 (ins GR16:$src1, GR16:$src2), 2072 "xchg{w}\t{$src1, $src2|$src2, $src1}", []>, 2073 OpSize16, NotMemoryFoldable; 2074def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst1, GR32:$dst2), 2075 (ins GR32:$src1, GR32:$src2), 2076 "xchg{l}\t{$src1, $src2|$src2, $src1}", []>, 2077 OpSize32, NotMemoryFoldable; 2078def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst1, GR64:$dst2), 2079 (ins GR64:$src1 ,GR64:$src2), 2080 "xchg{q}\t{$src1, $src2|$src2, $src1}", []>, NotMemoryFoldable; 2081} 2082 2083def NOOP19rr: I<0x19, MRMSrcReg, (outs), (ins GR32:$val, GR32:$src), 2084 "nop\t{$val, $src|$src, $val}", []>, TB, 2085 OpSize32; 2086 2087// Swap between EAX and other registers. 2088let Constraints = "$src = $dst", hasSideEffects = 0 in { 2089let Uses = [AX], Defs = [AX] in 2090def XCHG16ar : I<0x90, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), 2091 "xchg{w}\t{%ax, $src|$src, ax}", []>, OpSize16; 2092let Uses = [EAX], Defs = [EAX] in 2093def XCHG32ar : I<0x90, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), 2094 "xchg{l}\t{%eax, $src|$src, eax}", []>, OpSize32; 2095let Uses = [RAX], Defs = [RAX] in 2096def XCHG64ar : RI<0x90, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), 2097 "xchg{q}\t{%rax, $src|$src, rax}", []>; 2098} 2099} // SchedRW 2100 2101let hasSideEffects = 0, Constraints = "$src1 = $dst1, $src2 = $dst2", 2102 Defs = [EFLAGS], SchedRW = [WriteALU] in { 2103def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst1, GR8:$dst2), 2104 (ins GR8:$src1, GR8:$src2), 2105 "xadd{b}\t{$src2, $src1|$src1, $src2}", []>, TB; 2106def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst1, GR16:$dst2), 2107 (ins GR16:$src1, GR16:$src2), 2108 "xadd{w}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize16; 2109def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst1, GR32:$dst2), 2110 (ins GR32:$src1, GR32:$src2), 2111 "xadd{l}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize32; 2112def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst1, GR64:$dst2), 2113 (ins GR64:$src1, GR64:$src2), 2114 "xadd{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 2115} // SchedRW 2116 2117let mayLoad = 1, mayStore = 1, hasSideEffects = 0, Constraints = "$val = $dst", 2118 Defs = [EFLAGS], SchedRW = [WriteALULd, WriteRMW] in { 2119def XADD8rm : I<0xC0, MRMSrcMem, (outs GR8:$dst), 2120 (ins GR8:$val, i8mem:$ptr), 2121 "xadd{b}\t{$val, $ptr|$ptr, $val}", []>, TB; 2122def XADD16rm : I<0xC1, MRMSrcMem, (outs GR16:$dst), 2123 (ins GR16:$val, i16mem:$ptr), 2124 "xadd{w}\t{$val, $ptr|$ptr, $val}", []>, TB, 2125 OpSize16; 2126def XADD32rm : I<0xC1, MRMSrcMem, (outs GR32:$dst), 2127 (ins GR32:$val, i32mem:$ptr), 2128 "xadd{l}\t{$val, $ptr|$ptr, $val}", []>, TB, 2129 OpSize32; 2130def XADD64rm : RI<0xC1, MRMSrcMem, (outs GR64:$dst), 2131 (ins GR64:$val, i64mem:$ptr), 2132 "xadd{q}\t{$val, $ptr|$ptr, $val}", []>, TB; 2133 2134} 2135 2136let SchedRW = [WriteALU], hasSideEffects = 0 in { 2137let Defs = [AL, EFLAGS], Uses = [AL] in 2138def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), 2139 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB, 2140 NotMemoryFoldable; 2141let Defs = [AX, EFLAGS], Uses = [AX] in 2142def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 2143 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16, 2144 NotMemoryFoldable; 2145let Defs = [EAX, EFLAGS], Uses = [EAX] in 2146def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 2147 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32, 2148 NotMemoryFoldable; 2149let Defs = [RAX, EFLAGS], Uses = [RAX] in 2150def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 2151 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB, 2152 NotMemoryFoldable; 2153} // SchedRW, hasSideEffects 2154 2155let SchedRW = [WriteALULd, WriteRMW], mayLoad = 1, mayStore = 1, 2156 hasSideEffects = 0 in { 2157let Defs = [AL, EFLAGS], Uses = [AL] in 2158def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), 2159 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB, 2160 NotMemoryFoldable; 2161let Defs = [AX, EFLAGS], Uses = [AX] in 2162def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 2163 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16, 2164 NotMemoryFoldable; 2165let Defs = [EAX, EFLAGS], Uses = [EAX] in 2166def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 2167 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32, 2168 NotMemoryFoldable; 2169let Defs = [RAX, EFLAGS], Uses = [RAX] in 2170def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 2171 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB, 2172 NotMemoryFoldable; 2173 2174let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in 2175def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst), 2176 "cmpxchg8b\t$dst", []>, TB; 2177 2178let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in 2179def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst), 2180 "cmpxchg16b\t$dst", []>, 2181 TB, Requires<[HasCmpxchg16b, In64BitMode]>; 2182} // SchedRW, mayLoad, mayStore, hasSideEffects 2183 2184 2185// Lock instruction prefix 2186let SchedRW = [WriteMicrocoded] in 2187def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>; 2188 2189let SchedRW = [WriteNop] in { 2190 2191// Rex64 instruction prefix 2192def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>, 2193 Requires<[In64BitMode]>; 2194 2195// Data16 instruction prefix 2196def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>; 2197} // SchedRW 2198 2199// Repeat string operation instruction prefixes 2200let Defs = [ECX], Uses = [ECX,DF], SchedRW = [WriteMicrocoded] in { 2201// Repeat (used with INS, OUTS, MOVS, LODS and STOS) 2202def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>; 2203// Repeat while not equal (used with CMPS and SCAS) 2204def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>; 2205} 2206 2207// String manipulation instructions 2208let SchedRW = [WriteMicrocoded] in { 2209let Defs = [AL,ESI], Uses = [ESI,DF] in 2210def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src), 2211 "lodsb\t{$src, %al|al, $src}", []>; 2212let Defs = [AX,ESI], Uses = [ESI,DF] in 2213def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src), 2214 "lodsw\t{$src, %ax|ax, $src}", []>, OpSize16; 2215let Defs = [EAX,ESI], Uses = [ESI,DF] in 2216def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src), 2217 "lods{l|d}\t{$src, %eax|eax, $src}", []>, OpSize32; 2218let Defs = [RAX,ESI], Uses = [ESI,DF] in 2219def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src), 2220 "lodsq\t{$src, %rax|rax, $src}", []>, 2221 Requires<[In64BitMode]>; 2222} 2223 2224let SchedRW = [WriteSystem] in { 2225let Defs = [ESI], Uses = [DX,ESI,DF] in { 2226def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src), 2227 "outsb\t{$src, %dx|dx, $src}", []>; 2228def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src), 2229 "outsw\t{$src, %dx|dx, $src}", []>, OpSize16; 2230def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src), 2231 "outs{l|d}\t{$src, %dx|dx, $src}", []>, OpSize32; 2232} 2233 2234let Defs = [EDI], Uses = [DX,EDI,DF] in { 2235def INSB : I<0x6C, RawFrmDst, (outs), (ins dstidx8:$dst), 2236 "insb\t{%dx, $dst|$dst, dx}", []>; 2237def INSW : I<0x6D, RawFrmDst, (outs), (ins dstidx16:$dst), 2238 "insw\t{%dx, $dst|$dst, dx}", []>, OpSize16; 2239def INSL : I<0x6D, RawFrmDst, (outs), (ins dstidx32:$dst), 2240 "ins{l|d}\t{%dx, $dst|$dst, dx}", []>, OpSize32; 2241} 2242} 2243 2244// EFLAGS management instructions. 2245let SchedRW = [WriteALU], Defs = [EFLAGS], Uses = [EFLAGS] in { 2246def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>; 2247def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>; 2248def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>; 2249} 2250 2251// DF management instructions. 2252let SchedRW = [WriteALU], Defs = [DF] in { 2253def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>; 2254def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>; 2255} 2256 2257// Table lookup instructions 2258let Uses = [AL,EBX], Defs = [AL], hasSideEffects = 0, mayLoad = 1 in 2259def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>, Sched<[WriteLoad]>; 2260 2261let SchedRW = [WriteMicrocoded] in { 2262// ASCII Adjust After Addition 2263let Uses = [AL,EFLAGS], Defs = [AX,EFLAGS], hasSideEffects = 0 in 2264def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", []>, 2265 Requires<[Not64BitMode]>; 2266 2267// ASCII Adjust AX Before Division 2268let Uses = [AX], Defs = [AX,EFLAGS], hasSideEffects = 0 in 2269def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src), 2270 "aad\t$src", []>, Requires<[Not64BitMode]>; 2271 2272// ASCII Adjust AX After Multiply 2273let Uses = [AL], Defs = [AX,EFLAGS], hasSideEffects = 0 in 2274def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src), 2275 "aam\t$src", []>, Requires<[Not64BitMode]>; 2276 2277// ASCII Adjust AL After Subtraction - sets 2278let Uses = [AL,EFLAGS], Defs = [AX,EFLAGS], hasSideEffects = 0 in 2279def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", []>, 2280 Requires<[Not64BitMode]>; 2281 2282// Decimal Adjust AL after Addition 2283let Uses = [AL,EFLAGS], Defs = [AL,EFLAGS], hasSideEffects = 0 in 2284def DAA : I<0x27, RawFrm, (outs), (ins), "daa", []>, 2285 Requires<[Not64BitMode]>; 2286 2287// Decimal Adjust AL after Subtraction 2288let Uses = [AL,EFLAGS], Defs = [AL,EFLAGS], hasSideEffects = 0 in 2289def DAS : I<0x2F, RawFrm, (outs), (ins), "das", []>, 2290 Requires<[Not64BitMode]>; 2291} // SchedRW 2292 2293let SchedRW = [WriteSystem] in { 2294// Check Array Index Against Bounds 2295// Note: "bound" does not have reversed operands in at&t syntax. 2296def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i32mem:$src), 2297 "bound\t$dst, $src", []>, OpSize16, 2298 Requires<[Not64BitMode]>; 2299def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i64mem:$src), 2300 "bound\t$dst, $src", []>, OpSize32, 2301 Requires<[Not64BitMode]>; 2302 2303// Adjust RPL Field of Segment Selector 2304def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 2305 "arpl\t{$src, $dst|$dst, $src}", []>, 2306 Requires<[Not64BitMode]>, NotMemoryFoldable; 2307let mayStore = 1 in 2308def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 2309 "arpl\t{$src, $dst|$dst, $src}", []>, 2310 Requires<[Not64BitMode]>, NotMemoryFoldable; 2311} // SchedRW 2312 2313//===----------------------------------------------------------------------===// 2314// MOVBE Instructions 2315// 2316let Predicates = [HasMOVBE] in { 2317 let SchedRW = [WriteALULd] in { 2318 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 2319 "movbe{w}\t{$src, $dst|$dst, $src}", 2320 [(set GR16:$dst, (bswap (loadi16 addr:$src)))]>, 2321 OpSize16, T8PS; 2322 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 2323 "movbe{l}\t{$src, $dst|$dst, $src}", 2324 [(set GR32:$dst, (bswap (loadi32 addr:$src)))]>, 2325 OpSize32, T8PS; 2326 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 2327 "movbe{q}\t{$src, $dst|$dst, $src}", 2328 [(set GR64:$dst, (bswap (loadi64 addr:$src)))]>, 2329 T8PS; 2330 } 2331 let SchedRW = [WriteStore] in { 2332 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 2333 "movbe{w}\t{$src, $dst|$dst, $src}", 2334 [(store (bswap GR16:$src), addr:$dst)]>, 2335 OpSize16, T8PS; 2336 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 2337 "movbe{l}\t{$src, $dst|$dst, $src}", 2338 [(store (bswap GR32:$src), addr:$dst)]>, 2339 OpSize32, T8PS; 2340 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 2341 "movbe{q}\t{$src, $dst|$dst, $src}", 2342 [(store (bswap GR64:$src), addr:$dst)]>, 2343 T8PS; 2344 } 2345} 2346 2347//===----------------------------------------------------------------------===// 2348// RDRAND Instruction 2349// 2350let Predicates = [HasRDRAND], Defs = [EFLAGS], SchedRW = [WriteSystem] in { 2351 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins), 2352 "rdrand{w}\t$dst", [(set GR16:$dst, EFLAGS, (X86rdrand))]>, 2353 OpSize16, PS; 2354 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins), 2355 "rdrand{l}\t$dst", [(set GR32:$dst, EFLAGS, (X86rdrand))]>, 2356 OpSize32, PS; 2357 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins), 2358 "rdrand{q}\t$dst", [(set GR64:$dst, EFLAGS, (X86rdrand))]>, 2359 PS; 2360} 2361 2362//===----------------------------------------------------------------------===// 2363// RDSEED Instruction 2364// 2365let Predicates = [HasRDSEED], Defs = [EFLAGS], SchedRW = [WriteSystem] in { 2366 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins), "rdseed{w}\t$dst", 2367 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, PS; 2368 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins), "rdseed{l}\t$dst", 2369 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, PS; 2370 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdseed{q}\t$dst", 2371 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, PS; 2372} 2373 2374//===----------------------------------------------------------------------===// 2375// LZCNT Instruction 2376// 2377let Predicates = [HasLZCNT], Defs = [EFLAGS] in { 2378 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 2379 "lzcnt{w}\t{$src, $dst|$dst, $src}", 2380 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, 2381 XS, OpSize16, Sched<[WriteLZCNT]>; 2382 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 2383 "lzcnt{w}\t{$src, $dst|$dst, $src}", 2384 [(set GR16:$dst, (ctlz (loadi16 addr:$src))), 2385 (implicit EFLAGS)]>, XS, OpSize16, Sched<[WriteLZCNTLd]>; 2386 2387 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 2388 "lzcnt{l}\t{$src, $dst|$dst, $src}", 2389 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, 2390 XS, OpSize32, Sched<[WriteLZCNT]>; 2391 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 2392 "lzcnt{l}\t{$src, $dst|$dst, $src}", 2393 [(set GR32:$dst, (ctlz (loadi32 addr:$src))), 2394 (implicit EFLAGS)]>, XS, OpSize32, Sched<[WriteLZCNTLd]>; 2395 2396 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 2397 "lzcnt{q}\t{$src, $dst|$dst, $src}", 2398 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>, 2399 XS, Sched<[WriteLZCNT]>; 2400 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 2401 "lzcnt{q}\t{$src, $dst|$dst, $src}", 2402 [(set GR64:$dst, (ctlz (loadi64 addr:$src))), 2403 (implicit EFLAGS)]>, XS, Sched<[WriteLZCNTLd]>; 2404} 2405 2406//===----------------------------------------------------------------------===// 2407// BMI Instructions 2408// 2409let Predicates = [HasBMI], Defs = [EFLAGS] in { 2410 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 2411 "tzcnt{w}\t{$src, $dst|$dst, $src}", 2412 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, 2413 XS, OpSize16, Sched<[WriteTZCNT]>; 2414 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 2415 "tzcnt{w}\t{$src, $dst|$dst, $src}", 2416 [(set GR16:$dst, (cttz (loadi16 addr:$src))), 2417 (implicit EFLAGS)]>, XS, OpSize16, Sched<[WriteTZCNTLd]>; 2418 2419 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 2420 "tzcnt{l}\t{$src, $dst|$dst, $src}", 2421 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, 2422 XS, OpSize32, Sched<[WriteTZCNT]>; 2423 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 2424 "tzcnt{l}\t{$src, $dst|$dst, $src}", 2425 [(set GR32:$dst, (cttz (loadi32 addr:$src))), 2426 (implicit EFLAGS)]>, XS, OpSize32, Sched<[WriteTZCNTLd]>; 2427 2428 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 2429 "tzcnt{q}\t{$src, $dst|$dst, $src}", 2430 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>, 2431 XS, Sched<[WriteTZCNT]>; 2432 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 2433 "tzcnt{q}\t{$src, $dst|$dst, $src}", 2434 [(set GR64:$dst, (cttz (loadi64 addr:$src))), 2435 (implicit EFLAGS)]>, XS, Sched<[WriteTZCNTLd]>; 2436} 2437 2438multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM, 2439 RegisterClass RC, X86MemOperand x86memop> { 2440let hasSideEffects = 0 in { 2441 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src), 2442 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>, 2443 T8PS, VEX_4V, Sched<[WriteALU]>; 2444 let mayLoad = 1 in 2445 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src), 2446 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>, 2447 T8PS, VEX_4V, Sched<[WriteALULd]>; 2448} 2449} 2450 2451let Predicates = [HasBMI], Defs = [EFLAGS] in { 2452 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>; 2453 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W; 2454 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>; 2455 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W; 2456 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>; 2457 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W; 2458} 2459 2460//===----------------------------------------------------------------------===// 2461// Pattern fragments to auto generate BMI instructions. 2462//===----------------------------------------------------------------------===// 2463 2464let Predicates = [HasBMI] in { 2465 // FIXME: patterns for the load versions are not implemented 2466 def : Pat<(and GR32:$src, (add GR32:$src, -1)), 2467 (BLSR32rr GR32:$src)>; 2468 def : Pat<(and GR64:$src, (add GR64:$src, -1)), 2469 (BLSR64rr GR64:$src)>; 2470 2471 def : Pat<(xor GR32:$src, (add GR32:$src, -1)), 2472 (BLSMSK32rr GR32:$src)>; 2473 def : Pat<(xor GR64:$src, (add GR64:$src, -1)), 2474 (BLSMSK64rr GR64:$src)>; 2475 2476 def : Pat<(and GR32:$src, (ineg GR32:$src)), 2477 (BLSI32rr GR32:$src)>; 2478 def : Pat<(and GR64:$src, (ineg GR64:$src)), 2479 (BLSI64rr GR64:$src)>; 2480} 2481 2482multiclass bmi_bextr<bits<8> opc, string mnemonic, RegisterClass RC, 2483 X86MemOperand x86memop, SDNode OpNode, 2484 PatFrag ld_frag, X86FoldableSchedWrite Sched> { 2485 def rr : I<opc, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2), 2486 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2487 [(set RC:$dst, (OpNode RC:$src1, RC:$src2)), (implicit EFLAGS)]>, 2488 T8PS, VEX, Sched<[Sched]>; 2489 def rm : I<opc, MRMSrcMem4VOp3, (outs RC:$dst), (ins x86memop:$src1, RC:$src2), 2490 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2491 [(set RC:$dst, (OpNode (ld_frag addr:$src1), RC:$src2)), 2492 (implicit EFLAGS)]>, T8PS, VEX, 2493 Sched<[Sched.Folded, 2494 // x86memop:$src1 2495 ReadDefault, ReadDefault, ReadDefault, ReadDefault, 2496 ReadDefault, 2497 // RC:$src2 2498 ReadAfterLd]>; 2499} 2500 2501let Predicates = [HasBMI], Defs = [EFLAGS] in { 2502 defm BEXTR32 : bmi_bextr<0xF7, "bextr{l}", GR32, i32mem, 2503 X86bextr, loadi32, WriteBEXTR>; 2504 defm BEXTR64 : bmi_bextr<0xF7, "bextr{q}", GR64, i64mem, 2505 X86bextr, loadi64, WriteBEXTR>, VEX_W; 2506} 2507 2508multiclass bmi_bzhi<bits<8> opc, string mnemonic, RegisterClass RC, 2509 X86MemOperand x86memop, Intrinsic Int, 2510 PatFrag ld_frag, X86FoldableSchedWrite Sched> { 2511 def rr : I<opc, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2), 2512 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2513 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>, 2514 T8PS, VEX, Sched<[Sched]>; 2515 def rm : I<opc, MRMSrcMem4VOp3, (outs RC:$dst), (ins x86memop:$src1, RC:$src2), 2516 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2517 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)), 2518 (implicit EFLAGS)]>, T8PS, VEX, 2519 Sched<[Sched.Folded, 2520 // x86memop:$src1 2521 ReadDefault, ReadDefault, ReadDefault, ReadDefault, 2522 ReadDefault, 2523 // RC:$src2 2524 ReadAfterLd]>; 2525} 2526 2527let Predicates = [HasBMI2], Defs = [EFLAGS] in { 2528 defm BZHI32 : bmi_bzhi<0xF5, "bzhi{l}", GR32, i32mem, 2529 int_x86_bmi_bzhi_32, loadi32, WriteBZHI>; 2530 defm BZHI64 : bmi_bzhi<0xF5, "bzhi{q}", GR64, i64mem, 2531 int_x86_bmi_bzhi_64, loadi64, WriteBZHI>, VEX_W; 2532} 2533 2534def CountTrailingOnes : SDNodeXForm<imm, [{ 2535 // Count the trailing ones in the immediate. 2536 return getI8Imm(countTrailingOnes(N->getZExtValue()), SDLoc(N)); 2537}]>; 2538 2539def BEXTRMaskXForm : SDNodeXForm<imm, [{ 2540 unsigned Length = countTrailingOnes(N->getZExtValue()); 2541 return getI32Imm(Length << 8, SDLoc(N)); 2542}]>; 2543 2544def AndMask64 : ImmLeaf<i64, [{ 2545 return isMask_64(Imm) && !isUInt<32>(Imm); 2546}]>; 2547 2548// Use BEXTR for 64-bit 'and' with large immediate 'mask'. 2549let Predicates = [HasBMI, NoBMI2, NoTBM] in { 2550 def : Pat<(and GR64:$src, AndMask64:$mask), 2551 (BEXTR64rr GR64:$src, 2552 (SUBREG_TO_REG (i64 0), 2553 (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; 2554 def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), 2555 (BEXTR64rm addr:$src, 2556 (SUBREG_TO_REG (i64 0), 2557 (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; 2558} 2559 2560// Use BZHI for 64-bit 'and' with large immediate 'mask'. 2561let Predicates = [HasBMI2, NoTBM] in { 2562 def : Pat<(and GR64:$src, AndMask64:$mask), 2563 (BZHI64rr GR64:$src, 2564 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 2565 (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>; 2566 def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), 2567 (BZHI64rm addr:$src, 2568 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 2569 (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>; 2570} 2571 2572let Predicates = [HasBMI2] in { 2573 multiclass _bmi_bzhi_pattern<dag regpattern, dag mempattern, RegisterClass RC, 2574 ValueType VT, Instruction DstInst, 2575 Instruction DstMemInst> { 2576 def : Pat<regpattern, 2577 (DstInst RC:$src, 2578 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; 2579 def : Pat<mempattern, 2580 (DstMemInst addr:$src, 2581 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; 2582 } 2583 2584 multiclass bmi_bzhi_patterns<RegisterClass RC, int bitwidth, ValueType VT, 2585 Instruction DstInst, X86MemOperand x86memop, 2586 Instruction DstMemInst> { 2587 // x & ((1 << y) - 1) 2588 defm : _bmi_bzhi_pattern<(and RC:$src, (add (shl 1, GR8:$lz), -1)), 2589 (and (x86memop addr:$src), 2590 (add (shl 1, GR8:$lz), -1)), 2591 RC, VT, DstInst, DstMemInst>; 2592 2593 // x & ~(-1 << y) 2594 defm : _bmi_bzhi_pattern<(and RC:$src, (xor (shl -1, GR8:$lz), -1)), 2595 (and (x86memop addr:$src), 2596 (xor (shl -1, GR8:$lz), -1)), 2597 RC, VT, DstInst, DstMemInst>; 2598 2599 // x & (-1 >> (bitwidth - y)) 2600 defm : _bmi_bzhi_pattern<(and RC:$src, (srl -1, (sub bitwidth, GR8:$lz))), 2601 (and (x86memop addr:$src), 2602 (srl -1, (sub bitwidth, GR8:$lz))), 2603 RC, VT, DstInst, DstMemInst>; 2604 2605 // x << (bitwidth - y) >> (bitwidth - y) 2606 defm : _bmi_bzhi_pattern<(srl (shl RC:$src, (sub bitwidth, GR8:$lz)), 2607 (sub bitwidth, GR8:$lz)), 2608 (srl (shl (x86memop addr:$src), 2609 (sub bitwidth, GR8:$lz)), 2610 (sub bitwidth, GR8:$lz)), 2611 RC, VT, DstInst, DstMemInst>; 2612 } 2613 2614 defm : bmi_bzhi_patterns<GR32, 32, i32, BZHI32rr, loadi32, BZHI32rm>; 2615 defm : bmi_bzhi_patterns<GR64, 64, i64, BZHI64rr, loadi64, BZHI64rm>; 2616 2617 // x & (-1 >> (32 - y)) 2618 def : Pat<(and GR32:$src, (srl -1, (i8 (trunc (sub 32, GR32:$lz))))), 2619 (BZHI32rr GR32:$src, GR32:$lz)>; 2620 def : Pat<(and (loadi32 addr:$src), (srl -1, (i8 (trunc (sub 32, GR32:$lz))))), 2621 (BZHI32rm addr:$src, GR32:$lz)>; 2622 2623 // x & (-1 >> (64 - y)) 2624 def : Pat<(and GR64:$src, (srl -1, (i8 (trunc (sub 64, GR32:$lz))))), 2625 (BZHI64rr GR64:$src, 2626 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>; 2627 def : Pat<(and (loadi64 addr:$src), (srl -1, (i8 (trunc (sub 64, GR32:$lz))))), 2628 (BZHI64rm addr:$src, 2629 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>; 2630 2631 // x << (32 - y) >> (32 - y) 2632 def : Pat<(srl (shl GR32:$src, (i8 (trunc (sub 32, GR32:$lz)))), 2633 (i8 (trunc (sub 32, GR32:$lz)))), 2634 (BZHI32rr GR32:$src, GR32:$lz)>; 2635 def : Pat<(srl (shl (loadi32 addr:$src), (i8 (trunc (sub 32, GR32:$lz)))), 2636 (i8 (trunc (sub 32, GR32:$lz)))), 2637 (BZHI32rm addr:$src, GR32:$lz)>; 2638 2639 // x << (64 - y) >> (64 - y) 2640 def : Pat<(srl (shl GR64:$src, (i8 (trunc (sub 64, GR32:$lz)))), 2641 (i8 (trunc (sub 64, GR32:$lz)))), 2642 (BZHI64rr GR64:$src, 2643 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>; 2644 def : Pat<(srl (shl (loadi64 addr:$src), (i8 (trunc (sub 64, GR32:$lz)))), 2645 (i8 (trunc (sub 64, GR32:$lz)))), 2646 (BZHI64rm addr:$src, 2647 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>; 2648} // HasBMI2 2649 2650multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC, 2651 X86MemOperand x86memop, Intrinsic Int, 2652 PatFrag ld_frag> { 2653 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), 2654 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2655 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>, 2656 VEX_4V, Sched<[WriteALU]>; 2657 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), 2658 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2659 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, 2660 VEX_4V, Sched<[WriteALULd, ReadAfterLd]>; 2661} 2662 2663let Predicates = [HasBMI2] in { 2664 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem, 2665 int_x86_bmi_pdep_32, loadi32>, T8XD; 2666 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem, 2667 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W; 2668 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem, 2669 int_x86_bmi_pext_32, loadi32>, T8XS; 2670 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem, 2671 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W; 2672} 2673 2674//===----------------------------------------------------------------------===// 2675// TBM Instructions 2676// 2677let Predicates = [HasTBM], Defs = [EFLAGS] in { 2678 2679multiclass tbm_ternary_imm<bits<8> opc, RegisterClass RC, string OpcodeStr, 2680 X86MemOperand x86memop, PatFrag ld_frag, 2681 SDNode OpNode, Operand immtype, 2682 SDPatternOperator immoperator, 2683 X86FoldableSchedWrite Sched> { 2684 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl), 2685 !strconcat(OpcodeStr, 2686 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"), 2687 [(set RC:$dst, (OpNode RC:$src1, immoperator:$cntl))]>, 2688 XOP, XOPA, Sched<[Sched]>; 2689 def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst), 2690 (ins x86memop:$src1, immtype:$cntl), 2691 !strconcat(OpcodeStr, 2692 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"), 2693 [(set RC:$dst, (OpNode (ld_frag addr:$src1), immoperator:$cntl))]>, 2694 XOP, XOPA, Sched<[Sched.Folded]>; 2695} 2696 2697defm BEXTRI32 : tbm_ternary_imm<0x10, GR32, "bextr{l}", i32mem, loadi32, 2698 X86bextr, i32imm, imm, WriteBEXTR>; 2699let ImmT = Imm32S in 2700defm BEXTRI64 : tbm_ternary_imm<0x10, GR64, "bextr{q}", i64mem, loadi64, 2701 X86bextr, i64i32imm, 2702 i64immSExt32, WriteBEXTR>, VEX_W; 2703 2704multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem, 2705 RegisterClass RC, string OpcodeStr, 2706 X86MemOperand x86memop, X86FoldableSchedWrite Sched> { 2707let hasSideEffects = 0 in { 2708 def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src), 2709 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"), []>, 2710 XOP_4V, XOP9, Sched<[Sched]>; 2711 let mayLoad = 1 in 2712 def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src), 2713 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"), []>, 2714 XOP_4V, XOP9, Sched<[Sched.Folded]>; 2715} 2716} 2717 2718multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr, 2719 X86FoldableSchedWrite Sched, 2720 Format FormReg, Format FormMem> { 2721 defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr#"{l}", 2722 i32mem, Sched>; 2723 defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr#"{q}", 2724 i64mem, Sched>, VEX_W; 2725} 2726 2727defm BLCFILL : tbm_binary_intr<0x01, "blcfill", WriteALU, MRM1r, MRM1m>; 2728defm BLCI : tbm_binary_intr<0x02, "blci", WriteALU, MRM6r, MRM6m>; 2729defm BLCIC : tbm_binary_intr<0x01, "blcic", WriteALU, MRM5r, MRM5m>; 2730defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", WriteALU, MRM1r, MRM1m>; 2731defm BLCS : tbm_binary_intr<0x01, "blcs", WriteALU, MRM3r, MRM3m>; 2732defm BLSFILL : tbm_binary_intr<0x01, "blsfill", WriteALU, MRM2r, MRM2m>; 2733defm BLSIC : tbm_binary_intr<0x01, "blsic", WriteALU, MRM6r, MRM6m>; 2734defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", WriteALU, MRM7r, MRM7m>; 2735defm TZMSK : tbm_binary_intr<0x01, "tzmsk", WriteALU, MRM4r, MRM4m>; 2736} // HasTBM, EFLAGS 2737 2738// Use BEXTRI for 64-bit 'and' with large immediate 'mask'. 2739let Predicates = [HasTBM] in { 2740 def : Pat<(and GR64:$src, AndMask64:$mask), 2741 (BEXTRI64ri GR64:$src, (BEXTRMaskXForm imm:$mask))>; 2742 2743 def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), 2744 (BEXTRI64mi addr:$src, (BEXTRMaskXForm imm:$mask))>; 2745} 2746 2747//===----------------------------------------------------------------------===// 2748// Lightweight Profiling Instructions 2749 2750let Predicates = [HasLWP], SchedRW = [WriteSystem] in { 2751 2752def LLWPCB : I<0x12, MRM0r, (outs), (ins GR32:$src), "llwpcb\t$src", 2753 [(int_x86_llwpcb GR32:$src)]>, XOP, XOP9; 2754def SLWPCB : I<0x12, MRM1r, (outs GR32:$dst), (ins), "slwpcb\t$dst", 2755 [(set GR32:$dst, (int_x86_slwpcb))]>, XOP, XOP9; 2756 2757def LLWPCB64 : I<0x12, MRM0r, (outs), (ins GR64:$src), "llwpcb\t$src", 2758 [(int_x86_llwpcb GR64:$src)]>, XOP, XOP9, VEX_W; 2759def SLWPCB64 : I<0x12, MRM1r, (outs GR64:$dst), (ins), "slwpcb\t$dst", 2760 [(set GR64:$dst, (int_x86_slwpcb))]>, XOP, XOP9, VEX_W; 2761 2762multiclass lwpins_intr<RegisterClass RC> { 2763 def rri : Ii32<0x12, MRM0r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl), 2764 "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", 2765 [(set EFLAGS, (X86lwpins RC:$src0, GR32:$src1, imm:$cntl))]>, 2766 XOP_4V, XOPA; 2767 let mayLoad = 1 in 2768 def rmi : Ii32<0x12, MRM0m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl), 2769 "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", 2770 [(set EFLAGS, (X86lwpins RC:$src0, (loadi32 addr:$src1), imm:$cntl))]>, 2771 XOP_4V, XOPA; 2772} 2773 2774let Defs = [EFLAGS] in { 2775 defm LWPINS32 : lwpins_intr<GR32>; 2776 defm LWPINS64 : lwpins_intr<GR64>, VEX_W; 2777} // EFLAGS 2778 2779multiclass lwpval_intr<RegisterClass RC, Intrinsic Int> { 2780 def rri : Ii32<0x12, MRM1r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl), 2781 "lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", 2782 [(Int RC:$src0, GR32:$src1, imm:$cntl)]>, XOP_4V, XOPA; 2783 let mayLoad = 1 in 2784 def rmi : Ii32<0x12, MRM1m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl), 2785 "lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", 2786 [(Int RC:$src0, (loadi32 addr:$src1), imm:$cntl)]>, 2787 XOP_4V, XOPA; 2788} 2789 2790defm LWPVAL32 : lwpval_intr<GR32, int_x86_lwpval32>; 2791defm LWPVAL64 : lwpval_intr<GR64, int_x86_lwpval64>, VEX_W; 2792 2793} // HasLWP, SchedRW 2794 2795//===----------------------------------------------------------------------===// 2796// MONITORX/MWAITX Instructions 2797// 2798let SchedRW = [ WriteSystem ] in { 2799/* 2800 let usesCustomInserter = 1 in { 2801 def MONITORX : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3), 2802 [(int_x86_monitorx addr:$src1, GR32:$src2, GR32:$src3)]>, 2803 Requires<[ HasMWAITX ]>; 2804 } 2805*/ 2806 2807 let Uses = [ EAX, ECX, EDX ] in { 2808 def MONITORXrrr : I<0x01, MRM_FA, (outs), (ins), "monitorx", []>, 2809 TB, Requires<[ HasMWAITX ]>; 2810 } 2811 2812 let Uses = [ ECX, EAX, EBX ] in { 2813 def MWAITXrrr : I<0x01, MRM_FB, (outs), (ins), "mwaitx", 2814 [(int_x86_mwaitx ECX, EAX, EBX)]>, 2815 TB, Requires<[ HasMWAITX ]>; 2816 } 2817} // SchedRW 2818 2819// def : InstAlias<"mwaitx\t{%eax, %ecx, %ebx|ebx, ecx, eax}", (MWAITXrrr)>, 2820// Requires<[ Not64BitMode ]>; 2821// def : InstAlias<"mwaitx\t{%rax, %rcx, %rbx|rbx, rcx, rax}", (MWAITXrrr)>, 2822// Requires<[ In64BitMode ]>; 2823 2824// def : InstAlias<"monitorx\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORXrrr)>, 2825// Requires<[ Not64BitMode ]>; 2826// def : InstAlias<"monitorx\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORXrrr)>, 2827// Requires<[ In64BitMode ]>; 2828 2829//===----------------------------------------------------------------------===// 2830// WAITPKG Instructions 2831// 2832let SchedRW = [WriteSystem] in { 2833 def UMONITOR16 : I<0xAE, MRM6r, (outs), (ins GR16:$src), 2834 "umonitor\t$src", [(int_x86_umonitor GR16:$src)]>, 2835 XS, AdSize16, Requires<[HasWAITPKG, Not64BitMode]>; 2836 def UMONITOR32 : I<0xAE, MRM6r, (outs), (ins GR32:$src), 2837 "umonitor\t$src", [(int_x86_umonitor GR32:$src)]>, 2838 XS, AdSize32, Requires<[HasWAITPKG]>; 2839 def UMONITOR64 : I<0xAE, MRM6r, (outs), (ins GR64:$src), 2840 "umonitor\t$src", [(int_x86_umonitor GR64:$src)]>, 2841 XS, AdSize64, Requires<[HasWAITPKG, In64BitMode]>; 2842 let Uses = [EAX, EDX], Defs = [EFLAGS] in { 2843 def UMWAIT : I<0xAE, MRM6r, 2844 (outs), (ins GR32orGR64:$src), "umwait\t$src", 2845 [(set EFLAGS, (X86umwait GR32orGR64:$src, EDX, EAX))]>, 2846 XD, Requires<[HasWAITPKG]>; 2847 def TPAUSE : I<0xAE, MRM6r, 2848 (outs), (ins GR32orGR64:$src), "tpause\t$src", 2849 [(set EFLAGS, (X86tpause GR32orGR64:$src, EDX, EAX))]>, 2850 PD, Requires<[HasWAITPKG]>, NotMemoryFoldable; 2851 } 2852} // SchedRW 2853 2854//===----------------------------------------------------------------------===// 2855// MOVDIRI - Move doubleword/quadword as direct store 2856// 2857let SchedRW = [WriteStore] in { 2858def MOVDIRI32 : I<0xF9, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 2859 "movdiri\t{$src, $dst|$dst, $src}", 2860 [(int_x86_directstore32 addr:$dst, GR32:$src)]>, 2861 T8, Requires<[HasMOVDIRI]>; 2862def MOVDIRI64 : RI<0xF9, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 2863 "movdiri\t{$src, $dst|$dst, $src}", 2864 [(int_x86_directstore64 addr:$dst, GR64:$src)]>, 2865 T8, Requires<[In64BitMode, HasMOVDIRI]>; 2866} // SchedRW 2867 2868//===----------------------------------------------------------------------===// 2869// MOVDIR64B - Move 64 bytes as direct store 2870// 2871let SchedRW = [WriteStore] in { 2872def MOVDIR64B16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem:$src), 2873 "movdir64b\t{$src, $dst|$dst, $src}", []>, 2874 T8PD, AdSize16, Requires<[HasMOVDIR64B, Not64BitMode]>; 2875def MOVDIR64B32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem:$src), 2876 "movdir64b\t{$src, $dst|$dst, $src}", 2877 [(int_x86_movdir64b GR32:$dst, addr:$src)]>, 2878 T8PD, AdSize32, Requires<[HasMOVDIR64B]>; 2879def MOVDIR64B64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem:$src), 2880 "movdir64b\t{$src, $dst|$dst, $src}", 2881 [(int_x86_movdir64b GR64:$dst, addr:$src)]>, 2882 T8PD, AdSize64, Requires<[HasMOVDIR64B, In64BitMode]>; 2883} // SchedRW 2884 2885//===----------------------------------------------------------------------===// 2886// CLZERO Instruction 2887// 2888let SchedRW = [WriteSystem] in { 2889 let Uses = [EAX] in 2890 def CLZEROr : I<0x01, MRM_FC, (outs), (ins), "clzero", []>, 2891 TB, Requires<[HasCLZERO]>; 2892 2893/* 2894 let usesCustomInserter = 1 in { 2895 def CLZERO : PseudoI<(outs), (ins i32mem:$src1), 2896 [(int_x86_clzero addr:$src1)]>, Requires<[HasCLZERO]>; 2897 } 2898*/ 2899} // SchedRW 2900 2901// def : InstAlias<"clzero\t{%eax|eax}", (CLZEROr)>, Requires<[Not64BitMode]>; 2902// def : InstAlias<"clzero\t{%rax|rax}", (CLZEROr)>, Requires<[In64BitMode]>; 2903 2904//===----------------------------------------------------------------------===// 2905// Pattern fragments to auto generate TBM instructions. 2906//===----------------------------------------------------------------------===// 2907 2908let Predicates = [HasTBM] in { 2909 // FIXME: patterns for the load versions are not implemented 2910 def : Pat<(and GR32:$src, (add GR32:$src, 1)), 2911 (BLCFILL32rr GR32:$src)>; 2912 def : Pat<(and GR64:$src, (add GR64:$src, 1)), 2913 (BLCFILL64rr GR64:$src)>; 2914 2915 def : Pat<(or GR32:$src, (not (add GR32:$src, 1))), 2916 (BLCI32rr GR32:$src)>; 2917 def : Pat<(or GR64:$src, (not (add GR64:$src, 1))), 2918 (BLCI64rr GR64:$src)>; 2919 2920 // Extra patterns because opt can optimize the above patterns to this. 2921 def : Pat<(or GR32:$src, (sub -2, GR32:$src)), 2922 (BLCI32rr GR32:$src)>; 2923 def : Pat<(or GR64:$src, (sub -2, GR64:$src)), 2924 (BLCI64rr GR64:$src)>; 2925 2926 def : Pat<(and (not GR32:$src), (add GR32:$src, 1)), 2927 (BLCIC32rr GR32:$src)>; 2928 def : Pat<(and (not GR64:$src), (add GR64:$src, 1)), 2929 (BLCIC64rr GR64:$src)>; 2930 2931 def : Pat<(xor GR32:$src, (add GR32:$src, 1)), 2932 (BLCMSK32rr GR32:$src)>; 2933 def : Pat<(xor GR64:$src, (add GR64:$src, 1)), 2934 (BLCMSK64rr GR64:$src)>; 2935 2936 def : Pat<(or GR32:$src, (add GR32:$src, 1)), 2937 (BLCS32rr GR32:$src)>; 2938 def : Pat<(or GR64:$src, (add GR64:$src, 1)), 2939 (BLCS64rr GR64:$src)>; 2940 2941 def : Pat<(or GR32:$src, (add GR32:$src, -1)), 2942 (BLSFILL32rr GR32:$src)>; 2943 def : Pat<(or GR64:$src, (add GR64:$src, -1)), 2944 (BLSFILL64rr GR64:$src)>; 2945 2946 def : Pat<(or (not GR32:$src), (add GR32:$src, -1)), 2947 (BLSIC32rr GR32:$src)>; 2948 def : Pat<(or (not GR64:$src), (add GR64:$src, -1)), 2949 (BLSIC64rr GR64:$src)>; 2950 2951 def : Pat<(or (not GR32:$src), (add GR32:$src, 1)), 2952 (T1MSKC32rr GR32:$src)>; 2953 def : Pat<(or (not GR64:$src), (add GR64:$src, 1)), 2954 (T1MSKC64rr GR64:$src)>; 2955 2956 def : Pat<(and (not GR32:$src), (add GR32:$src, -1)), 2957 (TZMSK32rr GR32:$src)>; 2958 def : Pat<(and (not GR64:$src), (add GR64:$src, -1)), 2959 (TZMSK64rr GR64:$src)>; 2960} // HasTBM 2961 2962//===----------------------------------------------------------------------===// 2963// Memory Instructions 2964// 2965 2966let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in 2967def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src), 2968 "clflushopt\t$src", [(int_x86_clflushopt addr:$src)]>, PD; 2969 2970let Predicates = [HasCLWB], SchedRW = [WriteLoad] in 2971def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src", 2972 [(int_x86_clwb addr:$src)]>, PD, NotMemoryFoldable; 2973 2974let Predicates = [HasCLDEMOTE], SchedRW = [WriteLoad] in 2975def CLDEMOTE : I<0x1C, MRM0m, (outs), (ins i8mem:$src), "cldemote\t$src", 2976 [(int_x86_cldemote addr:$src)]>, TB; 2977 2978//===----------------------------------------------------------------------===// 2979// Subsystems. 2980//===----------------------------------------------------------------------===// 2981 2982include "X86Capstone.td" 2983 2984include "X86InstrArithmetic.td" 2985include "X86InstrCMovSetCC.td" 2986include "X86InstrExtension.td" 2987include "X86InstrControl.td" 2988include "X86InstrShiftRotate.td" 2989 2990// X87 Floating Point Stack. 2991//include "X86InstrFPStack.td" 2992 2993// SIMD support (SSE, MMX and AVX) 2994//include "X86InstrFragmentsSIMD.td" 2995 2996// FMA - Fused Multiply-Add support (requires FMA) 2997//include "X86InstrFMA.td" 2998 2999// XOP 3000//include "X86InstrXOP.td" 3001 3002// SSE, MMX and 3DNow! vector support. 3003//include "X86InstrSSE.td" 3004//include "X86InstrAVX512.td" 3005//include "X86InstrMMX.td" 3006//include "X86Instr3DNow.td" 3007 3008// MPX instructions 3009//include "X86InstrMPX.td" 3010 3011include "X86InstrVMX.td" 3012include "X86InstrSVM.td" 3013 3014//include "X86InstrTSX.td" 3015//include "X86InstrSGX.td" 3016 3017// System instructions. 3018include "X86InstrSystem.td" 3019 3020// Compiler Pseudo Instructions and Pat Patterns 3021//include "X86InstrCompiler.td" 3022//include "X86InstrVecCompiler.td" 3023 3024//===----------------------------------------------------------------------===// 3025// Assembler Mnemonic Aliases 3026//===----------------------------------------------------------------------===// 3027 3028def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>; 3029def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>; 3030def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>; 3031 3032def : MnemonicAlias<"cbw", "cbtw", "att">; 3033def : MnemonicAlias<"cwde", "cwtl", "att">; 3034def : MnemonicAlias<"cwd", "cwtd", "att">; 3035def : MnemonicAlias<"cdq", "cltd", "att">; 3036def : MnemonicAlias<"cdqe", "cltq", "att">; 3037def : MnemonicAlias<"cqo", "cqto", "att">; 3038 3039// In 64-bit mode lret maps to lretl; it is not ambiguous with lretq. 3040def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>; 3041def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>; 3042 3043def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>; 3044def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>; 3045 3046def : MnemonicAlias<"loopz", "loope">; 3047def : MnemonicAlias<"loopnz", "loopne">; 3048 3049def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>; 3050def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>; 3051def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>; 3052def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>; 3053def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>; 3054def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>; 3055def : MnemonicAlias<"popf", "popfq", "intel">, Requires<[In64BitMode]>; 3056def : MnemonicAlias<"popfd", "popfl", "att">; 3057 3058// FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in 3059// all modes. However: "push (addr)" and "push $42" should default to 3060// pushl/pushq depending on the current mode. Similar for "pop %bx" 3061def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>; 3062def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>; 3063def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>; 3064def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>; 3065def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>; 3066def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>; 3067def : MnemonicAlias<"pushf", "pushfq", "intel">, Requires<[In64BitMode]>; 3068def : MnemonicAlias<"pushfd", "pushfl", "att">; 3069 3070def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>; 3071def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>; 3072def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>; 3073def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>; 3074def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>; 3075def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>; 3076 3077def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>; 3078def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>; 3079def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>; 3080def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>; 3081 3082def : MnemonicAlias<"repe", "rep">; 3083def : MnemonicAlias<"repz", "rep">; 3084def : MnemonicAlias<"repnz", "repne">; 3085 3086def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>; 3087def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>; 3088def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>; 3089 3090// Apply 'ret' behavior to 'retn' 3091def : MnemonicAlias<"retn", "retw", "att">, Requires<[In16BitMode]>; 3092def : MnemonicAlias<"retn", "retl", "att">, Requires<[In32BitMode]>; 3093def : MnemonicAlias<"retn", "retq", "att">, Requires<[In64BitMode]>; 3094def : MnemonicAlias<"retn", "ret", "intel">; 3095 3096def : MnemonicAlias<"sal", "shl", "intel">; 3097def : MnemonicAlias<"salb", "shlb", "att">; 3098def : MnemonicAlias<"salw", "shlw", "att">; 3099def : MnemonicAlias<"sall", "shll", "att">; 3100def : MnemonicAlias<"salq", "shlq", "att">; 3101 3102def : MnemonicAlias<"smovb", "movsb", "att">; 3103def : MnemonicAlias<"smovw", "movsw", "att">; 3104def : MnemonicAlias<"smovl", "movsl", "att">; 3105def : MnemonicAlias<"smovq", "movsq", "att">; 3106 3107def : MnemonicAlias<"ud2a", "ud2", "att">; 3108def : MnemonicAlias<"verrw", "verr", "att">; 3109 3110// MS recognizes 'xacquire'/'xrelease' as 'acquire'/'release' 3111def : MnemonicAlias<"acquire", "xacquire", "intel">; 3112def : MnemonicAlias<"release", "xrelease", "intel">; 3113 3114// System instruction aliases. 3115def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>; 3116def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>; 3117def : MnemonicAlias<"sysret", "sysretl", "att">; 3118def : MnemonicAlias<"sysexit", "sysexitl", "att">; 3119 3120def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>; 3121def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>; 3122def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>; 3123def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>; 3124def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>; 3125def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>; 3126def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>; 3127def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>; 3128def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>; 3129def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>; 3130def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>; 3131def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>; 3132//def : MnemonicAlias<"lgdt", "lgdtw", "intel">, Requires<[In16BitMode]>; 3133//def : MnemonicAlias<"lgdt", "lgdtd", "intel">, Requires<[In32BitMode]>; 3134//def : MnemonicAlias<"lidt", "lidtw", "intel">, Requires<[In16BitMode]>; 3135//def : MnemonicAlias<"lidt", "lidtd", "intel">, Requires<[In32BitMode]>; 3136//def : MnemonicAlias<"sgdt", "sgdtw", "intel">, Requires<[In16BitMode]>; 3137//def : MnemonicAlias<"sgdt", "sgdtd", "intel">, Requires<[In32BitMode]>; 3138//def : MnemonicAlias<"sidt", "sidtw", "intel">, Requires<[In16BitMode]>; 3139//def : MnemonicAlias<"sidt", "sidtd", "intel">, Requires<[In32BitMode]>; 3140 3141 3142// Floating point stack aliases. 3143def : MnemonicAlias<"fcmovz", "fcmove", "att">; 3144def : MnemonicAlias<"fcmova", "fcmovnbe", "att">; 3145def : MnemonicAlias<"fcmovnae", "fcmovb", "att">; 3146def : MnemonicAlias<"fcmovna", "fcmovbe", "att">; 3147def : MnemonicAlias<"fcmovae", "fcmovnb", "att">; 3148def : MnemonicAlias<"fcomip", "fcompi">; 3149def : MnemonicAlias<"fildq", "fildll", "att">; 3150def : MnemonicAlias<"fistpq", "fistpll", "att">; 3151def : MnemonicAlias<"fisttpq", "fisttpll", "att">; 3152def : MnemonicAlias<"fldcww", "fldcw", "att">; 3153def : MnemonicAlias<"fnstcww", "fnstcw", "att">; 3154def : MnemonicAlias<"fnstsww", "fnstsw", "att">; 3155def : MnemonicAlias<"fucomip", "fucompi">; 3156def : MnemonicAlias<"fwait", "wait">; 3157 3158def : MnemonicAlias<"fxsaveq", "fxsave64", "att">; 3159def : MnemonicAlias<"fxrstorq", "fxrstor64", "att">; 3160def : MnemonicAlias<"xsaveq", "xsave64", "att">; 3161def : MnemonicAlias<"xrstorq", "xrstor64", "att">; 3162def : MnemonicAlias<"xsaveoptq", "xsaveopt64", "att">; 3163def : MnemonicAlias<"xrstorsq", "xrstors64", "att">; 3164def : MnemonicAlias<"xsavecq", "xsavec64", "att">; 3165def : MnemonicAlias<"xsavesq", "xsaves64", "att">; 3166 3167class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond, 3168 string VariantName> 3169 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix), 3170 !strconcat(Prefix, NewCond, Suffix), VariantName>; 3171 3172/// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of 3173/// MnemonicAlias's that canonicalize the condition code in a mnemonic, for 3174/// example "setz" -> "sete". 3175multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix, 3176 string V = ""> { 3177 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb 3178 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete 3179 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe 3180 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae 3181 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae 3182 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle 3183 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge 3184 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne 3185 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp 3186 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp 3187 3188 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb 3189 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta 3190 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl 3191 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg 3192} 3193 3194// Aliases for set<CC> 3195defm : IntegerCondCodeMnemonicAlias<"set", "">; 3196// Aliases for j<CC> 3197defm : IntegerCondCodeMnemonicAlias<"j", "">; 3198// Aliases for cmov<CC>{w,l,q} 3199defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">; 3200defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">; 3201defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">; 3202// No size suffix for intel-style asm. 3203defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">; 3204 3205 3206//===----------------------------------------------------------------------===// 3207// Assembler Instruction Aliases 3208//===----------------------------------------------------------------------===// 3209 3210// aad/aam default to base 10 if no operand is specified. 3211// def : InstAlias<"aad", (AAD8i8 10)>, Requires<[Not64BitMode]>; 3212// def : InstAlias<"aam", (AAM8i8 10)>, Requires<[Not64BitMode]>; 3213 3214// Disambiguate the mem/imm form of bt-without-a-suffix as btl. 3215// Likewise for btc/btr/bts. 3216// def : InstAlias<"bt\t{$imm, $mem|$mem, $imm}", 3217// (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0, "att">; 3218// def : InstAlias<"btc\t{$imm, $mem|$mem, $imm}", 3219// (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0, "att">; 3220// def : InstAlias<"btr\t{$imm, $mem|$mem, $imm}", 3221// (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0, "att">; 3222// def : InstAlias<"bts\t{$imm, $mem|$mem, $imm}", 3223// (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0, "att">; 3224 3225// clr aliases. 3226// def : InstAlias<"clr{b}\t$reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>; 3227// def : InstAlias<"clr{w}\t$reg", (XOR16rr GR16:$reg, GR16:$reg), 0>; 3228// def : InstAlias<"clr{l}\t$reg", (XOR32rr GR32:$reg, GR32:$reg), 0>; 3229// def : InstAlias<"clr{q}\t$reg", (XOR64rr GR64:$reg, GR64:$reg), 0>; 3230 3231// lods aliases. Accept the destination being omitted because it's implicit 3232// in the mnemonic, or the mnemonic suffix being omitted because it's implicit 3233// in the destination. 3234// def : InstAlias<"lodsb\t$src", (LODSB srcidx8:$src), 0>; 3235// def : InstAlias<"lodsw\t$src", (LODSW srcidx16:$src), 0>; 3236// def : InstAlias<"lods{l|d}\t$src", (LODSL srcidx32:$src), 0>; 3237// def : InstAlias<"lodsq\t$src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; 3238// def : InstAlias<"lods\t{$src, %al|al, $src}", (LODSB srcidx8:$src), 0>; 3239// def : InstAlias<"lods\t{$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>; 3240// def : InstAlias<"lods\t{$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>; 3241// def : InstAlias<"lods\t{$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; 3242// def : InstAlias<"lods\t$src", (LODSB srcidx8:$src), 0, "intel">; 3243// def : InstAlias<"lods\t$src", (LODSW srcidx16:$src), 0, "intel">; 3244// def : InstAlias<"lods\t$src", (LODSL srcidx32:$src), 0, "intel">; 3245// def : InstAlias<"lods\t$src", (LODSQ srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>; 3246 3247 3248// stos aliases. Accept the source being omitted because it's implicit in 3249// the mnemonic, or the mnemonic suffix being omitted because it's implicit 3250// in the source. 3251// def : InstAlias<"stosb\t$dst", (STOSB dstidx8:$dst), 0>; 3252// def : InstAlias<"stosw\t$dst", (STOSW dstidx16:$dst), 0>; 3253// def : InstAlias<"stos{l|d}\t$dst", (STOSL dstidx32:$dst), 0>; 3254// def : InstAlias<"stosq\t$dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 3255// def : InstAlias<"stos\t{%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>; 3256// def : InstAlias<"stos\t{%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>; 3257// def : InstAlias<"stos\t{%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>; 3258// def : InstAlias<"stos\t{%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 3259// def : InstAlias<"stos\t$dst", (STOSB dstidx8:$dst), 0, "intel">; 3260// def : InstAlias<"stos\t$dst", (STOSW dstidx16:$dst), 0, "intel">; 3261// def : InstAlias<"stos\t$dst", (STOSL dstidx32:$dst), 0, "intel">; 3262// def : InstAlias<"stos\t$dst", (STOSQ dstidx64:$dst), 0, "intel">, Requires<[In64BitMode]>; 3263 3264 3265// scas aliases. Accept the destination being omitted because it's implicit 3266// in the mnemonic, or the mnemonic suffix being omitted because it's implicit 3267// in the destination. 3268// def : InstAlias<"scasb\t$dst", (SCASB dstidx8:$dst), 0>; 3269// def : InstAlias<"scasw\t$dst", (SCASW dstidx16:$dst), 0>; 3270// def : InstAlias<"scas{l|d}\t$dst", (SCASL dstidx32:$dst), 0>; 3271// def : InstAlias<"scasq\t$dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 3272// def : InstAlias<"scas\t{$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>; 3273// def : InstAlias<"scas\t{$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>; 3274// def : InstAlias<"scas\t{$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>; 3275// def : InstAlias<"scas\t{$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 3276// def : InstAlias<"scas\t$dst", (SCASB dstidx8:$dst), 0, "intel">; 3277// def : InstAlias<"scas\t$dst", (SCASW dstidx16:$dst), 0, "intel">; 3278// def : InstAlias<"scas\t$dst", (SCASL dstidx32:$dst), 0, "intel">; 3279// def : InstAlias<"scas\t$dst", (SCASQ dstidx64:$dst), 0, "intel">, Requires<[In64BitMode]>; 3280 3281// cmps aliases. Mnemonic suffix being omitted because it's implicit 3282// in the destination. 3283// def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSB dstidx8:$dst, srcidx8:$src), 0, "intel">; 3284// def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSW dstidx16:$dst, srcidx16:$src), 0, "intel">; 3285// def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSL dstidx32:$dst, srcidx32:$src), 0, "intel">; 3286// def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSQ dstidx64:$dst, srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>; 3287 3288// movs aliases. Mnemonic suffix being omitted because it's implicit 3289// in the destination. 3290// def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSB dstidx8:$dst, srcidx8:$src), 0, "intel">; 3291// def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSW dstidx16:$dst, srcidx16:$src), 0, "intel">; 3292// def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSL dstidx32:$dst, srcidx32:$src), 0, "intel">; 3293// def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSQ dstidx64:$dst, srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>; 3294 3295// div and idiv aliases for explicit A register. 3296// def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>; 3297// def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>; 3298// def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>; 3299// def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>; 3300// def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>; 3301// def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>; 3302// def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>; 3303// def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>; 3304// def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>; 3305// def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>; 3306// def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>; 3307// def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>; 3308// def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>; 3309// def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>; 3310// def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>; 3311// def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>; 3312 3313 3314 3315// Various unary fpstack operations default to operating on ST1. 3316// For example, "fxch" -> "fxch %st(1)" 3317// def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>; 3318//def: InstAlias<"fadd", (ADD_FPrST0 ST1), 0>; 3319// def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>; 3320// def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>; 3321// def : InstAlias<"fmul", (MUL_FPrST0 ST1), 0>; 3322// def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>; 3323// def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>; 3324// def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>; 3325// def : InstAlias<"fxch", (XCH_F ST1), 0>; 3326// def : InstAlias<"fcom", (COM_FST0r ST1), 0>; 3327// def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>; 3328// def : InstAlias<"fcomi", (COM_FIr ST1), 0>; 3329// def : InstAlias<"fcompi", (COM_FIPr ST1), 0>; 3330// def : InstAlias<"fucom", (UCOM_Fr ST1), 0>; 3331// def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>; 3332// def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>; 3333// def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>; 3334 3335/* 3336// Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op. 3337// For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate 3338// instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with 3339// gas. 3340//multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> { 3341 def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"), 3342 (Inst RST:$op), EmitAlias>; 3343 def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"), 3344 (Inst ST0), EmitAlias>; 3345} 3346 3347defm : FpUnaryAlias<"fadd", ADD_FST0r>; 3348defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>; 3349defm : FpUnaryAlias<"fsub", SUB_FST0r>; 3350defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>; 3351defm : FpUnaryAlias<"fsubr", SUBR_FST0r>; 3352defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>; 3353defm : FpUnaryAlias<"fmul", MUL_FST0r>; 3354defm : FpUnaryAlias<"fmulp", MUL_FPrST0>; 3355defm : FpUnaryAlias<"fdiv", DIV_FST0r>; 3356defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>; 3357defm : FpUnaryAlias<"fdivr", DIVR_FST0r>; 3358defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>; 3359defm : FpUnaryAlias<"fcomi", COM_FIr, 0>; 3360defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>; 3361defm : FpUnaryAlias<"fcompi", COM_FIPr>; 3362defm : FpUnaryAlias<"fucompi", UCOM_FIPr>; 3363*/ 3364 3365 3366// Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they 3367// commute. We also allow fdiv[r]p/fsubrp even though they don't commute, 3368// solely because gas supports it. 3369// def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>; 3370// def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>; 3371// def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>; 3372// def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>; 3373// def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>; 3374// def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>; 3375 3376// def : InstAlias<"fnstsw" , (FNSTSW16r), 0>; 3377 3378// lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but 3379// this is compatible with what GAS does. 3380// def : InstAlias<"lcall\t$seg : $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[In32BitMode]>; 3381// def : InstAlias<"ljmp\t$seg : $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[In32BitMode]>; 3382// def : InstAlias<"lcall\t{*}$dst", (FARCALL32m opaquemem:$dst), 0>, Requires<[Not16BitMode]>; 3383// def : InstAlias<"ljmp\t{*}$dst", (FARJMP32m opaquemem:$dst), 0>, Requires<[Not16BitMode]>; 3384// def : InstAlias<"lcall\t$seg : $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; 3385// def : InstAlias<"ljmp\t$seg : $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; 3386// def : InstAlias<"lcall\t{*}$dst", (FARCALL16m opaquemem:$dst), 0>, Requires<[In16BitMode]>; 3387// def : InstAlias<"ljmp\t{*}$dst", (FARJMP16m opaquemem:$dst), 0>, Requires<[In16BitMode]>; 3388 3389// def : InstAlias<"jmp\t{*}$dst", (JMP64m i64mem:$dst), 0, "att">, Requires<[In64BitMode]>; 3390// def : InstAlias<"jmp\t{*}$dst", (JMP32m i32mem:$dst), 0, "att">, Requires<[In32BitMode]>; 3391// def : InstAlias<"jmp\t{*}$dst", (JMP16m i16mem:$dst), 0, "att">, Requires<[In16BitMode]>; 3392 3393 3394// "imul <imm>, B" is an alias for "imul <imm>, B, B". 3395// def : InstAlias<"imul{w}\t{$imm, $r|$r, $imm}", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm), 0>; 3396// def : InstAlias<"imul{w}\t{$imm, $r|$r, $imm}", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm), 0>; 3397// def : InstAlias<"imul{l}\t{$imm, $r|$r, $imm}", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm), 0>; 3398// def : InstAlias<"imul{l}\t{$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm), 0>; 3399// def : InstAlias<"imul{q}\t{$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>; 3400// def : InstAlias<"imul{q}\t{$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>; 3401 3402// ins aliases. Accept the mnemonic suffix being omitted because it's implicit 3403// in the destination. 3404// def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSB dstidx8:$dst), 0, "intel">; 3405// def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSW dstidx16:$dst), 0, "intel">; 3406// def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSL dstidx32:$dst), 0, "intel">; 3407 3408// outs aliases. Accept the mnemonic suffix being omitted because it's implicit 3409// in the source. 3410// def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSB srcidx8:$src), 0, "intel">; 3411// def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSW srcidx16:$src), 0, "intel">; 3412// def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSL srcidx32:$src), 0, "intel">; 3413 3414// inb %dx -> inb %al, %dx 3415// def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>; 3416// def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>; 3417// def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>; 3418// def : InstAlias<"inb\t$port", (IN8ri u8imm:$port), 0>; 3419// def : InstAlias<"inw\t$port", (IN16ri u8imm:$port), 0>; 3420// def : InstAlias<"inl\t$port", (IN32ri u8imm:$port), 0>; 3421 3422 3423// jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp 3424// def : InstAlias<"call\t$seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; 3425// def : InstAlias<"jmp\t$seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; 3426// def : InstAlias<"call\t$seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[In32BitMode]>; 3427// def : InstAlias<"jmp\t$seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[In32BitMode]>; 3428// def : InstAlias<"callw\t$seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; 3429// def : InstAlias<"jmpw\t$seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; 3430// def : InstAlias<"calll\t$seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; 3431// def : InstAlias<"jmpl\t$seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; 3432 3433// Match 'movq <largeimm>, <reg>' as an alias for movabsq. 3434// def : InstAlias<"mov{q}\t{$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>; 3435 3436// Match 'movd GR64, MMX' as an alias for movq to be compatible with gas, 3437// which supports this due to an old AMD documentation bug when 64-bit mode was 3438// created. 3439// def : InstAlias<"movd\t{$src, $dst|$dst, $src}", 3440// (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>; 3441// def : InstAlias<"movd\t{$src, $dst|$dst, $src}", 3442// (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>; 3443 3444// movsx aliases 3445// def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX16rr8 GR16:$dst, GR8:$src), 0, "att">; 3446// def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0, "att">; 3447// def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX32rr8 GR32:$dst, GR8:$src), 0, "att">; 3448// def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX32rr16 GR32:$dst, GR16:$src), 0, "att">; 3449// def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr8 GR64:$dst, GR8:$src), 0, "att">; 3450// def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr16 GR64:$dst, GR16:$src), 0, "att">; 3451// def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr32 GR64:$dst, GR32:$src), 0, "att">; 3452 3453// movzx aliases 3454// def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX16rr8 GR16:$dst, GR8:$src), 0, "att">; 3455// def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0, "att">; 3456// def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX32rr8 GR32:$dst, GR8:$src), 0, "att">; 3457// def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX32rr16 GR32:$dst, GR16:$src), 0, "att">; 3458// def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX64rr8 GR64:$dst, GR8:$src), 0, "att">; 3459// def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX64rr16 GR64:$dst, GR16:$src), 0, "att">; 3460// Note: No GR32->GR64 movzx form. 3461 3462// outb %dx -> outb %al, %dx 3463// def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>; 3464// def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>; 3465// def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>; 3466// def : InstAlias<"outb\t$port", (OUT8ir u8imm:$port), 0>; 3467// def : InstAlias<"outw\t$port", (OUT16ir u8imm:$port), 0>; 3468// def : InstAlias<"outl\t$port", (OUT32ir u8imm:$port), 0>; 3469 3470// 'sldt <mem>' can be encoded with either sldtw or sldtq with the same 3471// effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity 3472// errors, since its encoding is the most compact. 3473// def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>; 3474 3475// shld/shrd op,op -> shld op, op, CL 3476// def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>; 3477// def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>; 3478// def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>; 3479// def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>; 3480// def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>; 3481// def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>; 3482 3483// def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>; 3484// def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>; 3485// def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>; 3486// def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>; 3487// def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>; 3488// def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>; 3489 3490/* FIXME: This is disabled because the asm matcher is currently incapable of 3491 * matching a fixed immediate like $1. 3492// "shl X, $1" is an alias for "shl X". 3493multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> { 3494 // def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"), 3495 // (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>; 3496 // def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"), 3497 // (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>; 3498 // def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"), 3499 // (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>; 3500 // def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"), 3501 // (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>; 3502 // def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"), 3503 // (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>; 3504 // def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"), 3505 // (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>; 3506 // def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"), 3507 // (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>; 3508 // def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"), 3509 // (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>; 3510} 3511 3512defm : ShiftRotateByOneAlias<"rcl", "RCL">; 3513defm : ShiftRotateByOneAlias<"rcr", "RCR">; 3514defm : ShiftRotateByOneAlias<"rol", "ROL">; 3515defm : ShiftRotateByOneAlias<"ror", "ROR">; 3516FIXME */ 3517 3518// test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms. 3519// def : InstAlias<"test{b}\t{$mem, $val|$val, $mem}", 3520// (TEST8mr i8mem :$mem, GR8 :$val), 0>; 3521// def : InstAlias<"test{w}\t{$mem, $val|$val, $mem}", 3522// (TEST16mr i16mem:$mem, GR16:$val), 0>; 3523// def : InstAlias<"test{l}\t{$mem, $val|$val, $mem}", 3524// (TEST32mr i32mem:$mem, GR32:$val), 0>; 3525// def : InstAlias<"test{q}\t{$mem, $val|$val, $mem}", 3526// (TEST64mr i64mem:$mem, GR64:$val), 0>; 3527 3528// xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms. 3529// def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}", 3530// (XCHG8rm GR8 :$val, i8mem :$mem), 0>; 3531// def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}", 3532// (XCHG16rm GR16:$val, i16mem:$mem), 0>; 3533// def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}", 3534// (XCHG32rm GR32:$val, i32mem:$mem), 0>; 3535// def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}", 3536// (XCHG64rm GR64:$val, i64mem:$mem), 0>; 3537 3538// xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms. 3539// def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>; 3540// def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", (XCHG32ar GR32:$src), 0>; 3541// def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>; 3542 3543// In 64-bit mode, xchg %eax, %eax can't be encoded with the 0x90 opcode we 3544// would get by default because it's defined as NOP. But xchg %eax, %eax implies 3545// implicit zeroing of the upper 32 bits. So alias to the longer encoding. 3546// def : InstAlias<"xchg{l}\t{%eax, %eax|eax, eax}", 3547// (XCHG32rr EAX, EAX), 0>, Requires<[In64BitMode]>; 3548 3549// xchg %rax, %rax is a nop in x86-64 and can be encoded as such. Without this 3550// we emit an unneeded REX.w prefix. 3551// def : InstAlias<"xchg{q}\t{%rax, %rax|rax, rax}", (NOOP), 0>; 3552 3553// These aliases exist to get the parser to prioritize matching 8-bit 3554// immediate encodings over matching the implicit ax/eax/rax encodings. By 3555// explicitly mentioning the A register here, these entries will be ordered 3556// first due to the more explicit immediate type. 3557// def : InstAlias<"adc{w}\t{$imm, %ax|ax, $imm}", (ADC16ri8 AX, i16i8imm:$imm), 0>; 3558// def : InstAlias<"add{w}\t{$imm, %ax|ax, $imm}", (ADD16ri8 AX, i16i8imm:$imm), 0>; 3559// def : InstAlias<"and{w}\t{$imm, %ax|ax, $imm}", (AND16ri8 AX, i16i8imm:$imm), 0>; 3560// def : InstAlias<"cmp{w}\t{$imm, %ax|ax, $imm}", (CMP16ri8 AX, i16i8imm:$imm), 0>; 3561// def : InstAlias<"or{w}\t{$imm, %ax|ax, $imm}", (OR16ri8 AX, i16i8imm:$imm), 0>; 3562// def : InstAlias<"sbb{w}\t{$imm, %ax|ax, $imm}", (SBB16ri8 AX, i16i8imm:$imm), 0>; 3563// def : InstAlias<"sub{w}\t{$imm, %ax|ax, $imm}", (SUB16ri8 AX, i16i8imm:$imm), 0>; 3564// def : InstAlias<"xor{w}\t{$imm, %ax|ax, $imm}", (XOR16ri8 AX, i16i8imm:$imm), 0>; 3565 3566// def : InstAlias<"adc{l}\t{$imm, %eax|eax, $imm}", (ADC32ri8 EAX, i32i8imm:$imm), 0>; 3567// def : InstAlias<"add{l}\t{$imm, %eax|eax, $imm}", (ADD32ri8 EAX, i32i8imm:$imm), 0>; 3568// def : InstAlias<"and{l}\t{$imm, %eax|eax, $imm}", (AND32ri8 EAX, i32i8imm:$imm), 0>; 3569// def : InstAlias<"cmp{l}\t{$imm, %eax|eax, $imm}", (CMP32ri8 EAX, i32i8imm:$imm), 0>; 3570// def : InstAlias<"or{l}\t{$imm, %eax|eax, $imm}", (OR32ri8 EAX, i32i8imm:$imm), 0>; 3571// def : InstAlias<"sbb{l}\t{$imm, %eax|eax, $imm}", (SBB32ri8 EAX, i32i8imm:$imm), 0>; 3572// def : InstAlias<"sub{l}\t{$imm, %eax|eax, $imm}", (SUB32ri8 EAX, i32i8imm:$imm), 0>; 3573// def : InstAlias<"xor{l}\t{$imm, %eax|eax, $imm}", (XOR32ri8 EAX, i32i8imm:$imm), 0>; 3574 3575// def : InstAlias<"adc{q}\t{$imm, %rax|rax, $imm}", (ADC64ri8 RAX, i64i8imm:$imm), 0>; 3576// def : InstAlias<"add{q}\t{$imm, %rax|rax, $imm}", (ADD64ri8 RAX, i64i8imm:$imm), 0>; 3577// def : InstAlias<"and{q}\t{$imm, %rax|rax, $imm}", (AND64ri8 RAX, i64i8imm:$imm), 0>; 3578// def : InstAlias<"cmp{q}\t{$imm, %rax|rax, $imm}", (CMP64ri8 RAX, i64i8imm:$imm), 0>; 3579// def : InstAlias<"or{q}\t{$imm, %rax|rax, $imm}", (OR64ri8 RAX, i64i8imm:$imm), 0>; 3580// def : InstAlias<"sbb{q}\t{$imm, %rax|rax, $imm}", (SBB64ri8 RAX, i64i8imm:$imm), 0>; 3581// def : InstAlias<"sub{q}\t{$imm, %rax|rax, $imm}", (SUB64ri8 RAX, i64i8imm:$imm), 0>; 3582// def : InstAlias<"xor{q}\t{$imm, %rax|rax, $imm}", (XOR64ri8 RAX, i64i8imm:$imm), 0>; 3583