1 /*****************************************************************************
2 * Copyright (c) 2013 IBM Corporation
3 * All rights reserved.
4 * This program and the accompanying materials
5 * are made available under the terms of the BSD License
6 * which accompanies this distribution, and is available at
7 * http://www.opensource.org/licenses/bsd-license.php
8 *
9 * Contributors:
10 * IBM Corporation - initial implementation
11 *****************************************************************************/
12
13 #include <string.h>
14 #include "usb.h"
15 #include "usb-core.h"
16 #include "usb-xhci.h"
17 #include "tools.h"
18 #include "paflof.h"
19
20 #undef XHCI_DEBUG
21 //#define XHCI_DEBUG
22 #ifdef XHCI_DEBUG
23 #define dprintf(_x ...) do { printf("%s: ", __func__); printf(_x); } while (0)
24 #else
25 #define dprintf(_x ...) do {} while (0)
26 #endif
27
28 struct port_state ps_array_usb2[] = {
29 {1, 0, 0, 0, PORTSC_PLS_U0, "ERROR"}
30 };
31
32 struct port_state ps_array_usb3[] = {
33 {0, 0, 0, 0, PORTSC_PLS_DISABLED, "Powered-OFF"},
34 {1, 0, 0, 0, PORTSC_PLS_POLLING, "Polling"},
35 {1, 0, 0, 0, PORTSC_PLS_U0, "Polling"},
36 {1, 0, 0, 0, PORTSC_PLS_RXDETECT, "*** Disconnected ***"},
37 {1, 0, 0, 0, PORTSC_PLS_DISABLED, "Disabled"},
38 {1, 0, 0, 0, PORTSC_PLS_INACTIVE, "Error"},
39 {1, 0, 0, 0, PORTSC_PLS_TEST_MODE,"Loopback"},
40 {1, 0, 0, 0, PORTSC_PLS_COMP_MODE,"Compliancek"},
41 {1, 1, 0, 1, PORTSC_PLS_U0, "****** Reset ******"},
42 {1, 1, 1, 0, PORTSC_PLS_U0, "****** Enabled ******"},
43 };
44
45 #ifdef XHCI_DEBUG
dump_xhci_regs(struct xhci_hcd * xhcd)46 static void dump_xhci_regs(struct xhci_hcd *xhcd)
47 {
48 struct xhci_cap_regs *cap;
49 struct xhci_op_regs *op;
50 struct xhci_run_regs *run;
51
52 cap = xhcd->cap_regs;
53 op = xhcd->op_regs;
54 run = xhcd->run_regs;
55
56 dprintf("\n");
57 dprintf(" - CAPLENGTH %02X\n", read_reg8 (&cap->caplength));
58 dprintf(" - HCIVERSION %04X\n", read_reg16(&cap->hciversion));
59 dprintf(" - HCSPARAMS1 %08X\n", read_reg32(&cap->hcsparams1));
60 dprintf(" - HCSPARAMS2 %08X\n", read_reg32(&cap->hcsparams2));
61 dprintf(" - HCSPARAMS3 %08X\n", read_reg32(&cap->hcsparams3));
62 dprintf(" - HCCPARAMS %08X\n", read_reg32(&cap->hccparams));
63 dprintf(" - DBOFF %08X\n", read_reg32(&cap->dboff));
64 dprintf(" - RTSOFF %08X\n", read_reg32(&cap->rtsoff));
65 dprintf("\n");
66
67 dprintf(" - USBCMD %08X\n", read_reg32(&op->usbcmd));
68 dprintf(" - USBSTS %08X\n", read_reg32(&op->usbsts));
69 dprintf(" - PAGESIZE %08X\n", read_reg32(&op->pagesize));
70 dprintf(" - DNCTRL %08X\n", read_reg32(&op->dnctrl));
71 dprintf(" - CRCR %016llX\n", read_reg64(&op->crcr));
72 dprintf(" - DCBAAP %016llX\n", read_reg64(&op->dcbaap));
73 dprintf(" - CONFIG %08X\n", read_reg32(&op->config));
74 dprintf("\n");
75
76 dprintf(" - MFINDEX %08X\n", read_reg32(&run->mfindex));
77 dprintf("\n");
78 }
79
print_port_status(struct xhci_port_regs * prs)80 static void print_port_status(struct xhci_port_regs *prs)
81 {
82 uint32_t portsc;
83 uint32_t CCS, PED, PP, PLS, i, PR = 0;
84
85 portsc = read_reg32(&prs->portsc);
86 dprintf("portsc %08x portpmsc %08x portli %08x\n",
87 portsc,
88 read_reg32(&prs->portpmsc),
89 read_reg32(&prs->portli));
90
91 if (portsc & PORTSC_CCS) {
92 printf("CCS ");
93 CCS = 1;
94 }
95 if (portsc & PORTSC_PED) {
96 printf("PED ");
97 PED = 1;
98 }
99 if (portsc & PORTSC_OCA)
100 printf("OCA ");
101 if (portsc & PORTSC_PR)
102 printf("OCA ");
103 PLS = (portsc & PORTSC_PLS_MASK) >> 5;
104 printf("PLS:%d ", PLS);
105 if (portsc & PORTSC_PP) {
106 printf("PP ");
107 PP = 1;
108 }
109 printf("PS:%d ", (portsc & PORTSC_PS_MASK) >> 10);
110 printf("PIC:%d ", (portsc & PORTSC_PIC_MASK) >> 14);
111 if (portsc & PORTSC_LWS)
112 printf("LWS ");
113 if (portsc & PORTSC_CSC)
114 printf("CSC ");
115 if (portsc & PORTSC_PEC)
116 printf("PEC ");
117 if (portsc & PORTSC_WRC)
118 printf("WRC ");
119 if (portsc & PORTSC_OCC)
120 printf("OCC ");
121 if (portsc & PORTSC_PRC)
122 printf("PRC ");
123 if (portsc & PORTSC_PLC)
124 printf("PLC ");
125 if (portsc & PORTSC_CEC)
126 printf("CEC ");
127 if (portsc & PORTSC_CAS)
128 printf("CAS ");
129 if (portsc & PORTSC_WCE)
130 printf("WCE ");
131 if (portsc & PORTSC_WDE)
132 printf("WDE ");
133 if (portsc & PORTSC_WOE)
134 printf("WOE ");
135 if (portsc & PORTSC_DR)
136 printf("DR ");
137 if (portsc & PORTSC_WPR)
138 printf("WPR ");
139 printf("\n");
140
141 for (i = 0 ; i < (sizeof(ps_array_usb3)/sizeof(struct port_state)); i++) {
142 if (PP == ps_array_usb3[i].PP) {
143 if (CCS == ps_array_usb3[i].CCS) {
144 if (PED == ps_array_usb3[i].PED) {
145 if (PR == ps_array_usb3[i].PR) {
146 dprintf("%s - PLS %d\n", ps_array_usb3[i].state, PLS);
147 break;
148 }
149 }
150 }
151 }
152 }
153 }
154
155 #else
156 #define dump_xhci_regs(r) do {} while (0)
157 #define print_port_status(prs) do {} while (0)
158 #endif
159
xhci_is_hc_ready(uint32_t * usbsts)160 static inline bool xhci_is_hc_ready(uint32_t *usbsts)
161 {
162 return !(read_reg32(usbsts) & XHCI_USBSTS_CNR);
163 }
164
xhci_wait_for_cnr(uint32_t * usbsts)165 static inline bool xhci_wait_for_cnr(uint32_t *usbsts)
166 {
167 /* Standard:
168 * Note: The xHC should halt within 16 ms. of software clearing the
169 * R/S bit to ‘0’.
170 * Give some more time... 32ms
171 */
172 int count = 320;
173 dprintf("Waiting for Controller ready ..");
174 while (!xhci_is_hc_ready(usbsts)) {
175 dprintf(".");
176 count--;
177 if (!count) {
178 dprintf(" failed %08X\n", read_reg32(usbsts));
179 return false;
180 }
181 SLOF_usleep(100);
182 }
183 dprintf(" done\n");
184 return true;
185 }
186
xhci_hcd_set_runstop(struct xhci_op_regs * op,bool run_req)187 static bool xhci_hcd_set_runstop(struct xhci_op_regs *op, bool run_req)
188 {
189 uint32_t reg;
190
191 dprintf("Request %s\n", run_req ? "RUN" : "STOP");
192 if (!xhci_is_hc_ready(&op->usbsts)) {
193 dprintf("Controller not ready\n");
194 return false;
195 }
196
197 reg = read_reg32(&op->usbcmd);
198 if (run_req)
199 reg |= run_req;
200 else
201 reg &= (uint32_t)~1;
202 dprintf("writing %08X\n", reg);
203 write_reg32(&op->usbcmd, reg);
204 mb();
205 xhci_wait_for_cnr(&op->usbsts);
206 return true;
207 }
208
xhci_hcd_reset(struct xhci_op_regs * op)209 static bool xhci_hcd_reset(struct xhci_op_regs *op)
210 {
211 uint32_t reg;
212
213 /* Check if the controller is halted, else halt it */
214 if (!(read_reg32(&op->usbsts) & XHCI_USBSTS_HCH)) {
215 dprintf("HCHalted not set\n");
216 if (!xhci_hcd_set_runstop(op, false))
217 return false;
218 }
219
220 if (read_reg32(&op->usbsts) & XHCI_USBSTS_CNR) {
221 dprintf("Controller not ready\n");
222 return false;
223 }
224
225 reg = read_reg32(&op->usbcmd) | XHCI_USBCMD_HCRST;
226 /* Ready to Reset the controller now */
227 write_reg32(&op->usbcmd, reg);
228 xhci_wait_for_cnr(&op->usbsts);
229 return true;
230 }
231
xhci_handle_cmd_completion(struct xhci_hcd * xhcd,struct xhci_event_trb * event)232 static void xhci_handle_cmd_completion(struct xhci_hcd *xhcd,
233 struct xhci_event_trb *event)
234 {
235 uint32_t flags, slot_id, status;
236
237 status = le32_to_cpu(event->status);
238 flags = le32_to_cpu(event->flags);
239 slot_id = TRB_SLOT_ID(flags);
240 if (TRB_STATUS(status) == COMP_SUCCESS)
241 xhcd->slot_id = slot_id;
242 else
243 xhcd->slot_id = 0;
244 }
245
xhci_poll_event(struct xhci_hcd * xhcd,uint32_t event_type)246 static uint64_t xhci_poll_event(struct xhci_hcd *xhcd,
247 uint32_t event_type)
248 {
249 struct xhci_event_trb *event;
250 uint64_t val, retval = 0;
251 uint32_t flags, time;
252 int index;
253
254 mb();
255 event = (struct xhci_event_trb *)xhcd->ering.deq;
256 flags = le32_to_cpu(event->flags);
257
258 dprintf("Reading from event ptr %p %08x\n", event, flags);
259 time = SLOF_GetTimer() + ((event_type == XHCI_POLL_NO_WAIT)? 0: USB_TIMEOUT);
260
261 while ((flags & TRB_CYCLE_STATE) != xhcd->ering.cycle_state) {
262 mb();
263 flags = le32_to_cpu(event->flags);
264 if (time < SLOF_GetTimer())
265 return 0;
266 }
267
268 mb();
269 flags = le32_to_cpu(event->flags);
270 switch(TRB_TYPE(flags))
271 {
272 case TRB_CMD_COMPLETION:
273 dprintf("CMD Completion\n");
274 xhci_handle_cmd_completion(xhcd, event);
275 break;
276 case TRB_PORT_STATUS:
277 dprintf("Port status event\n");
278 break;
279 case TRB_TRANSFER_EVENT:
280 dprintf("XFER event addr %16lx, status %08x, flags %08x\n",
281 le64_to_cpu(event->addr),
282 le32_to_cpu(event->status),
283 le32_to_cpu(event->flags));
284 break;
285 default:
286 printf("TRB_TYPE %d\n", TRB_TYPE(flags));
287 dprintf("Event addr %16lx, status %08x, flags %08x state %d\n",
288 le64_to_cpu(event->addr),
289 le32_to_cpu(event->status),
290 flags, xhcd->ering.cycle_state);
291 break;
292 }
293 xhcd->ering.deq = (uint64_t) (event + 1);
294 retval = le64_to_cpu(event->addr);
295
296 event->addr = 0;
297 event->status = 0;
298 event->flags = cpu_to_le32(xhcd->ering.cycle_state);
299
300 index = xhcd->ering.deq - (uint64_t)xhcd->ering.trbs;
301 val = xhcd->ering.trbs_dma;
302 val += (index % XHCI_EVENT_TRBS_SIZE);
303 if (!(index % XHCI_EVENT_TRBS_SIZE)) {
304 xhcd->ering.deq = (uint64_t)xhcd->ering.trbs;
305 xhcd->ering.cycle_state = xhcd->ering.cycle_state ? 0 : 1;
306 dprintf("Rounding %d\n", xhcd->ering.cycle_state);
307 }
308 dprintf("Update start %x deq %x index %d\n",
309 xhcd->ering.trbs_dma, val, index/sizeof(*event));
310 write_reg64(&xhcd->run_regs->irs[0].erdp, val);
311
312 if (retval == 0)
313 return (uint64_t)event;
314 else
315 return retval;
316 }
317
xhci_send_cmd(struct xhci_hcd * xhcd,uint32_t field1,uint32_t field2,uint32_t field3,uint32_t field4)318 static void xhci_send_cmd(struct xhci_hcd *xhcd, uint32_t field1,
319 uint32_t field2, uint32_t field3, uint32_t field4)
320 {
321 struct xhci_db_regs *dbr;
322 struct xhci_command_trb *cmd;
323 uint32_t val, cycle_state;
324
325 dbr = xhcd->db_regs;
326 cmd = (struct xhci_command_trb *)xhcd->crseg.enq;
327
328 cmd->field[0] = cpu_to_le32(field1);
329 cmd->field[1] = cpu_to_le32(field2);
330 cmd->field[2] = cpu_to_le32(field3);
331
332 val = le32_to_cpu(cmd->field[3]);
333 cycle_state = (val & 0x1) ? 0 : 1;
334 val = field4 | cycle_state;
335 cmd->field[3] = cpu_to_le32(val);
336
337 dprintf("CMD %016lx val %08x cycle_state %d field1 %08x, field2 %08x, field3 %08x field4 %08x\n",
338 cmd, val, cycle_state,
339 le32_to_cpu(cmd->field[0]),
340 le32_to_cpu(cmd->field[1]),
341 le32_to_cpu(cmd->field[2]),
342 le32_to_cpu(cmd->field[3])
343 );
344
345 /* Ring the doorbell */
346 write_reg32(&dbr->db[0], 0);
347 xhci_poll_event(xhcd, 0);
348 cmd++;
349 xhcd->crseg.enq = (uint64_t)cmd;
350 return;
351 }
352
xhci_send_enable_slot(struct xhci_hcd * xhcd,uint32_t port)353 static void xhci_send_enable_slot(struct xhci_hcd *xhcd, uint32_t port)
354 {
355 uint32_t field1, field2, field3, field4;
356
357 field1 = 0;
358 field2 = 0;
359 field3 = 0;
360 field4 = TRB_CMD_TYPE(TRB_ENABLE_SLOT);
361 xhci_send_cmd(xhcd, field1, field2, field3, field4);
362 }
363
xhci_send_addr_device(struct xhci_hcd * xhcd,uint32_t slot_id,uint64_t dma_in_ctx)364 static void xhci_send_addr_device(struct xhci_hcd *xhcd, uint32_t slot_id,
365 uint64_t dma_in_ctx)
366 {
367 uint32_t field1, field2, field3, field4;
368
369 dprintf("Address device %lx, low %x, high %x\n", dma_in_ctx,
370 TRB_ADDR_LOW(dma_in_ctx),
371 TRB_ADDR_HIGH(dma_in_ctx));
372 field1 = TRB_ADDR_LOW(dma_in_ctx) & ~0xF;
373 field2 = TRB_ADDR_HIGH(dma_in_ctx);
374 field3 = 0;
375 field4 = TRB_CMD_TYPE(TRB_ADDRESS_DEV) | TRB_CMD_SLOT_ID(slot_id);
376 xhci_send_cmd(xhcd, field1, field2, field3, field4);
377 }
378
xhci_get_epno(struct usb_pipe * pipe)379 static uint32_t xhci_get_epno(struct usb_pipe *pipe)
380 {
381 uint32_t x_epno;
382 x_epno = pipe->dir | 2 * pipe->epno;
383 dprintf("EPno %d:%d DIR %d\n", pipe->epno, x_epno, pipe->dir);
384 return x_epno;
385 }
386
xhci_configure_ep(struct xhci_hcd * xhcd,uint32_t slot_id,uint64_t dma_in_ctx)387 static void xhci_configure_ep(struct xhci_hcd *xhcd, uint32_t slot_id,
388 uint64_t dma_in_ctx)
389 {
390 uint32_t field1, field2, field3, field4;
391
392 dprintf("Configure EP %lx, low %x, high %x\n", dma_in_ctx,
393 TRB_ADDR_LOW(dma_in_ctx),
394 TRB_ADDR_HIGH(dma_in_ctx));
395 field1 = TRB_ADDR_LOW(dma_in_ctx) & ~0xF;
396 field2 = TRB_ADDR_HIGH(dma_in_ctx);
397 field3 = 0;
398 field4 = TRB_CMD_TYPE(TRB_CONFIG_EP) | TRB_CMD_SLOT_ID(slot_id);
399 xhci_send_cmd(xhcd, field1, field2, field3, field4);
400 }
401
xhci_init_seg(struct xhci_seg * seg,uint32_t size,uint32_t type)402 static void xhci_init_seg(struct xhci_seg *seg, uint32_t size, uint32_t type)
403 {
404 struct xhci_link_trb *link;
405
406 seg->size = size / XHCI_TRB_SIZE;
407 seg->next = NULL;
408 seg->type = type;
409 seg->cycle_state = 1;
410 seg->enq = (uint64_t)seg->trbs;
411 seg->deq = (uint64_t)seg->trbs;
412 memset((void *)seg->trbs, 0, size);
413
414 if (type != TYPE_EVENT) {
415 link =(struct xhci_link_trb *) (seg->trbs + seg->size - 1);
416 link->addr = cpu_to_le64(seg->trbs_dma);
417 link->field2 = 0;
418 link->field3 = cpu_to_le32(0x1 | TRB_CMD_TYPE(TRB_LINK));
419 }
420 return;
421 }
422
xhci_alloc_seg(struct xhci_seg * seg,uint32_t size,uint32_t type)423 static bool xhci_alloc_seg(struct xhci_seg *seg, uint32_t size, uint32_t type)
424 {
425 seg->trbs = (union xhci_trb *)SLOF_dma_alloc(size);
426 if (!seg->trbs) {
427 dprintf("Alloc failed\n");
428 return false;
429 }
430 xhci_init_seg(seg, size, type);
431 seg->trbs_dma = SLOF_dma_map_in((void *)seg->trbs, size, false);
432
433 dprintf(" TRBs %016lX TRBS-DMA %016lX\n", seg->trbs, seg->trbs_dma);
434 return true;
435 }
436
xhci_free_seg(struct xhci_seg * seg,uint32_t size)437 static void xhci_free_seg(struct xhci_seg *seg, uint32_t size)
438 {
439 if (seg->trbs) {
440 dprintf(" TRBs %016lX TRBS-DMA %016lX size %x\n", seg->trbs, seg->trbs_dma, size);
441 SLOF_dma_map_out(seg->trbs_dma, (void *)seg->trbs, size);
442 SLOF_dma_free((void *)seg->trbs, size);
443 }
444 memset(seg, 0, sizeof(*seg));
445 }
446
447 #define CTX_SIZE(x) ( (x) ? 64 : 32 )
448
xhci_alloc_ctx(struct xhci_ctx * ctx,uint32_t size,uint32_t type)449 static bool xhci_alloc_ctx(struct xhci_ctx *ctx, uint32_t size, uint32_t type)
450 {
451 ctx->addr = (uint8_t *)SLOF_dma_alloc(size);
452 if (!ctx->addr) {
453 dprintf("Alloc failed\n");
454 return false;
455 }
456 ctx->size = size;
457 ctx->type = type;
458 memset((void *)ctx->addr, 0, size);
459 ctx->dma_addr = SLOF_dma_map_in((void *)ctx->addr, size, false);
460 dprintf("ctx %llx, ctx_dma %llx\n", ctx->addr, ctx->dma_addr);
461 return true;
462 }
463
xhci_get_control_ctx(struct xhci_ctx * ctx)464 static struct xhci_control_ctx *xhci_get_control_ctx(struct xhci_ctx *ctx)
465 {
466 if (ctx->type == XHCI_CTX_TYPE_INPUT)
467 return (struct xhci_control_ctx *) ctx->addr;
468 return NULL;
469 }
470
xhci_get_slot_ctx(struct xhci_ctx * ctx,uint32_t ctx_size)471 static struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_ctx *ctx, uint32_t ctx_size)
472 {
473 uint32_t offset = 0;
474
475 if (ctx->type == XHCI_CTX_TYPE_INPUT)
476 offset += ctx_size;
477 return (struct xhci_slot_ctx *)(ctx->addr + offset);
478 }
479
xhci_get_ep0_ctx(struct xhci_ctx * ctx,uint32_t ctx_size)480 static struct xhci_ep_ctx *xhci_get_ep0_ctx(struct xhci_ctx *ctx, uint32_t ctx_size)
481 {
482 uint32_t offset = 0;
483
484 offset = ctx_size;
485 if (ctx->type == XHCI_CTX_TYPE_INPUT)
486 offset += ctx_size;
487 return (struct xhci_ep_ctx *)(ctx->addr + offset);
488 }
489
xhci_get_ep_ctx(struct xhci_ctx * ctx,uint32_t ctx_size,uint32_t epno)490 static struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_ctx *ctx, uint32_t ctx_size,
491 uint32_t epno)
492 {
493 uint32_t offset = 0;
494
495 offset = ctx_size * epno;
496 if (ctx->type == XHCI_CTX_TYPE_INPUT)
497 offset += ctx_size;
498 return (struct xhci_ep_ctx *)(ctx->addr + offset);
499 }
500
xhci_free_ctx(struct xhci_ctx * ctx,uint32_t size)501 static void xhci_free_ctx(struct xhci_ctx *ctx, uint32_t size)
502 {
503 SLOF_dma_map_out(ctx->dma_addr, (void *)ctx->addr, size);
504 SLOF_dma_free((void *)ctx->addr, size);
505 }
506
usb_control_max_packet(uint32_t speed)507 static uint32_t usb_control_max_packet(uint32_t speed)
508 {
509 uint32_t max_packet = 0;
510
511 switch(speed)
512 {
513 case USB_LOW_SPEED:
514 max_packet = 8;
515 break;
516 case USB_FULL_SPEED:
517 max_packet = 8;
518 break;
519 case USB_HIGH_SPEED:
520 max_packet = 64;
521 break;
522 case USB_SUPER_SPEED:
523 max_packet = 512;
524 break;
525 default:
526 /* should not reach here */
527 dprintf("Unknown speed\n");
528 }
529 return max_packet;
530 }
531
xhci_alloc_dev(struct xhci_hcd * xhcd,struct usb_dev * hub,uint32_t slot_id,uint32_t port,uint32_t slotspeed)532 static bool xhci_alloc_dev(struct xhci_hcd *xhcd, struct usb_dev *hub,
533 uint32_t slot_id, uint32_t port, uint32_t slotspeed)
534 {
535 struct usb_dev *dev;
536 struct xhci_dev *xdev;
537 struct xhci_slot_ctx *slot;
538 struct xhci_control_ctx *ctrl;
539 struct xhci_ep_ctx *ep0;
540 uint32_t ctx_size, val;
541 uint16_t max_packet;
542 uint32_t newport, rootport;
543
544 if (slot_id > XHCI_CONFIG_MAX_SLOT) {
545 printf("USB3 slot ID %d is too high (max is %d)\n", slot_id,
546 XHCI_CONFIG_MAX_SLOT);
547 return false;
548 }
549
550 ctx_size = CTX_SIZE(xhcd->hcc_csz_64);
551 xdev = &xhcd->xdevs[slot_id];
552 xdev->slot_id = slot_id;
553 xdev->ctx_size = ctx_size;
554
555 /* 4.3.3 Device Slot initialization */
556 /* Step 1 */
557 if (!xhci_alloc_ctx(&xdev->in_ctx, XHCI_CTX_BUF_SIZE, XHCI_CTX_TYPE_INPUT)) {
558 dprintf("Failed allocating in_ctx\n");
559 return false;
560 }
561
562 /* Step 2 */
563 ctrl = xhci_get_control_ctx(&xdev->in_ctx);
564 ctrl->a_flags = cpu_to_le32(0x3); /* A0, A1 */
565 ctrl->d_flags = 0;
566
567 /* Step 3 */
568 slot = xhci_get_slot_ctx(&xdev->in_ctx, ctx_size);
569 newport = rootport = port + 1;
570 val = newport & 0xf;
571 for (dev = hub; dev != NULL; dev = dev->hub) {
572 val = (val << 4) | (dev->port & 0xf); /* Build route string */
573 rootport = dev->port;
574 }
575 val >>= 4; /* Remove root hub ID from the string */
576 val |= LAST_CONTEXT(1) | slotspeed;
577 slot->field1 = cpu_to_le32(val);
578 slot->field2 = cpu_to_le32(ROOT_HUB_PORT(rootport));
579
580 /* Step 4 */
581 if (!xhci_alloc_seg(&xdev->control, XHCI_CONTROL_TRBS_SIZE, TYPE_CTRL)) {
582 dprintf("Failed allocating control\n");
583 goto fail_in_ctx;
584 }
585
586 /* Step 5 */
587 ep0 = xhci_get_ep0_ctx(&xdev->in_ctx, ctx_size);
588 val = 0;
589 max_packet = usb_control_max_packet(USB_SUPER_SPEED);
590 max_packet = 64;
591 val = EP_TYPE(EP_CTRL) | MAX_BURST(0) | ERROR_COUNT(3) |
592 MAX_PACKET_SIZE(max_packet);
593 ep0->field2 = cpu_to_le32(val);;
594 ep0->deq_addr = cpu_to_le64(xdev->control.trbs_dma | xdev->control.cycle_state);
595 ep0->field4 = cpu_to_le32(8);
596
597 /* Step 6 */
598 if (!xhci_alloc_ctx(&xdev->out_ctx, XHCI_CTX_BUF_SIZE, XHCI_CTX_TYPE_DEVICE)) {
599 dprintf("Failed allocating out_ctx\n");
600 goto fail_control_seg;
601 }
602
603 /* Step 7 */
604 xhcd->dcbaap[slot_id] = cpu_to_le64(xdev->out_ctx.dma_addr);
605
606 /* Step 8 */
607 slot = xhci_get_slot_ctx(&xdev->out_ctx, ctx_size);
608 ep0 = xhci_get_ep0_ctx(&xdev->out_ctx, ctx_size);
609
610 dprintf("Slot State %x \n", SLOT_STATE(le32_to_cpu(slot->field4)));
611 xhci_send_addr_device(xhcd, slot_id, xdev->in_ctx.dma_addr);
612 mb();
613 dprintf("Slot State %x \n", SLOT_STATE(le32_to_cpu(slot->field4)));
614
615 dprintf("EP0 f0 %08X f1 %08X %016lX %08X\n",
616 le32_to_cpu(ep0->field1),
617 le32_to_cpu(ep0->field2),
618 le64_to_cpu(ep0->deq_addr),
619 le32_to_cpu(ep0->field4));
620
621 /* Step 9 - configure ep */
622 ctrl->a_flags = cpu_to_le32(0x1); /* A0 */
623 ctrl->d_flags = 0;
624 xhci_configure_ep(xhcd, slot_id, xdev->in_ctx.dma_addr);
625 mb();
626 dprintf("Slot State %x \n", SLOT_STATE(le32_to_cpu(slot->field4)));
627 dprintf("USB Device address %d \n", USB_DEV_ADDRESS(le32_to_cpu(slot->field4)));
628 dprintf("EP0 f0 %08X f1 %08X %016lX %08X\n",
629 le32_to_cpu(ep0->field1),
630 le32_to_cpu(ep0->field2),
631 le64_to_cpu(ep0->deq_addr),
632 le32_to_cpu(ep0->field4));
633
634 dev = usb_devpool_get();
635 dprintf("allocated device %p\n", dev);
636 dev->hcidev = xhcd->hcidev;
637 dev->speed = USB_SUPER_SPEED;
638 dev->addr = USB_DEV_ADDRESS(slot->field4);
639 dev->port = newport;
640 dev->hub = hub;
641 dev->priv = xdev;
642 xdev->dev = dev;
643 if (usb_setup_new_device(dev, newport)) {
644 usb_slof_populate_new_device(dev);
645 return true;
646 }
647
648 xhci_free_ctx(&xdev->out_ctx, XHCI_CTX_BUF_SIZE);
649 fail_control_seg:
650 xhci_free_seg(&xdev->control, XHCI_CONTROL_TRBS_SIZE);
651 fail_in_ctx:
652 xhci_free_ctx(&xdev->in_ctx, XHCI_CTX_BUF_SIZE);
653 return false;
654 }
655
xhci_free_dev(struct xhci_dev * xdev)656 static void xhci_free_dev(struct xhci_dev *xdev)
657 {
658 xhci_free_seg(&xdev->bulk_in, XHCI_DATA_TRBS_SIZE);
659 xhci_free_seg(&xdev->bulk_out, XHCI_DATA_TRBS_SIZE);
660 xhci_free_seg(&xdev->intr, XHCI_INTR_TRBS_SIZE);
661 xhci_free_seg(&xdev->control, XHCI_CONTROL_TRBS_SIZE);
662 xhci_free_ctx(&xdev->in_ctx, XHCI_CTX_BUF_SIZE);
663 xhci_free_ctx(&xdev->out_ctx, XHCI_CTX_BUF_SIZE);
664 }
665
usb3_dev_init(struct xhci_hcd * xhcd,struct usb_dev * hub,uint32_t port,uint32_t slotspeed)666 bool usb3_dev_init(struct xhci_hcd *xhcd, struct usb_dev *hub, uint32_t port,
667 uint32_t slotspeed)
668 {
669 /* Device enable slot */
670 xhci_send_enable_slot(xhcd, port);
671 if (!xhcd->slot_id) {
672 dprintf("Unable to get slot id\n");
673 return false;
674 }
675 dprintf("SLOT ID: %d\n", xhcd->slot_id);
676 if (!xhci_alloc_dev(xhcd, hub, xhcd->slot_id, port, slotspeed)) {
677 dprintf("Unable to allocate device\n");
678 return false;
679 }
680 return true;
681 }
682
xhci_device_present(uint32_t portsc,uint32_t usb_ver)683 static int xhci_device_present(uint32_t portsc, uint32_t usb_ver)
684 {
685 if (usb_ver == USB_XHCI) {
686 /* Device present and enabled state */
687 if ((portsc & PORTSC_CCS) &&
688 (portsc & PORTSC_PP) &&
689 (portsc & PORTSC_PED)) {
690 return true;
691 }
692 } else if (usb_ver == USB_EHCI) {
693 /* Device present and in disabled state */
694 if ((portsc & PORTSC_CCS) && (portsc & PORTSC_CSC))
695 return true;
696 }
697 return false;
698 }
699
xhci_port_scan(struct xhci_hcd * xhcd,uint32_t usb_ver)700 static int xhci_port_scan(struct xhci_hcd *xhcd,
701 uint32_t usb_ver)
702 {
703 uint32_t num_ports, portsc, i;
704 struct xhci_op_regs *op;
705 struct xhci_port_regs *prs;
706 struct xhci_cap_regs *cap;
707 uint32_t xecp_off;
708 uint32_t *xecp_addr, *base;
709 uint32_t port_off = 0, port_cnt;
710
711 dprintf("enter\n");
712
713 op = xhcd->op_regs;
714 cap = xhcd->cap_regs;
715 port_cnt = num_ports = read_reg32(&cap->hcsparams1) >> 24;
716
717 /* Read the xHCI extented capability to find usb3 ports and offset*/
718 xecp_off = XHCI_HCCPARAMS_XECP(read_reg32(&cap->hccparams));
719 base = (uint32_t *)cap;
720 while (xecp_off > 0) {
721 xecp_addr = base + xecp_off;
722 dprintf("xecp_off %d %p %p \n", xecp_off, base, xecp_addr);
723
724 if (XHCI_XECP_CAP_ID(read_reg32(xecp_addr)) == XHCI_XECP_CAP_SP &&
725 XHCI_XECP_CAP_SP_MJ(read_reg32(xecp_addr)) == usb_ver &&
726 XHCI_XECP_CAP_SP_MN(read_reg32(xecp_addr)) == 0) {
727 port_cnt = XHCI_XECP_CAP_SP_PC(read_reg32(xecp_addr + 2));
728 port_off = XHCI_XECP_CAP_SP_PO(read_reg32(xecp_addr + 2));
729 dprintf("PortCount %d Portoffset %d\n", port_cnt, port_off);
730 }
731 base = xecp_addr;
732 xecp_off = XHCI_XECP_NEXT_PTR(read_reg32(xecp_addr));
733 }
734 if (port_off == 0) /* port_off should always start from 1 */
735 return false;
736 for (i = (port_off - 1); i < (port_off + port_cnt - 1); i++) {
737 prs = &op->prs[i];
738 portsc = read_reg32(&prs->portsc);
739 if (xhci_device_present(portsc, usb_ver)) {
740 /* Device present */
741 dprintf("Device present on port %d\n", i);
742 /* Reset the port */
743 portsc = read_reg32(&prs->portsc);
744 portsc = portsc | PORTSC_PR;
745 write_reg32(&prs->portsc, portsc);
746 /* FIXME poll for port event */
747 SLOF_msleep(20);
748 xhci_poll_event(xhcd, 0);
749 portsc = read_reg32(&prs->portsc);
750 if (portsc & ~PORTSC_PRC) {
751 dprintf("Port reset complete %d\n", i);
752 }
753 print_port_status(prs);
754 if (!usb3_dev_init(xhcd, NULL, i - (port_off - 1),
755 ((portsc >> 10) & 0xf) << 20)) {
756 dprintf("USB device initialization failed\n");
757 }
758 }
759 }
760 dprintf("exit\n");
761 return true;
762 }
763
xhci_hub_check_ports(struct xhci_hcd * xhcd)764 static int xhci_hub_check_ports(struct xhci_hcd *xhcd)
765 {
766 return xhci_port_scan(xhcd, USB_XHCI) | xhci_port_scan(xhcd, USB_EHCI);
767 }
768
xhci_hcd_init(struct xhci_hcd * xhcd)769 static bool xhci_hcd_init(struct xhci_hcd *xhcd)
770 {
771 struct xhci_op_regs *op;
772 struct xhci_int_regs *irs;
773 uint64_t val;
774 uint32_t reg;
775
776 if (!xhcd) {
777 dprintf("NULL pointer\n");
778 goto fail;
779 }
780
781 op = xhcd->op_regs;
782 irs = &xhcd->run_regs->irs[0];
783 if (!xhci_hcd_reset(op)) {
784 dprintf("Reset failed\n");
785 goto fail;
786 }
787
788 write_reg32(&op->config, XHCI_CONFIG_MAX_SLOT);
789 reg = read_reg32(&xhcd->cap_regs->hccparams);
790 /* 64byte context !! */
791 xhcd->hcc_csz_64 = (reg & XHCI_HCCPARAMS_CSZ) ? 1 : 0;
792
793 if (xhcd->hcc_csz_64) {
794 printf("usb-xhci: 64 Byte context not supported\n");
795 goto fail;
796 }
797 /*
798 * 6.1 Device Context Base Address Array
799 *
800 * Allocate memory and initialize
801 */
802 xhcd->dcbaap = (uint64_t *)SLOF_dma_alloc(XHCI_DCBAAP_MAX_SIZE);
803 if (!xhcd->dcbaap) {
804 dprintf("Alloc failed\n");
805 goto fail;
806 }
807 memset((void *)xhcd->dcbaap, 0, XHCI_DCBAAP_MAX_SIZE);
808 xhcd->dcbaap_dma = SLOF_dma_map_in((void *)xhcd->dcbaap,
809 XHCI_DCBAAP_MAX_SIZE, false);
810 dprintf("dcbaap %llx, dcbaap_phys %llx\n", xhcd->dcbaap, xhcd->dcbaap_dma);
811 write_reg64(&op->dcbaap, xhcd->dcbaap_dma);
812
813 /*
814 * Command Ring Control - TRB
815 * FIXME - better way to allocate it...
816 */
817 if (!xhci_alloc_seg(&xhcd->crseg, XHCI_CRCR_CRP_SIZE, TYPE_COMMAND))
818 goto fail_dcbaap;
819
820 val = read_reg64(&op->crcr) & ~XHCI_CRCR_CRP_MASK;
821 val = val | (xhcd->crseg.trbs_dma & XHCI_CRCR_CRP_MASK);
822 write_reg64(&op->crcr, val);
823
824 /*
825 * Event Ring Control - TRB
826 * Allocate event TRBS
827 */
828 if (!xhci_alloc_seg(&xhcd->ering, XHCI_EVENT_TRBS_SIZE, TYPE_EVENT))
829 goto fail_crseg;
830
831 /*
832 * Populate event ring segment table.
833 * Note: only using one segment.
834 */
835 xhcd->erst.entries = SLOF_dma_alloc(XHCI_EVENT_TRBS_SIZE);
836 if (!xhcd->erst.entries)
837 goto fail_ering;
838 xhcd->erst.dma = SLOF_dma_map_in((void *)xhcd->erst.entries,
839 XHCI_EVENT_TRBS_SIZE, false);
840 xhcd->erst.num_segs = XHCI_ERST_NUM_SEGS;
841
842 /* populate entries[0] */
843 write_reg64(&xhcd->erst.entries->addr, xhcd->ering.trbs_dma);
844 write_reg32(&xhcd->erst.entries->size, xhcd->ering.size);
845 write_reg32(&xhcd->erst.entries->reserved, 0);
846
847 /* populate erdp */
848 val = read_reg64(&irs->erdp) & ~XHCI_ERDP_MASK;
849 val = val | (xhcd->ering.trbs_dma & XHCI_ERDP_MASK);
850 write_reg64(&irs->erdp, val);
851
852 /* populate erstsz */
853 val = read_reg32(&irs->erstsz) & ~XHCI_ERST_SIZE_MASK;
854 val = val | xhcd->erst.num_segs;
855 write_reg32(&irs->erstsz, val);
856
857 /* Now write the erstba */
858 val = read_reg64(&irs->erstba) & ~XHCI_ERST_ADDR_MASK;
859 val = val | (xhcd->erst.dma & XHCI_ERST_ADDR_MASK);
860 write_reg64(&irs->erstba, val);
861
862 dprintf("ERDP %llx TRB-DMA %llx\n", read_reg64(&irs->erdp),
863 xhcd->ering.trbs_dma);
864 dprintf("ERST %llx, ERST DMA %llx, size %d\n",
865 (uint64_t)xhcd->erst.entries, xhcd->erst.dma,
866 xhcd->erst.num_segs);
867
868 mb();
869 if (!xhci_hcd_set_runstop(op, true))
870 goto fail_erst_entries;
871
872 if (!xhci_hub_check_ports(xhcd))
873 goto fail_erst_entries;
874
875 return true;
876 fail_erst_entries:
877 write_reg32(&irs->erstsz, 0);
878 write_reg64(&irs->erstba, 0);
879 mb();
880 SLOF_dma_map_out(xhcd->erst.dma, (void *)xhcd->erst.entries, XHCI_EVENT_TRBS_SIZE);
881 SLOF_dma_free((void *)xhcd->erst.entries, XHCI_EVENT_TRBS_SIZE);
882 fail_ering:
883 xhci_free_seg(&xhcd->ering, XHCI_EVENT_TRBS_SIZE);
884 fail_crseg:
885 val = read_reg64(&op->crcr) & ~XHCI_CRCR_CRP_MASK;
886 write_reg64(&op->crcr, val);
887 mb();
888 xhci_free_seg(&xhcd->crseg, XHCI_CRCR_CRP_SIZE);
889 fail_dcbaap:
890 write_reg64(&op->dcbaap, 0);
891 mb();
892 SLOF_dma_map_out(xhcd->dcbaap_dma, (void *)xhcd->dcbaap, XHCI_DCBAAP_MAX_SIZE);
893 SLOF_dma_free((void *)xhcd->dcbaap, XHCI_DCBAAP_MAX_SIZE);
894 fail:
895 return false;
896 }
897
xhci_hcd_exit(struct xhci_hcd * xhcd)898 static bool xhci_hcd_exit(struct xhci_hcd *xhcd)
899 {
900 struct xhci_op_regs *op;
901 struct xhci_int_regs *irs;
902 uint64_t val;
903 int i;
904
905 if (!xhcd) {
906 dprintf("NULL pointer\n");
907 return false;
908 }
909 op = xhcd->op_regs;
910
911 if (!xhci_hcd_set_runstop(op, false)) {
912 dprintf("NULL pointer\n");
913 }
914
915 for (i = 1; i < XHCI_CONFIG_MAX_SLOT; i++) {
916 if (xhcd->xdevs[i].dev)
917 xhci_free_dev(&xhcd->xdevs[i]);
918 }
919
920 irs = &xhcd->run_regs->irs[0];
921 write_reg32(&irs->erstsz, 0);
922 write_reg64(&irs->erstba, 0);
923 mb();
924 if (xhcd->erst.entries) {
925 SLOF_dma_map_out(xhcd->erst.dma, xhcd->erst.entries, XHCI_EVENT_TRBS_SIZE);
926 SLOF_dma_free(xhcd->erst.entries, XHCI_EVENT_TRBS_SIZE);
927 }
928 xhci_free_seg(&xhcd->ering, XHCI_EVENT_TRBS_SIZE);
929
930 val = read_reg64(&op->crcr) & ~XHCI_CRCR_CRP_MASK;
931 write_reg64(&op->crcr, val);
932 xhci_free_seg(&xhcd->crseg, XHCI_CRCR_CRP_SIZE);
933 write_reg64(&op->dcbaap, 0);
934 if (xhcd->dcbaap) {
935 SLOF_dma_map_out(xhcd->dcbaap_dma, (void *)xhcd->dcbaap, XHCI_DCBAAP_MAX_SIZE);
936 SLOF_dma_free((void *)xhcd->dcbaap, XHCI_DCBAAP_MAX_SIZE);
937 }
938
939 /*
940 * QEMU implementation of XHCI doesn't implement halt
941 * properly. It basically says that it's halted immediately
942 * but doesn't actually terminate ongoing activities and
943 * DMAs. This needs to be fixed in QEMU.
944 *
945 * For now, wait for 50ms grace time till qemu stops using
946 * this device.
947 */
948 SLOF_msleep(50);
949
950 return true;
951 }
952
xhci_init(struct usb_hcd_dev * hcidev)953 static void xhci_init(struct usb_hcd_dev *hcidev)
954 {
955 struct xhci_hcd *xhcd;
956
957 printf(" XHCI: Initializing\n");
958 dprintf("device base address %p\n", hcidev->base);
959
960 hcidev->base = (void *)((uint64_t)hcidev->base & ~7);
961 xhcd = SLOF_alloc_mem(sizeof(*xhcd));
962 if (!xhcd) {
963 printf("usb-xhci: Unable to allocate memory\n");
964 return;
965 }
966 memset(xhcd, 0, sizeof(*xhcd));
967
968 hcidev->nextaddr = 1;
969 hcidev->priv = xhcd;
970 xhcd->hcidev = hcidev;
971 xhcd->cap_regs = (struct xhci_cap_regs *)(hcidev->base);
972 xhcd->op_regs = (struct xhci_op_regs *)(hcidev->base +
973 read_reg8(&xhcd->cap_regs->caplength));
974 xhcd->run_regs = (struct xhci_run_regs *)(hcidev->base +
975 read_reg32(&xhcd->cap_regs->rtsoff));
976 xhcd->db_regs = (struct xhci_db_regs *)(hcidev->base +
977 read_reg32(&xhcd->cap_regs->dboff));
978 dump_xhci_regs(xhcd);
979 if (!xhci_hcd_init(xhcd))
980 printf("usb-xhci: failed to initialize XHCI controller.\n");
981 dump_xhci_regs(xhcd);
982 }
983
xhci_exit(struct usb_hcd_dev * hcidev)984 static void xhci_exit(struct usb_hcd_dev *hcidev)
985 {
986 struct xhci_hcd *xhcd;
987
988 dprintf("%s: enter \n", __func__);
989 if (!hcidev && !hcidev->priv) {
990 return;
991 }
992
993 xhcd = hcidev->priv;
994 xhci_hcd_exit(xhcd);
995 SLOF_free_mem(xhcd, sizeof(*xhcd));
996 hcidev->priv = NULL;
997 }
998
fill_trb_buff(struct xhci_command_trb * cmd,uint32_t field1,uint32_t field2,uint32_t field3,uint32_t field4)999 static void fill_trb_buff(struct xhci_command_trb *cmd, uint32_t field1,
1000 uint32_t field2, uint32_t field3, uint32_t field4)
1001 {
1002 uint32_t val, cycle_state;
1003
1004 cmd->field[0] = cpu_to_le32(field1);
1005 cmd->field[1] = cpu_to_le32(field2);
1006 cmd->field[2] = cpu_to_le32(field3);
1007
1008 val = le32_to_cpu(cmd->field[3]);
1009 cycle_state = (val & 0x1) ? 0 : 1;
1010 val = cycle_state | (field4 & ~0x1);
1011 cmd->field[3] = cpu_to_le32(val);
1012 mb();
1013
1014 dprintf("CMD %016lx val %08x cycle_state %d field1 %08x, field2 %08x, field3 %08x field4 %08x\n",
1015 cmd, val, cycle_state,
1016 le32_to_cpu(cmd->field[0]),
1017 le32_to_cpu(cmd->field[1]),
1018 le32_to_cpu(cmd->field[2]),
1019 le32_to_cpu(cmd->field[3])
1020 );
1021
1022 return;
1023 }
1024
fill_setup_trb(struct xhci_command_trb * cmd,struct usb_dev_req * req,uint32_t size)1025 static void fill_setup_trb(struct xhci_command_trb *cmd, struct usb_dev_req *req,
1026 uint32_t size)
1027 {
1028 uint32_t field1, field2, field3, field4 = 0;
1029 uint64_t req_raw;
1030 uint32_t datalen = 0, pid = 0;
1031
1032 req_raw = *((uint64_t *)req);
1033 dprintf("%lx %lx \n", *((uint64_t *)req), req_raw);
1034 /* req_raw is already in right byte order... */
1035 field1 = cpu_to_le32(TRB_ADDR_HIGH(req_raw));
1036 field2 = cpu_to_le32(TRB_ADDR_LOW(req_raw));
1037 field3 = 8; /* ALWAYS 8 */
1038
1039 datalen = cpu_to_le16(req->wLength);
1040 if (datalen) {
1041 pid = (req->bmRequestType & REQT_DIR_IN) ? 3 : 2;
1042 field4 = TRB_TRT(pid);
1043 }
1044 field4 |= TRB_CMD_TYPE(TRB_SETUP_STAGE) | TRB_IDT;
1045 fill_trb_buff(cmd, field1, field2, field3, field4);
1046 }
1047
fill_setup_data(struct xhci_command_trb * cmd,void * data,uint32_t size,uint32_t dir)1048 static void fill_setup_data(struct xhci_command_trb *cmd, void *data,
1049 uint32_t size, uint32_t dir)
1050 {
1051 uint32_t field1, field2, field3, field4;
1052
1053 field1 = TRB_ADDR_LOW(data);
1054 field2 = TRB_ADDR_HIGH(data);
1055 field3 = size;
1056 field4 = TRB_CMD_TYPE(TRB_DATA_STAGE);
1057 if (dir)
1058 field4 |= TRB_DIR_IN;
1059 fill_trb_buff(cmd, field1, field2, field3, field4);
1060 }
1061
fill_status_trb(struct xhci_command_trb * cmd,uint32_t dir)1062 static void fill_status_trb(struct xhci_command_trb *cmd, uint32_t dir)
1063 {
1064 uint32_t field1, field2, field3, field4;
1065
1066 field1 = 0;
1067 field2 = 0;
1068 field3 = 0;
1069 field4 = TRB_CMD_TYPE(TRB_STATUS_STAGE) | TRB_IOC;
1070 if (dir)
1071 field4 |= TRB_DIR_IN;
1072 fill_trb_buff(cmd, field1, field2, field3, field4);
1073 }
1074
fill_normal_trb(struct xhci_transfer_trb * trb,void * data,uint32_t size)1075 static void fill_normal_trb(struct xhci_transfer_trb *trb, void *data,
1076 uint32_t size)
1077 {
1078 uint32_t field1, field2, field3, field4;
1079
1080 field1 = TRB_ADDR_LOW(data);
1081 field2 = TRB_ADDR_HIGH(data);
1082 field3 = size;
1083 field4 = TRB_CMD_TYPE(TRB_NORMAL) | TRB_IOC;
1084 fill_trb_buff((struct xhci_command_trb *)trb, field1, field2, field3, field4);
1085 }
1086
xhci_send_ctrl(struct usb_pipe * pipe,struct usb_dev_req * req,void * data)1087 static int xhci_send_ctrl(struct usb_pipe *pipe, struct usb_dev_req *req, void *data)
1088 {
1089 struct xhci_dev *xdev;
1090 struct xhci_seg *ctrl;
1091 struct xhci_hcd *xhcd;
1092 struct xhci_command_trb *cmd;
1093 struct xhci_db_regs *dbr;
1094 long req_phys = 0, data_phys = 0;
1095 int ret = true;
1096 uint32_t slot_id, pid = 0, datalen = 0;
1097
1098 if (!pipe->dev || !pipe->dev->hcidev) {
1099 dprintf(" NULL pointer\n");
1100 return false;
1101 }
1102
1103 xdev = pipe->dev->priv;
1104 slot_id = xdev->slot_id;
1105 ctrl = &xdev->control;
1106 xhcd = (struct xhci_hcd *)pipe->dev->hcidev->priv;
1107 dbr = xhcd->db_regs;
1108 if (!ctrl || !xdev || !xhcd) {
1109 dprintf(" NULL pointer\n");
1110 return false;
1111 }
1112
1113 cmd = (struct xhci_command_trb *)ctrl->enq;
1114 req_phys = SLOF_dma_map_in(req, sizeof(struct usb_dev_req), true);
1115 fill_setup_trb(cmd, req, sizeof(*req));
1116
1117 cmd++;
1118 datalen = cpu_to_le16(req->wLength);
1119 if (datalen)
1120 pid = 1;
1121 if (datalen) {
1122 data_phys = SLOF_dma_map_in(data, datalen, true);
1123 fill_setup_data(cmd, (void *) data_phys, datalen, pid);
1124 cmd++;
1125 }
1126
1127 fill_status_trb(cmd, pid);
1128 cmd++;
1129
1130 /* Ring the doorbell - ep0 */
1131 write_reg32(&dbr->db[slot_id], 1);
1132 if (!xhci_poll_event(xhcd, 0)) {
1133 dprintf("Command failed\n");
1134 ret = false;
1135 }
1136 ctrl->enq = (uint64_t) cmd;
1137 SLOF_dma_map_out(req_phys, req, sizeof(struct usb_dev_req));
1138 if (datalen)
1139 SLOF_dma_map_out(data_phys, data, datalen);
1140 return ret;
1141 }
1142
xhci_pipe_get_xpipe(struct usb_pipe * pipe)1143 static inline struct xhci_pipe *xhci_pipe_get_xpipe(struct usb_pipe *pipe)
1144 {
1145 struct xhci_pipe *xpipe;
1146 xpipe = container_of(pipe, struct xhci_pipe, pipe);
1147 dprintf("%s: xpipe is %p\n", __func__, xpipe);
1148 return xpipe;
1149 }
1150
xhci_pipe_get_seg(struct usb_pipe * pipe)1151 static inline struct xhci_seg *xhci_pipe_get_seg(struct usb_pipe *pipe)
1152 {
1153 struct xhci_pipe *xpipe;
1154 xpipe = xhci_pipe_get_xpipe(pipe);
1155 return xpipe->seg;
1156 }
1157
xhci_get_trb(struct xhci_seg * seg)1158 static inline void *xhci_get_trb(struct xhci_seg *seg)
1159 {
1160 uint64_t val, enq;
1161 unsigned index;
1162 struct xhci_link_trb *link;
1163
1164 enq = val = seg->enq;
1165 val = val + XHCI_TRB_SIZE;
1166 index = (enq - (uint64_t)seg->trbs) / XHCI_TRB_SIZE + 1;
1167 dprintf("%s: enq %llx, val %llx %x\n", __func__, enq, val, index);
1168 /* TRBs being a cyclic buffer, here we cycle back to beginning. */
1169 if (index == (seg->size - 1)) {
1170 dprintf("%s: rounding \n", __func__);
1171 seg->enq = (uint64_t)seg->trbs;
1172 seg->cycle_state ^= seg->cycle_state;
1173 link = (struct xhci_link_trb *) (seg->trbs + seg->size - 1);
1174 link->addr = cpu_to_le64(seg->trbs_dma);
1175 link->field2 = 0;
1176 link->field3 = cpu_to_le32(0x1 | TRB_CMD_TYPE(TRB_LINK));
1177 mb();
1178 }
1179 else {
1180 seg->enq = seg->enq + XHCI_TRB_SIZE;
1181 }
1182
1183 return (void *)enq;
1184 }
1185
xhci_get_trb_deq(struct xhci_seg * seg)1186 static inline void *xhci_get_trb_deq(struct xhci_seg *seg)
1187 {
1188 uint64_t deq_next, deq;
1189 unsigned index;
1190
1191 deq = seg->deq;
1192 deq_next = deq + XHCI_TRB_SIZE;
1193 index = (deq - (uint64_t)seg->trbs) / XHCI_TRB_SIZE + 1;
1194 dprintf("%s: deq %llx, deq_next %llx index %x\n", __func__, deq, deq_next, index);
1195 /* TRBs being a cyclic buffer, here we cycle back to beginning. */
1196 if (index == (seg->size - 1)) {
1197 dprintf("%s: rounding \n", __func__);
1198 seg->deq = (uint64_t)seg->trbs;
1199 }
1200 else {
1201 seg->deq = deq_next;
1202 }
1203 return (void *)deq;
1204 }
1205
xhci_get_trb_phys(struct xhci_seg * seg,uint64_t trb)1206 static uint64_t xhci_get_trb_phys(struct xhci_seg *seg, uint64_t trb)
1207 {
1208 return seg->trbs_dma + (trb - (uint64_t)seg->trbs);
1209 }
1210
xhci_trb_get_index(struct xhci_seg * seg,struct xhci_transfer_trb * trb)1211 static uint32_t xhci_trb_get_index(struct xhci_seg *seg, struct xhci_transfer_trb *trb)
1212 {
1213 return trb - (struct xhci_transfer_trb *)seg->trbs;
1214 }
1215
1216 static int usb_kb = false;
xhci_transfer_bulk(struct usb_pipe * pipe,void * td,void * td_phys,void * data,int datalen)1217 static int xhci_transfer_bulk(struct usb_pipe *pipe, void *td, void *td_phys,
1218 void *data, int datalen)
1219 {
1220 struct xhci_dev *xdev;
1221 struct xhci_seg *seg;
1222 struct xhci_hcd *xhcd;
1223 struct xhci_transfer_trb *trb;
1224 struct xhci_db_regs *dbr;
1225 int ret = true;
1226 uint32_t slot_id, epno, time;
1227 uint64_t trb_phys, event_phys;
1228
1229 if (!pipe->dev || !pipe->dev->hcidev) {
1230 dprintf(" NULL pointer\n");
1231 dprintf(" pipe dev %p hcidev %p\n", pipe->dev, pipe->dev->hcidev);
1232 return false;
1233 }
1234
1235 xdev = pipe->dev->priv;
1236 slot_id = xdev->slot_id;
1237 seg = xhci_pipe_get_seg(pipe);
1238 xhcd = (struct xhci_hcd *)pipe->dev->hcidev->priv;
1239 dbr = xhcd->db_regs;
1240 if (!seg || !xdev || !xhcd) {
1241 dprintf(" NULL pointer\n");
1242 dprintf(" seg %p xdev %p xhcd %p\n", seg, xdev, xhcd);
1243 return false;
1244 }
1245
1246 if (datalen > XHCI_MAX_BULK_SIZE) {
1247 printf("usb-xhci: bulk transfer size too big\n");
1248 return false;
1249 }
1250
1251 trb = xhci_get_trb(seg);
1252 trb_phys = xhci_get_trb_phys(seg, (uint64_t)trb);
1253 fill_normal_trb(trb, (void *)data, datalen);
1254
1255 epno = xhci_get_epno(pipe);
1256 write_reg32(&dbr->db[slot_id], epno);
1257
1258 time = SLOF_GetTimer() + USB_TIMEOUT;
1259 while (1) {
1260 event_phys = xhci_poll_event(xhcd, 0);
1261 if (event_phys == trb_phys) {
1262 break;
1263 } else if (event_phys == 0) { /* polling timed out */
1264 ret = false;
1265 break;
1266 } else
1267 usb_kb = true;
1268
1269 /* transfer timed out */
1270 if (time < SLOF_GetTimer())
1271 return false;
1272 }
1273 trb->addr = 0;
1274 trb->len = 0;
1275 trb->flags = 0;
1276 mb();
1277
1278 return ret;
1279 }
1280
xhci_alloc_pipe_pool(struct xhci_hcd * xhcd)1281 static int xhci_alloc_pipe_pool(struct xhci_hcd *xhcd)
1282 {
1283 struct xhci_pipe *xpipe, *curr, *prev;
1284 unsigned int i, count;
1285 long xpipe_phys = 0;
1286
1287 count = XHCI_PIPE_POOL_SIZE/sizeof(*xpipe);
1288 xhcd->pool = xpipe = SLOF_dma_alloc(XHCI_PIPE_POOL_SIZE);
1289 if (!xpipe)
1290 return -1;
1291 xhcd->pool_phys = xpipe_phys = SLOF_dma_map_in(xpipe, XHCI_PIPE_POOL_SIZE, true);
1292 dprintf("%s: xpipe %p, xpipe_phys %lx\n", __func__, xpipe, xpipe_phys);
1293
1294 /* Although an array, link them */
1295 for (i = 0, curr = xpipe, prev = NULL; i < count; i++, curr++) {
1296 if (prev)
1297 prev->pipe.next = &curr->pipe;
1298 curr->pipe.next = NULL;
1299 prev = curr;
1300 }
1301
1302 if (!xhcd->freelist)
1303 xhcd->freelist = &xpipe->pipe;
1304 else
1305 xhcd->end->next = &xpipe->pipe;
1306 xhcd->end = &prev->pipe;
1307
1308 return 0;
1309 }
1310
xhci_init_bulk_ep(struct usb_dev * dev,struct usb_pipe * pipe)1311 static void xhci_init_bulk_ep(struct usb_dev *dev, struct usb_pipe *pipe)
1312 {
1313 struct xhci_hcd *xhcd;
1314 struct xhci_dev *xdev;
1315 struct xhci_seg *seg;
1316 struct xhci_pipe *xpipe;
1317 struct xhci_control_ctx *ctrl;
1318 struct xhci_ep_ctx *ep;
1319 uint32_t x_epno, val, type;
1320
1321 if (!pipe || !dev || !dev->priv)
1322 return;
1323
1324 xdev = dev->priv;
1325 xhcd = dev->hcidev->priv;
1326 dprintf("dir %d\n", pipe->dir);
1327 seg = xhci_pipe_get_seg(pipe);
1328 xpipe = xhci_pipe_get_xpipe(pipe);
1329 if (pipe->dir) {
1330 type = EP_BULK_IN;
1331 seg = &xdev->bulk_in;
1332 }
1333 else {
1334 type = EP_BULK_OUT;
1335 seg = &xdev->bulk_out;
1336 }
1337
1338 if (!seg->trbs) {
1339 if (!xhci_alloc_seg(seg, XHCI_DATA_TRBS_SIZE, TYPE_BULK)) {
1340 printf("usb-xhci: allocation failed for bulk endpoint\n");
1341 return;
1342 }
1343 } else {
1344 xhci_init_seg(seg, XHCI_DATA_TRBS_SIZE, TYPE_BULK);
1345 }
1346
1347 pipe->mps = XHCI_MAX_BULK_SIZE;
1348 ctrl = xhci_get_control_ctx(&xdev->in_ctx);
1349 x_epno = xhci_get_epno(pipe);
1350 ep = xhci_get_ep_ctx(&xdev->in_ctx, xdev->ctx_size, x_epno);
1351 val = EP_TYPE(type) | MAX_BURST(0) | ERROR_COUNT(3) |
1352 MAX_PACKET_SIZE(pipe->mps);
1353 ep->field2 = cpu_to_le32(val);;
1354 ep->deq_addr = cpu_to_le64(seg->trbs_dma | seg->cycle_state);
1355 ep->field4 = cpu_to_le32(8);
1356 ctrl->a_flags = cpu_to_le32(BIT(x_epno) | 0x1);
1357 ctrl->d_flags = 0;
1358 xhci_configure_ep(xhcd, xdev->slot_id, xdev->in_ctx.dma_addr);
1359 xpipe->seg = seg;
1360 }
1361
xhci_get_pipe_intr(struct usb_pipe * pipe,struct xhci_hcd * xhcd,char * buf,size_t len)1362 static int xhci_get_pipe_intr(struct usb_pipe *pipe,
1363 struct xhci_hcd *xhcd,
1364 char *buf, size_t len)
1365 {
1366 struct xhci_dev *xdev;
1367 struct xhci_seg *seg;
1368 struct xhci_pipe *xpipe;
1369 struct xhci_control_ctx *ctrl;
1370 struct xhci_ep_ctx *ep;
1371 uint32_t x_epno, val, type;
1372 struct usb_dev *dev;
1373 struct xhci_transfer_trb *trb;
1374
1375 dev = pipe->dev;
1376 if (dev->class != DEV_HID_KEYB)
1377 return false;
1378
1379 xdev = dev->priv;
1380 pipe->mps = 8;
1381 seg = xhci_pipe_get_seg(pipe);
1382 xpipe = xhci_pipe_get_xpipe(pipe);
1383 type = EP_INT_IN;
1384 seg = &xdev->intr;
1385
1386 if (!seg->trbs) {
1387 if (!xhci_alloc_seg(seg, XHCI_INTR_TRBS_SIZE, TYPE_BULK)) {
1388 printf("usb-xhci: allocation failed for interrupt endpoint\n");
1389 return false;
1390 }
1391 } else {
1392 xhci_init_seg(seg, XHCI_EVENT_TRBS_SIZE, TYPE_BULK);
1393 }
1394
1395 xpipe->buflen = pipe->mps * XHCI_INTR_TRBS_SIZE/(sizeof(struct xhci_transfer_trb));
1396 xpipe->buf = SLOF_dma_alloc(xpipe->buflen);
1397 xpipe->buf_phys = SLOF_dma_map_in(xpipe->buf, xpipe->buflen, false);
1398
1399 ctrl = xhci_get_control_ctx(&xdev->in_ctx);
1400 x_epno = xhci_get_epno(pipe);
1401 ep = xhci_get_ep_ctx(&xdev->in_ctx, xdev->ctx_size, x_epno);
1402 val = EP_TYPE(type) | MAX_BURST(0) | ERROR_COUNT(3) |
1403 MAX_PACKET_SIZE(pipe->mps);
1404 ep->field2 = cpu_to_le32(val);
1405 ep->deq_addr = cpu_to_le64(seg->trbs_dma | seg->cycle_state);
1406 ep->field4 = cpu_to_le32(8);
1407 ctrl->a_flags = cpu_to_le32(BIT(x_epno) | 0x1);
1408 ctrl->d_flags = 0;
1409 xhci_configure_ep(xhcd, xdev->slot_id, xdev->in_ctx.dma_addr);
1410 xpipe->seg = seg;
1411
1412 trb = xhci_get_trb(seg);
1413 buf = (char *)(xpipe->buf_phys + xhci_trb_get_index(seg, trb) * pipe->mps);
1414 fill_normal_trb(trb, (void *)buf, pipe->mps);
1415 return true;
1416 }
1417
xhci_get_pipe(struct usb_dev * dev,struct usb_ep_descr * ep,char * buf,size_t len)1418 static struct usb_pipe* xhci_get_pipe(struct usb_dev *dev, struct usb_ep_descr *ep, char *buf, size_t len)
1419 {
1420 struct xhci_hcd *xhcd;
1421 struct usb_pipe *new = NULL;
1422
1423 if (!dev)
1424 return NULL;
1425
1426 xhcd = (struct xhci_hcd *)dev->hcidev->priv;
1427 if (!xhcd->freelist) {
1428 dprintf("usb-xhci: %s allocating pool\n", __func__);
1429 if (xhci_alloc_pipe_pool(xhcd))
1430 return NULL;
1431 }
1432
1433 new = xhcd->freelist;
1434 xhcd->freelist = xhcd->freelist->next;
1435 if (!xhcd->freelist)
1436 xhcd->end = NULL;
1437
1438 memset(new, 0, sizeof(*new));
1439 new->dev = dev;
1440 new->next = NULL;
1441 new->type = ep->bmAttributes & USB_EP_TYPE_MASK;
1442 new->speed = dev->speed;
1443 new->mps = ep->wMaxPacketSize;
1444 new->dir = (ep->bEndpointAddress & 0x80) >> 7;
1445 new->epno = ep->bEndpointAddress & 0x0f;
1446
1447 if (new->type == USB_EP_TYPE_INTR) {
1448 if (!xhci_get_pipe_intr(new, xhcd, buf, len)) {
1449 printf("usb-xhci: %s alloc_intr failed %p\n",
1450 __func__, new);
1451 }
1452 }
1453 if (new->type == USB_EP_TYPE_BULK)
1454 xhci_init_bulk_ep(dev, new);
1455
1456 return new;
1457 }
1458
xhci_put_pipe(struct usb_pipe * pipe)1459 static void xhci_put_pipe(struct usb_pipe *pipe)
1460 {
1461 struct xhci_hcd *xhcd;
1462 struct xhci_pipe *xpipe;
1463
1464 dprintf("usb-xhci: %s enter - %p\n", __func__, pipe);
1465 if (!pipe || !pipe->dev)
1466 return;
1467 xhcd = pipe->dev->hcidev->priv;
1468
1469 dprintf("dir %d\n", pipe->dir);
1470 if (pipe->type == USB_EP_TYPE_BULK) {
1471 xpipe = xhci_pipe_get_xpipe(pipe);
1472 xpipe->seg = NULL;
1473 } else if (pipe->type == USB_EP_TYPE_INTR) {
1474 xpipe = xhci_pipe_get_xpipe(pipe);
1475 SLOF_dma_map_out(xpipe->buf_phys, xpipe->buf, xpipe->buflen);
1476 SLOF_dma_free(xpipe->buf, xpipe->buflen);
1477 xpipe->seg = NULL;
1478 }
1479 if (xhcd->end)
1480 xhcd->end->next = pipe;
1481 else
1482 xhcd->freelist = pipe;
1483
1484 xhcd->end = pipe;
1485 pipe->next = NULL;
1486 pipe->dev = NULL;
1487 memset(pipe, 0, sizeof(*pipe));
1488
1489 dprintf("usb-xhci: %s exit\n", __func__);
1490 }
1491
xhci_poll_intr(struct usb_pipe * pipe,uint8_t * data)1492 static int xhci_poll_intr(struct usb_pipe *pipe, uint8_t *data)
1493 {
1494 struct xhci_transfer_trb *trb;
1495 struct xhci_seg *seg;
1496 struct xhci_pipe *xpipe;
1497 struct xhci_dev *xdev;
1498 struct xhci_hcd *xhcd;
1499 struct xhci_db_regs *dbr;
1500 uint32_t x_epno;
1501 uint8_t *buf, ret = 1;
1502
1503 if (!pipe || !pipe->dev || !pipe->dev->hcidev)
1504 return 0;
1505 xdev = pipe->dev->priv;
1506 xhcd = (struct xhci_hcd *)pipe->dev->hcidev->priv;
1507 x_epno = xhci_get_epno(pipe);
1508 seg = xhci_pipe_get_seg(pipe);
1509 xpipe = xhci_pipe_get_xpipe(pipe);
1510
1511 if (usb_kb == true) {
1512 /* This event was consumed by bulk transfer */
1513 usb_kb = false;
1514 xhci_get_trb_deq(seg);
1515 goto skip_poll;
1516 }
1517
1518 /* Ring the doorbell - x_epno */
1519 dbr = xhcd->db_regs;
1520 write_reg32(&dbr->db[xdev->slot_id], x_epno);
1521 if (!xhci_poll_event(xhcd, XHCI_POLL_NO_WAIT)) {
1522 return 0;
1523 }
1524 mb();
1525 trb = xhci_get_trb_deq(seg);
1526 buf = xpipe->buf + xhci_trb_get_index(seg, trb) * pipe->mps;
1527 memcpy(data, buf, 8);
1528 memset(buf, 0, 8);
1529
1530 skip_poll:
1531 trb = xhci_get_trb(seg);
1532 buf = (uint8_t *)(xpipe->buf_phys + xhci_trb_get_index(seg, trb) * pipe->mps);
1533 fill_normal_trb(trb, (void *)buf, pipe->mps);
1534 return ret;
1535 }
1536
1537 struct usb_hcd_ops xhci_ops = {
1538 .name = "xhci-hcd",
1539 .init = xhci_init,
1540 .exit = xhci_exit,
1541 .usb_type = USB_XHCI,
1542 .get_pipe = xhci_get_pipe,
1543 .put_pipe = xhci_put_pipe,
1544 .poll_intr = xhci_poll_intr,
1545 .send_ctrl = xhci_send_ctrl,
1546 .transfer_bulk = xhci_transfer_bulk,
1547 .next = NULL,
1548 };
1549
usb_xhci_register(void)1550 void usb_xhci_register(void)
1551 {
1552 usb_hcd_register(&xhci_ops);
1553 }
1554