1 /*
2 sis190.c: Silicon Integrated Systems SiS190 ethernet driver
3
4 Copyright (c) 2003 K.M. Liu <kmliu@sis.com>
5 Copyright (c) 2003, 2004 Jeff Garzik <jgarzik@pobox.com>
6 Copyright (c) 2003, 2004, 2005 Francois Romieu <romieu@fr.zoreil.com>
7
8 Modified for iPXE 2009 by Thomas Miletich <thomas.miletich@gmail.com>
9
10 Based on r8169.c, tg3.c, 8139cp.c, skge.c, epic100.c and SiS 190/191
11 genuine driver.
12
13 This software may be used and distributed according to the terms of
14 the GNU General Public License (GPL), incorporated herein by reference.
15 Drivers based on or derived from this code fall under the GPL and must
16 retain the authorship, copyright and license notice. This file is not
17 a complete program and may only be used when the entire operating
18 system is licensed under the GPL.
19
20 See the file COPYING in this distribution for more information.
21
22 */
23
24 FILE_LICENCE ( GPL_ANY );
25
26 #include "sis190.h"
27
28 static struct pci_device_id sis190_pci_tbl[] = {
29 PCI_ROM (0x1039, 0x0190, "sis190", "sis190", 0),
30 PCI_ROM (0x1039, 0x0191, "sis191", "sis191", 0),
31 };
32
33 /******************************************************************************
34 *************** HACK to keep ISA bridge in the PCI device list ***************
35 ******************************************************************************/
36
37 /* Some sis190 variants store the MAC address in the BIOS CMOS. To read it, we
38 * have to use a PCI to ISA bridge. To access the bridge we need a few things
39 * from it's struct pci_device. We fake the successful probe of a driver to
40 * keep the bridge's struct pci_device in the list of pci_devices.
41 * See details in sis190_get_mac_addr_from_apc().
42 */
43
44 static struct pci_device_id sis190_isa_bridge_tbl[] = {
45 PCI_ID (0x1039, 0x0965, "", "", 0),
46 PCI_ID (0x1039, 0x0966, "", "", 0),
47 PCI_ID (0x1039, 0x0968, "", "", 0),
48 };
49
sis190_isa_bridge_probe(struct pci_device * pdev __unused)50 static int sis190_isa_bridge_probe(struct pci_device *pdev __unused)
51 {
52 return 0;
53 }
54
sis190_isa_bridge_remove(struct pci_device * pdev __unused)55 static void sis190_isa_bridge_remove(struct pci_device *pdev __unused)
56 {
57 return;
58 }
59
60 struct pci_driver sis190_isa_bridge_driver __pci_driver = {
61 .ids = sis190_isa_bridge_tbl,
62 .id_count = (sizeof(sis190_isa_bridge_tbl) /
63 sizeof(sis190_isa_bridge_tbl[0])),
64 .probe = sis190_isa_bridge_probe,
65 .remove = sis190_isa_bridge_remove,
66 };
67
68 /******************************************************************************
69 *********************************** </HACK> **********************************
70 ******************************************************************************/
71
72 static const u32 sis190_intr_mask =
73 RxQEmpty | RxQInt | TxQ1Int | TxQ0Int | RxHalt | TxHalt | LinkChange;
74
__mdio_cmd(void * ioaddr,u32 ctl)75 static void __mdio_cmd(void *ioaddr, u32 ctl)
76 {
77 unsigned int i;
78
79 SIS_W32(GMIIControl, ctl);
80
81 mdelay(1);
82
83 for (i = 0; i < 100; i++) {
84 if (!(SIS_R32(GMIIControl) & EhnMIInotDone))
85 break;
86 mdelay(1);
87 }
88
89 if (i > 99)
90 DBG("sis190: PHY command timed out !\n");
91 }
92
mdio_write(void * ioaddr,int phy_id,int reg,int val)93 static void mdio_write(void *ioaddr, int phy_id, int reg, int val)
94 {
95 __mdio_cmd(ioaddr, EhnMIIreq | EhnMIIwrite |
96 (((u32) reg) << EhnMIIregShift) | (phy_id << EhnMIIpmdShift) |
97 (((u32) val) << EhnMIIdataShift));
98 }
99
mdio_read(void * ioaddr,int phy_id,int reg)100 static int mdio_read(void *ioaddr, int phy_id, int reg)
101 {
102 __mdio_cmd(ioaddr, EhnMIIreq | EhnMIIread |
103 (((u32) reg) << EhnMIIregShift) | (phy_id << EhnMIIpmdShift));
104
105 return (u16) (SIS_R32(GMIIControl) >> EhnMIIdataShift);
106 }
107
__mdio_write(struct net_device * dev,int phy_id,int reg,int val)108 static void __mdio_write(struct net_device *dev, int phy_id, int reg, int val)
109 {
110 struct sis190_private *tp = netdev_priv(dev);
111
112 mdio_write(tp->mmio_addr, phy_id, reg, val);
113 }
114
__mdio_read(struct net_device * dev,int phy_id,int reg)115 static int __mdio_read(struct net_device *dev, int phy_id, int reg)
116 {
117 struct sis190_private *tp = netdev_priv(dev);
118
119 return mdio_read(tp->mmio_addr, phy_id, reg);
120 }
121
mdio_read_latched(void * ioaddr,int phy_id,int reg)122 static u16 mdio_read_latched(void *ioaddr, int phy_id, int reg)
123 {
124 mdio_read(ioaddr, phy_id, reg);
125 return mdio_read(ioaddr, phy_id, reg);
126 }
127
sis190_read_eeprom(void * ioaddr,u32 reg)128 static u16 sis190_read_eeprom(void *ioaddr, u32 reg)
129 {
130 u16 data = 0xffff;
131 unsigned int i;
132
133 if (!(SIS_R32(ROMControl) & 0x0002))
134 return 0;
135
136 SIS_W32(ROMInterface, EEREQ | EEROP | (reg << 10));
137
138 for (i = 0; i < 200; i++) {
139 if (!(SIS_R32(ROMInterface) & EEREQ)) {
140 data = (SIS_R32(ROMInterface) & 0xffff0000) >> 16;
141 break;
142 }
143 mdelay(1);
144 }
145
146 return data;
147 }
148
sis190_irq_mask_and_ack(void * ioaddr)149 static void sis190_irq_mask_and_ack(void *ioaddr)
150 {
151 SIS_W32(IntrMask, 0x00);
152 SIS_W32(IntrStatus, 0xffffffff);
153 SIS_PCI_COMMIT();
154 }
155
sis190_asic_down(void * ioaddr)156 static void sis190_asic_down(void *ioaddr)
157 {
158 /* Stop the chip's Tx and Rx DMA processes. */
159
160 SIS_W32(TxControl, 0x1a00);
161 SIS_W32(RxControl, 0x1a00);
162
163 sis190_irq_mask_and_ack(ioaddr);
164 }
165
sis190_mark_as_last_descriptor(struct RxDesc * desc)166 static inline void sis190_mark_as_last_descriptor(struct RxDesc *desc)
167 {
168 desc->size |= cpu_to_le32(RingEnd);
169 }
170
sis190_give_to_asic(struct RxDesc * desc)171 static inline void sis190_give_to_asic(struct RxDesc *desc)
172 {
173 u32 eor = le32_to_cpu(desc->size) & RingEnd;
174
175 desc->PSize = 0x0;
176 desc->size = cpu_to_le32((RX_BUF_SIZE & RX_BUF_MASK) | eor);
177 wmb();
178 desc->status = cpu_to_le32(OWNbit | INTbit);
179 }
180
sis190_map_to_asic(struct RxDesc * desc,u32 mapping)181 static inline void sis190_map_to_asic(struct RxDesc *desc, u32 mapping)
182 {
183 desc->addr = cpu_to_le32(mapping);
184 sis190_give_to_asic(desc);
185 }
186
sis190_make_unusable_by_asic(struct RxDesc * desc)187 static inline void sis190_make_unusable_by_asic(struct RxDesc *desc)
188 {
189 desc->PSize = 0x0;
190 desc->addr = cpu_to_le32(0xdeadbeef);
191 desc->size &= cpu_to_le32(RingEnd);
192 wmb();
193 desc->status = 0x0;
194 }
195
sis190_alloc_rx_iob(struct RxDesc * desc)196 static struct io_buffer *sis190_alloc_rx_iob(struct RxDesc *desc)
197 {
198 struct io_buffer *iob;
199
200 iob = alloc_iob(RX_BUF_SIZE);
201 if (iob) {
202 u32 mapping;
203
204 mapping = virt_to_bus(iob->data);
205 sis190_map_to_asic(desc, mapping);
206 } else {
207 DBG("sis190: alloc_iob failed\n");
208 sis190_make_unusable_by_asic(desc);
209 }
210
211 return iob;
212 }
213
sis190_rx_fill(struct sis190_private * tp,u32 start,u32 end)214 static u32 sis190_rx_fill(struct sis190_private *tp, u32 start, u32 end)
215 {
216 u32 cur;
217
218 for (cur = start; cur < end; cur++) {
219 unsigned int i = cur % NUM_RX_DESC;
220
221 if (tp->Rx_iobuf[i])
222 continue;
223
224 tp->Rx_iobuf[i] = sis190_alloc_rx_iob(tp->RxDescRing + i);
225
226 if (!tp->Rx_iobuf[i])
227 break;
228 }
229 return cur - start;
230 }
231
sis190_rx_pkt_err(u32 status)232 static inline int sis190_rx_pkt_err(u32 status)
233 {
234 #define ErrMask (OVRUN | SHORT | LIMIT | MIIER | NIBON | COLON | ABORT)
235
236 if ((status & CRCOK) && !(status & ErrMask))
237 return 0;
238
239 return -1;
240 }
241
sis190_process_rx(struct sis190_private * tp)242 static int sis190_process_rx(struct sis190_private *tp)
243 {
244 u32 rx_left, cur_rx = tp->cur_rx;
245 u32 delta, count;
246
247 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
248
249 for (; rx_left > 0; rx_left--, cur_rx++) {
250 unsigned int entry = cur_rx % NUM_RX_DESC;
251 struct RxDesc *desc = tp->RxDescRing + entry;
252 u32 status;
253
254 if (le32_to_cpu(desc->status) & OWNbit)
255 break;
256
257 status = le32_to_cpu(desc->PSize);
258
259 if (sis190_rx_pkt_err(status) < 0) {
260 sis190_give_to_asic(desc);
261 } else {
262 struct io_buffer *iob = tp->Rx_iobuf[entry];
263 unsigned int pkt_size = (status & RxSizeMask) - 4;
264
265 if (pkt_size > RX_BUF_SIZE) {
266 DBG("sis190: (frag) status = %08x.\n", status);
267 sis190_give_to_asic(desc);
268 continue;
269 }
270
271 sis190_make_unusable_by_asic(desc);
272
273 iob_put(iob, pkt_size);
274
275 DBG2("sis190: received packet. len: %d\n", pkt_size);
276 netdev_rx(tp->dev, iob);
277 DBGIO_HD(iob->data, 60);
278 tp->Rx_iobuf[entry] = NULL;
279 }
280 }
281 count = cur_rx - tp->cur_rx;
282 tp->cur_rx = cur_rx;
283
284 delta = sis190_rx_fill(tp, tp->dirty_rx, tp->cur_rx);
285 if (!delta && count)
286 DBG("sis190: no Rx buffer allocated.\n");
287 tp->dirty_rx += delta;
288
289 if (((tp->dirty_rx + NUM_RX_DESC) == tp->cur_rx))
290 DBG("sis190: Rx buffers exhausted.\n");
291
292 return count;
293 }
294
sis190_tx_pkt_err(u32 status)295 static inline int sis190_tx_pkt_err(u32 status)
296 {
297 #define TxErrMask (WND | TABRT | FIFO | LINK)
298
299 if (!(status & TxErrMask))
300 return 0;
301
302 return -1;
303 }
304
sis190_process_tx(struct sis190_private * tp)305 static void sis190_process_tx(struct sis190_private *tp)
306 {
307 u32 pending, dirty_tx = tp->dirty_tx;
308
309 pending = tp->cur_tx - dirty_tx;
310
311 for (; pending; pending--, dirty_tx++) {
312 unsigned int entry = dirty_tx % NUM_TX_DESC;
313 struct TxDesc *txd = tp->TxDescRing + entry;
314 u32 status = le32_to_cpu(txd->status);
315 struct io_buffer *iob;
316
317 if (status & OWNbit)
318 break;
319
320 iob = tp->Tx_iobuf[entry];
321
322 if (!iob)
323 break;
324
325 if (sis190_tx_pkt_err(status) == 0) {
326 DBG2("sis190: Transmitted packet: %#08x\n", status);
327 netdev_tx_complete(tp->dev, iob);
328 } else {
329 DBG("sis190: Transmit error: %#08x\n", status);
330 netdev_tx_complete_err(tp->dev, iob, -EINVAL);
331 }
332
333 tp->Tx_iobuf[entry] = NULL;
334 }
335
336 if (tp->dirty_tx != dirty_tx)
337 tp->dirty_tx = dirty_tx;
338 }
339
340 /*
341 * The interrupt handler does all of the Rx thread work and cleans up after
342 * the Tx thread.
343 */
sis190_poll(struct net_device * dev)344 static void sis190_poll(struct net_device *dev)
345 {
346 struct sis190_private *tp = netdev_priv(dev);
347 void *ioaddr = tp->mmio_addr;
348 u32 status;
349
350 status = SIS_R32(IntrStatus);
351
352 if ((status == 0xffffffff) || !status)
353 return;
354
355 SIS_W32(IntrStatus, status);
356
357 /* sis190_phy_task() needs to be called in event of a LinkChange and
358 * after auto-negotiation is finished. Finishing auto-neg won't generate
359 * any indication, hence we call it every time if the link is bad. */
360 if ((status & LinkChange) || !netdev_link_ok(dev))
361 sis190_phy_task(tp);
362
363 if (status & RxQInt)
364 sis190_process_rx(tp);
365
366 if (status & TxQ0Int)
367 sis190_process_tx(tp);
368 }
369
sis190_init_ring_indexes(struct sis190_private * tp)370 static inline void sis190_init_ring_indexes(struct sis190_private *tp)
371 {
372 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
373 }
374
sis190_init_ring(struct net_device * dev)375 static int sis190_init_ring(struct net_device *dev)
376 {
377 struct sis190_private *tp = netdev_priv(dev);
378
379 sis190_init_ring_indexes(tp);
380
381 memset(tp->Tx_iobuf, 0, NUM_TX_DESC * sizeof(struct io_buffer *));
382 memset(tp->Rx_iobuf, 0, NUM_RX_DESC * sizeof(struct io_buffer *));
383
384 if (sis190_rx_fill(tp, 0, NUM_RX_DESC) != NUM_RX_DESC)
385 goto err;
386
387 sis190_mark_as_last_descriptor(tp->RxDescRing + NUM_RX_DESC - 1);
388
389 return 0;
390
391 err:
392 sis190_free(dev);
393 return -ENOMEM;
394 }
395
sis190_set_rx_mode(struct net_device * dev)396 static void sis190_set_rx_mode(struct net_device *dev)
397 {
398 struct sis190_private *tp = netdev_priv(dev);
399 void *ioaddr = tp->mmio_addr;
400 u32 mc_filter[2]; /* Multicast hash filter */
401 u16 rx_mode;
402
403 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
404 mc_filter[1] = mc_filter[0] = 0xffffffff;
405
406 SIS_W16(RxMacControl, rx_mode | 0x2);
407 SIS_W32(RxHashTable, mc_filter[0]);
408 SIS_W32(RxHashTable + 4, mc_filter[1]);
409
410 }
411
sis190_soft_reset(void * ioaddr)412 static void sis190_soft_reset(void *ioaddr)
413 {
414 SIS_W32(IntrControl, 0x8000);
415 SIS_PCI_COMMIT();
416 SIS_W32(IntrControl, 0x0);
417 sis190_asic_down(ioaddr);
418 }
419
sis190_hw_start(struct net_device * dev)420 static void sis190_hw_start(struct net_device *dev)
421 {
422 struct sis190_private *tp = netdev_priv(dev);
423 void *ioaddr = tp->mmio_addr;
424
425 sis190_soft_reset(ioaddr);
426
427 SIS_W32(TxDescStartAddr, tp->tx_dma);
428 SIS_W32(RxDescStartAddr, tp->rx_dma);
429
430 SIS_W32(IntrStatus, 0xffffffff);
431 SIS_W32(IntrMask, 0x0);
432 SIS_W32(GMIIControl, 0x0);
433 SIS_W32(TxMacControl, 0x60);
434 SIS_W16(RxMacControl, 0x02);
435 SIS_W32(RxHashTable, 0x0);
436 SIS_W32(0x6c, 0x0);
437 SIS_W32(RxWolCtrl, 0x0);
438 SIS_W32(RxWolData, 0x0);
439
440 SIS_PCI_COMMIT();
441
442 sis190_set_rx_mode(dev);
443
444 SIS_W32(TxControl, 0x1a00 | CmdTxEnb);
445 SIS_W32(RxControl, 0x1a1d);
446 }
447
sis190_phy_task(struct sis190_private * tp)448 static void sis190_phy_task(struct sis190_private *tp)
449 {
450 struct net_device *dev = tp->dev;
451 void *ioaddr = tp->mmio_addr;
452 int phy_id = tp->mii_if.phy_id;
453 int cnt = 0;
454 u16 val;
455
456 val = mdio_read(ioaddr, phy_id, MII_BMCR);
457
458 /* 100ms timeout is completely arbitrary. I have no datasheet to
459 * check whether that's a sensible value or not.
460 */
461 while ((val & BMCR_RESET) && (cnt < 100)) {
462 val = mdio_read(ioaddr, phy_id, MII_BMCR);
463 mdelay(1);
464 cnt++;
465 }
466
467 if (cnt > 99) {
468 DBG("sis190: BMCR_RESET timeout\n");
469 return;
470 }
471
472 if (!(mdio_read_latched(ioaddr, phy_id, MII_BMSR) &
473 BMSR_ANEGCOMPLETE)) {
474 DBG("sis190: auto-negotiating...\n");
475 netdev_link_down(dev);
476 } else {
477 /* Rejoice ! */
478 struct {
479 int val;
480 u32 ctl;
481 const char *msg;
482 } reg31[] = {
483 { LPA_1000FULL, 0x07000c00 | 0x00001000,
484 "1000 Mbps Full Duplex" },
485 { LPA_1000HALF, 0x07000c00,
486 "1000 Mbps Half Duplex" },
487 { LPA_100FULL, 0x04000800 | 0x00001000,
488 "100 Mbps Full Duplex" },
489 { LPA_100HALF, 0x04000800,
490 "100 Mbps Half Duplex" },
491 { LPA_10FULL, 0x04000400 | 0x00001000,
492 "10 Mbps Full Duplex" },
493 { LPA_10HALF, 0x04000400,
494 "10 Mbps Half Duplex" },
495 { 0, 0x04000400, "unknown" }
496 }, *p = NULL;
497 u16 adv, autoexp, gigadv, gigrec;
498
499 val = mdio_read(ioaddr, phy_id, 0x1f);
500
501 val = mdio_read(ioaddr, phy_id, MII_LPA);
502 adv = mdio_read(ioaddr, phy_id, MII_ADVERTISE);
503
504 autoexp = mdio_read(ioaddr, phy_id, MII_EXPANSION);
505
506 if (val & LPA_NPAGE && autoexp & EXPANSION_NWAY) {
507 /* check for gigabit speed */
508 gigadv = mdio_read(ioaddr, phy_id, MII_CTRL1000);
509 gigrec = mdio_read(ioaddr, phy_id, MII_STAT1000);
510 val = (gigadv & (gigrec >> 2));
511 if (val & ADVERTISE_1000FULL)
512 p = reg31;
513 else if (val & ADVERTISE_1000HALF)
514 p = reg31 + 1;
515 }
516
517 if (!p) {
518 val &= adv;
519
520 for (p = reg31; p->val; p++) {
521 if ((val & p->val) == p->val)
522 break;
523 }
524 }
525
526 p->ctl |= SIS_R32(StationControl) & ~0x0f001c00;
527
528 if ((tp->features & F_HAS_RGMII) &&
529 (tp->features & F_PHY_BCM5461)) {
530 // Set Tx Delay in RGMII mode.
531 mdio_write(ioaddr, phy_id, 0x18, 0xf1c7);
532 udelay(200);
533 mdio_write(ioaddr, phy_id, 0x1c, 0x8c00);
534 p->ctl |= 0x03000000;
535 }
536
537 SIS_W32(StationControl, p->ctl);
538
539 if (tp->features & F_HAS_RGMII) {
540 SIS_W32(RGDelay, 0x0441);
541 SIS_W32(RGDelay, 0x0440);
542 }
543
544 DBG("sis190: link on %s mode.\n", p->msg);
545 netdev_link_up(dev);
546 }
547 }
548
sis190_open(struct net_device * dev)549 static int sis190_open(struct net_device *dev)
550 {
551 struct sis190_private *tp = netdev_priv(dev);
552 int rc;
553
554 /* Allocate TX ring */
555 tp->TxDescRing = malloc_dma(TX_RING_BYTES, RING_ALIGNMENT);
556 if (!tp->TxDescRing) {
557 DBG("sis190: TX ring allocation failed\n");
558 rc = -ENOMEM;
559 goto out;
560 }
561 tp->tx_dma = cpu_to_le32(virt_to_bus(tp->TxDescRing));
562
563 /* Allocate RX ring */
564 tp->RxDescRing = malloc_dma(RX_RING_BYTES, RING_ALIGNMENT);
565 if (!tp->RxDescRing) {
566 DBG("sis190: RX ring allocation failed\n");
567 rc = -ENOMEM;
568 goto error;
569 }
570 tp->rx_dma = cpu_to_le32(virt_to_bus(tp->RxDescRing));
571
572 rc = sis190_init_ring(dev);
573 if (rc < 0)
574 goto error;
575
576 /* init rx filter, also program MAC address to card */
577 sis190_init_rxfilter(dev);
578
579 sis190_hw_start(dev);
580 out:
581 return rc;
582
583 error:
584 sis190_free(dev);
585 goto out;
586 }
587
sis190_down(struct net_device * dev)588 static void sis190_down(struct net_device *dev)
589 {
590 struct sis190_private *tp = netdev_priv(dev);
591 void *ioaddr = tp->mmio_addr;
592
593 do {
594 sis190_asic_down(ioaddr);
595 } while (SIS_R32(IntrMask));
596 }
597
sis190_free(struct net_device * dev)598 static void sis190_free(struct net_device *dev)
599 {
600 struct sis190_private *tp = netdev_priv(dev);
601 int i;
602
603 free_dma(tp->TxDescRing, TX_RING_BYTES);
604 free_dma(tp->RxDescRing, RX_RING_BYTES);
605
606 tp->TxDescRing = NULL;
607 tp->RxDescRing = NULL;
608
609 tp->tx_dma = 0;
610 tp->rx_dma = 0;
611
612 tp->cur_tx = tp->dirty_tx = 0;
613 tp->cur_rx = tp->dirty_rx = 0;
614
615 for (i = 0; i < NUM_RX_DESC; i++) {
616 free_iob(tp->Rx_iobuf[i]);
617 tp->Rx_iobuf[i] = NULL;
618 }
619
620 /* tx io_buffers aren't owned by the driver, so don't free them */
621 for(i = 0; i < NUM_TX_DESC; i++)
622 tp->Tx_iobuf[i] = NULL;
623 }
624
sis190_close(struct net_device * dev)625 static void sis190_close(struct net_device *dev)
626 {
627 sis190_down(dev);
628 sis190_free(dev);
629 }
630
sis190_transmit(struct net_device * dev,struct io_buffer * iob)631 static int sis190_transmit(struct net_device *dev, struct io_buffer *iob)
632 {
633 struct sis190_private *tp = netdev_priv(dev);
634 void *ioaddr = tp->mmio_addr;
635 u32 len, entry;
636 struct TxDesc *desc;
637
638 len = iob_len(iob);
639 if (len < ETH_ZLEN) {
640 iob_pad(iob, ETH_ZLEN);
641 len = ETH_ZLEN;
642 }
643
644 entry = tp->cur_tx % NUM_TX_DESC;
645 desc = tp->TxDescRing + entry;
646
647 if (le32_to_cpu(desc->status) & OWNbit) {
648 DBG("sis190: Tx Ring full\n");
649 return -EINVAL;
650 }
651
652 tp->Tx_iobuf[entry] = iob;
653
654 desc->PSize = cpu_to_le32(len);
655 desc->addr = cpu_to_le32(virt_to_bus(iob->data));
656
657 desc->size = cpu_to_le32(len);
658 if (entry == (NUM_TX_DESC - 1))
659 desc->size |= cpu_to_le32(RingEnd);
660
661 wmb();
662
663 desc->status = cpu_to_le32(OWNbit | INTbit | DEFbit | CRCbit | PADbit);
664
665 tp->cur_tx++;
666
667 SIS_W32(TxControl, 0x1a00 | CmdReset | CmdTxEnb);
668
669 return 0;
670 }
671
sis190_free_phy(struct list_head * first_phy)672 static void sis190_free_phy(struct list_head *first_phy)
673 {
674 struct sis190_phy *cur, *next;
675
676 list_for_each_entry_safe(cur, next, first_phy, list) {
677 free(cur);
678 }
679 }
680
681 /**
682 * sis190_default_phy - Select default PHY for sis190 mac.
683 * @dev: the net device to probe for
684 *
685 * Select first detected PHY with link as default.
686 * If no one is link on, select PHY whose types is HOME as default.
687 * If HOME doesn't exist, select LAN.
688 */
sis190_default_phy(struct sis190_private * tp)689 static u16 sis190_default_phy(struct sis190_private *tp)
690 {
691 struct sis190_phy *phy, *phy_home, *phy_default, *phy_lan;
692 struct mii_if_info *mii_if = &tp->mii_if;
693 void *ioaddr = tp->mmio_addr;
694 u16 status;
695
696 phy_home = phy_default = phy_lan = NULL;
697
698 list_for_each_entry(phy, &tp->first_phy, list) {
699 status = mdio_read_latched(ioaddr, phy->phy_id, MII_BMSR);
700
701 // Link ON & Not select default PHY & not ghost PHY.
702 if ((status & BMSR_LSTATUS) &&
703 !phy_default &&
704 (phy->type != UNKNOWN)) {
705 phy_default = phy;
706 } else {
707 status = mdio_read(ioaddr, phy->phy_id, MII_BMCR);
708 mdio_write(ioaddr, phy->phy_id, MII_BMCR,
709 status | BMCR_ANENABLE | BMCR_ISOLATE);
710 if (phy->type == HOME)
711 phy_home = phy;
712 else if (phy->type == LAN)
713 phy_lan = phy;
714 }
715 }
716
717 if (!phy_default) {
718 if (phy_home)
719 phy_default = phy_home;
720 else if (phy_lan)
721 phy_default = phy_lan;
722 else
723 phy_default = list_entry(&tp->first_phy,
724 struct sis190_phy, list);
725 }
726
727 if (mii_if->phy_id != phy_default->phy_id) {
728 mii_if->phy_id = phy_default->phy_id;
729 DBG("sis190: Using transceiver at address %d as default.\n",
730 mii_if->phy_id);
731 }
732
733 status = mdio_read(ioaddr, mii_if->phy_id, MII_BMCR);
734 status &= (~BMCR_ISOLATE);
735
736 mdio_write(ioaddr, mii_if->phy_id, MII_BMCR, status);
737 status = mdio_read_latched(ioaddr, mii_if->phy_id, MII_BMSR);
738
739 return status;
740 }
741
sis190_init_phy(struct sis190_private * tp,struct sis190_phy * phy,unsigned int phy_id,u16 mii_status)742 static void sis190_init_phy(struct sis190_private *tp,
743 struct sis190_phy *phy, unsigned int phy_id,
744 u16 mii_status)
745 {
746 void *ioaddr = tp->mmio_addr;
747 struct mii_chip_info *p;
748
749 INIT_LIST_HEAD(&phy->list);
750 phy->status = mii_status;
751 phy->phy_id = phy_id;
752
753 phy->id[0] = mdio_read(ioaddr, phy_id, MII_PHYSID1);
754 phy->id[1] = mdio_read(ioaddr, phy_id, MII_PHYSID2);
755
756 for (p = mii_chip_table; p->type; p++) {
757 if ((p->id[0] == phy->id[0]) &&
758 (p->id[1] == (phy->id[1] & 0xfff0))) {
759 break;
760 }
761 }
762
763 if (p->id[1]) {
764 phy->type = (p->type == MIX) ?
765 ((mii_status & (BMSR_100FULL | BMSR_100HALF)) ?
766 LAN : HOME) : p->type;
767 tp->features |= p->feature;
768
769 DBG("sis190: %s transceiver at address %d.\n", p->name, phy_id);
770 } else {
771 phy->type = UNKNOWN;
772
773 DBG("sis190: unknown PHY 0x%x:0x%x transceiver at address %d\n",
774 phy->id[0], (phy->id[1] & 0xfff0), phy_id);
775 }
776 }
777
sis190_mii_probe_88e1111_fixup(struct sis190_private * tp)778 static void sis190_mii_probe_88e1111_fixup(struct sis190_private *tp)
779 {
780 if (tp->features & F_PHY_88E1111) {
781 void *ioaddr = tp->mmio_addr;
782 int phy_id = tp->mii_if.phy_id;
783 u16 reg[2][2] = {
784 { 0x808b, 0x0ce1 },
785 { 0x808f, 0x0c60 }
786 }, *p;
787
788 p = (tp->features & F_HAS_RGMII) ? reg[0] : reg[1];
789
790 mdio_write(ioaddr, phy_id, 0x1b, p[0]);
791 udelay(200);
792 mdio_write(ioaddr, phy_id, 0x14, p[1]);
793 udelay(200);
794 }
795 }
796
797 /**
798 * sis190_mii_probe - Probe MII PHY for sis190
799 * @dev: the net device to probe for
800 *
801 * Search for total of 32 possible mii phy addresses.
802 * Identify and set current phy if found one,
803 * return error if it failed to found.
804 */
sis190_mii_probe(struct net_device * dev)805 static int sis190_mii_probe(struct net_device *dev)
806 {
807 struct sis190_private *tp = netdev_priv(dev);
808 struct mii_if_info *mii_if = &tp->mii_if;
809 void *ioaddr = tp->mmio_addr;
810 int phy_id;
811 int rc = 0;
812
813 INIT_LIST_HEAD(&tp->first_phy);
814
815 for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
816 struct sis190_phy *phy;
817 u16 status;
818
819 status = mdio_read_latched(ioaddr, phy_id, MII_BMSR);
820
821 // Try next mii if the current one is not accessible.
822 if (status == 0xffff || status == 0x0000)
823 continue;
824
825 phy = zalloc(sizeof(*phy));
826 if (!phy) {
827 sis190_free_phy(&tp->first_phy);
828 rc = -ENOMEM;
829 goto out;
830 }
831
832 DBG("sis190: found PHY\n");
833
834 sis190_init_phy(tp, phy, phy_id, status);
835
836 list_add(&tp->first_phy, &phy->list);
837 }
838
839 if (list_empty(&tp->first_phy)) {
840 DBG("sis190: No MII transceivers found!\n");
841 rc = -EIO;
842 goto out;
843 }
844
845 /* Select default PHY for mac */
846 sis190_default_phy(tp);
847
848 sis190_mii_probe_88e1111_fixup(tp);
849
850 mii_if->dev = dev;
851 mii_if->mdio_read = __mdio_read;
852 mii_if->mdio_write = __mdio_write;
853 mii_if->phy_id_mask = PHY_ID_ANY;
854 mii_if->reg_num_mask = MII_REG_ANY;
855 out:
856 return rc;
857 }
858
sis190_mii_remove(struct net_device * dev)859 static void sis190_mii_remove(struct net_device *dev)
860 {
861 struct sis190_private *tp = netdev_priv(dev);
862
863 sis190_free_phy(&tp->first_phy);
864 }
865
sis190_init_board(struct pci_device * pdev,struct net_device ** netdev)866 static int sis190_init_board(struct pci_device *pdev, struct net_device **netdev)
867 {
868 struct sis190_private *tp;
869 struct net_device *dev;
870 void *ioaddr;
871 int rc;
872
873 dev = alloc_etherdev(sizeof(*tp));
874 if (!dev) {
875 DBG("sis190: unable to alloc new etherdev\n");
876 rc = -ENOMEM;
877 goto err;
878 }
879
880 dev->dev = &pdev->dev;
881
882 tp = netdev_priv(dev);
883 memset(tp, 0, sizeof(*tp));
884
885 tp->dev = dev;
886
887 adjust_pci_device(pdev);
888
889 ioaddr = ioremap(pdev->membase, SIS190_REGS_SIZE);
890 if (!ioaddr) {
891 DBG("sis190: cannot remap MMIO, aborting\n");
892 rc = -EIO;
893 goto err;
894 }
895
896 tp->pci_device = pdev;
897 tp->mmio_addr = ioaddr;
898
899 sis190_irq_mask_and_ack(ioaddr);
900
901 sis190_soft_reset(ioaddr);
902
903 *netdev = dev;
904
905 return 0;
906
907 err:
908 return rc;
909 }
910
sis190_set_rgmii(struct sis190_private * tp,u8 reg)911 static void sis190_set_rgmii(struct sis190_private *tp, u8 reg)
912 {
913 tp->features |= (reg & 0x80) ? F_HAS_RGMII : 0;
914 }
915
sis190_get_mac_addr_from_eeprom(struct pci_device * pdev __unused,struct net_device * dev)916 static int sis190_get_mac_addr_from_eeprom(struct pci_device *pdev __unused,
917 struct net_device *dev)
918 {
919 struct sis190_private *tp = netdev_priv(dev);
920 void *ioaddr = tp->mmio_addr;
921 u16 sig;
922 int i;
923
924 DBG("sis190: Read MAC address from EEPROM\n");
925
926 /* Check to see if there is a sane EEPROM */
927 sig = (u16) sis190_read_eeprom(ioaddr, EEPROMSignature);
928
929 if ((sig == 0xffff) || (sig == 0x0000)) {
930 DBG("sis190: Error EEPROM read.\n");
931 return -EIO;
932 }
933
934 /* Get MAC address from EEPROM */
935 for (i = 0; i < ETH_ALEN / 2; i++) {
936 u16 w = sis190_read_eeprom(ioaddr, EEPROMMACAddr + i);
937
938 ((u16 *)dev->hw_addr)[i] = cpu_to_le16(w);
939 }
940
941 sis190_set_rgmii(tp, sis190_read_eeprom(ioaddr, EEPROMInfo));
942
943 return 0;
944 }
945
946 /**
947 * sis190_get_mac_addr_from_apc - Get MAC address for SiS96x model
948 * @pdev: PCI device
949 * @dev: network device to get address for
950 *
951 * SiS96x model, use APC CMOS RAM to store MAC address.
952 * APC CMOS RAM is accessed through ISA bridge.
953 * MAC address is read into @net_dev->dev_addr.
954 */
sis190_get_mac_addr_from_apc(struct pci_device * pdev,struct net_device * dev)955 static int sis190_get_mac_addr_from_apc(struct pci_device *pdev,
956 struct net_device *dev)
957 {
958 struct sis190_private *tp = netdev_priv(dev);
959 struct pci_device *isa_bridge = NULL;
960 struct device *d;
961 u8 reg, tmp8;
962 unsigned int i;
963
964 DBG("sis190: Read MAC address from APC.\n");
965
966 list_for_each_entry(d, &(pdev->dev.siblings), siblings) {
967 unsigned int i;
968 for(i = 0; i < sis190_isa_bridge_driver.id_count; i++) {
969 isa_bridge = container_of(d, struct pci_device, dev);
970 if(isa_bridge->vendor ==
971 sis190_isa_bridge_driver.ids[i].vendor
972 && isa_bridge->device ==
973 sis190_isa_bridge_driver.ids[i].device) {
974 DBG("sis190: ISA bridge found\n");
975 break;
976 } else {
977 isa_bridge = NULL;
978 }
979 }
980 if(isa_bridge)
981 break;
982 }
983
984 if (!isa_bridge) {
985 DBG("sis190: Can not find ISA bridge.\n");
986 return -EIO;
987 }
988
989 /* Enable port 78h & 79h to access APC Registers. */
990 pci_read_config_byte(isa_bridge, 0x48, &tmp8);
991 reg = (tmp8 & ~0x02);
992 pci_write_config_byte(isa_bridge, 0x48, reg);
993 udelay(50);
994 pci_read_config_byte(isa_bridge, 0x48, ®);
995
996 for (i = 0; i < ETH_ALEN; i++) {
997 outb(0x9 + i, 0x78);
998 dev->hw_addr[i] = inb(0x79);
999 }
1000
1001 outb(0x12, 0x78);
1002 reg = inb(0x79);
1003
1004 sis190_set_rgmii(tp, reg);
1005
1006 /* Restore the value to ISA Bridge */
1007 pci_write_config_byte(isa_bridge, 0x48, tmp8);
1008
1009 return 0;
1010 }
1011
1012 /**
1013 * sis190_init_rxfilter - Initialize the Rx filter
1014 * @dev: network device to initialize
1015 *
1016 * Set receive filter address to our MAC address
1017 * and enable packet filtering.
1018 */
sis190_init_rxfilter(struct net_device * dev)1019 static inline void sis190_init_rxfilter(struct net_device *dev)
1020 {
1021 struct sis190_private *tp = netdev_priv(dev);
1022 void *ioaddr = tp->mmio_addr;
1023 u16 ctl;
1024 int i;
1025
1026 ctl = SIS_R16(RxMacControl);
1027 /*
1028 * Disable packet filtering before setting filter.
1029 * Note: SiS's driver writes 32 bits but RxMacControl is 16 bits
1030 * only and followed by RxMacAddr (6 bytes). Strange. -- FR
1031 */
1032 SIS_W16(RxMacControl, ctl & ~0x0f00);
1033
1034 for (i = 0; i < ETH_ALEN; i++)
1035 SIS_W8(RxMacAddr + i, dev->ll_addr[i]);
1036
1037 SIS_W16(RxMacControl, ctl);
1038 SIS_PCI_COMMIT();
1039 }
1040
sis190_get_mac_addr(struct pci_device * pdev,struct net_device * dev)1041 static int sis190_get_mac_addr(struct pci_device *pdev,
1042 struct net_device *dev)
1043 {
1044 int rc;
1045
1046 rc = sis190_get_mac_addr_from_eeprom(pdev, dev);
1047 if (rc < 0) {
1048 u8 reg;
1049
1050 pci_read_config_byte(pdev, 0x73, ®);
1051
1052 if (reg & 0x00000001)
1053 rc = sis190_get_mac_addr_from_apc(pdev, dev);
1054 }
1055 return rc;
1056 }
1057
sis190_set_speed_auto(struct net_device * dev)1058 static void sis190_set_speed_auto(struct net_device *dev)
1059 {
1060 struct sis190_private *tp = netdev_priv(dev);
1061 void *ioaddr = tp->mmio_addr;
1062 int phy_id = tp->mii_if.phy_id;
1063 int val;
1064
1065 DBG("sis190: Enabling Auto-negotiation.\n");
1066
1067 val = mdio_read(ioaddr, phy_id, MII_ADVERTISE);
1068
1069 // Enable 10/100 Full/Half Mode, leave MII_ADVERTISE bit4:0
1070 // unchanged.
1071 mdio_write(ioaddr, phy_id, MII_ADVERTISE, (val & ADVERTISE_SLCT) |
1072 ADVERTISE_100FULL | ADVERTISE_10FULL |
1073 ADVERTISE_100HALF | ADVERTISE_10HALF);
1074
1075 // Enable 1000 Full Mode.
1076 mdio_write(ioaddr, phy_id, MII_CTRL1000, ADVERTISE_1000FULL);
1077
1078 // Enable auto-negotiation and restart auto-negotiation.
1079 mdio_write(ioaddr, phy_id, MII_BMCR,
1080 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET);
1081 }
1082
sis190_irq(struct net_device * dev,int enable)1083 static void sis190_irq(struct net_device *dev, int enable)
1084 {
1085 struct sis190_private *tp = netdev_priv(dev);
1086 void *ioaddr = tp->mmio_addr;
1087
1088 SIS_W32(IntrStatus, 0xffffffff);
1089
1090 if (enable == 0)
1091 SIS_W32(IntrMask, 0x00);
1092 else
1093 SIS_W32(IntrMask, sis190_intr_mask);
1094
1095 SIS_PCI_COMMIT();
1096 }
1097
1098 static struct net_device_operations sis190_netdev_ops = {
1099 .open = sis190_open,
1100 .close = sis190_close,
1101 .poll = sis190_poll,
1102 .transmit = sis190_transmit,
1103 .irq = sis190_irq,
1104 };
1105
sis190_probe(struct pci_device * pdev)1106 static int sis190_probe(struct pci_device *pdev)
1107 {
1108 struct sis190_private *tp;
1109 struct net_device *dev;
1110 int rc;
1111
1112 rc = sis190_init_board(pdev, &dev);
1113 if (rc < 0)
1114 goto out;
1115 netdev_init(dev, &sis190_netdev_ops);
1116
1117 pci_set_drvdata(pdev, dev);
1118
1119 tp = netdev_priv(dev);
1120
1121 rc = sis190_get_mac_addr(pdev, dev);
1122 if (rc < 0)
1123 goto err;
1124
1125 rc = sis190_mii_probe(dev);
1126 if (rc < 0)
1127 goto err;
1128
1129 rc = register_netdev(dev);
1130 if (rc < 0)
1131 goto err;
1132
1133 sis190_set_speed_auto(dev);
1134 sis190_phy_task(tp);
1135
1136 out:
1137 return rc;
1138
1139 err:
1140 sis190_mii_remove(dev);
1141 iounmap(tp->mmio_addr);
1142 goto out;
1143 }
1144
sis190_remove(struct pci_device * pdev)1145 static void sis190_remove(struct pci_device *pdev)
1146 {
1147 struct net_device *dev = pci_get_drvdata(pdev);
1148 struct sis190_private *tp = dev->priv;
1149 void *ioaddr = tp->mmio_addr;
1150
1151 sis190_mii_remove(dev);
1152
1153 /* shutdown chip, disable interrupts, etc */
1154 sis190_soft_reset(ioaddr);
1155
1156 iounmap(tp->mmio_addr);
1157
1158 unregister_netdev(dev);
1159 netdev_nullify(dev);
1160 netdev_put(dev);
1161 }
1162
1163 struct pci_driver sis190_pci_driver __pci_driver = {
1164 .ids = sis190_pci_tbl,
1165 .id_count = (sizeof(sis190_pci_tbl) / sizeof(sis190_pci_tbl[0])),
1166 .probe = sis190_probe,
1167 .remove = sis190_remove,
1168 };
1169