1 /* DO NOT EDIT THIS FILE 2 * Automatically generated by generate-cdef-headers.xsl 3 * DO NOT EDIT THIS FILE 4 */ 5 6 #ifndef __BFIN_CDEF_ADSP_EDN_DUAL_CORE_extended__ 7 #define __BFIN_CDEF_ADSP_EDN_DUAL_CORE_extended__ 8 9 #define pPLL_CTL ((uint16_t volatile *)PLL_CTL) 10 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 11 #define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) 12 #define pPLL_DIV ((uint16_t volatile *)PLL_DIV) 13 #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 14 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) 15 #define pVR_CTL ((uint16_t volatile *)VR_CTL) 16 #define bfin_read_VR_CTL() bfin_read16(VR_CTL) 17 #define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) 18 #define pPLL_STAT ((uint16_t volatile *)PLL_STAT) 19 #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 20 #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) 21 #define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) 22 #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) 23 #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) 24 #define pCHIPID ((uint32_t volatile *)CHIPID) 25 #define bfin_read_CHIPID() bfin_read32(CHIPID) 26 #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) 27 #define pSPI_CTL ((uint16_t volatile *)SPI_CTL) 28 #define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) 29 #define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val) 30 #define pSPI_FLG ((uint16_t volatile *)SPI_FLG) 31 #define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) 32 #define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val) 33 #define pSPI_STAT ((uint16_t volatile *)SPI_STAT) 34 #define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) 35 #define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val) 36 #define pSPI_TDBR ((uint16_t volatile *)SPI_TDBR) 37 #define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) 38 #define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val) 39 #define pSPI_RDBR ((uint16_t volatile *)SPI_RDBR) 40 #define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) 41 #define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val) 42 #define pSPI_BAUD ((uint16_t volatile *)SPI_BAUD) 43 #define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) 44 #define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val) 45 #define pSPI_SHADOW ((uint16_t volatile *)SPI_SHADOW) 46 #define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) 47 #define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val) 48 #define pWDOGA_CTL ((uint16_t volatile *)WDOGA_CTL) 49 #define bfin_read_WDOGA_CTL() bfin_read16(WDOGA_CTL) 50 #define bfin_write_WDOGA_CTL(val) bfin_write16(WDOGA_CTL, val) 51 #define pWDOGA_CNT ((uint32_t volatile *)WDOGA_CNT) 52 #define bfin_read_WDOGA_CNT() bfin_read32(WDOGA_CNT) 53 #define bfin_write_WDOGA_CNT(val) bfin_write32(WDOGA_CNT, val) 54 #define pWDOGA_STAT ((uint32_t volatile *)WDOGA_STAT) 55 #define bfin_read_WDOGA_STAT() bfin_read32(WDOGA_STAT) 56 #define bfin_write_WDOGA_STAT(val) bfin_write32(WDOGA_STAT, val) 57 #define pWDOGB_CTL ((uint16_t volatile *)WDOGB_CTL) 58 #define bfin_read_WDOGB_CTL() bfin_read16(WDOGB_CTL) 59 #define bfin_write_WDOGB_CTL(val) bfin_write16(WDOGB_CTL, val) 60 #define pWDOGB_CNT ((uint32_t volatile *)WDOGB_CNT) 61 #define bfin_read_WDOGB_CNT() bfin_read32(WDOGB_CNT) 62 #define bfin_write_WDOGB_CNT(val) bfin_write32(WDOGB_CNT, val) 63 #define pWDOGB_STAT ((uint32_t volatile *)WDOGB_STAT) 64 #define bfin_read_WDOGB_STAT() bfin_read32(WDOGB_STAT) 65 #define bfin_write_WDOGB_STAT(val) bfin_write32(WDOGB_STAT, val) 66 #define pDMA1_TC_PER ((uint16_t volatile *)DMA1_TC_PER) /* Traffic Control Periods */ 67 #define bfin_read_DMA1_TC_PER() bfin_read16(DMA1_TC_PER) 68 #define bfin_write_DMA1_TC_PER(val) bfin_write16(DMA1_TC_PER, val) 69 #define pDMA1_TC_CNT ((uint16_t volatile *)DMA1_TC_CNT) /* Traffic Control Current Counts */ 70 #define bfin_read_DMA1_TC_CNT() bfin_read16(DMA1_TC_CNT) 71 #define bfin_write_DMA1_TC_CNT(val) bfin_write16(DMA1_TC_CNT, val) 72 #define pDMA1_0_CONFIG ((uint16_t volatile *)DMA1_0_CONFIG) 73 #define bfin_read_DMA1_0_CONFIG() bfin_read16(DMA1_0_CONFIG) 74 #define bfin_write_DMA1_0_CONFIG(val) bfin_write16(DMA1_0_CONFIG, val) 75 #define pDMA1_0_NEXT_DESC_PTR ((void * volatile *)DMA1_0_NEXT_DESC_PTR) 76 #define bfin_read_DMA1_0_NEXT_DESC_PTR() bfin_readPTR(DMA1_0_NEXT_DESC_PTR) 77 #define bfin_write_DMA1_0_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_0_NEXT_DESC_PTR, val) 78 #define pDMA1_0_START_ADDR ((void * volatile *)DMA1_0_START_ADDR) 79 #define bfin_read_DMA1_0_START_ADDR() bfin_readPTR(DMA1_0_START_ADDR) 80 #define bfin_write_DMA1_0_START_ADDR(val) bfin_writePTR(DMA1_0_START_ADDR, val) 81 #define pDMA1_0_X_COUNT ((uint16_t volatile *)DMA1_0_X_COUNT) 82 #define bfin_read_DMA1_0_X_COUNT() bfin_read16(DMA1_0_X_COUNT) 83 #define bfin_write_DMA1_0_X_COUNT(val) bfin_write16(DMA1_0_X_COUNT, val) 84 #define pDMA1_0_Y_COUNT ((uint16_t volatile *)DMA1_0_Y_COUNT) 85 #define bfin_read_DMA1_0_Y_COUNT() bfin_read16(DMA1_0_Y_COUNT) 86 #define bfin_write_DMA1_0_Y_COUNT(val) bfin_write16(DMA1_0_Y_COUNT, val) 87 #define pDMA1_0_X_MODIFY ((uint16_t volatile *)DMA1_0_X_MODIFY) 88 #define bfin_read_DMA1_0_X_MODIFY() bfin_read16(DMA1_0_X_MODIFY) 89 #define bfin_write_DMA1_0_X_MODIFY(val) bfin_write16(DMA1_0_X_MODIFY, val) 90 #define pDMA1_0_Y_MODIFY ((uint16_t volatile *)DMA1_0_Y_MODIFY) 91 #define bfin_read_DMA1_0_Y_MODIFY() bfin_read16(DMA1_0_Y_MODIFY) 92 #define bfin_write_DMA1_0_Y_MODIFY(val) bfin_write16(DMA1_0_Y_MODIFY, val) 93 #define pDMA1_0_CURR_DESC_PTR ((void * volatile *)DMA1_0_CURR_DESC_PTR) 94 #define bfin_read_DMA1_0_CURR_DESC_PTR() bfin_readPTR(DMA1_0_CURR_DESC_PTR) 95 #define bfin_write_DMA1_0_CURR_DESC_PTR(val) bfin_writePTR(DMA1_0_CURR_DESC_PTR, val) 96 #define pDMA1_0_CURR_ADDR ((void * volatile *)DMA1_0_CURR_ADDR) 97 #define bfin_read_DMA1_0_CURR_ADDR() bfin_readPTR(DMA1_0_CURR_ADDR) 98 #define bfin_write_DMA1_0_CURR_ADDR(val) bfin_writePTR(DMA1_0_CURR_ADDR, val) 99 #define pDMA1_0_CURR_X_COUNT ((uint16_t volatile *)DMA1_0_CURR_X_COUNT) 100 #define bfin_read_DMA1_0_CURR_X_COUNT() bfin_read16(DMA1_0_CURR_X_COUNT) 101 #define bfin_write_DMA1_0_CURR_X_COUNT(val) bfin_write16(DMA1_0_CURR_X_COUNT, val) 102 #define pDMA1_0_CURR_Y_COUNT ((uint16_t volatile *)DMA1_0_CURR_Y_COUNT) 103 #define bfin_read_DMA1_0_CURR_Y_COUNT() bfin_read16(DMA1_0_CURR_Y_COUNT) 104 #define bfin_write_DMA1_0_CURR_Y_COUNT(val) bfin_write16(DMA1_0_CURR_Y_COUNT, val) 105 #define pDMA1_0_IRQ_STATUS ((uint16_t volatile *)DMA1_0_IRQ_STATUS) 106 #define bfin_read_DMA1_0_IRQ_STATUS() bfin_read16(DMA1_0_IRQ_STATUS) 107 #define bfin_write_DMA1_0_IRQ_STATUS(val) bfin_write16(DMA1_0_IRQ_STATUS, val) 108 #define pDMA1_0_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_0_PERIPHERAL_MAP) 109 #define bfin_read_DMA1_0_PERIPHERAL_MAP() bfin_read16(DMA1_0_PERIPHERAL_MAP) 110 #define bfin_write_DMA1_0_PERIPHERAL_MAP(val) bfin_write16(DMA1_0_PERIPHERAL_MAP, val) 111 #define pDMA1_1_CONFIG ((uint16_t volatile *)DMA1_1_CONFIG) 112 #define bfin_read_DMA1_1_CONFIG() bfin_read16(DMA1_1_CONFIG) 113 #define bfin_write_DMA1_1_CONFIG(val) bfin_write16(DMA1_1_CONFIG, val) 114 #define pDMA1_1_NEXT_DESC_PTR ((void * volatile *)DMA1_1_NEXT_DESC_PTR) 115 #define bfin_read_DMA1_1_NEXT_DESC_PTR() bfin_readPTR(DMA1_1_NEXT_DESC_PTR) 116 #define bfin_write_DMA1_1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_1_NEXT_DESC_PTR, val) 117 #define pDMA1_1_START_ADDR ((void * volatile *)DMA1_1_START_ADDR) 118 #define bfin_read_DMA1_1_START_ADDR() bfin_readPTR(DMA1_1_START_ADDR) 119 #define bfin_write_DMA1_1_START_ADDR(val) bfin_writePTR(DMA1_1_START_ADDR, val) 120 #define pDMA1_1_X_COUNT ((uint16_t volatile *)DMA1_1_X_COUNT) 121 #define bfin_read_DMA1_1_X_COUNT() bfin_read16(DMA1_1_X_COUNT) 122 #define bfin_write_DMA1_1_X_COUNT(val) bfin_write16(DMA1_1_X_COUNT, val) 123 #define pDMA1_1_Y_COUNT ((uint16_t volatile *)DMA1_1_Y_COUNT) 124 #define bfin_read_DMA1_1_Y_COUNT() bfin_read16(DMA1_1_Y_COUNT) 125 #define bfin_write_DMA1_1_Y_COUNT(val) bfin_write16(DMA1_1_Y_COUNT, val) 126 #define pDMA1_1_X_MODIFY ((uint16_t volatile *)DMA1_1_X_MODIFY) 127 #define bfin_read_DMA1_1_X_MODIFY() bfin_read16(DMA1_1_X_MODIFY) 128 #define bfin_write_DMA1_1_X_MODIFY(val) bfin_write16(DMA1_1_X_MODIFY, val) 129 #define pDMA1_1_Y_MODIFY ((uint16_t volatile *)DMA1_1_Y_MODIFY) 130 #define bfin_read_DMA1_1_Y_MODIFY() bfin_read16(DMA1_1_Y_MODIFY) 131 #define bfin_write_DMA1_1_Y_MODIFY(val) bfin_write16(DMA1_1_Y_MODIFY, val) 132 #define pDMA1_1_CURR_DESC_PTR ((void * volatile *)DMA1_1_CURR_DESC_PTR) 133 #define bfin_read_DMA1_1_CURR_DESC_PTR() bfin_readPTR(DMA1_1_CURR_DESC_PTR) 134 #define bfin_write_DMA1_1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_1_CURR_DESC_PTR, val) 135 #define pDMA1_1_CURR_ADDR ((void * volatile *)DMA1_1_CURR_ADDR) 136 #define bfin_read_DMA1_1_CURR_ADDR() bfin_readPTR(DMA1_1_CURR_ADDR) 137 #define bfin_write_DMA1_1_CURR_ADDR(val) bfin_writePTR(DMA1_1_CURR_ADDR, val) 138 #define pDMA1_1_CURR_X_COUNT ((uint16_t volatile *)DMA1_1_CURR_X_COUNT) 139 #define bfin_read_DMA1_1_CURR_X_COUNT() bfin_read16(DMA1_1_CURR_X_COUNT) 140 #define bfin_write_DMA1_1_CURR_X_COUNT(val) bfin_write16(DMA1_1_CURR_X_COUNT, val) 141 #define pDMA1_1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_1_CURR_Y_COUNT) 142 #define bfin_read_DMA1_1_CURR_Y_COUNT() bfin_read16(DMA1_1_CURR_Y_COUNT) 143 #define bfin_write_DMA1_1_CURR_Y_COUNT(val) bfin_write16(DMA1_1_CURR_Y_COUNT, val) 144 #define pDMA1_1_IRQ_STATUS ((uint16_t volatile *)DMA1_1_IRQ_STATUS) 145 #define bfin_read_DMA1_1_IRQ_STATUS() bfin_read16(DMA1_1_IRQ_STATUS) 146 #define bfin_write_DMA1_1_IRQ_STATUS(val) bfin_write16(DMA1_1_IRQ_STATUS, val) 147 #define pDMA1_1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_1_PERIPHERAL_MAP) 148 #define bfin_read_DMA1_1_PERIPHERAL_MAP() bfin_read16(DMA1_1_PERIPHERAL_MAP) 149 #define bfin_write_DMA1_1_PERIPHERAL_MAP(val) bfin_write16(DMA1_1_PERIPHERAL_MAP, val) 150 #define pDMA1_2_CONFIG ((uint16_t volatile *)DMA1_2_CONFIG) 151 #define bfin_read_DMA1_2_CONFIG() bfin_read16(DMA1_2_CONFIG) 152 #define bfin_write_DMA1_2_CONFIG(val) bfin_write16(DMA1_2_CONFIG, val) 153 #define pDMA1_2_NEXT_DESC_PTR ((void * volatile *)DMA1_2_NEXT_DESC_PTR) 154 #define bfin_read_DMA1_2_NEXT_DESC_PTR() bfin_readPTR(DMA1_2_NEXT_DESC_PTR) 155 #define bfin_write_DMA1_2_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_2_NEXT_DESC_PTR, val) 156 #define pDMA1_2_START_ADDR ((void * volatile *)DMA1_2_START_ADDR) 157 #define bfin_read_DMA1_2_START_ADDR() bfin_readPTR(DMA1_2_START_ADDR) 158 #define bfin_write_DMA1_2_START_ADDR(val) bfin_writePTR(DMA1_2_START_ADDR, val) 159 #define pDMA1_2_X_COUNT ((uint16_t volatile *)DMA1_2_X_COUNT) 160 #define bfin_read_DMA1_2_X_COUNT() bfin_read16(DMA1_2_X_COUNT) 161 #define bfin_write_DMA1_2_X_COUNT(val) bfin_write16(DMA1_2_X_COUNT, val) 162 #define pDMA1_2_Y_COUNT ((uint16_t volatile *)DMA1_2_Y_COUNT) 163 #define bfin_read_DMA1_2_Y_COUNT() bfin_read16(DMA1_2_Y_COUNT) 164 #define bfin_write_DMA1_2_Y_COUNT(val) bfin_write16(DMA1_2_Y_COUNT, val) 165 #define pDMA1_2_X_MODIFY ((uint16_t volatile *)DMA1_2_X_MODIFY) 166 #define bfin_read_DMA1_2_X_MODIFY() bfin_read16(DMA1_2_X_MODIFY) 167 #define bfin_write_DMA1_2_X_MODIFY(val) bfin_write16(DMA1_2_X_MODIFY, val) 168 #define pDMA1_2_Y_MODIFY ((uint16_t volatile *)DMA1_2_Y_MODIFY) 169 #define bfin_read_DMA1_2_Y_MODIFY() bfin_read16(DMA1_2_Y_MODIFY) 170 #define bfin_write_DMA1_2_Y_MODIFY(val) bfin_write16(DMA1_2_Y_MODIFY, val) 171 #define pDMA1_2_CURR_DESC_PTR ((void * volatile *)DMA1_2_CURR_DESC_PTR) 172 #define bfin_read_DMA1_2_CURR_DESC_PTR() bfin_readPTR(DMA1_2_CURR_DESC_PTR) 173 #define bfin_write_DMA1_2_CURR_DESC_PTR(val) bfin_writePTR(DMA1_2_CURR_DESC_PTR, val) 174 #define pDMA1_2_CURR_ADDR ((void * volatile *)DMA1_2_CURR_ADDR) 175 #define bfin_read_DMA1_2_CURR_ADDR() bfin_readPTR(DMA1_2_CURR_ADDR) 176 #define bfin_write_DMA1_2_CURR_ADDR(val) bfin_writePTR(DMA1_2_CURR_ADDR, val) 177 #define pDMA1_2_CURR_X_COUNT ((uint16_t volatile *)DMA1_2_CURR_X_COUNT) 178 #define bfin_read_DMA1_2_CURR_X_COUNT() bfin_read16(DMA1_2_CURR_X_COUNT) 179 #define bfin_write_DMA1_2_CURR_X_COUNT(val) bfin_write16(DMA1_2_CURR_X_COUNT, val) 180 #define pDMA1_2_CURR_Y_COUNT ((uint16_t volatile *)DMA1_2_CURR_Y_COUNT) 181 #define bfin_read_DMA1_2_CURR_Y_COUNT() bfin_read16(DMA1_2_CURR_Y_COUNT) 182 #define bfin_write_DMA1_2_CURR_Y_COUNT(val) bfin_write16(DMA1_2_CURR_Y_COUNT, val) 183 #define pDMA1_2_IRQ_STATUS ((uint16_t volatile *)DMA1_2_IRQ_STATUS) 184 #define bfin_read_DMA1_2_IRQ_STATUS() bfin_read16(DMA1_2_IRQ_STATUS) 185 #define bfin_write_DMA1_2_IRQ_STATUS(val) bfin_write16(DMA1_2_IRQ_STATUS, val) 186 #define pDMA1_2_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_2_PERIPHERAL_MAP) 187 #define bfin_read_DMA1_2_PERIPHERAL_MAP() bfin_read16(DMA1_2_PERIPHERAL_MAP) 188 #define bfin_write_DMA1_2_PERIPHERAL_MAP(val) bfin_write16(DMA1_2_PERIPHERAL_MAP, val) 189 #define pDMA1_3_CONFIG ((uint16_t volatile *)DMA1_3_CONFIG) 190 #define bfin_read_DMA1_3_CONFIG() bfin_read16(DMA1_3_CONFIG) 191 #define bfin_write_DMA1_3_CONFIG(val) bfin_write16(DMA1_3_CONFIG, val) 192 #define pDMA1_3_NEXT_DESC_PTR ((void * volatile *)DMA1_3_NEXT_DESC_PTR) 193 #define bfin_read_DMA1_3_NEXT_DESC_PTR() bfin_readPTR(DMA1_3_NEXT_DESC_PTR) 194 #define bfin_write_DMA1_3_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_3_NEXT_DESC_PTR, val) 195 #define pDMA1_3_START_ADDR ((void * volatile *)DMA1_3_START_ADDR) 196 #define bfin_read_DMA1_3_START_ADDR() bfin_readPTR(DMA1_3_START_ADDR) 197 #define bfin_write_DMA1_3_START_ADDR(val) bfin_writePTR(DMA1_3_START_ADDR, val) 198 #define pDMA1_3_X_COUNT ((uint16_t volatile *)DMA1_3_X_COUNT) 199 #define bfin_read_DMA1_3_X_COUNT() bfin_read16(DMA1_3_X_COUNT) 200 #define bfin_write_DMA1_3_X_COUNT(val) bfin_write16(DMA1_3_X_COUNT, val) 201 #define pDMA1_3_Y_COUNT ((uint16_t volatile *)DMA1_3_Y_COUNT) 202 #define bfin_read_DMA1_3_Y_COUNT() bfin_read16(DMA1_3_Y_COUNT) 203 #define bfin_write_DMA1_3_Y_COUNT(val) bfin_write16(DMA1_3_Y_COUNT, val) 204 #define pDMA1_3_X_MODIFY ((uint16_t volatile *)DMA1_3_X_MODIFY) 205 #define bfin_read_DMA1_3_X_MODIFY() bfin_read16(DMA1_3_X_MODIFY) 206 #define bfin_write_DMA1_3_X_MODIFY(val) bfin_write16(DMA1_3_X_MODIFY, val) 207 #define pDMA1_3_Y_MODIFY ((uint16_t volatile *)DMA1_3_Y_MODIFY) 208 #define bfin_read_DMA1_3_Y_MODIFY() bfin_read16(DMA1_3_Y_MODIFY) 209 #define bfin_write_DMA1_3_Y_MODIFY(val) bfin_write16(DMA1_3_Y_MODIFY, val) 210 #define pDMA1_3_CURR_DESC_PTR ((void * volatile *)DMA1_3_CURR_DESC_PTR) 211 #define bfin_read_DMA1_3_CURR_DESC_PTR() bfin_readPTR(DMA1_3_CURR_DESC_PTR) 212 #define bfin_write_DMA1_3_CURR_DESC_PTR(val) bfin_writePTR(DMA1_3_CURR_DESC_PTR, val) 213 #define pDMA1_3_CURR_ADDR ((void * volatile *)DMA1_3_CURR_ADDR) 214 #define bfin_read_DMA1_3_CURR_ADDR() bfin_readPTR(DMA1_3_CURR_ADDR) 215 #define bfin_write_DMA1_3_CURR_ADDR(val) bfin_writePTR(DMA1_3_CURR_ADDR, val) 216 #define pDMA1_3_CURR_X_COUNT ((uint16_t volatile *)DMA1_3_CURR_X_COUNT) 217 #define bfin_read_DMA1_3_CURR_X_COUNT() bfin_read16(DMA1_3_CURR_X_COUNT) 218 #define bfin_write_DMA1_3_CURR_X_COUNT(val) bfin_write16(DMA1_3_CURR_X_COUNT, val) 219 #define pDMA1_3_CURR_Y_COUNT ((uint16_t volatile *)DMA1_3_CURR_Y_COUNT) 220 #define bfin_read_DMA1_3_CURR_Y_COUNT() bfin_read16(DMA1_3_CURR_Y_COUNT) 221 #define bfin_write_DMA1_3_CURR_Y_COUNT(val) bfin_write16(DMA1_3_CURR_Y_COUNT, val) 222 #define pDMA1_3_IRQ_STATUS ((uint16_t volatile *)DMA1_3_IRQ_STATUS) 223 #define bfin_read_DMA1_3_IRQ_STATUS() bfin_read16(DMA1_3_IRQ_STATUS) 224 #define bfin_write_DMA1_3_IRQ_STATUS(val) bfin_write16(DMA1_3_IRQ_STATUS, val) 225 #define pDMA1_3_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_3_PERIPHERAL_MAP) 226 #define bfin_read_DMA1_3_PERIPHERAL_MAP() bfin_read16(DMA1_3_PERIPHERAL_MAP) 227 #define bfin_write_DMA1_3_PERIPHERAL_MAP(val) bfin_write16(DMA1_3_PERIPHERAL_MAP, val) 228 #define pDMA1_4_CONFIG ((uint16_t volatile *)DMA1_4_CONFIG) 229 #define bfin_read_DMA1_4_CONFIG() bfin_read16(DMA1_4_CONFIG) 230 #define bfin_write_DMA1_4_CONFIG(val) bfin_write16(DMA1_4_CONFIG, val) 231 #define pDMA1_4_NEXT_DESC_PTR ((void * volatile *)DMA1_4_NEXT_DESC_PTR) 232 #define bfin_read_DMA1_4_NEXT_DESC_PTR() bfin_readPTR(DMA1_4_NEXT_DESC_PTR) 233 #define bfin_write_DMA1_4_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_4_NEXT_DESC_PTR, val) 234 #define pDMA1_4_START_ADDR ((void * volatile *)DMA1_4_START_ADDR) 235 #define bfin_read_DMA1_4_START_ADDR() bfin_readPTR(DMA1_4_START_ADDR) 236 #define bfin_write_DMA1_4_START_ADDR(val) bfin_writePTR(DMA1_4_START_ADDR, val) 237 #define pDMA1_4_X_COUNT ((uint16_t volatile *)DMA1_4_X_COUNT) 238 #define bfin_read_DMA1_4_X_COUNT() bfin_read16(DMA1_4_X_COUNT) 239 #define bfin_write_DMA1_4_X_COUNT(val) bfin_write16(DMA1_4_X_COUNT, val) 240 #define pDMA1_4_Y_COUNT ((uint16_t volatile *)DMA1_4_Y_COUNT) 241 #define bfin_read_DMA1_4_Y_COUNT() bfin_read16(DMA1_4_Y_COUNT) 242 #define bfin_write_DMA1_4_Y_COUNT(val) bfin_write16(DMA1_4_Y_COUNT, val) 243 #define pDMA1_4_X_MODIFY ((uint16_t volatile *)DMA1_4_X_MODIFY) 244 #define bfin_read_DMA1_4_X_MODIFY() bfin_read16(DMA1_4_X_MODIFY) 245 #define bfin_write_DMA1_4_X_MODIFY(val) bfin_write16(DMA1_4_X_MODIFY, val) 246 #define pDMA1_4_Y_MODIFY ((uint16_t volatile *)DMA1_4_Y_MODIFY) 247 #define bfin_read_DMA1_4_Y_MODIFY() bfin_read16(DMA1_4_Y_MODIFY) 248 #define bfin_write_DMA1_4_Y_MODIFY(val) bfin_write16(DMA1_4_Y_MODIFY, val) 249 #define pDMA1_4_CURR_DESC_PTR ((void * volatile *)DMA1_4_CURR_DESC_PTR) 250 #define bfin_read_DMA1_4_CURR_DESC_PTR() bfin_readPTR(DMA1_4_CURR_DESC_PTR) 251 #define bfin_write_DMA1_4_CURR_DESC_PTR(val) bfin_writePTR(DMA1_4_CURR_DESC_PTR, val) 252 #define pDMA1_4_CURR_ADDR ((void * volatile *)DMA1_4_CURR_ADDR) 253 #define bfin_read_DMA1_4_CURR_ADDR() bfin_readPTR(DMA1_4_CURR_ADDR) 254 #define bfin_write_DMA1_4_CURR_ADDR(val) bfin_writePTR(DMA1_4_CURR_ADDR, val) 255 #define pDMA1_4_CURR_X_COUNT ((uint16_t volatile *)DMA1_4_CURR_X_COUNT) 256 #define bfin_read_DMA1_4_CURR_X_COUNT() bfin_read16(DMA1_4_CURR_X_COUNT) 257 #define bfin_write_DMA1_4_CURR_X_COUNT(val) bfin_write16(DMA1_4_CURR_X_COUNT, val) 258 #define pDMA1_4_CURR_Y_COUNT ((uint16_t volatile *)DMA1_4_CURR_Y_COUNT) 259 #define bfin_read_DMA1_4_CURR_Y_COUNT() bfin_read16(DMA1_4_CURR_Y_COUNT) 260 #define bfin_write_DMA1_4_CURR_Y_COUNT(val) bfin_write16(DMA1_4_CURR_Y_COUNT, val) 261 #define pDMA1_4_IRQ_STATUS ((uint16_t volatile *)DMA1_4_IRQ_STATUS) 262 #define bfin_read_DMA1_4_IRQ_STATUS() bfin_read16(DMA1_4_IRQ_STATUS) 263 #define bfin_write_DMA1_4_IRQ_STATUS(val) bfin_write16(DMA1_4_IRQ_STATUS, val) 264 #define pDMA1_4_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_4_PERIPHERAL_MAP) 265 #define bfin_read_DMA1_4_PERIPHERAL_MAP() bfin_read16(DMA1_4_PERIPHERAL_MAP) 266 #define bfin_write_DMA1_4_PERIPHERAL_MAP(val) bfin_write16(DMA1_4_PERIPHERAL_MAP, val) 267 #define pDMA1_5_CONFIG ((uint16_t volatile *)DMA1_5_CONFIG) 268 #define bfin_read_DMA1_5_CONFIG() bfin_read16(DMA1_5_CONFIG) 269 #define bfin_write_DMA1_5_CONFIG(val) bfin_write16(DMA1_5_CONFIG, val) 270 #define pDMA1_5_NEXT_DESC_PTR ((void * volatile *)DMA1_5_NEXT_DESC_PTR) 271 #define bfin_read_DMA1_5_NEXT_DESC_PTR() bfin_readPTR(DMA1_5_NEXT_DESC_PTR) 272 #define bfin_write_DMA1_5_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_5_NEXT_DESC_PTR, val) 273 #define pDMA1_5_START_ADDR ((void * volatile *)DMA1_5_START_ADDR) 274 #define bfin_read_DMA1_5_START_ADDR() bfin_readPTR(DMA1_5_START_ADDR) 275 #define bfin_write_DMA1_5_START_ADDR(val) bfin_writePTR(DMA1_5_START_ADDR, val) 276 #define pDMA1_5_X_COUNT ((uint16_t volatile *)DMA1_5_X_COUNT) 277 #define bfin_read_DMA1_5_X_COUNT() bfin_read16(DMA1_5_X_COUNT) 278 #define bfin_write_DMA1_5_X_COUNT(val) bfin_write16(DMA1_5_X_COUNT, val) 279 #define pDMA1_5_Y_COUNT ((uint16_t volatile *)DMA1_5_Y_COUNT) 280 #define bfin_read_DMA1_5_Y_COUNT() bfin_read16(DMA1_5_Y_COUNT) 281 #define bfin_write_DMA1_5_Y_COUNT(val) bfin_write16(DMA1_5_Y_COUNT, val) 282 #define pDMA1_5_X_MODIFY ((uint16_t volatile *)DMA1_5_X_MODIFY) 283 #define bfin_read_DMA1_5_X_MODIFY() bfin_read16(DMA1_5_X_MODIFY) 284 #define bfin_write_DMA1_5_X_MODIFY(val) bfin_write16(DMA1_5_X_MODIFY, val) 285 #define pDMA1_5_Y_MODIFY ((uint16_t volatile *)DMA1_5_Y_MODIFY) 286 #define bfin_read_DMA1_5_Y_MODIFY() bfin_read16(DMA1_5_Y_MODIFY) 287 #define bfin_write_DMA1_5_Y_MODIFY(val) bfin_write16(DMA1_5_Y_MODIFY, val) 288 #define pDMA1_5_CURR_DESC_PTR ((void * volatile *)DMA1_5_CURR_DESC_PTR) 289 #define bfin_read_DMA1_5_CURR_DESC_PTR() bfin_readPTR(DMA1_5_CURR_DESC_PTR) 290 #define bfin_write_DMA1_5_CURR_DESC_PTR(val) bfin_writePTR(DMA1_5_CURR_DESC_PTR, val) 291 #define pDMA1_5_CURR_ADDR ((void * volatile *)DMA1_5_CURR_ADDR) 292 #define bfin_read_DMA1_5_CURR_ADDR() bfin_readPTR(DMA1_5_CURR_ADDR) 293 #define bfin_write_DMA1_5_CURR_ADDR(val) bfin_writePTR(DMA1_5_CURR_ADDR, val) 294 #define pDMA1_5_CURR_X_COUNT ((uint16_t volatile *)DMA1_5_CURR_X_COUNT) 295 #define bfin_read_DMA1_5_CURR_X_COUNT() bfin_read16(DMA1_5_CURR_X_COUNT) 296 #define bfin_write_DMA1_5_CURR_X_COUNT(val) bfin_write16(DMA1_5_CURR_X_COUNT, val) 297 #define pDMA1_5_CURR_Y_COUNT ((uint16_t volatile *)DMA1_5_CURR_Y_COUNT) 298 #define bfin_read_DMA1_5_CURR_Y_COUNT() bfin_read16(DMA1_5_CURR_Y_COUNT) 299 #define bfin_write_DMA1_5_CURR_Y_COUNT(val) bfin_write16(DMA1_5_CURR_Y_COUNT, val) 300 #define pDMA1_5_IRQ_STATUS ((uint16_t volatile *)DMA1_5_IRQ_STATUS) 301 #define bfin_read_DMA1_5_IRQ_STATUS() bfin_read16(DMA1_5_IRQ_STATUS) 302 #define bfin_write_DMA1_5_IRQ_STATUS(val) bfin_write16(DMA1_5_IRQ_STATUS, val) 303 #define pDMA1_5_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_5_PERIPHERAL_MAP) 304 #define bfin_read_DMA1_5_PERIPHERAL_MAP() bfin_read16(DMA1_5_PERIPHERAL_MAP) 305 #define bfin_write_DMA1_5_PERIPHERAL_MAP(val) bfin_write16(DMA1_5_PERIPHERAL_MAP, val) 306 #define pDMA1_6_CONFIG ((uint16_t volatile *)DMA1_6_CONFIG) 307 #define bfin_read_DMA1_6_CONFIG() bfin_read16(DMA1_6_CONFIG) 308 #define bfin_write_DMA1_6_CONFIG(val) bfin_write16(DMA1_6_CONFIG, val) 309 #define pDMA1_6_NEXT_DESC_PTR ((void * volatile *)DMA1_6_NEXT_DESC_PTR) 310 #define bfin_read_DMA1_6_NEXT_DESC_PTR() bfin_readPTR(DMA1_6_NEXT_DESC_PTR) 311 #define bfin_write_DMA1_6_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_6_NEXT_DESC_PTR, val) 312 #define pDMA1_6_START_ADDR ((void * volatile *)DMA1_6_START_ADDR) 313 #define bfin_read_DMA1_6_START_ADDR() bfin_readPTR(DMA1_6_START_ADDR) 314 #define bfin_write_DMA1_6_START_ADDR(val) bfin_writePTR(DMA1_6_START_ADDR, val) 315 #define pDMA1_6_X_COUNT ((uint16_t volatile *)DMA1_6_X_COUNT) 316 #define bfin_read_DMA1_6_X_COUNT() bfin_read16(DMA1_6_X_COUNT) 317 #define bfin_write_DMA1_6_X_COUNT(val) bfin_write16(DMA1_6_X_COUNT, val) 318 #define pDMA1_6_Y_COUNT ((uint16_t volatile *)DMA1_6_Y_COUNT) 319 #define bfin_read_DMA1_6_Y_COUNT() bfin_read16(DMA1_6_Y_COUNT) 320 #define bfin_write_DMA1_6_Y_COUNT(val) bfin_write16(DMA1_6_Y_COUNT, val) 321 #define pDMA1_6_X_MODIFY ((uint16_t volatile *)DMA1_6_X_MODIFY) 322 #define bfin_read_DMA1_6_X_MODIFY() bfin_read16(DMA1_6_X_MODIFY) 323 #define bfin_write_DMA1_6_X_MODIFY(val) bfin_write16(DMA1_6_X_MODIFY, val) 324 #define pDMA1_6_Y_MODIFY ((uint16_t volatile *)DMA1_6_Y_MODIFY) 325 #define bfin_read_DMA1_6_Y_MODIFY() bfin_read16(DMA1_6_Y_MODIFY) 326 #define bfin_write_DMA1_6_Y_MODIFY(val) bfin_write16(DMA1_6_Y_MODIFY, val) 327 #define pDMA1_6_CURR_DESC_PTR ((void * volatile *)DMA1_6_CURR_DESC_PTR) 328 #define bfin_read_DMA1_6_CURR_DESC_PTR() bfin_readPTR(DMA1_6_CURR_DESC_PTR) 329 #define bfin_write_DMA1_6_CURR_DESC_PTR(val) bfin_writePTR(DMA1_6_CURR_DESC_PTR, val) 330 #define pDMA1_6_CURR_ADDR ((void * volatile *)DMA1_6_CURR_ADDR) 331 #define bfin_read_DMA1_6_CURR_ADDR() bfin_readPTR(DMA1_6_CURR_ADDR) 332 #define bfin_write_DMA1_6_CURR_ADDR(val) bfin_writePTR(DMA1_6_CURR_ADDR, val) 333 #define pDMA1_6_CURR_X_COUNT ((uint16_t volatile *)DMA1_6_CURR_X_COUNT) 334 #define bfin_read_DMA1_6_CURR_X_COUNT() bfin_read16(DMA1_6_CURR_X_COUNT) 335 #define bfin_write_DMA1_6_CURR_X_COUNT(val) bfin_write16(DMA1_6_CURR_X_COUNT, val) 336 #define pDMA1_6_CURR_Y_COUNT ((uint16_t volatile *)DMA1_6_CURR_Y_COUNT) 337 #define bfin_read_DMA1_6_CURR_Y_COUNT() bfin_read16(DMA1_6_CURR_Y_COUNT) 338 #define bfin_write_DMA1_6_CURR_Y_COUNT(val) bfin_write16(DMA1_6_CURR_Y_COUNT, val) 339 #define pDMA1_6_IRQ_STATUS ((uint16_t volatile *)DMA1_6_IRQ_STATUS) 340 #define bfin_read_DMA1_6_IRQ_STATUS() bfin_read16(DMA1_6_IRQ_STATUS) 341 #define bfin_write_DMA1_6_IRQ_STATUS(val) bfin_write16(DMA1_6_IRQ_STATUS, val) 342 #define pDMA1_6_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_6_PERIPHERAL_MAP) 343 #define bfin_read_DMA1_6_PERIPHERAL_MAP() bfin_read16(DMA1_6_PERIPHERAL_MAP) 344 #define bfin_write_DMA1_6_PERIPHERAL_MAP(val) bfin_write16(DMA1_6_PERIPHERAL_MAP, val) 345 #define pDMA1_7_CONFIG ((uint16_t volatile *)DMA1_7_CONFIG) 346 #define bfin_read_DMA1_7_CONFIG() bfin_read16(DMA1_7_CONFIG) 347 #define bfin_write_DMA1_7_CONFIG(val) bfin_write16(DMA1_7_CONFIG, val) 348 #define pDMA1_7_NEXT_DESC_PTR ((void * volatile *)DMA1_7_NEXT_DESC_PTR) 349 #define bfin_read_DMA1_7_NEXT_DESC_PTR() bfin_readPTR(DMA1_7_NEXT_DESC_PTR) 350 #define bfin_write_DMA1_7_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_7_NEXT_DESC_PTR, val) 351 #define pDMA1_7_START_ADDR ((void * volatile *)DMA1_7_START_ADDR) 352 #define bfin_read_DMA1_7_START_ADDR() bfin_readPTR(DMA1_7_START_ADDR) 353 #define bfin_write_DMA1_7_START_ADDR(val) bfin_writePTR(DMA1_7_START_ADDR, val) 354 #define pDMA1_7_X_COUNT ((uint16_t volatile *)DMA1_7_X_COUNT) 355 #define bfin_read_DMA1_7_X_COUNT() bfin_read16(DMA1_7_X_COUNT) 356 #define bfin_write_DMA1_7_X_COUNT(val) bfin_write16(DMA1_7_X_COUNT, val) 357 #define pDMA1_7_Y_COUNT ((uint16_t volatile *)DMA1_7_Y_COUNT) 358 #define bfin_read_DMA1_7_Y_COUNT() bfin_read16(DMA1_7_Y_COUNT) 359 #define bfin_write_DMA1_7_Y_COUNT(val) bfin_write16(DMA1_7_Y_COUNT, val) 360 #define pDMA1_7_X_MODIFY ((uint16_t volatile *)DMA1_7_X_MODIFY) 361 #define bfin_read_DMA1_7_X_MODIFY() bfin_read16(DMA1_7_X_MODIFY) 362 #define bfin_write_DMA1_7_X_MODIFY(val) bfin_write16(DMA1_7_X_MODIFY, val) 363 #define pDMA1_7_Y_MODIFY ((uint16_t volatile *)DMA1_7_Y_MODIFY) 364 #define bfin_read_DMA1_7_Y_MODIFY() bfin_read16(DMA1_7_Y_MODIFY) 365 #define bfin_write_DMA1_7_Y_MODIFY(val) bfin_write16(DMA1_7_Y_MODIFY, val) 366 #define pDMA1_7_CURR_DESC_PTR ((void * volatile *)DMA1_7_CURR_DESC_PTR) 367 #define bfin_read_DMA1_7_CURR_DESC_PTR() bfin_readPTR(DMA1_7_CURR_DESC_PTR) 368 #define bfin_write_DMA1_7_CURR_DESC_PTR(val) bfin_writePTR(DMA1_7_CURR_DESC_PTR, val) 369 #define pDMA1_7_CURR_ADDR ((void * volatile *)DMA1_7_CURR_ADDR) 370 #define bfin_read_DMA1_7_CURR_ADDR() bfin_readPTR(DMA1_7_CURR_ADDR) 371 #define bfin_write_DMA1_7_CURR_ADDR(val) bfin_writePTR(DMA1_7_CURR_ADDR, val) 372 #define pDMA1_7_CURR_X_COUNT ((uint16_t volatile *)DMA1_7_CURR_X_COUNT) 373 #define bfin_read_DMA1_7_CURR_X_COUNT() bfin_read16(DMA1_7_CURR_X_COUNT) 374 #define bfin_write_DMA1_7_CURR_X_COUNT(val) bfin_write16(DMA1_7_CURR_X_COUNT, val) 375 #define pDMA1_7_CURR_Y_COUNT ((uint16_t volatile *)DMA1_7_CURR_Y_COUNT) 376 #define bfin_read_DMA1_7_CURR_Y_COUNT() bfin_read16(DMA1_7_CURR_Y_COUNT) 377 #define bfin_write_DMA1_7_CURR_Y_COUNT(val) bfin_write16(DMA1_7_CURR_Y_COUNT, val) 378 #define pDMA1_7_IRQ_STATUS ((uint16_t volatile *)DMA1_7_IRQ_STATUS) 379 #define bfin_read_DMA1_7_IRQ_STATUS() bfin_read16(DMA1_7_IRQ_STATUS) 380 #define bfin_write_DMA1_7_IRQ_STATUS(val) bfin_write16(DMA1_7_IRQ_STATUS, val) 381 #define pDMA1_7_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_7_PERIPHERAL_MAP) 382 #define bfin_read_DMA1_7_PERIPHERAL_MAP() bfin_read16(DMA1_7_PERIPHERAL_MAP) 383 #define bfin_write_DMA1_7_PERIPHERAL_MAP(val) bfin_write16(DMA1_7_PERIPHERAL_MAP, val) 384 #define pDMA1_8_CONFIG ((uint16_t volatile *)DMA1_8_CONFIG) 385 #define bfin_read_DMA1_8_CONFIG() bfin_read16(DMA1_8_CONFIG) 386 #define bfin_write_DMA1_8_CONFIG(val) bfin_write16(DMA1_8_CONFIG, val) 387 #define pDMA1_8_NEXT_DESC_PTR ((void * volatile *)DMA1_8_NEXT_DESC_PTR) 388 #define bfin_read_DMA1_8_NEXT_DESC_PTR() bfin_readPTR(DMA1_8_NEXT_DESC_PTR) 389 #define bfin_write_DMA1_8_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_8_NEXT_DESC_PTR, val) 390 #define pDMA1_8_START_ADDR ((void * volatile *)DMA1_8_START_ADDR) 391 #define bfin_read_DMA1_8_START_ADDR() bfin_readPTR(DMA1_8_START_ADDR) 392 #define bfin_write_DMA1_8_START_ADDR(val) bfin_writePTR(DMA1_8_START_ADDR, val) 393 #define pDMA1_8_X_COUNT ((uint16_t volatile *)DMA1_8_X_COUNT) 394 #define bfin_read_DMA1_8_X_COUNT() bfin_read16(DMA1_8_X_COUNT) 395 #define bfin_write_DMA1_8_X_COUNT(val) bfin_write16(DMA1_8_X_COUNT, val) 396 #define pDMA1_8_Y_COUNT ((uint16_t volatile *)DMA1_8_Y_COUNT) 397 #define bfin_read_DMA1_8_Y_COUNT() bfin_read16(DMA1_8_Y_COUNT) 398 #define bfin_write_DMA1_8_Y_COUNT(val) bfin_write16(DMA1_8_Y_COUNT, val) 399 #define pDMA1_8_X_MODIFY ((uint16_t volatile *)DMA1_8_X_MODIFY) 400 #define bfin_read_DMA1_8_X_MODIFY() bfin_read16(DMA1_8_X_MODIFY) 401 #define bfin_write_DMA1_8_X_MODIFY(val) bfin_write16(DMA1_8_X_MODIFY, val) 402 #define pDMA1_8_Y_MODIFY ((uint16_t volatile *)DMA1_8_Y_MODIFY) 403 #define bfin_read_DMA1_8_Y_MODIFY() bfin_read16(DMA1_8_Y_MODIFY) 404 #define bfin_write_DMA1_8_Y_MODIFY(val) bfin_write16(DMA1_8_Y_MODIFY, val) 405 #define pDMA1_8_CURR_DESC_PTR ((void * volatile *)DMA1_8_CURR_DESC_PTR) 406 #define bfin_read_DMA1_8_CURR_DESC_PTR() bfin_readPTR(DMA1_8_CURR_DESC_PTR) 407 #define bfin_write_DMA1_8_CURR_DESC_PTR(val) bfin_writePTR(DMA1_8_CURR_DESC_PTR, val) 408 #define pDMA1_8_CURR_ADDR ((void * volatile *)DMA1_8_CURR_ADDR) 409 #define bfin_read_DMA1_8_CURR_ADDR() bfin_readPTR(DMA1_8_CURR_ADDR) 410 #define bfin_write_DMA1_8_CURR_ADDR(val) bfin_writePTR(DMA1_8_CURR_ADDR, val) 411 #define pDMA1_8_CURR_X_COUNT ((uint16_t volatile *)DMA1_8_CURR_X_COUNT) 412 #define bfin_read_DMA1_8_CURR_X_COUNT() bfin_read16(DMA1_8_CURR_X_COUNT) 413 #define bfin_write_DMA1_8_CURR_X_COUNT(val) bfin_write16(DMA1_8_CURR_X_COUNT, val) 414 #define pDMA1_8_CURR_Y_COUNT ((uint16_t volatile *)DMA1_8_CURR_Y_COUNT) 415 #define bfin_read_DMA1_8_CURR_Y_COUNT() bfin_read16(DMA1_8_CURR_Y_COUNT) 416 #define bfin_write_DMA1_8_CURR_Y_COUNT(val) bfin_write16(DMA1_8_CURR_Y_COUNT, val) 417 #define pDMA1_8_IRQ_STATUS ((uint16_t volatile *)DMA1_8_IRQ_STATUS) 418 #define bfin_read_DMA1_8_IRQ_STATUS() bfin_read16(DMA1_8_IRQ_STATUS) 419 #define bfin_write_DMA1_8_IRQ_STATUS(val) bfin_write16(DMA1_8_IRQ_STATUS, val) 420 #define pDMA1_8_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_8_PERIPHERAL_MAP) 421 #define bfin_read_DMA1_8_PERIPHERAL_MAP() bfin_read16(DMA1_8_PERIPHERAL_MAP) 422 #define bfin_write_DMA1_8_PERIPHERAL_MAP(val) bfin_write16(DMA1_8_PERIPHERAL_MAP, val) 423 #define pDMA1_9_CONFIG ((uint16_t volatile *)DMA1_9_CONFIG) 424 #define bfin_read_DMA1_9_CONFIG() bfin_read16(DMA1_9_CONFIG) 425 #define bfin_write_DMA1_9_CONFIG(val) bfin_write16(DMA1_9_CONFIG, val) 426 #define pDMA1_9_NEXT_DESC_PTR ((void * volatile *)DMA1_9_NEXT_DESC_PTR) 427 #define bfin_read_DMA1_9_NEXT_DESC_PTR() bfin_readPTR(DMA1_9_NEXT_DESC_PTR) 428 #define bfin_write_DMA1_9_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_9_NEXT_DESC_PTR, val) 429 #define pDMA1_9_START_ADDR ((void * volatile *)DMA1_9_START_ADDR) 430 #define bfin_read_DMA1_9_START_ADDR() bfin_readPTR(DMA1_9_START_ADDR) 431 #define bfin_write_DMA1_9_START_ADDR(val) bfin_writePTR(DMA1_9_START_ADDR, val) 432 #define pDMA1_9_X_COUNT ((uint16_t volatile *)DMA1_9_X_COUNT) 433 #define bfin_read_DMA1_9_X_COUNT() bfin_read16(DMA1_9_X_COUNT) 434 #define bfin_write_DMA1_9_X_COUNT(val) bfin_write16(DMA1_9_X_COUNT, val) 435 #define pDMA1_9_Y_COUNT ((uint16_t volatile *)DMA1_9_Y_COUNT) 436 #define bfin_read_DMA1_9_Y_COUNT() bfin_read16(DMA1_9_Y_COUNT) 437 #define bfin_write_DMA1_9_Y_COUNT(val) bfin_write16(DMA1_9_Y_COUNT, val) 438 #define pDMA1_9_X_MODIFY ((uint16_t volatile *)DMA1_9_X_MODIFY) 439 #define bfin_read_DMA1_9_X_MODIFY() bfin_read16(DMA1_9_X_MODIFY) 440 #define bfin_write_DMA1_9_X_MODIFY(val) bfin_write16(DMA1_9_X_MODIFY, val) 441 #define pDMA1_9_Y_MODIFY ((uint16_t volatile *)DMA1_9_Y_MODIFY) 442 #define bfin_read_DMA1_9_Y_MODIFY() bfin_read16(DMA1_9_Y_MODIFY) 443 #define bfin_write_DMA1_9_Y_MODIFY(val) bfin_write16(DMA1_9_Y_MODIFY, val) 444 #define pDMA1_9_CURR_DESC_PTR ((void * volatile *)DMA1_9_CURR_DESC_PTR) 445 #define bfin_read_DMA1_9_CURR_DESC_PTR() bfin_readPTR(DMA1_9_CURR_DESC_PTR) 446 #define bfin_write_DMA1_9_CURR_DESC_PTR(val) bfin_writePTR(DMA1_9_CURR_DESC_PTR, val) 447 #define pDMA1_9_CURR_ADDR ((void * volatile *)DMA1_9_CURR_ADDR) 448 #define bfin_read_DMA1_9_CURR_ADDR() bfin_readPTR(DMA1_9_CURR_ADDR) 449 #define bfin_write_DMA1_9_CURR_ADDR(val) bfin_writePTR(DMA1_9_CURR_ADDR, val) 450 #define pDMA1_9_CURR_X_COUNT ((uint16_t volatile *)DMA1_9_CURR_X_COUNT) 451 #define bfin_read_DMA1_9_CURR_X_COUNT() bfin_read16(DMA1_9_CURR_X_COUNT) 452 #define bfin_write_DMA1_9_CURR_X_COUNT(val) bfin_write16(DMA1_9_CURR_X_COUNT, val) 453 #define pDMA1_9_CURR_Y_COUNT ((uint16_t volatile *)DMA1_9_CURR_Y_COUNT) 454 #define bfin_read_DMA1_9_CURR_Y_COUNT() bfin_read16(DMA1_9_CURR_Y_COUNT) 455 #define bfin_write_DMA1_9_CURR_Y_COUNT(val) bfin_write16(DMA1_9_CURR_Y_COUNT, val) 456 #define pDMA1_9_IRQ_STATUS ((uint16_t volatile *)DMA1_9_IRQ_STATUS) 457 #define bfin_read_DMA1_9_IRQ_STATUS() bfin_read16(DMA1_9_IRQ_STATUS) 458 #define bfin_write_DMA1_9_IRQ_STATUS(val) bfin_write16(DMA1_9_IRQ_STATUS, val) 459 #define pDMA1_9_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_9_PERIPHERAL_MAP) 460 #define bfin_read_DMA1_9_PERIPHERAL_MAP() bfin_read16(DMA1_9_PERIPHERAL_MAP) 461 #define bfin_write_DMA1_9_PERIPHERAL_MAP(val) bfin_write16(DMA1_9_PERIPHERAL_MAP, val) 462 #define pDMA1_10_CONFIG ((uint16_t volatile *)DMA1_10_CONFIG) 463 #define bfin_read_DMA1_10_CONFIG() bfin_read16(DMA1_10_CONFIG) 464 #define bfin_write_DMA1_10_CONFIG(val) bfin_write16(DMA1_10_CONFIG, val) 465 #define pDMA1_10_NEXT_DESC_PTR ((void * volatile *)DMA1_10_NEXT_DESC_PTR) 466 #define bfin_read_DMA1_10_NEXT_DESC_PTR() bfin_readPTR(DMA1_10_NEXT_DESC_PTR) 467 #define bfin_write_DMA1_10_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_10_NEXT_DESC_PTR, val) 468 #define pDMA1_10_START_ADDR ((void * volatile *)DMA1_10_START_ADDR) 469 #define bfin_read_DMA1_10_START_ADDR() bfin_readPTR(DMA1_10_START_ADDR) 470 #define bfin_write_DMA1_10_START_ADDR(val) bfin_writePTR(DMA1_10_START_ADDR, val) 471 #define pDMA1_10_X_COUNT ((uint16_t volatile *)DMA1_10_X_COUNT) 472 #define bfin_read_DMA1_10_X_COUNT() bfin_read16(DMA1_10_X_COUNT) 473 #define bfin_write_DMA1_10_X_COUNT(val) bfin_write16(DMA1_10_X_COUNT, val) 474 #define pDMA1_10_Y_COUNT ((uint16_t volatile *)DMA1_10_Y_COUNT) 475 #define bfin_read_DMA1_10_Y_COUNT() bfin_read16(DMA1_10_Y_COUNT) 476 #define bfin_write_DMA1_10_Y_COUNT(val) bfin_write16(DMA1_10_Y_COUNT, val) 477 #define pDMA1_10_X_MODIFY ((uint16_t volatile *)DMA1_10_X_MODIFY) 478 #define bfin_read_DMA1_10_X_MODIFY() bfin_read16(DMA1_10_X_MODIFY) 479 #define bfin_write_DMA1_10_X_MODIFY(val) bfin_write16(DMA1_10_X_MODIFY, val) 480 #define pDMA1_10_Y_MODIFY ((uint16_t volatile *)DMA1_10_Y_MODIFY) 481 #define bfin_read_DMA1_10_Y_MODIFY() bfin_read16(DMA1_10_Y_MODIFY) 482 #define bfin_write_DMA1_10_Y_MODIFY(val) bfin_write16(DMA1_10_Y_MODIFY, val) 483 #define pDMA1_10_CURR_DESC_PTR ((void * volatile *)DMA1_10_CURR_DESC_PTR) 484 #define bfin_read_DMA1_10_CURR_DESC_PTR() bfin_readPTR(DMA1_10_CURR_DESC_PTR) 485 #define bfin_write_DMA1_10_CURR_DESC_PTR(val) bfin_writePTR(DMA1_10_CURR_DESC_PTR, val) 486 #define pDMA1_10_CURR_ADDR ((void * volatile *)DMA1_10_CURR_ADDR) 487 #define bfin_read_DMA1_10_CURR_ADDR() bfin_readPTR(DMA1_10_CURR_ADDR) 488 #define bfin_write_DMA1_10_CURR_ADDR(val) bfin_writePTR(DMA1_10_CURR_ADDR, val) 489 #define pDMA1_10_CURR_X_COUNT ((uint16_t volatile *)DMA1_10_CURR_X_COUNT) 490 #define bfin_read_DMA1_10_CURR_X_COUNT() bfin_read16(DMA1_10_CURR_X_COUNT) 491 #define bfin_write_DMA1_10_CURR_X_COUNT(val) bfin_write16(DMA1_10_CURR_X_COUNT, val) 492 #define pDMA1_10_CURR_Y_COUNT ((uint16_t volatile *)DMA1_10_CURR_Y_COUNT) 493 #define bfin_read_DMA1_10_CURR_Y_COUNT() bfin_read16(DMA1_10_CURR_Y_COUNT) 494 #define bfin_write_DMA1_10_CURR_Y_COUNT(val) bfin_write16(DMA1_10_CURR_Y_COUNT, val) 495 #define pDMA1_10_IRQ_STATUS ((uint16_t volatile *)DMA1_10_IRQ_STATUS) 496 #define bfin_read_DMA1_10_IRQ_STATUS() bfin_read16(DMA1_10_IRQ_STATUS) 497 #define bfin_write_DMA1_10_IRQ_STATUS(val) bfin_write16(DMA1_10_IRQ_STATUS, val) 498 #define pDMA1_10_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_10_PERIPHERAL_MAP) 499 #define bfin_read_DMA1_10_PERIPHERAL_MAP() bfin_read16(DMA1_10_PERIPHERAL_MAP) 500 #define bfin_write_DMA1_10_PERIPHERAL_MAP(val) bfin_write16(DMA1_10_PERIPHERAL_MAP, val) 501 #define pDMA1_11_CONFIG ((uint16_t volatile *)DMA1_11_CONFIG) 502 #define bfin_read_DMA1_11_CONFIG() bfin_read16(DMA1_11_CONFIG) 503 #define bfin_write_DMA1_11_CONFIG(val) bfin_write16(DMA1_11_CONFIG, val) 504 #define pDMA1_11_NEXT_DESC_PTR ((void * volatile *)DMA1_11_NEXT_DESC_PTR) 505 #define bfin_read_DMA1_11_NEXT_DESC_PTR() bfin_readPTR(DMA1_11_NEXT_DESC_PTR) 506 #define bfin_write_DMA1_11_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_11_NEXT_DESC_PTR, val) 507 #define pDMA1_11_START_ADDR ((void * volatile *)DMA1_11_START_ADDR) 508 #define bfin_read_DMA1_11_START_ADDR() bfin_readPTR(DMA1_11_START_ADDR) 509 #define bfin_write_DMA1_11_START_ADDR(val) bfin_writePTR(DMA1_11_START_ADDR, val) 510 #define pDMA1_11_X_COUNT ((uint16_t volatile *)DMA1_11_X_COUNT) 511 #define bfin_read_DMA1_11_X_COUNT() bfin_read16(DMA1_11_X_COUNT) 512 #define bfin_write_DMA1_11_X_COUNT(val) bfin_write16(DMA1_11_X_COUNT, val) 513 #define pDMA1_11_Y_COUNT ((uint16_t volatile *)DMA1_11_Y_COUNT) 514 #define bfin_read_DMA1_11_Y_COUNT() bfin_read16(DMA1_11_Y_COUNT) 515 #define bfin_write_DMA1_11_Y_COUNT(val) bfin_write16(DMA1_11_Y_COUNT, val) 516 #define pDMA1_11_X_MODIFY ((uint16_t volatile *)DMA1_11_X_MODIFY) 517 #define bfin_read_DMA1_11_X_MODIFY() bfin_read16(DMA1_11_X_MODIFY) 518 #define bfin_write_DMA1_11_X_MODIFY(val) bfin_write16(DMA1_11_X_MODIFY, val) 519 #define pDMA1_11_Y_MODIFY ((uint16_t volatile *)DMA1_11_Y_MODIFY) 520 #define bfin_read_DMA1_11_Y_MODIFY() bfin_read16(DMA1_11_Y_MODIFY) 521 #define bfin_write_DMA1_11_Y_MODIFY(val) bfin_write16(DMA1_11_Y_MODIFY, val) 522 #define pDMA1_11_CURR_DESC_PTR ((void * volatile *)DMA1_11_CURR_DESC_PTR) 523 #define bfin_read_DMA1_11_CURR_DESC_PTR() bfin_readPTR(DMA1_11_CURR_DESC_PTR) 524 #define bfin_write_DMA1_11_CURR_DESC_PTR(val) bfin_writePTR(DMA1_11_CURR_DESC_PTR, val) 525 #define pDMA1_11_CURR_ADDR ((void * volatile *)DMA1_11_CURR_ADDR) 526 #define bfin_read_DMA1_11_CURR_ADDR() bfin_readPTR(DMA1_11_CURR_ADDR) 527 #define bfin_write_DMA1_11_CURR_ADDR(val) bfin_writePTR(DMA1_11_CURR_ADDR, val) 528 #define pDMA1_11_CURR_X_COUNT ((uint16_t volatile *)DMA1_11_CURR_X_COUNT) 529 #define bfin_read_DMA1_11_CURR_X_COUNT() bfin_read16(DMA1_11_CURR_X_COUNT) 530 #define bfin_write_DMA1_11_CURR_X_COUNT(val) bfin_write16(DMA1_11_CURR_X_COUNT, val) 531 #define pDMA1_11_CURR_Y_COUNT ((uint16_t volatile *)DMA1_11_CURR_Y_COUNT) 532 #define bfin_read_DMA1_11_CURR_Y_COUNT() bfin_read16(DMA1_11_CURR_Y_COUNT) 533 #define bfin_write_DMA1_11_CURR_Y_COUNT(val) bfin_write16(DMA1_11_CURR_Y_COUNT, val) 534 #define pDMA1_11_IRQ_STATUS ((uint16_t volatile *)DMA1_11_IRQ_STATUS) 535 #define bfin_read_DMA1_11_IRQ_STATUS() bfin_read16(DMA1_11_IRQ_STATUS) 536 #define bfin_write_DMA1_11_IRQ_STATUS(val) bfin_write16(DMA1_11_IRQ_STATUS, val) 537 #define pDMA1_11_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_11_PERIPHERAL_MAP) 538 #define bfin_read_DMA1_11_PERIPHERAL_MAP() bfin_read16(DMA1_11_PERIPHERAL_MAP) 539 #define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP, val) 540 #define pDMA2_TC_PER ((uint16_t volatile *)DMA2_TC_PER) 541 #define bfin_read_DMA2_TC_PER() bfin_read16(DMA2_TC_PER) 542 #define bfin_write_DMA2_TC_PER(val) bfin_write16(DMA2_TC_PER, val) 543 #define pDMA2_TC_CNT ((uint16_t volatile *)DMA2_TC_CNT) /* Traffic Control Current Counts */ 544 #define bfin_read_DMA2_TC_CNT() bfin_read16(DMA2_TC_CNT) 545 #define bfin_write_DMA2_TC_CNT(val) bfin_write16(DMA2_TC_CNT, val) 546 #define pDMA2_0_CONFIG ((uint16_t volatile *)DMA2_0_CONFIG) 547 #define bfin_read_DMA2_0_CONFIG() bfin_read16(DMA2_0_CONFIG) 548 #define bfin_write_DMA2_0_CONFIG(val) bfin_write16(DMA2_0_CONFIG, val) 549 #define pDMA2_0_NEXT_DESC_PTR ((void * volatile *)DMA2_0_NEXT_DESC_PTR) 550 #define bfin_read_DMA2_0_NEXT_DESC_PTR() bfin_readPTR(DMA2_0_NEXT_DESC_PTR) 551 #define bfin_write_DMA2_0_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_0_NEXT_DESC_PTR, val) 552 #define pDMA2_0_START_ADDR ((void * volatile *)DMA2_0_START_ADDR) 553 #define bfin_read_DMA2_0_START_ADDR() bfin_readPTR(DMA2_0_START_ADDR) 554 #define bfin_write_DMA2_0_START_ADDR(val) bfin_writePTR(DMA2_0_START_ADDR, val) 555 #define pDMA2_0_X_COUNT ((uint16_t volatile *)DMA2_0_X_COUNT) 556 #define bfin_read_DMA2_0_X_COUNT() bfin_read16(DMA2_0_X_COUNT) 557 #define bfin_write_DMA2_0_X_COUNT(val) bfin_write16(DMA2_0_X_COUNT, val) 558 #define pDMA2_0_Y_COUNT ((uint16_t volatile *)DMA2_0_Y_COUNT) 559 #define bfin_read_DMA2_0_Y_COUNT() bfin_read16(DMA2_0_Y_COUNT) 560 #define bfin_write_DMA2_0_Y_COUNT(val) bfin_write16(DMA2_0_Y_COUNT, val) 561 #define pDMA2_0_X_MODIFY ((uint16_t volatile *)DMA2_0_X_MODIFY) 562 #define bfin_read_DMA2_0_X_MODIFY() bfin_read16(DMA2_0_X_MODIFY) 563 #define bfin_write_DMA2_0_X_MODIFY(val) bfin_write16(DMA2_0_X_MODIFY, val) 564 #define pDMA2_0_Y_MODIFY ((uint16_t volatile *)DMA2_0_Y_MODIFY) 565 #define bfin_read_DMA2_0_Y_MODIFY() bfin_read16(DMA2_0_Y_MODIFY) 566 #define bfin_write_DMA2_0_Y_MODIFY(val) bfin_write16(DMA2_0_Y_MODIFY, val) 567 #define pDMA2_0_CURR_DESC_PTR ((void * volatile *)DMA2_0_CURR_DESC_PTR) 568 #define bfin_read_DMA2_0_CURR_DESC_PTR() bfin_readPTR(DMA2_0_CURR_DESC_PTR) 569 #define bfin_write_DMA2_0_CURR_DESC_PTR(val) bfin_writePTR(DMA2_0_CURR_DESC_PTR, val) 570 #define pDMA2_0_CURR_ADDR ((void * volatile *)DMA2_0_CURR_ADDR) 571 #define bfin_read_DMA2_0_CURR_ADDR() bfin_readPTR(DMA2_0_CURR_ADDR) 572 #define bfin_write_DMA2_0_CURR_ADDR(val) bfin_writePTR(DMA2_0_CURR_ADDR, val) 573 #define pDMA2_0_CURR_X_COUNT ((uint16_t volatile *)DMA2_0_CURR_X_COUNT) 574 #define bfin_read_DMA2_0_CURR_X_COUNT() bfin_read16(DMA2_0_CURR_X_COUNT) 575 #define bfin_write_DMA2_0_CURR_X_COUNT(val) bfin_write16(DMA2_0_CURR_X_COUNT, val) 576 #define pDMA2_0_CURR_Y_COUNT ((uint16_t volatile *)DMA2_0_CURR_Y_COUNT) 577 #define bfin_read_DMA2_0_CURR_Y_COUNT() bfin_read16(DMA2_0_CURR_Y_COUNT) 578 #define bfin_write_DMA2_0_CURR_Y_COUNT(val) bfin_write16(DMA2_0_CURR_Y_COUNT, val) 579 #define pDMA2_0_IRQ_STATUS ((uint16_t volatile *)DMA2_0_IRQ_STATUS) 580 #define bfin_read_DMA2_0_IRQ_STATUS() bfin_read16(DMA2_0_IRQ_STATUS) 581 #define bfin_write_DMA2_0_IRQ_STATUS(val) bfin_write16(DMA2_0_IRQ_STATUS, val) 582 #define pDMA2_0_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_0_PERIPHERAL_MAP) 583 #define bfin_read_DMA2_0_PERIPHERAL_MAP() bfin_read16(DMA2_0_PERIPHERAL_MAP) 584 #define bfin_write_DMA2_0_PERIPHERAL_MAP(val) bfin_write16(DMA2_0_PERIPHERAL_MAP, val) 585 #define pDMA2_1_CONFIG ((uint16_t volatile *)DMA2_1_CONFIG) 586 #define bfin_read_DMA2_1_CONFIG() bfin_read16(DMA2_1_CONFIG) 587 #define bfin_write_DMA2_1_CONFIG(val) bfin_write16(DMA2_1_CONFIG, val) 588 #define pDMA2_1_NEXT_DESC_PTR ((void * volatile *)DMA2_1_NEXT_DESC_PTR) 589 #define bfin_read_DMA2_1_NEXT_DESC_PTR() bfin_readPTR(DMA2_1_NEXT_DESC_PTR) 590 #define bfin_write_DMA2_1_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_1_NEXT_DESC_PTR, val) 591 #define pDMA2_1_START_ADDR ((void * volatile *)DMA2_1_START_ADDR) 592 #define bfin_read_DMA2_1_START_ADDR() bfin_readPTR(DMA2_1_START_ADDR) 593 #define bfin_write_DMA2_1_START_ADDR(val) bfin_writePTR(DMA2_1_START_ADDR, val) 594 #define pDMA2_1_X_COUNT ((uint16_t volatile *)DMA2_1_X_COUNT) 595 #define bfin_read_DMA2_1_X_COUNT() bfin_read16(DMA2_1_X_COUNT) 596 #define bfin_write_DMA2_1_X_COUNT(val) bfin_write16(DMA2_1_X_COUNT, val) 597 #define pDMA2_1_Y_COUNT ((uint16_t volatile *)DMA2_1_Y_COUNT) 598 #define bfin_read_DMA2_1_Y_COUNT() bfin_read16(DMA2_1_Y_COUNT) 599 #define bfin_write_DMA2_1_Y_COUNT(val) bfin_write16(DMA2_1_Y_COUNT, val) 600 #define pDMA2_1_X_MODIFY ((uint16_t volatile *)DMA2_1_X_MODIFY) 601 #define bfin_read_DMA2_1_X_MODIFY() bfin_read16(DMA2_1_X_MODIFY) 602 #define bfin_write_DMA2_1_X_MODIFY(val) bfin_write16(DMA2_1_X_MODIFY, val) 603 #define pDMA2_1_Y_MODIFY ((uint16_t volatile *)DMA2_1_Y_MODIFY) 604 #define bfin_read_DMA2_1_Y_MODIFY() bfin_read16(DMA2_1_Y_MODIFY) 605 #define bfin_write_DMA2_1_Y_MODIFY(val) bfin_write16(DMA2_1_Y_MODIFY, val) 606 #define pDMA2_1_CURR_DESC_PTR ((void * volatile *)DMA2_1_CURR_DESC_PTR) 607 #define bfin_read_DMA2_1_CURR_DESC_PTR() bfin_readPTR(DMA2_1_CURR_DESC_PTR) 608 #define bfin_write_DMA2_1_CURR_DESC_PTR(val) bfin_writePTR(DMA2_1_CURR_DESC_PTR, val) 609 #define pDMA2_1_CURR_ADDR ((void * volatile *)DMA2_1_CURR_ADDR) 610 #define bfin_read_DMA2_1_CURR_ADDR() bfin_readPTR(DMA2_1_CURR_ADDR) 611 #define bfin_write_DMA2_1_CURR_ADDR(val) bfin_writePTR(DMA2_1_CURR_ADDR, val) 612 #define pDMA2_1_CURR_X_COUNT ((uint16_t volatile *)DMA2_1_CURR_X_COUNT) 613 #define bfin_read_DMA2_1_CURR_X_COUNT() bfin_read16(DMA2_1_CURR_X_COUNT) 614 #define bfin_write_DMA2_1_CURR_X_COUNT(val) bfin_write16(DMA2_1_CURR_X_COUNT, val) 615 #define pDMA2_1_CURR_Y_COUNT ((uint16_t volatile *)DMA2_1_CURR_Y_COUNT) 616 #define bfin_read_DMA2_1_CURR_Y_COUNT() bfin_read16(DMA2_1_CURR_Y_COUNT) 617 #define bfin_write_DMA2_1_CURR_Y_COUNT(val) bfin_write16(DMA2_1_CURR_Y_COUNT, val) 618 #define pDMA2_1_IRQ_STATUS ((uint16_t volatile *)DMA2_1_IRQ_STATUS) 619 #define bfin_read_DMA2_1_IRQ_STATUS() bfin_read16(DMA2_1_IRQ_STATUS) 620 #define bfin_write_DMA2_1_IRQ_STATUS(val) bfin_write16(DMA2_1_IRQ_STATUS, val) 621 #define pDMA2_1_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_1_PERIPHERAL_MAP) 622 #define bfin_read_DMA2_1_PERIPHERAL_MAP() bfin_read16(DMA2_1_PERIPHERAL_MAP) 623 #define bfin_write_DMA2_1_PERIPHERAL_MAP(val) bfin_write16(DMA2_1_PERIPHERAL_MAP, val) 624 #define pDMA2_2_CONFIG ((uint16_t volatile *)DMA2_2_CONFIG) 625 #define bfin_read_DMA2_2_CONFIG() bfin_read16(DMA2_2_CONFIG) 626 #define bfin_write_DMA2_2_CONFIG(val) bfin_write16(DMA2_2_CONFIG, val) 627 #define pDMA2_2_NEXT_DESC_PTR ((void * volatile *)DMA2_2_NEXT_DESC_PTR) 628 #define bfin_read_DMA2_2_NEXT_DESC_PTR() bfin_readPTR(DMA2_2_NEXT_DESC_PTR) 629 #define bfin_write_DMA2_2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_2_NEXT_DESC_PTR, val) 630 #define pDMA2_2_START_ADDR ((void * volatile *)DMA2_2_START_ADDR) 631 #define bfin_read_DMA2_2_START_ADDR() bfin_readPTR(DMA2_2_START_ADDR) 632 #define bfin_write_DMA2_2_START_ADDR(val) bfin_writePTR(DMA2_2_START_ADDR, val) 633 #define pDMA2_2_X_COUNT ((uint16_t volatile *)DMA2_2_X_COUNT) 634 #define bfin_read_DMA2_2_X_COUNT() bfin_read16(DMA2_2_X_COUNT) 635 #define bfin_write_DMA2_2_X_COUNT(val) bfin_write16(DMA2_2_X_COUNT, val) 636 #define pDMA2_2_Y_COUNT ((uint16_t volatile *)DMA2_2_Y_COUNT) 637 #define bfin_read_DMA2_2_Y_COUNT() bfin_read16(DMA2_2_Y_COUNT) 638 #define bfin_write_DMA2_2_Y_COUNT(val) bfin_write16(DMA2_2_Y_COUNT, val) 639 #define pDMA2_2_X_MODIFY ((uint16_t volatile *)DMA2_2_X_MODIFY) 640 #define bfin_read_DMA2_2_X_MODIFY() bfin_read16(DMA2_2_X_MODIFY) 641 #define bfin_write_DMA2_2_X_MODIFY(val) bfin_write16(DMA2_2_X_MODIFY, val) 642 #define pDMA2_2_Y_MODIFY ((uint16_t volatile *)DMA2_2_Y_MODIFY) 643 #define bfin_read_DMA2_2_Y_MODIFY() bfin_read16(DMA2_2_Y_MODIFY) 644 #define bfin_write_DMA2_2_Y_MODIFY(val) bfin_write16(DMA2_2_Y_MODIFY, val) 645 #define pDMA2_2_CURR_DESC_PTR ((void * volatile *)DMA2_2_CURR_DESC_PTR) 646 #define bfin_read_DMA2_2_CURR_DESC_PTR() bfin_readPTR(DMA2_2_CURR_DESC_PTR) 647 #define bfin_write_DMA2_2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_2_CURR_DESC_PTR, val) 648 #define pDMA2_2_CURR_ADDR ((void * volatile *)DMA2_2_CURR_ADDR) 649 #define bfin_read_DMA2_2_CURR_ADDR() bfin_readPTR(DMA2_2_CURR_ADDR) 650 #define bfin_write_DMA2_2_CURR_ADDR(val) bfin_writePTR(DMA2_2_CURR_ADDR, val) 651 #define pDMA2_2_CURR_X_COUNT ((uint16_t volatile *)DMA2_2_CURR_X_COUNT) 652 #define bfin_read_DMA2_2_CURR_X_COUNT() bfin_read16(DMA2_2_CURR_X_COUNT) 653 #define bfin_write_DMA2_2_CURR_X_COUNT(val) bfin_write16(DMA2_2_CURR_X_COUNT, val) 654 #define pDMA2_2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_2_CURR_Y_COUNT) 655 #define bfin_read_DMA2_2_CURR_Y_COUNT() bfin_read16(DMA2_2_CURR_Y_COUNT) 656 #define bfin_write_DMA2_2_CURR_Y_COUNT(val) bfin_write16(DMA2_2_CURR_Y_COUNT, val) 657 #define pDMA2_2_IRQ_STATUS ((uint16_t volatile *)DMA2_2_IRQ_STATUS) 658 #define bfin_read_DMA2_2_IRQ_STATUS() bfin_read16(DMA2_2_IRQ_STATUS) 659 #define bfin_write_DMA2_2_IRQ_STATUS(val) bfin_write16(DMA2_2_IRQ_STATUS, val) 660 #define pDMA2_2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_2_PERIPHERAL_MAP) 661 #define bfin_read_DMA2_2_PERIPHERAL_MAP() bfin_read16(DMA2_2_PERIPHERAL_MAP) 662 #define bfin_write_DMA2_2_PERIPHERAL_MAP(val) bfin_write16(DMA2_2_PERIPHERAL_MAP, val) 663 #define pDMA2_3_CONFIG ((uint16_t volatile *)DMA2_3_CONFIG) 664 #define bfin_read_DMA2_3_CONFIG() bfin_read16(DMA2_3_CONFIG) 665 #define bfin_write_DMA2_3_CONFIG(val) bfin_write16(DMA2_3_CONFIG, val) 666 #define pDMA2_3_NEXT_DESC_PTR ((void * volatile *)DMA2_3_NEXT_DESC_PTR) 667 #define bfin_read_DMA2_3_NEXT_DESC_PTR() bfin_readPTR(DMA2_3_NEXT_DESC_PTR) 668 #define bfin_write_DMA2_3_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_3_NEXT_DESC_PTR, val) 669 #define pDMA2_3_START_ADDR ((void * volatile *)DMA2_3_START_ADDR) 670 #define bfin_read_DMA2_3_START_ADDR() bfin_readPTR(DMA2_3_START_ADDR) 671 #define bfin_write_DMA2_3_START_ADDR(val) bfin_writePTR(DMA2_3_START_ADDR, val) 672 #define pDMA2_3_X_COUNT ((uint16_t volatile *)DMA2_3_X_COUNT) 673 #define bfin_read_DMA2_3_X_COUNT() bfin_read16(DMA2_3_X_COUNT) 674 #define bfin_write_DMA2_3_X_COUNT(val) bfin_write16(DMA2_3_X_COUNT, val) 675 #define pDMA2_3_Y_COUNT ((uint16_t volatile *)DMA2_3_Y_COUNT) 676 #define bfin_read_DMA2_3_Y_COUNT() bfin_read16(DMA2_3_Y_COUNT) 677 #define bfin_write_DMA2_3_Y_COUNT(val) bfin_write16(DMA2_3_Y_COUNT, val) 678 #define pDMA2_3_X_MODIFY ((uint16_t volatile *)DMA2_3_X_MODIFY) 679 #define bfin_read_DMA2_3_X_MODIFY() bfin_read16(DMA2_3_X_MODIFY) 680 #define bfin_write_DMA2_3_X_MODIFY(val) bfin_write16(DMA2_3_X_MODIFY, val) 681 #define pDMA2_3_Y_MODIFY ((uint16_t volatile *)DMA2_3_Y_MODIFY) 682 #define bfin_read_DMA2_3_Y_MODIFY() bfin_read16(DMA2_3_Y_MODIFY) 683 #define bfin_write_DMA2_3_Y_MODIFY(val) bfin_write16(DMA2_3_Y_MODIFY, val) 684 #define pDMA2_3_CURR_DESC_PTR ((void * volatile *)DMA2_3_CURR_DESC_PTR) 685 #define bfin_read_DMA2_3_CURR_DESC_PTR() bfin_readPTR(DMA2_3_CURR_DESC_PTR) 686 #define bfin_write_DMA2_3_CURR_DESC_PTR(val) bfin_writePTR(DMA2_3_CURR_DESC_PTR, val) 687 #define pDMA2_3_CURR_ADDR ((void * volatile *)DMA2_3_CURR_ADDR) 688 #define bfin_read_DMA2_3_CURR_ADDR() bfin_readPTR(DMA2_3_CURR_ADDR) 689 #define bfin_write_DMA2_3_CURR_ADDR(val) bfin_writePTR(DMA2_3_CURR_ADDR, val) 690 #define pDMA2_3_CURR_X_COUNT ((uint16_t volatile *)DMA2_3_CURR_X_COUNT) 691 #define bfin_read_DMA2_3_CURR_X_COUNT() bfin_read16(DMA2_3_CURR_X_COUNT) 692 #define bfin_write_DMA2_3_CURR_X_COUNT(val) bfin_write16(DMA2_3_CURR_X_COUNT, val) 693 #define pDMA2_3_CURR_Y_COUNT ((uint16_t volatile *)DMA2_3_CURR_Y_COUNT) 694 #define bfin_read_DMA2_3_CURR_Y_COUNT() bfin_read16(DMA2_3_CURR_Y_COUNT) 695 #define bfin_write_DMA2_3_CURR_Y_COUNT(val) bfin_write16(DMA2_3_CURR_Y_COUNT, val) 696 #define pDMA2_3_IRQ_STATUS ((uint16_t volatile *)DMA2_3_IRQ_STATUS) 697 #define bfin_read_DMA2_3_IRQ_STATUS() bfin_read16(DMA2_3_IRQ_STATUS) 698 #define bfin_write_DMA2_3_IRQ_STATUS(val) bfin_write16(DMA2_3_IRQ_STATUS, val) 699 #define pDMA2_3_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_3_PERIPHERAL_MAP) 700 #define bfin_read_DMA2_3_PERIPHERAL_MAP() bfin_read16(DMA2_3_PERIPHERAL_MAP) 701 #define bfin_write_DMA2_3_PERIPHERAL_MAP(val) bfin_write16(DMA2_3_PERIPHERAL_MAP, val) 702 #define pDMA2_4_CONFIG ((uint16_t volatile *)DMA2_4_CONFIG) 703 #define bfin_read_DMA2_4_CONFIG() bfin_read16(DMA2_4_CONFIG) 704 #define bfin_write_DMA2_4_CONFIG(val) bfin_write16(DMA2_4_CONFIG, val) 705 #define pDMA2_4_NEXT_DESC_PTR ((void * volatile *)DMA2_4_NEXT_DESC_PTR) 706 #define bfin_read_DMA2_4_NEXT_DESC_PTR() bfin_readPTR(DMA2_4_NEXT_DESC_PTR) 707 #define bfin_write_DMA2_4_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_4_NEXT_DESC_PTR, val) 708 #define pDMA2_4_START_ADDR ((void * volatile *)DMA2_4_START_ADDR) 709 #define bfin_read_DMA2_4_START_ADDR() bfin_readPTR(DMA2_4_START_ADDR) 710 #define bfin_write_DMA2_4_START_ADDR(val) bfin_writePTR(DMA2_4_START_ADDR, val) 711 #define pDMA2_4_X_COUNT ((uint16_t volatile *)DMA2_4_X_COUNT) 712 #define bfin_read_DMA2_4_X_COUNT() bfin_read16(DMA2_4_X_COUNT) 713 #define bfin_write_DMA2_4_X_COUNT(val) bfin_write16(DMA2_4_X_COUNT, val) 714 #define pDMA2_4_Y_COUNT ((uint16_t volatile *)DMA2_4_Y_COUNT) 715 #define bfin_read_DMA2_4_Y_COUNT() bfin_read16(DMA2_4_Y_COUNT) 716 #define bfin_write_DMA2_4_Y_COUNT(val) bfin_write16(DMA2_4_Y_COUNT, val) 717 #define pDMA2_4_X_MODIFY ((uint16_t volatile *)DMA2_4_X_MODIFY) 718 #define bfin_read_DMA2_4_X_MODIFY() bfin_read16(DMA2_4_X_MODIFY) 719 #define bfin_write_DMA2_4_X_MODIFY(val) bfin_write16(DMA2_4_X_MODIFY, val) 720 #define pDMA2_4_Y_MODIFY ((uint16_t volatile *)DMA2_4_Y_MODIFY) 721 #define bfin_read_DMA2_4_Y_MODIFY() bfin_read16(DMA2_4_Y_MODIFY) 722 #define bfin_write_DMA2_4_Y_MODIFY(val) bfin_write16(DMA2_4_Y_MODIFY, val) 723 #define pDMA2_4_CURR_DESC_PTR ((void * volatile *)DMA2_4_CURR_DESC_PTR) 724 #define bfin_read_DMA2_4_CURR_DESC_PTR() bfin_readPTR(DMA2_4_CURR_DESC_PTR) 725 #define bfin_write_DMA2_4_CURR_DESC_PTR(val) bfin_writePTR(DMA2_4_CURR_DESC_PTR, val) 726 #define pDMA2_4_CURR_ADDR ((void * volatile *)DMA2_4_CURR_ADDR) 727 #define bfin_read_DMA2_4_CURR_ADDR() bfin_readPTR(DMA2_4_CURR_ADDR) 728 #define bfin_write_DMA2_4_CURR_ADDR(val) bfin_writePTR(DMA2_4_CURR_ADDR, val) 729 #define pDMA2_4_CURR_X_COUNT ((uint16_t volatile *)DMA2_4_CURR_X_COUNT) 730 #define bfin_read_DMA2_4_CURR_X_COUNT() bfin_read16(DMA2_4_CURR_X_COUNT) 731 #define bfin_write_DMA2_4_CURR_X_COUNT(val) bfin_write16(DMA2_4_CURR_X_COUNT, val) 732 #define pDMA2_4_CURR_Y_COUNT ((uint16_t volatile *)DMA2_4_CURR_Y_COUNT) 733 #define bfin_read_DMA2_4_CURR_Y_COUNT() bfin_read16(DMA2_4_CURR_Y_COUNT) 734 #define bfin_write_DMA2_4_CURR_Y_COUNT(val) bfin_write16(DMA2_4_CURR_Y_COUNT, val) 735 #define pDMA2_4_IRQ_STATUS ((uint16_t volatile *)DMA2_4_IRQ_STATUS) 736 #define bfin_read_DMA2_4_IRQ_STATUS() bfin_read16(DMA2_4_IRQ_STATUS) 737 #define bfin_write_DMA2_4_IRQ_STATUS(val) bfin_write16(DMA2_4_IRQ_STATUS, val) 738 #define pDMA2_4_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_4_PERIPHERAL_MAP) 739 #define bfin_read_DMA2_4_PERIPHERAL_MAP() bfin_read16(DMA2_4_PERIPHERAL_MAP) 740 #define bfin_write_DMA2_4_PERIPHERAL_MAP(val) bfin_write16(DMA2_4_PERIPHERAL_MAP, val) 741 #define pDMA2_5_CONFIG ((uint16_t volatile *)DMA2_5_CONFIG) 742 #define bfin_read_DMA2_5_CONFIG() bfin_read16(DMA2_5_CONFIG) 743 #define bfin_write_DMA2_5_CONFIG(val) bfin_write16(DMA2_5_CONFIG, val) 744 #define pDMA2_5_NEXT_DESC_PTR ((void * volatile *)DMA2_5_NEXT_DESC_PTR) 745 #define bfin_read_DMA2_5_NEXT_DESC_PTR() bfin_readPTR(DMA2_5_NEXT_DESC_PTR) 746 #define bfin_write_DMA2_5_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_5_NEXT_DESC_PTR, val) 747 #define pDMA2_5_START_ADDR ((void * volatile *)DMA2_5_START_ADDR) 748 #define bfin_read_DMA2_5_START_ADDR() bfin_readPTR(DMA2_5_START_ADDR) 749 #define bfin_write_DMA2_5_START_ADDR(val) bfin_writePTR(DMA2_5_START_ADDR, val) 750 #define pDMA2_5_X_COUNT ((uint16_t volatile *)DMA2_5_X_COUNT) 751 #define bfin_read_DMA2_5_X_COUNT() bfin_read16(DMA2_5_X_COUNT) 752 #define bfin_write_DMA2_5_X_COUNT(val) bfin_write16(DMA2_5_X_COUNT, val) 753 #define pDMA2_5_Y_COUNT ((uint16_t volatile *)DMA2_5_Y_COUNT) 754 #define bfin_read_DMA2_5_Y_COUNT() bfin_read16(DMA2_5_Y_COUNT) 755 #define bfin_write_DMA2_5_Y_COUNT(val) bfin_write16(DMA2_5_Y_COUNT, val) 756 #define pDMA2_5_X_MODIFY ((uint16_t volatile *)DMA2_5_X_MODIFY) 757 #define bfin_read_DMA2_5_X_MODIFY() bfin_read16(DMA2_5_X_MODIFY) 758 #define bfin_write_DMA2_5_X_MODIFY(val) bfin_write16(DMA2_5_X_MODIFY, val) 759 #define pDMA2_5_Y_MODIFY ((uint16_t volatile *)DMA2_5_Y_MODIFY) 760 #define bfin_read_DMA2_5_Y_MODIFY() bfin_read16(DMA2_5_Y_MODIFY) 761 #define bfin_write_DMA2_5_Y_MODIFY(val) bfin_write16(DMA2_5_Y_MODIFY, val) 762 #define pDMA2_5_CURR_DESC_PTR ((void * volatile *)DMA2_5_CURR_DESC_PTR) 763 #define bfin_read_DMA2_5_CURR_DESC_PTR() bfin_readPTR(DMA2_5_CURR_DESC_PTR) 764 #define bfin_write_DMA2_5_CURR_DESC_PTR(val) bfin_writePTR(DMA2_5_CURR_DESC_PTR, val) 765 #define pDMA2_5_CURR_ADDR ((void * volatile *)DMA2_5_CURR_ADDR) 766 #define bfin_read_DMA2_5_CURR_ADDR() bfin_readPTR(DMA2_5_CURR_ADDR) 767 #define bfin_write_DMA2_5_CURR_ADDR(val) bfin_writePTR(DMA2_5_CURR_ADDR, val) 768 #define pDMA2_5_CURR_X_COUNT ((uint16_t volatile *)DMA2_5_CURR_X_COUNT) 769 #define bfin_read_DMA2_5_CURR_X_COUNT() bfin_read16(DMA2_5_CURR_X_COUNT) 770 #define bfin_write_DMA2_5_CURR_X_COUNT(val) bfin_write16(DMA2_5_CURR_X_COUNT, val) 771 #define pDMA2_5_CURR_Y_COUNT ((uint16_t volatile *)DMA2_5_CURR_Y_COUNT) 772 #define bfin_read_DMA2_5_CURR_Y_COUNT() bfin_read16(DMA2_5_CURR_Y_COUNT) 773 #define bfin_write_DMA2_5_CURR_Y_COUNT(val) bfin_write16(DMA2_5_CURR_Y_COUNT, val) 774 #define pDMA2_5_IRQ_STATUS ((uint16_t volatile *)DMA2_5_IRQ_STATUS) 775 #define bfin_read_DMA2_5_IRQ_STATUS() bfin_read16(DMA2_5_IRQ_STATUS) 776 #define bfin_write_DMA2_5_IRQ_STATUS(val) bfin_write16(DMA2_5_IRQ_STATUS, val) 777 #define pDMA2_5_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_5_PERIPHERAL_MAP) 778 #define bfin_read_DMA2_5_PERIPHERAL_MAP() bfin_read16(DMA2_5_PERIPHERAL_MAP) 779 #define bfin_write_DMA2_5_PERIPHERAL_MAP(val) bfin_write16(DMA2_5_PERIPHERAL_MAP, val) 780 #define pDMA2_6_CONFIG ((uint16_t volatile *)DMA2_6_CONFIG) 781 #define bfin_read_DMA2_6_CONFIG() bfin_read16(DMA2_6_CONFIG) 782 #define bfin_write_DMA2_6_CONFIG(val) bfin_write16(DMA2_6_CONFIG, val) 783 #define pDMA2_6_NEXT_DESC_PTR ((void * volatile *)DMA2_6_NEXT_DESC_PTR) 784 #define bfin_read_DMA2_6_NEXT_DESC_PTR() bfin_readPTR(DMA2_6_NEXT_DESC_PTR) 785 #define bfin_write_DMA2_6_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_6_NEXT_DESC_PTR, val) 786 #define pDMA2_6_START_ADDR ((void * volatile *)DMA2_6_START_ADDR) 787 #define bfin_read_DMA2_6_START_ADDR() bfin_readPTR(DMA2_6_START_ADDR) 788 #define bfin_write_DMA2_6_START_ADDR(val) bfin_writePTR(DMA2_6_START_ADDR, val) 789 #define pDMA2_6_X_COUNT ((uint16_t volatile *)DMA2_6_X_COUNT) 790 #define bfin_read_DMA2_6_X_COUNT() bfin_read16(DMA2_6_X_COUNT) 791 #define bfin_write_DMA2_6_X_COUNT(val) bfin_write16(DMA2_6_X_COUNT, val) 792 #define pDMA2_6_Y_COUNT ((uint16_t volatile *)DMA2_6_Y_COUNT) 793 #define bfin_read_DMA2_6_Y_COUNT() bfin_read16(DMA2_6_Y_COUNT) 794 #define bfin_write_DMA2_6_Y_COUNT(val) bfin_write16(DMA2_6_Y_COUNT, val) 795 #define pDMA2_6_X_MODIFY ((uint16_t volatile *)DMA2_6_X_MODIFY) 796 #define bfin_read_DMA2_6_X_MODIFY() bfin_read16(DMA2_6_X_MODIFY) 797 #define bfin_write_DMA2_6_X_MODIFY(val) bfin_write16(DMA2_6_X_MODIFY, val) 798 #define pDMA2_6_Y_MODIFY ((uint16_t volatile *)DMA2_6_Y_MODIFY) 799 #define bfin_read_DMA2_6_Y_MODIFY() bfin_read16(DMA2_6_Y_MODIFY) 800 #define bfin_write_DMA2_6_Y_MODIFY(val) bfin_write16(DMA2_6_Y_MODIFY, val) 801 #define pDMA2_6_CURR_DESC_PTR ((void * volatile *)DMA2_6_CURR_DESC_PTR) 802 #define bfin_read_DMA2_6_CURR_DESC_PTR() bfin_readPTR(DMA2_6_CURR_DESC_PTR) 803 #define bfin_write_DMA2_6_CURR_DESC_PTR(val) bfin_writePTR(DMA2_6_CURR_DESC_PTR, val) 804 #define pDMA2_6_CURR_ADDR ((void * volatile *)DMA2_6_CURR_ADDR) 805 #define bfin_read_DMA2_6_CURR_ADDR() bfin_readPTR(DMA2_6_CURR_ADDR) 806 #define bfin_write_DMA2_6_CURR_ADDR(val) bfin_writePTR(DMA2_6_CURR_ADDR, val) 807 #define pDMA2_6_CURR_X_COUNT ((uint16_t volatile *)DMA2_6_CURR_X_COUNT) 808 #define bfin_read_DMA2_6_CURR_X_COUNT() bfin_read16(DMA2_6_CURR_X_COUNT) 809 #define bfin_write_DMA2_6_CURR_X_COUNT(val) bfin_write16(DMA2_6_CURR_X_COUNT, val) 810 #define pDMA2_6_CURR_Y_COUNT ((uint16_t volatile *)DMA2_6_CURR_Y_COUNT) 811 #define bfin_read_DMA2_6_CURR_Y_COUNT() bfin_read16(DMA2_6_CURR_Y_COUNT) 812 #define bfin_write_DMA2_6_CURR_Y_COUNT(val) bfin_write16(DMA2_6_CURR_Y_COUNT, val) 813 #define pDMA2_6_IRQ_STATUS ((uint16_t volatile *)DMA2_6_IRQ_STATUS) 814 #define bfin_read_DMA2_6_IRQ_STATUS() bfin_read16(DMA2_6_IRQ_STATUS) 815 #define bfin_write_DMA2_6_IRQ_STATUS(val) bfin_write16(DMA2_6_IRQ_STATUS, val) 816 #define pDMA2_6_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_6_PERIPHERAL_MAP) 817 #define bfin_read_DMA2_6_PERIPHERAL_MAP() bfin_read16(DMA2_6_PERIPHERAL_MAP) 818 #define bfin_write_DMA2_6_PERIPHERAL_MAP(val) bfin_write16(DMA2_6_PERIPHERAL_MAP, val) 819 #define pDMA2_7_CONFIG ((uint16_t volatile *)DMA2_7_CONFIG) 820 #define bfin_read_DMA2_7_CONFIG() bfin_read16(DMA2_7_CONFIG) 821 #define bfin_write_DMA2_7_CONFIG(val) bfin_write16(DMA2_7_CONFIG, val) 822 #define pDMA2_7_NEXT_DESC_PTR ((void * volatile *)DMA2_7_NEXT_DESC_PTR) 823 #define bfin_read_DMA2_7_NEXT_DESC_PTR() bfin_readPTR(DMA2_7_NEXT_DESC_PTR) 824 #define bfin_write_DMA2_7_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_7_NEXT_DESC_PTR, val) 825 #define pDMA2_7_START_ADDR ((void * volatile *)DMA2_7_START_ADDR) 826 #define bfin_read_DMA2_7_START_ADDR() bfin_readPTR(DMA2_7_START_ADDR) 827 #define bfin_write_DMA2_7_START_ADDR(val) bfin_writePTR(DMA2_7_START_ADDR, val) 828 #define pDMA2_7_X_COUNT ((uint16_t volatile *)DMA2_7_X_COUNT) 829 #define bfin_read_DMA2_7_X_COUNT() bfin_read16(DMA2_7_X_COUNT) 830 #define bfin_write_DMA2_7_X_COUNT(val) bfin_write16(DMA2_7_X_COUNT, val) 831 #define pDMA2_7_Y_COUNT ((uint16_t volatile *)DMA2_7_Y_COUNT) 832 #define bfin_read_DMA2_7_Y_COUNT() bfin_read16(DMA2_7_Y_COUNT) 833 #define bfin_write_DMA2_7_Y_COUNT(val) bfin_write16(DMA2_7_Y_COUNT, val) 834 #define pDMA2_7_X_MODIFY ((uint16_t volatile *)DMA2_7_X_MODIFY) 835 #define bfin_read_DMA2_7_X_MODIFY() bfin_read16(DMA2_7_X_MODIFY) 836 #define bfin_write_DMA2_7_X_MODIFY(val) bfin_write16(DMA2_7_X_MODIFY, val) 837 #define pDMA2_7_Y_MODIFY ((uint16_t volatile *)DMA2_7_Y_MODIFY) 838 #define bfin_read_DMA2_7_Y_MODIFY() bfin_read16(DMA2_7_Y_MODIFY) 839 #define bfin_write_DMA2_7_Y_MODIFY(val) bfin_write16(DMA2_7_Y_MODIFY, val) 840 #define pDMA2_7_CURR_DESC_PTR ((void * volatile *)DMA2_7_CURR_DESC_PTR) 841 #define bfin_read_DMA2_7_CURR_DESC_PTR() bfin_readPTR(DMA2_7_CURR_DESC_PTR) 842 #define bfin_write_DMA2_7_CURR_DESC_PTR(val) bfin_writePTR(DMA2_7_CURR_DESC_PTR, val) 843 #define pDMA2_7_CURR_ADDR ((void * volatile *)DMA2_7_CURR_ADDR) 844 #define bfin_read_DMA2_7_CURR_ADDR() bfin_readPTR(DMA2_7_CURR_ADDR) 845 #define bfin_write_DMA2_7_CURR_ADDR(val) bfin_writePTR(DMA2_7_CURR_ADDR, val) 846 #define pDMA2_7_CURR_X_COUNT ((uint16_t volatile *)DMA2_7_CURR_X_COUNT) 847 #define bfin_read_DMA2_7_CURR_X_COUNT() bfin_read16(DMA2_7_CURR_X_COUNT) 848 #define bfin_write_DMA2_7_CURR_X_COUNT(val) bfin_write16(DMA2_7_CURR_X_COUNT, val) 849 #define pDMA2_7_CURR_Y_COUNT ((uint16_t volatile *)DMA2_7_CURR_Y_COUNT) 850 #define bfin_read_DMA2_7_CURR_Y_COUNT() bfin_read16(DMA2_7_CURR_Y_COUNT) 851 #define bfin_write_DMA2_7_CURR_Y_COUNT(val) bfin_write16(DMA2_7_CURR_Y_COUNT, val) 852 #define pDMA2_7_IRQ_STATUS ((uint16_t volatile *)DMA2_7_IRQ_STATUS) 853 #define bfin_read_DMA2_7_IRQ_STATUS() bfin_read16(DMA2_7_IRQ_STATUS) 854 #define bfin_write_DMA2_7_IRQ_STATUS(val) bfin_write16(DMA2_7_IRQ_STATUS, val) 855 #define pDMA2_7_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_7_PERIPHERAL_MAP) 856 #define bfin_read_DMA2_7_PERIPHERAL_MAP() bfin_read16(DMA2_7_PERIPHERAL_MAP) 857 #define bfin_write_DMA2_7_PERIPHERAL_MAP(val) bfin_write16(DMA2_7_PERIPHERAL_MAP, val) 858 #define pDMA2_8_CONFIG ((uint16_t volatile *)DMA2_8_CONFIG) 859 #define bfin_read_DMA2_8_CONFIG() bfin_read16(DMA2_8_CONFIG) 860 #define bfin_write_DMA2_8_CONFIG(val) bfin_write16(DMA2_8_CONFIG, val) 861 #define pDMA2_8_NEXT_DESC_PTR ((void * volatile *)DMA2_8_NEXT_DESC_PTR) 862 #define bfin_read_DMA2_8_NEXT_DESC_PTR() bfin_readPTR(DMA2_8_NEXT_DESC_PTR) 863 #define bfin_write_DMA2_8_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_8_NEXT_DESC_PTR, val) 864 #define pDMA2_8_START_ADDR ((void * volatile *)DMA2_8_START_ADDR) 865 #define bfin_read_DMA2_8_START_ADDR() bfin_readPTR(DMA2_8_START_ADDR) 866 #define bfin_write_DMA2_8_START_ADDR(val) bfin_writePTR(DMA2_8_START_ADDR, val) 867 #define pDMA2_8_X_COUNT ((uint16_t volatile *)DMA2_8_X_COUNT) 868 #define bfin_read_DMA2_8_X_COUNT() bfin_read16(DMA2_8_X_COUNT) 869 #define bfin_write_DMA2_8_X_COUNT(val) bfin_write16(DMA2_8_X_COUNT, val) 870 #define pDMA2_8_Y_COUNT ((uint16_t volatile *)DMA2_8_Y_COUNT) 871 #define bfin_read_DMA2_8_Y_COUNT() bfin_read16(DMA2_8_Y_COUNT) 872 #define bfin_write_DMA2_8_Y_COUNT(val) bfin_write16(DMA2_8_Y_COUNT, val) 873 #define pDMA2_8_X_MODIFY ((uint16_t volatile *)DMA2_8_X_MODIFY) 874 #define bfin_read_DMA2_8_X_MODIFY() bfin_read16(DMA2_8_X_MODIFY) 875 #define bfin_write_DMA2_8_X_MODIFY(val) bfin_write16(DMA2_8_X_MODIFY, val) 876 #define pDMA2_8_Y_MODIFY ((uint16_t volatile *)DMA2_8_Y_MODIFY) 877 #define bfin_read_DMA2_8_Y_MODIFY() bfin_read16(DMA2_8_Y_MODIFY) 878 #define bfin_write_DMA2_8_Y_MODIFY(val) bfin_write16(DMA2_8_Y_MODIFY, val) 879 #define pDMA2_8_CURR_DESC_PTR ((void * volatile *)DMA2_8_CURR_DESC_PTR) 880 #define bfin_read_DMA2_8_CURR_DESC_PTR() bfin_readPTR(DMA2_8_CURR_DESC_PTR) 881 #define bfin_write_DMA2_8_CURR_DESC_PTR(val) bfin_writePTR(DMA2_8_CURR_DESC_PTR, val) 882 #define pDMA2_8_CURR_ADDR ((void * volatile *)DMA2_8_CURR_ADDR) 883 #define bfin_read_DMA2_8_CURR_ADDR() bfin_readPTR(DMA2_8_CURR_ADDR) 884 #define bfin_write_DMA2_8_CURR_ADDR(val) bfin_writePTR(DMA2_8_CURR_ADDR, val) 885 #define pDMA2_8_CURR_X_COUNT ((uint16_t volatile *)DMA2_8_CURR_X_COUNT) 886 #define bfin_read_DMA2_8_CURR_X_COUNT() bfin_read16(DMA2_8_CURR_X_COUNT) 887 #define bfin_write_DMA2_8_CURR_X_COUNT(val) bfin_write16(DMA2_8_CURR_X_COUNT, val) 888 #define pDMA2_8_CURR_Y_COUNT ((uint16_t volatile *)DMA2_8_CURR_Y_COUNT) 889 #define bfin_read_DMA2_8_CURR_Y_COUNT() bfin_read16(DMA2_8_CURR_Y_COUNT) 890 #define bfin_write_DMA2_8_CURR_Y_COUNT(val) bfin_write16(DMA2_8_CURR_Y_COUNT, val) 891 #define pDMA2_8_IRQ_STATUS ((uint16_t volatile *)DMA2_8_IRQ_STATUS) 892 #define bfin_read_DMA2_8_IRQ_STATUS() bfin_read16(DMA2_8_IRQ_STATUS) 893 #define bfin_write_DMA2_8_IRQ_STATUS(val) bfin_write16(DMA2_8_IRQ_STATUS, val) 894 #define pDMA2_8_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_8_PERIPHERAL_MAP) 895 #define bfin_read_DMA2_8_PERIPHERAL_MAP() bfin_read16(DMA2_8_PERIPHERAL_MAP) 896 #define bfin_write_DMA2_8_PERIPHERAL_MAP(val) bfin_write16(DMA2_8_PERIPHERAL_MAP, val) 897 #define pDMA2_9_CONFIG ((uint16_t volatile *)DMA2_9_CONFIG) 898 #define bfin_read_DMA2_9_CONFIG() bfin_read16(DMA2_9_CONFIG) 899 #define bfin_write_DMA2_9_CONFIG(val) bfin_write16(DMA2_9_CONFIG, val) 900 #define pDMA2_9_NEXT_DESC_PTR ((void * volatile *)DMA2_9_NEXT_DESC_PTR) 901 #define bfin_read_DMA2_9_NEXT_DESC_PTR() bfin_readPTR(DMA2_9_NEXT_DESC_PTR) 902 #define bfin_write_DMA2_9_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_9_NEXT_DESC_PTR, val) 903 #define pDMA2_9_START_ADDR ((void * volatile *)DMA2_9_START_ADDR) 904 #define bfin_read_DMA2_9_START_ADDR() bfin_readPTR(DMA2_9_START_ADDR) 905 #define bfin_write_DMA2_9_START_ADDR(val) bfin_writePTR(DMA2_9_START_ADDR, val) 906 #define pDMA2_9_X_COUNT ((uint16_t volatile *)DMA2_9_X_COUNT) 907 #define bfin_read_DMA2_9_X_COUNT() bfin_read16(DMA2_9_X_COUNT) 908 #define bfin_write_DMA2_9_X_COUNT(val) bfin_write16(DMA2_9_X_COUNT, val) 909 #define pDMA2_9_Y_COUNT ((uint16_t volatile *)DMA2_9_Y_COUNT) 910 #define bfin_read_DMA2_9_Y_COUNT() bfin_read16(DMA2_9_Y_COUNT) 911 #define bfin_write_DMA2_9_Y_COUNT(val) bfin_write16(DMA2_9_Y_COUNT, val) 912 #define pDMA2_9_X_MODIFY ((uint16_t volatile *)DMA2_9_X_MODIFY) 913 #define bfin_read_DMA2_9_X_MODIFY() bfin_read16(DMA2_9_X_MODIFY) 914 #define bfin_write_DMA2_9_X_MODIFY(val) bfin_write16(DMA2_9_X_MODIFY, val) 915 #define pDMA2_9_Y_MODIFY ((uint16_t volatile *)DMA2_9_Y_MODIFY) 916 #define bfin_read_DMA2_9_Y_MODIFY() bfin_read16(DMA2_9_Y_MODIFY) 917 #define bfin_write_DMA2_9_Y_MODIFY(val) bfin_write16(DMA2_9_Y_MODIFY, val) 918 #define pDMA2_9_CURR_DESC_PTR ((void * volatile *)DMA2_9_CURR_DESC_PTR) 919 #define bfin_read_DMA2_9_CURR_DESC_PTR() bfin_readPTR(DMA2_9_CURR_DESC_PTR) 920 #define bfin_write_DMA2_9_CURR_DESC_PTR(val) bfin_writePTR(DMA2_9_CURR_DESC_PTR, val) 921 #define pDMA2_9_CURR_ADDR ((void * volatile *)DMA2_9_CURR_ADDR) 922 #define bfin_read_DMA2_9_CURR_ADDR() bfin_readPTR(DMA2_9_CURR_ADDR) 923 #define bfin_write_DMA2_9_CURR_ADDR(val) bfin_writePTR(DMA2_9_CURR_ADDR, val) 924 #define pDMA2_9_CURR_X_COUNT ((uint16_t volatile *)DMA2_9_CURR_X_COUNT) 925 #define bfin_read_DMA2_9_CURR_X_COUNT() bfin_read16(DMA2_9_CURR_X_COUNT) 926 #define bfin_write_DMA2_9_CURR_X_COUNT(val) bfin_write16(DMA2_9_CURR_X_COUNT, val) 927 #define pDMA2_9_CURR_Y_COUNT ((uint16_t volatile *)DMA2_9_CURR_Y_COUNT) 928 #define bfin_read_DMA2_9_CURR_Y_COUNT() bfin_read16(DMA2_9_CURR_Y_COUNT) 929 #define bfin_write_DMA2_9_CURR_Y_COUNT(val) bfin_write16(DMA2_9_CURR_Y_COUNT, val) 930 #define pDMA2_9_IRQ_STATUS ((uint16_t volatile *)DMA2_9_IRQ_STATUS) 931 #define bfin_read_DMA2_9_IRQ_STATUS() bfin_read16(DMA2_9_IRQ_STATUS) 932 #define bfin_write_DMA2_9_IRQ_STATUS(val) bfin_write16(DMA2_9_IRQ_STATUS, val) 933 #define pDMA2_9_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_9_PERIPHERAL_MAP) 934 #define bfin_read_DMA2_9_PERIPHERAL_MAP() bfin_read16(DMA2_9_PERIPHERAL_MAP) 935 #define bfin_write_DMA2_9_PERIPHERAL_MAP(val) bfin_write16(DMA2_9_PERIPHERAL_MAP, val) 936 #define pDMA2_10_CONFIG ((uint16_t volatile *)DMA2_10_CONFIG) 937 #define bfin_read_DMA2_10_CONFIG() bfin_read16(DMA2_10_CONFIG) 938 #define bfin_write_DMA2_10_CONFIG(val) bfin_write16(DMA2_10_CONFIG, val) 939 #define pDMA2_10_NEXT_DESC_PTR ((void * volatile *)DMA2_10_NEXT_DESC_PTR) 940 #define bfin_read_DMA2_10_NEXT_DESC_PTR() bfin_readPTR(DMA2_10_NEXT_DESC_PTR) 941 #define bfin_write_DMA2_10_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_10_NEXT_DESC_PTR, val) 942 #define pDMA2_10_START_ADDR ((void * volatile *)DMA2_10_START_ADDR) 943 #define bfin_read_DMA2_10_START_ADDR() bfin_readPTR(DMA2_10_START_ADDR) 944 #define bfin_write_DMA2_10_START_ADDR(val) bfin_writePTR(DMA2_10_START_ADDR, val) 945 #define pDMA2_10_X_COUNT ((uint16_t volatile *)DMA2_10_X_COUNT) 946 #define bfin_read_DMA2_10_X_COUNT() bfin_read16(DMA2_10_X_COUNT) 947 #define bfin_write_DMA2_10_X_COUNT(val) bfin_write16(DMA2_10_X_COUNT, val) 948 #define pDMA2_10_Y_COUNT ((uint16_t volatile *)DMA2_10_Y_COUNT) 949 #define bfin_read_DMA2_10_Y_COUNT() bfin_read16(DMA2_10_Y_COUNT) 950 #define bfin_write_DMA2_10_Y_COUNT(val) bfin_write16(DMA2_10_Y_COUNT, val) 951 #define pDMA2_10_X_MODIFY ((uint16_t volatile *)DMA2_10_X_MODIFY) 952 #define bfin_read_DMA2_10_X_MODIFY() bfin_read16(DMA2_10_X_MODIFY) 953 #define bfin_write_DMA2_10_X_MODIFY(val) bfin_write16(DMA2_10_X_MODIFY, val) 954 #define pDMA2_10_Y_MODIFY ((uint16_t volatile *)DMA2_10_Y_MODIFY) 955 #define bfin_read_DMA2_10_Y_MODIFY() bfin_read16(DMA2_10_Y_MODIFY) 956 #define bfin_write_DMA2_10_Y_MODIFY(val) bfin_write16(DMA2_10_Y_MODIFY, val) 957 #define pDMA2_10_CURR_DESC_PTR ((void * volatile *)DMA2_10_CURR_DESC_PTR) 958 #define bfin_read_DMA2_10_CURR_DESC_PTR() bfin_readPTR(DMA2_10_CURR_DESC_PTR) 959 #define bfin_write_DMA2_10_CURR_DESC_PTR(val) bfin_writePTR(DMA2_10_CURR_DESC_PTR, val) 960 #define pDMA2_10_CURR_ADDR ((void * volatile *)DMA2_10_CURR_ADDR) 961 #define bfin_read_DMA2_10_CURR_ADDR() bfin_readPTR(DMA2_10_CURR_ADDR) 962 #define bfin_write_DMA2_10_CURR_ADDR(val) bfin_writePTR(DMA2_10_CURR_ADDR, val) 963 #define pDMA2_10_CURR_X_COUNT ((uint16_t volatile *)DMA2_10_CURR_X_COUNT) 964 #define bfin_read_DMA2_10_CURR_X_COUNT() bfin_read16(DMA2_10_CURR_X_COUNT) 965 #define bfin_write_DMA2_10_CURR_X_COUNT(val) bfin_write16(DMA2_10_CURR_X_COUNT, val) 966 #define pDMA2_10_CURR_Y_COUNT ((uint16_t volatile *)DMA2_10_CURR_Y_COUNT) 967 #define bfin_read_DMA2_10_CURR_Y_COUNT() bfin_read16(DMA2_10_CURR_Y_COUNT) 968 #define bfin_write_DMA2_10_CURR_Y_COUNT(val) bfin_write16(DMA2_10_CURR_Y_COUNT, val) 969 #define pDMA2_10_IRQ_STATUS ((uint16_t volatile *)DMA2_10_IRQ_STATUS) 970 #define bfin_read_DMA2_10_IRQ_STATUS() bfin_read16(DMA2_10_IRQ_STATUS) 971 #define bfin_write_DMA2_10_IRQ_STATUS(val) bfin_write16(DMA2_10_IRQ_STATUS, val) 972 #define pDMA2_10_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_10_PERIPHERAL_MAP) 973 #define bfin_read_DMA2_10_PERIPHERAL_MAP() bfin_read16(DMA2_10_PERIPHERAL_MAP) 974 #define bfin_write_DMA2_10_PERIPHERAL_MAP(val) bfin_write16(DMA2_10_PERIPHERAL_MAP, val) 975 #define pDMA2_11_CONFIG ((uint16_t volatile *)DMA2_11_CONFIG) 976 #define bfin_read_DMA2_11_CONFIG() bfin_read16(DMA2_11_CONFIG) 977 #define bfin_write_DMA2_11_CONFIG(val) bfin_write16(DMA2_11_CONFIG, val) 978 #define pDMA2_11_NEXT_DESC_PTR ((void * volatile *)DMA2_11_NEXT_DESC_PTR) 979 #define bfin_read_DMA2_11_NEXT_DESC_PTR() bfin_readPTR(DMA2_11_NEXT_DESC_PTR) 980 #define bfin_write_DMA2_11_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_11_NEXT_DESC_PTR, val) 981 #define pDMA2_11_START_ADDR ((void * volatile *)DMA2_11_START_ADDR) 982 #define bfin_read_DMA2_11_START_ADDR() bfin_readPTR(DMA2_11_START_ADDR) 983 #define bfin_write_DMA2_11_START_ADDR(val) bfin_writePTR(DMA2_11_START_ADDR, val) 984 #define pDMA2_11_X_COUNT ((uint16_t volatile *)DMA2_11_X_COUNT) 985 #define bfin_read_DMA2_11_X_COUNT() bfin_read16(DMA2_11_X_COUNT) 986 #define bfin_write_DMA2_11_X_COUNT(val) bfin_write16(DMA2_11_X_COUNT, val) 987 #define pDMA2_11_Y_COUNT ((uint16_t volatile *)DMA2_11_Y_COUNT) 988 #define bfin_read_DMA2_11_Y_COUNT() bfin_read16(DMA2_11_Y_COUNT) 989 #define bfin_write_DMA2_11_Y_COUNT(val) bfin_write16(DMA2_11_Y_COUNT, val) 990 #define pDMA2_11_X_MODIFY ((uint16_t volatile *)DMA2_11_X_MODIFY) 991 #define bfin_read_DMA2_11_X_MODIFY() bfin_read16(DMA2_11_X_MODIFY) 992 #define bfin_write_DMA2_11_X_MODIFY(val) bfin_write16(DMA2_11_X_MODIFY, val) 993 #define pDMA2_11_Y_MODIFY ((uint16_t volatile *)DMA2_11_Y_MODIFY) 994 #define bfin_read_DMA2_11_Y_MODIFY() bfin_read16(DMA2_11_Y_MODIFY) 995 #define bfin_write_DMA2_11_Y_MODIFY(val) bfin_write16(DMA2_11_Y_MODIFY, val) 996 #define pDMA2_11_CURR_DESC_PTR ((void * volatile *)DMA2_11_CURR_DESC_PTR) 997 #define bfin_read_DMA2_11_CURR_DESC_PTR() bfin_readPTR(DMA2_11_CURR_DESC_PTR) 998 #define bfin_write_DMA2_11_CURR_DESC_PTR(val) bfin_writePTR(DMA2_11_CURR_DESC_PTR, val) 999 #define pDMA2_11_CURR_ADDR ((void * volatile *)DMA2_11_CURR_ADDR) 1000 #define bfin_read_DMA2_11_CURR_ADDR() bfin_readPTR(DMA2_11_CURR_ADDR) 1001 #define bfin_write_DMA2_11_CURR_ADDR(val) bfin_writePTR(DMA2_11_CURR_ADDR, val) 1002 #define pDMA2_11_CURR_X_COUNT ((uint16_t volatile *)DMA2_11_CURR_X_COUNT) 1003 #define bfin_read_DMA2_11_CURR_X_COUNT() bfin_read16(DMA2_11_CURR_X_COUNT) 1004 #define bfin_write_DMA2_11_CURR_X_COUNT(val) bfin_write16(DMA2_11_CURR_X_COUNT, val) 1005 #define pDMA2_11_CURR_Y_COUNT ((uint16_t volatile *)DMA2_11_CURR_Y_COUNT) 1006 #define bfin_read_DMA2_11_CURR_Y_COUNT() bfin_read16(DMA2_11_CURR_Y_COUNT) 1007 #define bfin_write_DMA2_11_CURR_Y_COUNT(val) bfin_write16(DMA2_11_CURR_Y_COUNT, val) 1008 #define pDMA2_11_IRQ_STATUS ((uint16_t volatile *)DMA2_11_IRQ_STATUS) 1009 #define bfin_read_DMA2_11_IRQ_STATUS() bfin_read16(DMA2_11_IRQ_STATUS) 1010 #define bfin_write_DMA2_11_IRQ_STATUS(val) bfin_write16(DMA2_11_IRQ_STATUS, val) 1011 #define pDMA2_11_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_11_PERIPHERAL_MAP) 1012 #define bfin_read_DMA2_11_PERIPHERAL_MAP() bfin_read16(DMA2_11_PERIPHERAL_MAP) 1013 #define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP, val) 1014 #define pIMDMA_S0_CONFIG ((uint16_t volatile *)IMDMA_S0_CONFIG) 1015 #define bfin_read_IMDMA_S0_CONFIG() bfin_read16(IMDMA_S0_CONFIG) 1016 #define bfin_write_IMDMA_S0_CONFIG(val) bfin_write16(IMDMA_S0_CONFIG, val) 1017 #define pIMDMA_S0_NEXT_DESC_PTR ((void * volatile *)IMDMA_S0_NEXT_DESC_PTR) 1018 #define bfin_read_IMDMA_S0_NEXT_DESC_PTR() bfin_readPTR(IMDMA_S0_NEXT_DESC_PTR) 1019 #define bfin_write_IMDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_S0_NEXT_DESC_PTR, val) 1020 #define pIMDMA_S0_START_ADDR ((void * volatile *)IMDMA_S0_START_ADDR) 1021 #define bfin_read_IMDMA_S0_START_ADDR() bfin_readPTR(IMDMA_S0_START_ADDR) 1022 #define bfin_write_IMDMA_S0_START_ADDR(val) bfin_writePTR(IMDMA_S0_START_ADDR, val) 1023 #define pIMDMA_S0_X_COUNT ((uint16_t volatile *)IMDMA_S0_X_COUNT) 1024 #define bfin_read_IMDMA_S0_X_COUNT() bfin_read16(IMDMA_S0_X_COUNT) 1025 #define bfin_write_IMDMA_S0_X_COUNT(val) bfin_write16(IMDMA_S0_X_COUNT, val) 1026 #define pIMDMA_S0_Y_COUNT ((uint16_t volatile *)IMDMA_S0_Y_COUNT) 1027 #define bfin_read_IMDMA_S0_Y_COUNT() bfin_read16(IMDMA_S0_Y_COUNT) 1028 #define bfin_write_IMDMA_S0_Y_COUNT(val) bfin_write16(IMDMA_S0_Y_COUNT, val) 1029 #define pIMDMA_S0_X_MODIFY ((uint16_t volatile *)IMDMA_S0_X_MODIFY) 1030 #define bfin_read_IMDMA_S0_X_MODIFY() bfin_read16(IMDMA_S0_X_MODIFY) 1031 #define bfin_write_IMDMA_S0_X_MODIFY(val) bfin_write16(IMDMA_S0_X_MODIFY, val) 1032 #define pIMDMA_S0_Y_MODIFY ((uint16_t volatile *)IMDMA_S0_Y_MODIFY) 1033 #define bfin_read_IMDMA_S0_Y_MODIFY() bfin_read16(IMDMA_S0_Y_MODIFY) 1034 #define bfin_write_IMDMA_S0_Y_MODIFY(val) bfin_write16(IMDMA_S0_Y_MODIFY, val) 1035 #define pIMDMA_S0_CURR_DESC_PTR ((void * volatile *)IMDMA_S0_CURR_DESC_PTR) 1036 #define bfin_read_IMDMA_S0_CURR_DESC_PTR() bfin_readPTR(IMDMA_S0_CURR_DESC_PTR) 1037 #define bfin_write_IMDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_S0_CURR_DESC_PTR, val) 1038 #define pIMDMA_S0_CURR_ADDR ((void * volatile *)IMDMA_S0_CURR_ADDR) 1039 #define bfin_read_IMDMA_S0_CURR_ADDR() bfin_readPTR(IMDMA_S0_CURR_ADDR) 1040 #define bfin_write_IMDMA_S0_CURR_ADDR(val) bfin_writePTR(IMDMA_S0_CURR_ADDR, val) 1041 #define pIMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)IMDMA_S0_CURR_X_COUNT) 1042 #define bfin_read_IMDMA_S0_CURR_X_COUNT() bfin_read16(IMDMA_S0_CURR_X_COUNT) 1043 #define bfin_write_IMDMA_S0_CURR_X_COUNT(val) bfin_write16(IMDMA_S0_CURR_X_COUNT, val) 1044 #define pIMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)IMDMA_S0_CURR_Y_COUNT) 1045 #define bfin_read_IMDMA_S0_CURR_Y_COUNT() bfin_read16(IMDMA_S0_CURR_Y_COUNT) 1046 #define bfin_write_IMDMA_S0_CURR_Y_COUNT(val) bfin_write16(IMDMA_S0_CURR_Y_COUNT, val) 1047 #define pIMDMA_S0_IRQ_STATUS ((uint16_t volatile *)IMDMA_S0_IRQ_STATUS) 1048 #define bfin_read_IMDMA_S0_IRQ_STATUS() bfin_read16(IMDMA_S0_IRQ_STATUS) 1049 #define bfin_write_IMDMA_S0_IRQ_STATUS(val) bfin_write16(IMDMA_S0_IRQ_STATUS, val) 1050 #define pIMDMA_D0_CONFIG ((uint16_t volatile *)IMDMA_D0_CONFIG) 1051 #define bfin_read_IMDMA_D0_CONFIG() bfin_read16(IMDMA_D0_CONFIG) 1052 #define bfin_write_IMDMA_D0_CONFIG(val) bfin_write16(IMDMA_D0_CONFIG, val) 1053 #define pIMDMA_D0_NEXT_DESC_PTR ((void * volatile *)IMDMA_D0_NEXT_DESC_PTR) 1054 #define bfin_read_IMDMA_D0_NEXT_DESC_PTR() bfin_readPTR(IMDMA_D0_NEXT_DESC_PTR) 1055 #define bfin_write_IMDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_D0_NEXT_DESC_PTR, val) 1056 #define pIMDMA_D0_START_ADDR ((void * volatile *)IMDMA_D0_START_ADDR) 1057 #define bfin_read_IMDMA_D0_START_ADDR() bfin_readPTR(IMDMA_D0_START_ADDR) 1058 #define bfin_write_IMDMA_D0_START_ADDR(val) bfin_writePTR(IMDMA_D0_START_ADDR, val) 1059 #define pIMDMA_D0_X_COUNT ((uint16_t volatile *)IMDMA_D0_X_COUNT) 1060 #define bfin_read_IMDMA_D0_X_COUNT() bfin_read16(IMDMA_D0_X_COUNT) 1061 #define bfin_write_IMDMA_D0_X_COUNT(val) bfin_write16(IMDMA_D0_X_COUNT, val) 1062 #define pIMDMA_D0_Y_COUNT ((uint16_t volatile *)IMDMA_D0_Y_COUNT) 1063 #define bfin_read_IMDMA_D0_Y_COUNT() bfin_read16(IMDMA_D0_Y_COUNT) 1064 #define bfin_write_IMDMA_D0_Y_COUNT(val) bfin_write16(IMDMA_D0_Y_COUNT, val) 1065 #define pIMDMA_D0_X_MODIFY ((uint16_t volatile *)IMDMA_D0_X_MODIFY) 1066 #define bfin_read_IMDMA_D0_X_MODIFY() bfin_read16(IMDMA_D0_X_MODIFY) 1067 #define bfin_write_IMDMA_D0_X_MODIFY(val) bfin_write16(IMDMA_D0_X_MODIFY, val) 1068 #define pIMDMA_D0_Y_MODIFY ((uint16_t volatile *)IMDMA_D0_Y_MODIFY) 1069 #define bfin_read_IMDMA_D0_Y_MODIFY() bfin_read16(IMDMA_D0_Y_MODIFY) 1070 #define bfin_write_IMDMA_D0_Y_MODIFY(val) bfin_write16(IMDMA_D0_Y_MODIFY, val) 1071 #define pIMDMA_D0_CURR_DESC_PTR ((void * volatile *)IMDMA_D0_CURR_DESC_PTR) 1072 #define bfin_read_IMDMA_D0_CURR_DESC_PTR() bfin_readPTR(IMDMA_D0_CURR_DESC_PTR) 1073 #define bfin_write_IMDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_D0_CURR_DESC_PTR, val) 1074 #define pIMDMA_D0_CURR_ADDR ((void * volatile *)IMDMA_D0_CURR_ADDR) 1075 #define bfin_read_IMDMA_D0_CURR_ADDR() bfin_readPTR(IMDMA_D0_CURR_ADDR) 1076 #define bfin_write_IMDMA_D0_CURR_ADDR(val) bfin_writePTR(IMDMA_D0_CURR_ADDR, val) 1077 #define pIMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)IMDMA_D0_CURR_X_COUNT) 1078 #define bfin_read_IMDMA_D0_CURR_X_COUNT() bfin_read16(IMDMA_D0_CURR_X_COUNT) 1079 #define bfin_write_IMDMA_D0_CURR_X_COUNT(val) bfin_write16(IMDMA_D0_CURR_X_COUNT, val) 1080 #define pIMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)IMDMA_D0_CURR_Y_COUNT) 1081 #define bfin_read_IMDMA_D0_CURR_Y_COUNT() bfin_read16(IMDMA_D0_CURR_Y_COUNT) 1082 #define bfin_write_IMDMA_D0_CURR_Y_COUNT(val) bfin_write16(IMDMA_D0_CURR_Y_COUNT, val) 1083 #define pIMDMA_D0_IRQ_STATUS ((uint16_t volatile *)IMDMA_D0_IRQ_STATUS) 1084 #define bfin_read_IMDMA_D0_IRQ_STATUS() bfin_read16(IMDMA_D0_IRQ_STATUS) 1085 #define bfin_write_IMDMA_D0_IRQ_STATUS(val) bfin_write16(IMDMA_D0_IRQ_STATUS, val) 1086 #define pIMDMA_S1_CONFIG ((uint16_t volatile *)IMDMA_S1_CONFIG) 1087 #define bfin_read_IMDMA_S1_CONFIG() bfin_read16(IMDMA_S1_CONFIG) 1088 #define bfin_write_IMDMA_S1_CONFIG(val) bfin_write16(IMDMA_S1_CONFIG, val) 1089 #define pIMDMA_S1_NEXT_DESC_PTR ((void * volatile *)IMDMA_S1_NEXT_DESC_PTR) 1090 #define bfin_read_IMDMA_S1_NEXT_DESC_PTR() bfin_readPTR(IMDMA_S1_NEXT_DESC_PTR) 1091 #define bfin_write_IMDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_S1_NEXT_DESC_PTR, val) 1092 #define pIMDMA_S1_START_ADDR ((void * volatile *)IMDMA_S1_START_ADDR) 1093 #define bfin_read_IMDMA_S1_START_ADDR() bfin_readPTR(IMDMA_S1_START_ADDR) 1094 #define bfin_write_IMDMA_S1_START_ADDR(val) bfin_writePTR(IMDMA_S1_START_ADDR, val) 1095 #define pIMDMA_S1_X_COUNT ((uint16_t volatile *)IMDMA_S1_X_COUNT) 1096 #define bfin_read_IMDMA_S1_X_COUNT() bfin_read16(IMDMA_S1_X_COUNT) 1097 #define bfin_write_IMDMA_S1_X_COUNT(val) bfin_write16(IMDMA_S1_X_COUNT, val) 1098 #define pIMDMA_S1_Y_COUNT ((uint16_t volatile *)IMDMA_S1_Y_COUNT) 1099 #define bfin_read_IMDMA_S1_Y_COUNT() bfin_read16(IMDMA_S1_Y_COUNT) 1100 #define bfin_write_IMDMA_S1_Y_COUNT(val) bfin_write16(IMDMA_S1_Y_COUNT, val) 1101 #define pIMDMA_S1_X_MODIFY ((uint16_t volatile *)IMDMA_S1_X_MODIFY) 1102 #define bfin_read_IMDMA_S1_X_MODIFY() bfin_read16(IMDMA_S1_X_MODIFY) 1103 #define bfin_write_IMDMA_S1_X_MODIFY(val) bfin_write16(IMDMA_S1_X_MODIFY, val) 1104 #define pIMDMA_S1_Y_MODIFY ((uint16_t volatile *)IMDMA_S1_Y_MODIFY) 1105 #define bfin_read_IMDMA_S1_Y_MODIFY() bfin_read16(IMDMA_S1_Y_MODIFY) 1106 #define bfin_write_IMDMA_S1_Y_MODIFY(val) bfin_write16(IMDMA_S1_Y_MODIFY, val) 1107 #define pIMDMA_S1_CURR_DESC_PTR ((void * volatile *)IMDMA_S1_CURR_DESC_PTR) 1108 #define bfin_read_IMDMA_S1_CURR_DESC_PTR() bfin_readPTR(IMDMA_S1_CURR_DESC_PTR) 1109 #define bfin_write_IMDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_S1_CURR_DESC_PTR, val) 1110 #define pIMDMA_S1_CURR_ADDR ((void * volatile *)IMDMA_S1_CURR_ADDR) 1111 #define bfin_read_IMDMA_S1_CURR_ADDR() bfin_readPTR(IMDMA_S1_CURR_ADDR) 1112 #define bfin_write_IMDMA_S1_CURR_ADDR(val) bfin_writePTR(IMDMA_S1_CURR_ADDR, val) 1113 #define pIMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)IMDMA_S1_CURR_X_COUNT) 1114 #define bfin_read_IMDMA_S1_CURR_X_COUNT() bfin_read16(IMDMA_S1_CURR_X_COUNT) 1115 #define bfin_write_IMDMA_S1_CURR_X_COUNT(val) bfin_write16(IMDMA_S1_CURR_X_COUNT, val) 1116 #define pIMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)IMDMA_S1_CURR_Y_COUNT) 1117 #define bfin_read_IMDMA_S1_CURR_Y_COUNT() bfin_read16(IMDMA_S1_CURR_Y_COUNT) 1118 #define bfin_write_IMDMA_S1_CURR_Y_COUNT(val) bfin_write16(IMDMA_S1_CURR_Y_COUNT, val) 1119 #define pIMDMA_S1_IRQ_STATUS ((uint16_t volatile *)IMDMA_S1_IRQ_STATUS) 1120 #define bfin_read_IMDMA_S1_IRQ_STATUS() bfin_read16(IMDMA_S1_IRQ_STATUS) 1121 #define bfin_write_IMDMA_S1_IRQ_STATUS(val) bfin_write16(IMDMA_S1_IRQ_STATUS, val) 1122 #define pIMDMA_D1_CONFIG ((uint16_t volatile *)IMDMA_D1_CONFIG) 1123 #define bfin_read_IMDMA_D1_CONFIG() bfin_read16(IMDMA_D1_CONFIG) 1124 #define bfin_write_IMDMA_D1_CONFIG(val) bfin_write16(IMDMA_D1_CONFIG, val) 1125 #define pIMDMA_D1_NEXT_DESC_PTR ((void * volatile *)IMDMA_D1_NEXT_DESC_PTR) 1126 #define bfin_read_IMDMA_D1_NEXT_DESC_PTR() bfin_readPTR(IMDMA_D1_NEXT_DESC_PTR) 1127 #define bfin_write_IMDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_D1_NEXT_DESC_PTR, val) 1128 #define pIMDMA_D1_START_ADDR ((void * volatile *)IMDMA_D1_START_ADDR) 1129 #define bfin_read_IMDMA_D1_START_ADDR() bfin_readPTR(IMDMA_D1_START_ADDR) 1130 #define bfin_write_IMDMA_D1_START_ADDR(val) bfin_writePTR(IMDMA_D1_START_ADDR, val) 1131 #define pIMDMA_D1_X_COUNT ((uint16_t volatile *)IMDMA_D1_X_COUNT) 1132 #define bfin_read_IMDMA_D1_X_COUNT() bfin_read16(IMDMA_D1_X_COUNT) 1133 #define bfin_write_IMDMA_D1_X_COUNT(val) bfin_write16(IMDMA_D1_X_COUNT, val) 1134 #define pIMDMA_D1_Y_COUNT ((uint16_t volatile *)IMDMA_D1_Y_COUNT) 1135 #define bfin_read_IMDMA_D1_Y_COUNT() bfin_read16(IMDMA_D1_Y_COUNT) 1136 #define bfin_write_IMDMA_D1_Y_COUNT(val) bfin_write16(IMDMA_D1_Y_COUNT, val) 1137 #define pIMDMA_D1_X_MODIFY ((uint16_t volatile *)IMDMA_D1_X_MODIFY) 1138 #define bfin_read_IMDMA_D1_X_MODIFY() bfin_read16(IMDMA_D1_X_MODIFY) 1139 #define bfin_write_IMDMA_D1_X_MODIFY(val) bfin_write16(IMDMA_D1_X_MODIFY, val) 1140 #define pIMDMA_D1_Y_MODIFY ((uint16_t volatile *)IMDMA_D1_Y_MODIFY) 1141 #define bfin_read_IMDMA_D1_Y_MODIFY() bfin_read16(IMDMA_D1_Y_MODIFY) 1142 #define bfin_write_IMDMA_D1_Y_MODIFY(val) bfin_write16(IMDMA_D1_Y_MODIFY, val) 1143 #define pIMDMA_D1_CURR_DESC_PTR ((void * volatile *)IMDMA_D1_CURR_DESC_PTR) 1144 #define bfin_read_IMDMA_D1_CURR_DESC_PTR() bfin_readPTR(IMDMA_D1_CURR_DESC_PTR) 1145 #define bfin_write_IMDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_D1_CURR_DESC_PTR, val) 1146 #define pIMDMA_D1_CURR_ADDR ((void * volatile *)IMDMA_D1_CURR_ADDR) 1147 #define bfin_read_IMDMA_D1_CURR_ADDR() bfin_readPTR(IMDMA_D1_CURR_ADDR) 1148 #define bfin_write_IMDMA_D1_CURR_ADDR(val) bfin_writePTR(IMDMA_D1_CURR_ADDR, val) 1149 #define pIMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)IMDMA_D1_CURR_X_COUNT) 1150 #define bfin_read_IMDMA_D1_CURR_X_COUNT() bfin_read16(IMDMA_D1_CURR_X_COUNT) 1151 #define bfin_write_IMDMA_D1_CURR_X_COUNT(val) bfin_write16(IMDMA_D1_CURR_X_COUNT, val) 1152 #define pIMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)IMDMA_D1_CURR_Y_COUNT) 1153 #define bfin_read_IMDMA_D1_CURR_Y_COUNT() bfin_read16(IMDMA_D1_CURR_Y_COUNT) 1154 #define bfin_write_IMDMA_D1_CURR_Y_COUNT(val) bfin_write16(IMDMA_D1_CURR_Y_COUNT, val) 1155 #define pIMDMA_D1_IRQ_STATUS ((uint16_t volatile *)IMDMA_D1_IRQ_STATUS) 1156 #define bfin_read_IMDMA_D1_IRQ_STATUS() bfin_read16(IMDMA_D1_IRQ_STATUS) 1157 #define bfin_write_IMDMA_D1_IRQ_STATUS(val) bfin_write16(IMDMA_D1_IRQ_STATUS, val) 1158 #define pMDMA1_S0_CONFIG ((uint16_t volatile *)MDMA1_S0_CONFIG) 1159 #define bfin_read_MDMA1_S0_CONFIG() bfin_read16(MDMA1_S0_CONFIG) 1160 #define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG, val) 1161 #define pMDMA1_S0_NEXT_DESC_PTR ((void * volatile *)MDMA1_S0_NEXT_DESC_PTR) 1162 #define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S0_NEXT_DESC_PTR) 1163 #define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S0_NEXT_DESC_PTR, val) 1164 #define pMDMA1_S0_START_ADDR ((void * volatile *)MDMA1_S0_START_ADDR) 1165 #define bfin_read_MDMA1_S0_START_ADDR() bfin_readPTR(MDMA1_S0_START_ADDR) 1166 #define bfin_write_MDMA1_S0_START_ADDR(val) bfin_writePTR(MDMA1_S0_START_ADDR, val) 1167 #define pMDMA1_S0_X_COUNT ((uint16_t volatile *)MDMA1_S0_X_COUNT) 1168 #define bfin_read_MDMA1_S0_X_COUNT() bfin_read16(MDMA1_S0_X_COUNT) 1169 #define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT, val) 1170 #define pMDMA1_S0_Y_COUNT ((uint16_t volatile *)MDMA1_S0_Y_COUNT) 1171 #define bfin_read_MDMA1_S0_Y_COUNT() bfin_read16(MDMA1_S0_Y_COUNT) 1172 #define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT, val) 1173 #define pMDMA1_S0_X_MODIFY ((uint16_t volatile *)MDMA1_S0_X_MODIFY) 1174 #define bfin_read_MDMA1_S0_X_MODIFY() bfin_read16(MDMA1_S0_X_MODIFY) 1175 #define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY, val) 1176 #define pMDMA1_S0_Y_MODIFY ((uint16_t volatile *)MDMA1_S0_Y_MODIFY) 1177 #define bfin_read_MDMA1_S0_Y_MODIFY() bfin_read16(MDMA1_S0_Y_MODIFY) 1178 #define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY, val) 1179 #define pMDMA1_S0_CURR_DESC_PTR ((void * volatile *)MDMA1_S0_CURR_DESC_PTR) 1180 #define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_readPTR(MDMA1_S0_CURR_DESC_PTR) 1181 #define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S0_CURR_DESC_PTR, val) 1182 #define pMDMA1_S0_CURR_ADDR ((void * volatile *)MDMA1_S0_CURR_ADDR) 1183 #define bfin_read_MDMA1_S0_CURR_ADDR() bfin_readPTR(MDMA1_S0_CURR_ADDR) 1184 #define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_writePTR(MDMA1_S0_CURR_ADDR, val) 1185 #define pMDMA1_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA1_S0_CURR_X_COUNT) 1186 #define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT) 1187 #define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT, val) 1188 #define pMDMA1_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA1_S0_CURR_Y_COUNT) 1189 #define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT) 1190 #define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT, val) 1191 #define pMDMA1_S0_IRQ_STATUS ((uint16_t volatile *)MDMA1_S0_IRQ_STATUS) 1192 #define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS) 1193 #define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS, val) 1194 #define pMDMA1_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA1_S0_PERIPHERAL_MAP) 1195 #define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP) 1196 #define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP, val) 1197 #define pMDMA1_D0_CONFIG ((uint16_t volatile *)MDMA1_D0_CONFIG) 1198 #define bfin_read_MDMA1_D0_CONFIG() bfin_read16(MDMA1_D0_CONFIG) 1199 #define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG, val) 1200 #define pMDMA1_D0_NEXT_DESC_PTR ((void * volatile *)MDMA1_D0_NEXT_DESC_PTR) 1201 #define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D0_NEXT_DESC_PTR) 1202 #define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D0_NEXT_DESC_PTR, val) 1203 #define pMDMA1_D0_START_ADDR ((void * volatile *)MDMA1_D0_START_ADDR) 1204 #define bfin_read_MDMA1_D0_START_ADDR() bfin_readPTR(MDMA1_D0_START_ADDR) 1205 #define bfin_write_MDMA1_D0_START_ADDR(val) bfin_writePTR(MDMA1_D0_START_ADDR, val) 1206 #define pMDMA1_D0_X_COUNT ((uint16_t volatile *)MDMA1_D0_X_COUNT) 1207 #define bfin_read_MDMA1_D0_X_COUNT() bfin_read16(MDMA1_D0_X_COUNT) 1208 #define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT, val) 1209 #define pMDMA1_D0_Y_COUNT ((uint16_t volatile *)MDMA1_D0_Y_COUNT) 1210 #define bfin_read_MDMA1_D0_Y_COUNT() bfin_read16(MDMA1_D0_Y_COUNT) 1211 #define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT, val) 1212 #define pMDMA1_D0_X_MODIFY ((uint16_t volatile *)MDMA1_D0_X_MODIFY) 1213 #define bfin_read_MDMA1_D0_X_MODIFY() bfin_read16(MDMA1_D0_X_MODIFY) 1214 #define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY, val) 1215 #define pMDMA1_D0_Y_MODIFY ((uint16_t volatile *)MDMA1_D0_Y_MODIFY) 1216 #define bfin_read_MDMA1_D0_Y_MODIFY() bfin_read16(MDMA1_D0_Y_MODIFY) 1217 #define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY, val) 1218 #define pMDMA1_D0_CURR_DESC_PTR ((void * volatile *)MDMA1_D0_CURR_DESC_PTR) 1219 #define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_readPTR(MDMA1_D0_CURR_DESC_PTR) 1220 #define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D0_CURR_DESC_PTR, val) 1221 #define pMDMA1_D0_CURR_ADDR ((void * volatile *)MDMA1_D0_CURR_ADDR) 1222 #define bfin_read_MDMA1_D0_CURR_ADDR() bfin_readPTR(MDMA1_D0_CURR_ADDR) 1223 #define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_writePTR(MDMA1_D0_CURR_ADDR, val) 1224 #define pMDMA1_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA1_D0_CURR_X_COUNT) 1225 #define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT) 1226 #define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT, val) 1227 #define pMDMA1_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA1_D0_CURR_Y_COUNT) 1228 #define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT) 1229 #define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT, val) 1230 #define pMDMA1_D0_IRQ_STATUS ((uint16_t volatile *)MDMA1_D0_IRQ_STATUS) 1231 #define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS) 1232 #define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS, val) 1233 #define pMDMA1_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA1_D0_PERIPHERAL_MAP) 1234 #define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP) 1235 #define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP, val) 1236 #define pMDMA1_S1_CONFIG ((uint16_t volatile *)MDMA1_S1_CONFIG) 1237 #define bfin_read_MDMA1_S1_CONFIG() bfin_read16(MDMA1_S1_CONFIG) 1238 #define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG, val) 1239 #define pMDMA1_S1_NEXT_DESC_PTR ((void * volatile *)MDMA1_S1_NEXT_DESC_PTR) 1240 #define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S1_NEXT_DESC_PTR) 1241 #define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S1_NEXT_DESC_PTR, val) 1242 #define pMDMA1_S1_START_ADDR ((void * volatile *)MDMA1_S1_START_ADDR) 1243 #define bfin_read_MDMA1_S1_START_ADDR() bfin_readPTR(MDMA1_S1_START_ADDR) 1244 #define bfin_write_MDMA1_S1_START_ADDR(val) bfin_writePTR(MDMA1_S1_START_ADDR, val) 1245 #define pMDMA1_S1_X_COUNT ((uint16_t volatile *)MDMA1_S1_X_COUNT) 1246 #define bfin_read_MDMA1_S1_X_COUNT() bfin_read16(MDMA1_S1_X_COUNT) 1247 #define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT, val) 1248 #define pMDMA1_S1_Y_COUNT ((uint16_t volatile *)MDMA1_S1_Y_COUNT) 1249 #define bfin_read_MDMA1_S1_Y_COUNT() bfin_read16(MDMA1_S1_Y_COUNT) 1250 #define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT, val) 1251 #define pMDMA1_S1_X_MODIFY ((uint16_t volatile *)MDMA1_S1_X_MODIFY) 1252 #define bfin_read_MDMA1_S1_X_MODIFY() bfin_read16(MDMA1_S1_X_MODIFY) 1253 #define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY, val) 1254 #define pMDMA1_S1_Y_MODIFY ((uint16_t volatile *)MDMA1_S1_Y_MODIFY) 1255 #define bfin_read_MDMA1_S1_Y_MODIFY() bfin_read16(MDMA1_S1_Y_MODIFY) 1256 #define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY, val) 1257 #define pMDMA1_S1_CURR_DESC_PTR ((void * volatile *)MDMA1_S1_CURR_DESC_PTR) 1258 #define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_readPTR(MDMA1_S1_CURR_DESC_PTR) 1259 #define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S1_CURR_DESC_PTR, val) 1260 #define pMDMA1_S1_CURR_ADDR ((void * volatile *)MDMA1_S1_CURR_ADDR) 1261 #define bfin_read_MDMA1_S1_CURR_ADDR() bfin_readPTR(MDMA1_S1_CURR_ADDR) 1262 #define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_writePTR(MDMA1_S1_CURR_ADDR, val) 1263 #define pMDMA1_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA1_S1_CURR_X_COUNT) 1264 #define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT) 1265 #define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT, val) 1266 #define pMDMA1_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA1_S1_CURR_Y_COUNT) 1267 #define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT) 1268 #define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT, val) 1269 #define pMDMA1_S1_IRQ_STATUS ((uint16_t volatile *)MDMA1_S1_IRQ_STATUS) 1270 #define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS) 1271 #define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS, val) 1272 #define pMDMA1_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA1_S1_PERIPHERAL_MAP) 1273 #define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP) 1274 #define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP, val) 1275 #define pMDMA1_D1_CONFIG ((uint16_t volatile *)MDMA1_D1_CONFIG) 1276 #define bfin_read_MDMA1_D1_CONFIG() bfin_read16(MDMA1_D1_CONFIG) 1277 #define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG, val) 1278 #define pMDMA1_D1_NEXT_DESC_PTR ((void * volatile *)MDMA1_D1_NEXT_DESC_PTR) 1279 #define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D1_NEXT_DESC_PTR) 1280 #define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D1_NEXT_DESC_PTR, val) 1281 #define pMDMA1_D1_START_ADDR ((void * volatile *)MDMA1_D1_START_ADDR) 1282 #define bfin_read_MDMA1_D1_START_ADDR() bfin_readPTR(MDMA1_D1_START_ADDR) 1283 #define bfin_write_MDMA1_D1_START_ADDR(val) bfin_writePTR(MDMA1_D1_START_ADDR, val) 1284 #define pMDMA1_D1_X_COUNT ((uint16_t volatile *)MDMA1_D1_X_COUNT) 1285 #define bfin_read_MDMA1_D1_X_COUNT() bfin_read16(MDMA1_D1_X_COUNT) 1286 #define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT, val) 1287 #define pMDMA1_D1_Y_COUNT ((uint16_t volatile *)MDMA1_D1_Y_COUNT) 1288 #define bfin_read_MDMA1_D1_Y_COUNT() bfin_read16(MDMA1_D1_Y_COUNT) 1289 #define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT, val) 1290 #define pMDMA1_D1_X_MODIFY ((uint16_t volatile *)MDMA1_D1_X_MODIFY) 1291 #define bfin_read_MDMA1_D1_X_MODIFY() bfin_read16(MDMA1_D1_X_MODIFY) 1292 #define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY, val) 1293 #define pMDMA1_D1_Y_MODIFY ((uint16_t volatile *)MDMA1_D1_Y_MODIFY) 1294 #define bfin_read_MDMA1_D1_Y_MODIFY() bfin_read16(MDMA1_D1_Y_MODIFY) 1295 #define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY, val) 1296 #define pMDMA1_D1_CURR_DESC_PTR ((void * volatile *)MDMA1_D1_CURR_DESC_PTR) 1297 #define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_readPTR(MDMA1_D1_CURR_DESC_PTR) 1298 #define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D1_CURR_DESC_PTR, val) 1299 #define pMDMA1_D1_CURR_ADDR ((void * volatile *)MDMA1_D1_CURR_ADDR) 1300 #define bfin_read_MDMA1_D1_CURR_ADDR() bfin_readPTR(MDMA1_D1_CURR_ADDR) 1301 #define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_writePTR(MDMA1_D1_CURR_ADDR, val) 1302 #define pMDMA1_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA1_D1_CURR_X_COUNT) 1303 #define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT) 1304 #define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT, val) 1305 #define pMDMA1_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA1_D1_CURR_Y_COUNT) 1306 #define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT) 1307 #define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT, val) 1308 #define pMDMA1_D1_IRQ_STATUS ((uint16_t volatile *)MDMA1_D1_IRQ_STATUS) 1309 #define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS) 1310 #define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS, val) 1311 #define pMDMA1_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA1_D1_PERIPHERAL_MAP) 1312 #define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP) 1313 #define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP, val) 1314 #define pMDMA2_S0_CONFIG ((uint16_t volatile *)MDMA2_S0_CONFIG) 1315 #define bfin_read_MDMA2_S0_CONFIG() bfin_read16(MDMA2_S0_CONFIG) 1316 #define bfin_write_MDMA2_S0_CONFIG(val) bfin_write16(MDMA2_S0_CONFIG, val) 1317 #define pMDMA2_S0_NEXT_DESC_PTR ((void * volatile *)MDMA2_S0_NEXT_DESC_PTR) 1318 #define bfin_read_MDMA2_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA2_S0_NEXT_DESC_PTR) 1319 #define bfin_write_MDMA2_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_S0_NEXT_DESC_PTR, val) 1320 #define pMDMA2_S0_START_ADDR ((void * volatile *)MDMA2_S0_START_ADDR) 1321 #define bfin_read_MDMA2_S0_START_ADDR() bfin_readPTR(MDMA2_S0_START_ADDR) 1322 #define bfin_write_MDMA2_S0_START_ADDR(val) bfin_writePTR(MDMA2_S0_START_ADDR, val) 1323 #define pMDMA2_S0_X_COUNT ((uint16_t volatile *)MDMA2_S0_X_COUNT) 1324 #define bfin_read_MDMA2_S0_X_COUNT() bfin_read16(MDMA2_S0_X_COUNT) 1325 #define bfin_write_MDMA2_S0_X_COUNT(val) bfin_write16(MDMA2_S0_X_COUNT, val) 1326 #define pMDMA2_S0_Y_COUNT ((uint16_t volatile *)MDMA2_S0_Y_COUNT) 1327 #define bfin_read_MDMA2_S0_Y_COUNT() bfin_read16(MDMA2_S0_Y_COUNT) 1328 #define bfin_write_MDMA2_S0_Y_COUNT(val) bfin_write16(MDMA2_S0_Y_COUNT, val) 1329 #define pMDMA2_S0_X_MODIFY ((uint16_t volatile *)MDMA2_S0_X_MODIFY) 1330 #define bfin_read_MDMA2_S0_X_MODIFY() bfin_read16(MDMA2_S0_X_MODIFY) 1331 #define bfin_write_MDMA2_S0_X_MODIFY(val) bfin_write16(MDMA2_S0_X_MODIFY, val) 1332 #define pMDMA2_S0_Y_MODIFY ((uint16_t volatile *)MDMA2_S0_Y_MODIFY) 1333 #define bfin_read_MDMA2_S0_Y_MODIFY() bfin_read16(MDMA2_S0_Y_MODIFY) 1334 #define bfin_write_MDMA2_S0_Y_MODIFY(val) bfin_write16(MDMA2_S0_Y_MODIFY, val) 1335 #define pMDMA2_S0_CURR_DESC_PTR ((void * volatile *)MDMA2_S0_CURR_DESC_PTR) 1336 #define bfin_read_MDMA2_S0_CURR_DESC_PTR() bfin_readPTR(MDMA2_S0_CURR_DESC_PTR) 1337 #define bfin_write_MDMA2_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_S0_CURR_DESC_PTR, val) 1338 #define pMDMA2_S0_CURR_ADDR ((void * volatile *)MDMA2_S0_CURR_ADDR) 1339 #define bfin_read_MDMA2_S0_CURR_ADDR() bfin_readPTR(MDMA2_S0_CURR_ADDR) 1340 #define bfin_write_MDMA2_S0_CURR_ADDR(val) bfin_writePTR(MDMA2_S0_CURR_ADDR, val) 1341 #define pMDMA2_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA2_S0_CURR_X_COUNT) 1342 #define bfin_read_MDMA2_S0_CURR_X_COUNT() bfin_read16(MDMA2_S0_CURR_X_COUNT) 1343 #define bfin_write_MDMA2_S0_CURR_X_COUNT(val) bfin_write16(MDMA2_S0_CURR_X_COUNT, val) 1344 #define pMDMA2_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA2_S0_CURR_Y_COUNT) 1345 #define bfin_read_MDMA2_S0_CURR_Y_COUNT() bfin_read16(MDMA2_S0_CURR_Y_COUNT) 1346 #define bfin_write_MDMA2_S0_CURR_Y_COUNT(val) bfin_write16(MDMA2_S0_CURR_Y_COUNT, val) 1347 #define pMDMA2_S0_IRQ_STATUS ((uint16_t volatile *)MDMA2_S0_IRQ_STATUS) 1348 #define bfin_read_MDMA2_S0_IRQ_STATUS() bfin_read16(MDMA2_S0_IRQ_STATUS) 1349 #define bfin_write_MDMA2_S0_IRQ_STATUS(val) bfin_write16(MDMA2_S0_IRQ_STATUS, val) 1350 #define pMDMA2_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA2_S0_PERIPHERAL_MAP) 1351 #define bfin_read_MDMA2_S0_PERIPHERAL_MAP() bfin_read16(MDMA2_S0_PERIPHERAL_MAP) 1352 #define bfin_write_MDMA2_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S0_PERIPHERAL_MAP, val) 1353 #define pMDMA2_D0_CONFIG ((uint16_t volatile *)MDMA2_D0_CONFIG) 1354 #define bfin_read_MDMA2_D0_CONFIG() bfin_read16(MDMA2_D0_CONFIG) 1355 #define bfin_write_MDMA2_D0_CONFIG(val) bfin_write16(MDMA2_D0_CONFIG, val) 1356 #define pMDMA2_D0_NEXT_DESC_PTR ((void * volatile *)MDMA2_D0_NEXT_DESC_PTR) 1357 #define bfin_read_MDMA2_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA2_D0_NEXT_DESC_PTR) 1358 #define bfin_write_MDMA2_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_D0_NEXT_DESC_PTR, val) 1359 #define pMDMA2_D0_START_ADDR ((void * volatile *)MDMA2_D0_START_ADDR) 1360 #define bfin_read_MDMA2_D0_START_ADDR() bfin_readPTR(MDMA2_D0_START_ADDR) 1361 #define bfin_write_MDMA2_D0_START_ADDR(val) bfin_writePTR(MDMA2_D0_START_ADDR, val) 1362 #define pMDMA2_D0_X_COUNT ((uint16_t volatile *)MDMA2_D0_X_COUNT) 1363 #define bfin_read_MDMA2_D0_X_COUNT() bfin_read16(MDMA2_D0_X_COUNT) 1364 #define bfin_write_MDMA2_D0_X_COUNT(val) bfin_write16(MDMA2_D0_X_COUNT, val) 1365 #define pMDMA2_D0_Y_COUNT ((uint16_t volatile *)MDMA2_D0_Y_COUNT) 1366 #define bfin_read_MDMA2_D0_Y_COUNT() bfin_read16(MDMA2_D0_Y_COUNT) 1367 #define bfin_write_MDMA2_D0_Y_COUNT(val) bfin_write16(MDMA2_D0_Y_COUNT, val) 1368 #define pMDMA2_D0_X_MODIFY ((uint16_t volatile *)MDMA2_D0_X_MODIFY) 1369 #define bfin_read_MDMA2_D0_X_MODIFY() bfin_read16(MDMA2_D0_X_MODIFY) 1370 #define bfin_write_MDMA2_D0_X_MODIFY(val) bfin_write16(MDMA2_D0_X_MODIFY, val) 1371 #define pMDMA2_D0_Y_MODIFY ((uint16_t volatile *)MDMA2_D0_Y_MODIFY) 1372 #define bfin_read_MDMA2_D0_Y_MODIFY() bfin_read16(MDMA2_D0_Y_MODIFY) 1373 #define bfin_write_MDMA2_D0_Y_MODIFY(val) bfin_write16(MDMA2_D0_Y_MODIFY, val) 1374 #define pMDMA2_D0_CURR_DESC_PTR ((void * volatile *)MDMA2_D0_CURR_DESC_PTR) 1375 #define bfin_read_MDMA2_D0_CURR_DESC_PTR() bfin_readPTR(MDMA2_D0_CURR_DESC_PTR) 1376 #define bfin_write_MDMA2_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_D0_CURR_DESC_PTR, val) 1377 #define pMDMA2_D0_CURR_ADDR ((void * volatile *)MDMA2_D0_CURR_ADDR) 1378 #define bfin_read_MDMA2_D0_CURR_ADDR() bfin_readPTR(MDMA2_D0_CURR_ADDR) 1379 #define bfin_write_MDMA2_D0_CURR_ADDR(val) bfin_writePTR(MDMA2_D0_CURR_ADDR, val) 1380 #define pMDMA2_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA2_D0_CURR_X_COUNT) 1381 #define bfin_read_MDMA2_D0_CURR_X_COUNT() bfin_read16(MDMA2_D0_CURR_X_COUNT) 1382 #define bfin_write_MDMA2_D0_CURR_X_COUNT(val) bfin_write16(MDMA2_D0_CURR_X_COUNT, val) 1383 #define pMDMA2_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA2_D0_CURR_Y_COUNT) 1384 #define bfin_read_MDMA2_D0_CURR_Y_COUNT() bfin_read16(MDMA2_D0_CURR_Y_COUNT) 1385 #define bfin_write_MDMA2_D0_CURR_Y_COUNT(val) bfin_write16(MDMA2_D0_CURR_Y_COUNT, val) 1386 #define pMDMA2_D0_IRQ_STATUS ((uint16_t volatile *)MDMA2_D0_IRQ_STATUS) 1387 #define bfin_read_MDMA2_D0_IRQ_STATUS() bfin_read16(MDMA2_D0_IRQ_STATUS) 1388 #define bfin_write_MDMA2_D0_IRQ_STATUS(val) bfin_write16(MDMA2_D0_IRQ_STATUS, val) 1389 #define pMDMA2_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA2_D0_PERIPHERAL_MAP) 1390 #define bfin_read_MDMA2_D0_PERIPHERAL_MAP() bfin_read16(MDMA2_D0_PERIPHERAL_MAP) 1391 #define bfin_write_MDMA2_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D0_PERIPHERAL_MAP, val) 1392 #define pMDMA2_S1_CONFIG ((uint16_t volatile *)MDMA2_S1_CONFIG) 1393 #define bfin_read_MDMA2_S1_CONFIG() bfin_read16(MDMA2_S1_CONFIG) 1394 #define bfin_write_MDMA2_S1_CONFIG(val) bfin_write16(MDMA2_S1_CONFIG, val) 1395 #define pMDMA2_S1_NEXT_DESC_PTR ((void * volatile *)MDMA2_S1_NEXT_DESC_PTR) 1396 #define bfin_read_MDMA2_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA2_S1_NEXT_DESC_PTR) 1397 #define bfin_write_MDMA2_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_S1_NEXT_DESC_PTR, val) 1398 #define pMDMA2_S1_START_ADDR ((void * volatile *)MDMA2_S1_START_ADDR) 1399 #define bfin_read_MDMA2_S1_START_ADDR() bfin_readPTR(MDMA2_S1_START_ADDR) 1400 #define bfin_write_MDMA2_S1_START_ADDR(val) bfin_writePTR(MDMA2_S1_START_ADDR, val) 1401 #define pMDMA2_S1_X_COUNT ((uint16_t volatile *)MDMA2_S1_X_COUNT) 1402 #define bfin_read_MDMA2_S1_X_COUNT() bfin_read16(MDMA2_S1_X_COUNT) 1403 #define bfin_write_MDMA2_S1_X_COUNT(val) bfin_write16(MDMA2_S1_X_COUNT, val) 1404 #define pMDMA2_S1_Y_COUNT ((uint16_t volatile *)MDMA2_S1_Y_COUNT) 1405 #define bfin_read_MDMA2_S1_Y_COUNT() bfin_read16(MDMA2_S1_Y_COUNT) 1406 #define bfin_write_MDMA2_S1_Y_COUNT(val) bfin_write16(MDMA2_S1_Y_COUNT, val) 1407 #define pMDMA2_S1_X_MODIFY ((uint16_t volatile *)MDMA2_S1_X_MODIFY) 1408 #define bfin_read_MDMA2_S1_X_MODIFY() bfin_read16(MDMA2_S1_X_MODIFY) 1409 #define bfin_write_MDMA2_S1_X_MODIFY(val) bfin_write16(MDMA2_S1_X_MODIFY, val) 1410 #define pMDMA2_S1_Y_MODIFY ((uint16_t volatile *)MDMA2_S1_Y_MODIFY) 1411 #define bfin_read_MDMA2_S1_Y_MODIFY() bfin_read16(MDMA2_S1_Y_MODIFY) 1412 #define bfin_write_MDMA2_S1_Y_MODIFY(val) bfin_write16(MDMA2_S1_Y_MODIFY, val) 1413 #define pMDMA2_S1_CURR_DESC_PTR ((void * volatile *)MDMA2_S1_CURR_DESC_PTR) 1414 #define bfin_read_MDMA2_S1_CURR_DESC_PTR() bfin_readPTR(MDMA2_S1_CURR_DESC_PTR) 1415 #define bfin_write_MDMA2_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_S1_CURR_DESC_PTR, val) 1416 #define pMDMA2_S1_CURR_ADDR ((void * volatile *)MDMA2_S1_CURR_ADDR) 1417 #define bfin_read_MDMA2_S1_CURR_ADDR() bfin_readPTR(MDMA2_S1_CURR_ADDR) 1418 #define bfin_write_MDMA2_S1_CURR_ADDR(val) bfin_writePTR(MDMA2_S1_CURR_ADDR, val) 1419 #define pMDMA2_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA2_S1_CURR_X_COUNT) 1420 #define bfin_read_MDMA2_S1_CURR_X_COUNT() bfin_read16(MDMA2_S1_CURR_X_COUNT) 1421 #define bfin_write_MDMA2_S1_CURR_X_COUNT(val) bfin_write16(MDMA2_S1_CURR_X_COUNT, val) 1422 #define pMDMA2_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA2_S1_CURR_Y_COUNT) 1423 #define bfin_read_MDMA2_S1_CURR_Y_COUNT() bfin_read16(MDMA2_S1_CURR_Y_COUNT) 1424 #define bfin_write_MDMA2_S1_CURR_Y_COUNT(val) bfin_write16(MDMA2_S1_CURR_Y_COUNT, val) 1425 #define pMDMA2_S1_IRQ_STATUS ((uint16_t volatile *)MDMA2_S1_IRQ_STATUS) 1426 #define bfin_read_MDMA2_S1_IRQ_STATUS() bfin_read16(MDMA2_S1_IRQ_STATUS) 1427 #define bfin_write_MDMA2_S1_IRQ_STATUS(val) bfin_write16(MDMA2_S1_IRQ_STATUS, val) 1428 #define pMDMA2_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA2_S1_PERIPHERAL_MAP) 1429 #define bfin_read_MDMA2_S1_PERIPHERAL_MAP() bfin_read16(MDMA2_S1_PERIPHERAL_MAP) 1430 #define bfin_write_MDMA2_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S1_PERIPHERAL_MAP, val) 1431 #define pMDMA2_D1_CONFIG ((uint16_t volatile *)MDMA2_D1_CONFIG) 1432 #define bfin_read_MDMA2_D1_CONFIG() bfin_read16(MDMA2_D1_CONFIG) 1433 #define bfin_write_MDMA2_D1_CONFIG(val) bfin_write16(MDMA2_D1_CONFIG, val) 1434 #define pMDMA2_D1_NEXT_DESC_PTR ((void * volatile *)MDMA2_D1_NEXT_DESC_PTR) 1435 #define bfin_read_MDMA2_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA2_D1_NEXT_DESC_PTR) 1436 #define bfin_write_MDMA2_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_D1_NEXT_DESC_PTR, val) 1437 #define pMDMA2_D1_START_ADDR ((void * volatile *)MDMA2_D1_START_ADDR) 1438 #define bfin_read_MDMA2_D1_START_ADDR() bfin_readPTR(MDMA2_D1_START_ADDR) 1439 #define bfin_write_MDMA2_D1_START_ADDR(val) bfin_writePTR(MDMA2_D1_START_ADDR, val) 1440 #define pMDMA2_D1_X_COUNT ((uint16_t volatile *)MDMA2_D1_X_COUNT) 1441 #define bfin_read_MDMA2_D1_X_COUNT() bfin_read16(MDMA2_D1_X_COUNT) 1442 #define bfin_write_MDMA2_D1_X_COUNT(val) bfin_write16(MDMA2_D1_X_COUNT, val) 1443 #define pMDMA2_D1_Y_COUNT ((uint16_t volatile *)MDMA2_D1_Y_COUNT) 1444 #define bfin_read_MDMA2_D1_Y_COUNT() bfin_read16(MDMA2_D1_Y_COUNT) 1445 #define bfin_write_MDMA2_D1_Y_COUNT(val) bfin_write16(MDMA2_D1_Y_COUNT, val) 1446 #define pMDMA2_D1_X_MODIFY ((uint16_t volatile *)MDMA2_D1_X_MODIFY) 1447 #define bfin_read_MDMA2_D1_X_MODIFY() bfin_read16(MDMA2_D1_X_MODIFY) 1448 #define bfin_write_MDMA2_D1_X_MODIFY(val) bfin_write16(MDMA2_D1_X_MODIFY, val) 1449 #define pMDMA2_D1_Y_MODIFY ((uint16_t volatile *)MDMA2_D1_Y_MODIFY) 1450 #define bfin_read_MDMA2_D1_Y_MODIFY() bfin_read16(MDMA2_D1_Y_MODIFY) 1451 #define bfin_write_MDMA2_D1_Y_MODIFY(val) bfin_write16(MDMA2_D1_Y_MODIFY, val) 1452 #define pMDMA2_D1_CURR_DESC_PTR ((void * volatile *)MDMA2_D1_CURR_DESC_PTR) 1453 #define bfin_read_MDMA2_D1_CURR_DESC_PTR() bfin_readPTR(MDMA2_D1_CURR_DESC_PTR) 1454 #define bfin_write_MDMA2_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_D1_CURR_DESC_PTR, val) 1455 #define pMDMA2_D1_CURR_ADDR ((void * volatile *)MDMA2_D1_CURR_ADDR) 1456 #define bfin_read_MDMA2_D1_CURR_ADDR() bfin_readPTR(MDMA2_D1_CURR_ADDR) 1457 #define bfin_write_MDMA2_D1_CURR_ADDR(val) bfin_writePTR(MDMA2_D1_CURR_ADDR, val) 1458 #define pMDMA2_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA2_D1_CURR_X_COUNT) 1459 #define bfin_read_MDMA2_D1_CURR_X_COUNT() bfin_read16(MDMA2_D1_CURR_X_COUNT) 1460 #define bfin_write_MDMA2_D1_CURR_X_COUNT(val) bfin_write16(MDMA2_D1_CURR_X_COUNT, val) 1461 #define pMDMA2_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA2_D1_CURR_Y_COUNT) 1462 #define bfin_read_MDMA2_D1_CURR_Y_COUNT() bfin_read16(MDMA2_D1_CURR_Y_COUNT) 1463 #define bfin_write_MDMA2_D1_CURR_Y_COUNT(val) bfin_write16(MDMA2_D1_CURR_Y_COUNT, val) 1464 #define pMDMA2_D1_IRQ_STATUS ((uint16_t volatile *)MDMA2_D1_IRQ_STATUS) 1465 #define bfin_read_MDMA2_D1_IRQ_STATUS() bfin_read16(MDMA2_D1_IRQ_STATUS) 1466 #define bfin_write_MDMA2_D1_IRQ_STATUS(val) bfin_write16(MDMA2_D1_IRQ_STATUS, val) 1467 #define pMDMA2_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA2_D1_PERIPHERAL_MAP) 1468 #define bfin_read_MDMA2_D1_PERIPHERAL_MAP() bfin_read16(MDMA2_D1_PERIPHERAL_MAP) 1469 #define bfin_write_MDMA2_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D1_PERIPHERAL_MAP, val) 1470 #define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG) 1471 #define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) 1472 #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) 1473 #define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER) 1474 #define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) 1475 #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) 1476 #define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD) 1477 #define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) 1478 #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) 1479 #define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH) 1480 #define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) 1481 #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) 1482 #define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG) 1483 #define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) 1484 #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) 1485 #define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER) 1486 #define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) 1487 #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) 1488 #define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD) 1489 #define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) 1490 #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) 1491 #define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH) 1492 #define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) 1493 #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) 1494 #define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG) 1495 #define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) 1496 #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) 1497 #define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER) 1498 #define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) 1499 #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) 1500 #define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD) 1501 #define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) 1502 #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) 1503 #define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH) 1504 #define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) 1505 #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) 1506 #define pTIMER3_CONFIG ((uint16_t volatile *)TIMER3_CONFIG) 1507 #define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) 1508 #define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) 1509 #define pTIMER3_COUNTER ((uint32_t volatile *)TIMER3_COUNTER) 1510 #define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) 1511 #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) 1512 #define pTIMER3_PERIOD ((uint32_t volatile *)TIMER3_PERIOD) 1513 #define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) 1514 #define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) 1515 #define pTIMER3_WIDTH ((uint32_t volatile *)TIMER3_WIDTH) 1516 #define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) 1517 #define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) 1518 #define pTIMER4_CONFIG ((uint16_t volatile *)TIMER4_CONFIG) 1519 #define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) 1520 #define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) 1521 #define pTIMER4_COUNTER ((uint32_t volatile *)TIMER4_COUNTER) 1522 #define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) 1523 #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) 1524 #define pTIMER4_PERIOD ((uint32_t volatile *)TIMER4_PERIOD) 1525 #define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) 1526 #define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) 1527 #define pTIMER4_WIDTH ((uint32_t volatile *)TIMER4_WIDTH) 1528 #define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) 1529 #define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) 1530 #define pTIMER5_CONFIG ((uint16_t volatile *)TIMER5_CONFIG) 1531 #define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) 1532 #define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) 1533 #define pTIMER5_COUNTER ((uint32_t volatile *)TIMER5_COUNTER) 1534 #define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) 1535 #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) 1536 #define pTIMER5_PERIOD ((uint32_t volatile *)TIMER5_PERIOD) 1537 #define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) 1538 #define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) 1539 #define pTIMER5_WIDTH ((uint32_t volatile *)TIMER5_WIDTH) 1540 #define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) 1541 #define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) 1542 #define pTIMER6_CONFIG ((uint16_t volatile *)TIMER6_CONFIG) 1543 #define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) 1544 #define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) 1545 #define pTIMER6_COUNTER ((uint32_t volatile *)TIMER6_COUNTER) 1546 #define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) 1547 #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) 1548 #define pTIMER6_PERIOD ((uint32_t volatile *)TIMER6_PERIOD) 1549 #define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) 1550 #define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) 1551 #define pTIMER6_WIDTH ((uint32_t volatile *)TIMER6_WIDTH) 1552 #define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) 1553 #define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) 1554 #define pTIMER7_CONFIG ((uint16_t volatile *)TIMER7_CONFIG) 1555 #define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) 1556 #define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) 1557 #define pTIMER7_COUNTER ((uint32_t volatile *)TIMER7_COUNTER) 1558 #define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) 1559 #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) 1560 #define pTIMER7_PERIOD ((uint32_t volatile *)TIMER7_PERIOD) 1561 #define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) 1562 #define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) 1563 #define pTIMER7_WIDTH ((uint32_t volatile *)TIMER7_WIDTH) 1564 #define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) 1565 #define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) 1566 #define pTIMER8_CONFIG ((uint16_t volatile *)TIMER8_CONFIG) 1567 #define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG) 1568 #define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val) 1569 #define pTIMER8_COUNTER ((uint32_t volatile *)TIMER8_COUNTER) 1570 #define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER) 1571 #define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val) 1572 #define pTIMER8_PERIOD ((uint32_t volatile *)TIMER8_PERIOD) 1573 #define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD) 1574 #define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val) 1575 #define pTIMER8_WIDTH ((uint32_t volatile *)TIMER8_WIDTH) 1576 #define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH) 1577 #define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val) 1578 #define pTIMER9_CONFIG ((uint16_t volatile *)TIMER9_CONFIG) 1579 #define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG) 1580 #define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val) 1581 #define pTIMER9_COUNTER ((uint32_t volatile *)TIMER9_COUNTER) 1582 #define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER) 1583 #define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val) 1584 #define pTIMER9_PERIOD ((uint32_t volatile *)TIMER9_PERIOD) 1585 #define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD) 1586 #define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val) 1587 #define pTIMER9_WIDTH ((uint32_t volatile *)TIMER9_WIDTH) 1588 #define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH) 1589 #define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val) 1590 #define pTIMER10_CONFIG ((uint16_t volatile *)TIMER10_CONFIG) 1591 #define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG) 1592 #define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val) 1593 #define pTIMER10_COUNTER ((uint32_t volatile *)TIMER10_COUNTER) 1594 #define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER) 1595 #define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val) 1596 #define pTIMER10_PERIOD ((uint32_t volatile *)TIMER10_PERIOD) 1597 #define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD) 1598 #define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val) 1599 #define pTIMER10_WIDTH ((uint32_t volatile *)TIMER10_WIDTH) 1600 #define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH) 1601 #define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val) 1602 #define pTIMER11_CONFIG ((uint16_t volatile *)TIMER11_CONFIG) 1603 #define bfin_read_TIMER11_CONFIG() bfin_read16(TIMER11_CONFIG) 1604 #define bfin_write_TIMER11_CONFIG(val) bfin_write16(TIMER11_CONFIG, val) 1605 #define pTIMER11_COUNTER ((uint32_t volatile *)TIMER11_COUNTER) 1606 #define bfin_read_TIMER11_COUNTER() bfin_read32(TIMER11_COUNTER) 1607 #define bfin_write_TIMER11_COUNTER(val) bfin_write32(TIMER11_COUNTER, val) 1608 #define pTIMER11_PERIOD ((uint32_t volatile *)TIMER11_PERIOD) 1609 #define bfin_read_TIMER11_PERIOD() bfin_read32(TIMER11_PERIOD) 1610 #define bfin_write_TIMER11_PERIOD(val) bfin_write32(TIMER11_PERIOD, val) 1611 #define pTIMER11_WIDTH ((uint32_t volatile *)TIMER11_WIDTH) 1612 #define bfin_read_TIMER11_WIDTH() bfin_read32(TIMER11_WIDTH) 1613 #define bfin_write_TIMER11_WIDTH(val) bfin_write32(TIMER11_WIDTH, val) 1614 #define pTMRS4_ENABLE ((uint32_t volatile *)TMRS4_ENABLE) 1615 #define bfin_read_TMRS4_ENABLE() bfin_read32(TMRS4_ENABLE) 1616 #define bfin_write_TMRS4_ENABLE(val) bfin_write32(TMRS4_ENABLE, val) 1617 #define pTMRS4_DISABLE ((uint32_t volatile *)TMRS4_DISABLE) 1618 #define bfin_read_TMRS4_DISABLE() bfin_read32(TMRS4_DISABLE) 1619 #define bfin_write_TMRS4_DISABLE(val) bfin_write32(TMRS4_DISABLE, val) 1620 #define pTMRS4_STATUS ((uint32_t volatile *)TMRS4_STATUS) 1621 #define bfin_read_TMRS4_STATUS() bfin_read32(TMRS4_STATUS) 1622 #define bfin_write_TMRS4_STATUS(val) bfin_write32(TMRS4_STATUS, val) 1623 #define pTMRS8_ENABLE ((uint32_t volatile *)TMRS8_ENABLE) 1624 #define bfin_read_TMRS8_ENABLE() bfin_read32(TMRS8_ENABLE) 1625 #define bfin_write_TMRS8_ENABLE(val) bfin_write32(TMRS8_ENABLE, val) 1626 #define pTMRS8_DISABLE ((uint32_t volatile *)TMRS8_DISABLE) 1627 #define bfin_read_TMRS8_DISABLE() bfin_read32(TMRS8_DISABLE) 1628 #define bfin_write_TMRS8_DISABLE(val) bfin_write32(TMRS8_DISABLE, val) 1629 #define pTMRS8_STATUS ((uint32_t volatile *)TMRS8_STATUS) 1630 #define bfin_read_TMRS8_STATUS() bfin_read32(TMRS8_STATUS) 1631 #define bfin_write_TMRS8_STATUS(val) bfin_write32(TMRS8_STATUS, val) 1632 #define pFIO0_FLAG_D ((uint16_t volatile *)FIO0_FLAG_D) 1633 #define bfin_read_FIO0_FLAG_D() bfin_read16(FIO0_FLAG_D) 1634 #define bfin_write_FIO0_FLAG_D(val) bfin_write16(FIO0_FLAG_D, val) 1635 #define pFIO0_FLAG_C ((uint16_t volatile *)FIO0_FLAG_C) 1636 #define bfin_read_FIO0_FLAG_C() bfin_read16(FIO0_FLAG_C) 1637 #define bfin_write_FIO0_FLAG_C(val) bfin_write16(FIO0_FLAG_C, val) 1638 #define pFIO0_FLAG_S ((uint16_t volatile *)FIO0_FLAG_S) 1639 #define bfin_read_FIO0_FLAG_S() bfin_read16(FIO0_FLAG_S) 1640 #define bfin_write_FIO0_FLAG_S(val) bfin_write16(FIO0_FLAG_S, val) 1641 #define pFIO0_FLAG_T ((uint16_t volatile *)FIO0_FLAG_T) 1642 #define bfin_read_FIO0_FLAG_T() bfin_read16(FIO0_FLAG_T) 1643 #define bfin_write_FIO0_FLAG_T(val) bfin_write16(FIO0_FLAG_T, val) 1644 #define pFIO0_MASKA_D ((uint16_t volatile *)FIO0_MASKA_D) 1645 #define bfin_read_FIO0_MASKA_D() bfin_read16(FIO0_MASKA_D) 1646 #define bfin_write_FIO0_MASKA_D(val) bfin_write16(FIO0_MASKA_D, val) 1647 #define pFIO0_MASKA_C ((uint16_t volatile *)FIO0_MASKA_C) 1648 #define bfin_read_FIO0_MASKA_C() bfin_read16(FIO0_MASKA_C) 1649 #define bfin_write_FIO0_MASKA_C(val) bfin_write16(FIO0_MASKA_C, val) 1650 #define pFIO0_MASKA_S ((uint16_t volatile *)FIO0_MASKA_S) 1651 #define bfin_read_FIO0_MASKA_S() bfin_read16(FIO0_MASKA_S) 1652 #define bfin_write_FIO0_MASKA_S(val) bfin_write16(FIO0_MASKA_S, val) 1653 #define pFIO0_MASKA_T ((uint16_t volatile *)FIO0_MASKA_T) 1654 #define bfin_read_FIO0_MASKA_T() bfin_read16(FIO0_MASKA_T) 1655 #define bfin_write_FIO0_MASKA_T(val) bfin_write16(FIO0_MASKA_T, val) 1656 #define pFIO0_MASKB_D ((uint16_t volatile *)FIO0_MASKB_D) 1657 #define bfin_read_FIO0_MASKB_D() bfin_read16(FIO0_MASKB_D) 1658 #define bfin_write_FIO0_MASKB_D(val) bfin_write16(FIO0_MASKB_D, val) 1659 #define pFIO0_MASKB_C ((uint16_t volatile *)FIO0_MASKB_C) 1660 #define bfin_read_FIO0_MASKB_C() bfin_read16(FIO0_MASKB_C) 1661 #define bfin_write_FIO0_MASKB_C(val) bfin_write16(FIO0_MASKB_C, val) 1662 #define pFIO0_MASKB_S ((uint16_t volatile *)FIO0_MASKB_S) 1663 #define bfin_read_FIO0_MASKB_S() bfin_read16(FIO0_MASKB_S) 1664 #define bfin_write_FIO0_MASKB_S(val) bfin_write16(FIO0_MASKB_S, val) 1665 #define pFIO0_MASKB_T ((uint16_t volatile *)FIO0_MASKB_T) 1666 #define bfin_read_FIO0_MASKB_T() bfin_read16(FIO0_MASKB_T) 1667 #define bfin_write_FIO0_MASKB_T(val) bfin_write16(FIO0_MASKB_T, val) 1668 #define pFIO0_DIR ((uint16_t volatile *)FIO0_DIR) 1669 #define bfin_read_FIO0_DIR() bfin_read16(FIO0_DIR) 1670 #define bfin_write_FIO0_DIR(val) bfin_write16(FIO0_DIR, val) 1671 #define pFIO0_POLAR ((uint16_t volatile *)FIO0_POLAR) 1672 #define bfin_read_FIO0_POLAR() bfin_read16(FIO0_POLAR) 1673 #define bfin_write_FIO0_POLAR(val) bfin_write16(FIO0_POLAR, val) 1674 #define pFIO0_EDGE ((uint16_t volatile *)FIO0_EDGE) 1675 #define bfin_read_FIO0_EDGE() bfin_read16(FIO0_EDGE) 1676 #define bfin_write_FIO0_EDGE(val) bfin_write16(FIO0_EDGE, val) 1677 #define pFIO0_BOTH ((uint16_t volatile *)FIO0_BOTH) 1678 #define bfin_read_FIO0_BOTH() bfin_read16(FIO0_BOTH) 1679 #define bfin_write_FIO0_BOTH(val) bfin_write16(FIO0_BOTH, val) 1680 #define pFIO0_INEN ((uint16_t volatile *)FIO0_INEN) 1681 #define bfin_read_FIO0_INEN() bfin_read16(FIO0_INEN) 1682 #define bfin_write_FIO0_INEN(val) bfin_write16(FIO0_INEN, val) 1683 #define pFIO1_FLAG_D ((uint16_t volatile *)FIO1_FLAG_D) 1684 #define bfin_read_FIO1_FLAG_D() bfin_read16(FIO1_FLAG_D) 1685 #define bfin_write_FIO1_FLAG_D(val) bfin_write16(FIO1_FLAG_D, val) 1686 #define pFIO1_FLAG_C ((uint16_t volatile *)FIO1_FLAG_C) 1687 #define bfin_read_FIO1_FLAG_C() bfin_read16(FIO1_FLAG_C) 1688 #define bfin_write_FIO1_FLAG_C(val) bfin_write16(FIO1_FLAG_C, val) 1689 #define pFIO1_FLAG_S ((uint16_t volatile *)FIO1_FLAG_S) 1690 #define bfin_read_FIO1_FLAG_S() bfin_read16(FIO1_FLAG_S) 1691 #define bfin_write_FIO1_FLAG_S(val) bfin_write16(FIO1_FLAG_S, val) 1692 #define pFIO1_FLAG_T ((uint16_t volatile *)FIO1_FLAG_T) 1693 #define bfin_read_FIO1_FLAG_T() bfin_read16(FIO1_FLAG_T) 1694 #define bfin_write_FIO1_FLAG_T(val) bfin_write16(FIO1_FLAG_T, val) 1695 #define pFIO1_MASKA_D ((uint16_t volatile *)FIO1_MASKA_D) 1696 #define bfin_read_FIO1_MASKA_D() bfin_read16(FIO1_MASKA_D) 1697 #define bfin_write_FIO1_MASKA_D(val) bfin_write16(FIO1_MASKA_D, val) 1698 #define pFIO1_MASKA_C ((uint16_t volatile *)FIO1_MASKA_C) 1699 #define bfin_read_FIO1_MASKA_C() bfin_read16(FIO1_MASKA_C) 1700 #define bfin_write_FIO1_MASKA_C(val) bfin_write16(FIO1_MASKA_C, val) 1701 #define pFIO1_MASKA_S ((uint16_t volatile *)FIO1_MASKA_S) 1702 #define bfin_read_FIO1_MASKA_S() bfin_read16(FIO1_MASKA_S) 1703 #define bfin_write_FIO1_MASKA_S(val) bfin_write16(FIO1_MASKA_S, val) 1704 #define pFIO1_MASKA_T ((uint16_t volatile *)FIO1_MASKA_T) 1705 #define bfin_read_FIO1_MASKA_T() bfin_read16(FIO1_MASKA_T) 1706 #define bfin_write_FIO1_MASKA_T(val) bfin_write16(FIO1_MASKA_T, val) 1707 #define pFIO1_MASKB_D ((uint16_t volatile *)FIO1_MASKB_D) 1708 #define bfin_read_FIO1_MASKB_D() bfin_read16(FIO1_MASKB_D) 1709 #define bfin_write_FIO1_MASKB_D(val) bfin_write16(FIO1_MASKB_D, val) 1710 #define pFIO1_MASKB_C ((uint16_t volatile *)FIO1_MASKB_C) 1711 #define bfin_read_FIO1_MASKB_C() bfin_read16(FIO1_MASKB_C) 1712 #define bfin_write_FIO1_MASKB_C(val) bfin_write16(FIO1_MASKB_C, val) 1713 #define pFIO1_MASKB_S ((uint16_t volatile *)FIO1_MASKB_S) 1714 #define bfin_read_FIO1_MASKB_S() bfin_read16(FIO1_MASKB_S) 1715 #define bfin_write_FIO1_MASKB_S(val) bfin_write16(FIO1_MASKB_S, val) 1716 #define pFIO1_MASKB_T ((uint16_t volatile *)FIO1_MASKB_T) 1717 #define bfin_read_FIO1_MASKB_T() bfin_read16(FIO1_MASKB_T) 1718 #define bfin_write_FIO1_MASKB_T(val) bfin_write16(FIO1_MASKB_T, val) 1719 #define pFIO1_DIR ((uint16_t volatile *)FIO1_DIR) 1720 #define bfin_read_FIO1_DIR() bfin_read16(FIO1_DIR) 1721 #define bfin_write_FIO1_DIR(val) bfin_write16(FIO1_DIR, val) 1722 #define pFIO1_POLAR ((uint16_t volatile *)FIO1_POLAR) 1723 #define bfin_read_FIO1_POLAR() bfin_read16(FIO1_POLAR) 1724 #define bfin_write_FIO1_POLAR(val) bfin_write16(FIO1_POLAR, val) 1725 #define pFIO1_EDGE ((uint16_t volatile *)FIO1_EDGE) 1726 #define bfin_read_FIO1_EDGE() bfin_read16(FIO1_EDGE) 1727 #define bfin_write_FIO1_EDGE(val) bfin_write16(FIO1_EDGE, val) 1728 #define pFIO1_BOTH ((uint16_t volatile *)FIO1_BOTH) 1729 #define bfin_read_FIO1_BOTH() bfin_read16(FIO1_BOTH) 1730 #define bfin_write_FIO1_BOTH(val) bfin_write16(FIO1_BOTH, val) 1731 #define pFIO1_INEN ((uint16_t volatile *)FIO1_INEN) 1732 #define bfin_read_FIO1_INEN() bfin_read16(FIO1_INEN) 1733 #define bfin_write_FIO1_INEN(val) bfin_write16(FIO1_INEN, val) 1734 #define pFIO2_FLAG_D ((uint16_t volatile *)FIO2_FLAG_D) 1735 #define bfin_read_FIO2_FLAG_D() bfin_read16(FIO2_FLAG_D) 1736 #define bfin_write_FIO2_FLAG_D(val) bfin_write16(FIO2_FLAG_D, val) 1737 #define pFIO2_FLAG_C ((uint16_t volatile *)FIO2_FLAG_C) 1738 #define bfin_read_FIO2_FLAG_C() bfin_read16(FIO2_FLAG_C) 1739 #define bfin_write_FIO2_FLAG_C(val) bfin_write16(FIO2_FLAG_C, val) 1740 #define pFIO2_FLAG_S ((uint16_t volatile *)FIO2_FLAG_S) 1741 #define bfin_read_FIO2_FLAG_S() bfin_read16(FIO2_FLAG_S) 1742 #define bfin_write_FIO2_FLAG_S(val) bfin_write16(FIO2_FLAG_S, val) 1743 #define pFIO2_FLAG_T ((uint16_t volatile *)FIO2_FLAG_T) 1744 #define bfin_read_FIO2_FLAG_T() bfin_read16(FIO2_FLAG_T) 1745 #define bfin_write_FIO2_FLAG_T(val) bfin_write16(FIO2_FLAG_T, val) 1746 #define pFIO2_MASKA_D ((uint16_t volatile *)FIO2_MASKA_D) 1747 #define bfin_read_FIO2_MASKA_D() bfin_read16(FIO2_MASKA_D) 1748 #define bfin_write_FIO2_MASKA_D(val) bfin_write16(FIO2_MASKA_D, val) 1749 #define pFIO2_MASKA_C ((uint16_t volatile *)FIO2_MASKA_C) 1750 #define bfin_read_FIO2_MASKA_C() bfin_read16(FIO2_MASKA_C) 1751 #define bfin_write_FIO2_MASKA_C(val) bfin_write16(FIO2_MASKA_C, val) 1752 #define pFIO2_MASKA_S ((uint16_t volatile *)FIO2_MASKA_S) 1753 #define bfin_read_FIO2_MASKA_S() bfin_read16(FIO2_MASKA_S) 1754 #define bfin_write_FIO2_MASKA_S(val) bfin_write16(FIO2_MASKA_S, val) 1755 #define pFIO2_MASKA_T ((uint16_t volatile *)FIO2_MASKA_T) 1756 #define bfin_read_FIO2_MASKA_T() bfin_read16(FIO2_MASKA_T) 1757 #define bfin_write_FIO2_MASKA_T(val) bfin_write16(FIO2_MASKA_T, val) 1758 #define pFIO2_MASKB_D ((uint16_t volatile *)FIO2_MASKB_D) 1759 #define bfin_read_FIO2_MASKB_D() bfin_read16(FIO2_MASKB_D) 1760 #define bfin_write_FIO2_MASKB_D(val) bfin_write16(FIO2_MASKB_D, val) 1761 #define pFIO2_MASKB_C ((uint16_t volatile *)FIO2_MASKB_C) 1762 #define bfin_read_FIO2_MASKB_C() bfin_read16(FIO2_MASKB_C) 1763 #define bfin_write_FIO2_MASKB_C(val) bfin_write16(FIO2_MASKB_C, val) 1764 #define pFIO2_MASKB_S ((uint16_t volatile *)FIO2_MASKB_S) 1765 #define bfin_read_FIO2_MASKB_S() bfin_read16(FIO2_MASKB_S) 1766 #define bfin_write_FIO2_MASKB_S(val) bfin_write16(FIO2_MASKB_S, val) 1767 #define pFIO2_MASKB_T ((uint16_t volatile *)FIO2_MASKB_T) 1768 #define bfin_read_FIO2_MASKB_T() bfin_read16(FIO2_MASKB_T) 1769 #define bfin_write_FIO2_MASKB_T(val) bfin_write16(FIO2_MASKB_T, val) 1770 #define pFIO2_DIR ((uint16_t volatile *)FIO2_DIR) 1771 #define bfin_read_FIO2_DIR() bfin_read16(FIO2_DIR) 1772 #define bfin_write_FIO2_DIR(val) bfin_write16(FIO2_DIR, val) 1773 #define pFIO2_POLAR ((uint16_t volatile *)FIO2_POLAR) 1774 #define bfin_read_FIO2_POLAR() bfin_read16(FIO2_POLAR) 1775 #define bfin_write_FIO2_POLAR(val) bfin_write16(FIO2_POLAR, val) 1776 #define pFIO2_EDGE ((uint16_t volatile *)FIO2_EDGE) 1777 #define bfin_read_FIO2_EDGE() bfin_read16(FIO2_EDGE) 1778 #define bfin_write_FIO2_EDGE(val) bfin_write16(FIO2_EDGE, val) 1779 #define pFIO2_BOTH ((uint16_t volatile *)FIO2_BOTH) 1780 #define bfin_read_FIO2_BOTH() bfin_read16(FIO2_BOTH) 1781 #define bfin_write_FIO2_BOTH(val) bfin_write16(FIO2_BOTH, val) 1782 #define pFIO2_INEN ((uint16_t volatile *)FIO2_INEN) 1783 #define bfin_read_FIO2_INEN() bfin_read16(FIO2_INEN) 1784 #define bfin_write_FIO2_INEN(val) bfin_write16(FIO2_INEN, val) 1785 #define pSPORT0_TCR1 ((uint16_t volatile *)SPORT0_TCR1) 1786 #define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) 1787 #define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) 1788 #define pSPORT0_TCR2 ((uint16_t volatile *)SPORT0_TCR2) 1789 #define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) 1790 #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) 1791 #define pSPORT0_TCLKDIV ((uint16_t volatile *)SPORT0_TCLKDIV) 1792 #define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) 1793 #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) 1794 #define pSPORT0_TFSDIV ((uint16_t volatile *)SPORT0_TFSDIV) 1795 #define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) 1796 #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) 1797 #define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) 1798 #define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) 1799 #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) 1800 #define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) 1801 #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) 1802 #define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) 1803 #define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) 1804 #define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) 1805 #define pSPORT0_RCR2 ((uint16_t volatile *)SPORT0_RCR2) 1806 #define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) 1807 #define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) 1808 #define pSPORT0_RCLKDIV ((uint16_t volatile *)SPORT0_RCLKDIV) 1809 #define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) 1810 #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) 1811 #define pSPORT0_RFSDIV ((uint16_t volatile *)SPORT0_RFSDIV) 1812 #define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) 1813 #define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) 1814 #define pSPORT0_STAT ((uint16_t volatile *)SPORT0_STAT) 1815 #define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) 1816 #define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) 1817 #define pSPORT0_CHNL ((uint16_t volatile *)SPORT0_CHNL) 1818 #define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) 1819 #define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) 1820 #define pSPORT0_MCMC1 ((uint16_t volatile *)SPORT0_MCMC1) 1821 #define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) 1822 #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) 1823 #define pSPORT0_MCMC2 ((uint16_t volatile *)SPORT0_MCMC2) 1824 #define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) 1825 #define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) 1826 #define pSPORT0_MTCS0 ((uint32_t volatile *)SPORT0_MTCS0) 1827 #define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) 1828 #define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) 1829 #define pSPORT0_MTCS1 ((uint32_t volatile *)SPORT0_MTCS1) 1830 #define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) 1831 #define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) 1832 #define pSPORT0_MTCS2 ((uint32_t volatile *)SPORT0_MTCS2) 1833 #define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) 1834 #define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) 1835 #define pSPORT0_MTCS3 ((uint32_t volatile *)SPORT0_MTCS3) 1836 #define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) 1837 #define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) 1838 #define pSPORT0_MRCS0 ((uint32_t volatile *)SPORT0_MRCS0) 1839 #define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) 1840 #define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) 1841 #define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1) 1842 #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) 1843 #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) 1844 #define pSPORT0_MRCS2 ((uint32_t volatile *)SPORT0_MRCS2) 1845 #define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) 1846 #define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) 1847 #define pSPORT0_MRCS3 ((uint32_t volatile *)SPORT0_MRCS3) 1848 #define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) 1849 #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) 1850 #define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1) 1851 #define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) 1852 #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) 1853 #define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2) 1854 #define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) 1855 #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) 1856 #define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV) 1857 #define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) 1858 #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) 1859 #define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) 1860 #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) 1861 #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) 1862 #define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) 1863 #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) 1864 #define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) 1865 #define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) 1866 #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) 1867 #define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) 1868 #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) 1869 #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) 1870 #define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2) 1871 #define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) 1872 #define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) 1873 #define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV) 1874 #define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) 1875 #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) 1876 #define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) 1877 #define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) 1878 #define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) 1879 #define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) 1880 #define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) 1881 #define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) 1882 #define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL) 1883 #define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) 1884 #define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) 1885 #define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) 1886 #define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) 1887 #define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) 1888 #define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) 1889 #define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) 1890 #define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) 1891 #define pSPORT1_MTCS0 ((uint32_t volatile *)SPORT1_MTCS0) 1892 #define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) 1893 #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) 1894 #define pSPORT1_MTCS1 ((uint32_t volatile *)SPORT1_MTCS1) 1895 #define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) 1896 #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) 1897 #define pSPORT1_MTCS2 ((uint32_t volatile *)SPORT1_MTCS2) 1898 #define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) 1899 #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) 1900 #define pSPORT1_MTCS3 ((uint32_t volatile *)SPORT1_MTCS3) 1901 #define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) 1902 #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) 1903 #define pSPORT1_MRCS0 ((uint32_t volatile *)SPORT1_MRCS0) 1904 #define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) 1905 #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) 1906 #define pSPORT1_MRCS1 ((uint32_t volatile *)SPORT1_MRCS1) 1907 #define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) 1908 #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) 1909 #define pSPORT1_MRCS2 ((uint32_t volatile *)SPORT1_MRCS2) 1910 #define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) 1911 #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) 1912 #define pSPORT1_MRCS3 ((uint32_t volatile *)SPORT1_MRCS3) 1913 #define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) 1914 #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) 1915 #define pEVT0 ((void * volatile *)EVT0) 1916 #define bfin_read_EVT0() bfin_readPTR(EVT0) 1917 #define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) 1918 #define pEVT1 ((void * volatile *)EVT1) 1919 #define bfin_read_EVT1() bfin_readPTR(EVT1) 1920 #define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) 1921 #define pEVT2 ((void * volatile *)EVT2) 1922 #define bfin_read_EVT2() bfin_readPTR(EVT2) 1923 #define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) 1924 #define pEVT3 ((void * volatile *)EVT3) 1925 #define bfin_read_EVT3() bfin_readPTR(EVT3) 1926 #define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) 1927 #define pEVT4 ((void * volatile *)EVT4) 1928 #define bfin_read_EVT4() bfin_readPTR(EVT4) 1929 #define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) 1930 #define pEVT5 ((void * volatile *)EVT5) 1931 #define bfin_read_EVT5() bfin_readPTR(EVT5) 1932 #define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) 1933 #define pEVT6 ((void * volatile *)EVT6) 1934 #define bfin_read_EVT6() bfin_readPTR(EVT6) 1935 #define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) 1936 #define pEVT7 ((void * volatile *)EVT7) 1937 #define bfin_read_EVT7() bfin_readPTR(EVT7) 1938 #define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) 1939 #define pEVT8 ((void * volatile *)EVT8) 1940 #define bfin_read_EVT8() bfin_readPTR(EVT8) 1941 #define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) 1942 #define pEVT9 ((void * volatile *)EVT9) 1943 #define bfin_read_EVT9() bfin_readPTR(EVT9) 1944 #define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) 1945 #define pEVT10 ((void * volatile *)EVT10) 1946 #define bfin_read_EVT10() bfin_readPTR(EVT10) 1947 #define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) 1948 #define pEVT11 ((void * volatile *)EVT11) 1949 #define bfin_read_EVT11() bfin_readPTR(EVT11) 1950 #define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) 1951 #define pEVT12 ((void * volatile *)EVT12) 1952 #define bfin_read_EVT12() bfin_readPTR(EVT12) 1953 #define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) 1954 #define pEVT13 ((void * volatile *)EVT13) 1955 #define bfin_read_EVT13() bfin_readPTR(EVT13) 1956 #define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) 1957 #define pEVT14 ((void * volatile *)EVT14) 1958 #define bfin_read_EVT14() bfin_readPTR(EVT14) 1959 #define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) 1960 #define pEVT15 ((void * volatile *)EVT15) 1961 #define bfin_read_EVT15() bfin_readPTR(EVT15) 1962 #define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) 1963 #define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ 1964 #define bfin_read_ILAT() bfin_read32(ILAT) 1965 #define bfin_write_ILAT(val) bfin_write32(ILAT, val) 1966 #define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ 1967 #define bfin_read_IMASK() bfin_read32(IMASK) 1968 #define bfin_write_IMASK(val) bfin_write32(IMASK, val) 1969 #define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ 1970 #define bfin_read_IPEND() bfin_read32(IPEND) 1971 #define bfin_write_IPEND(val) bfin_write32(IPEND, val) 1972 #define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ 1973 #define bfin_read_IPRIO() bfin_read32(IPRIO) 1974 #define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) 1975 #define pTCNTL ((uint32_t volatile *)TCNTL) 1976 #define bfin_read_TCNTL() bfin_read32(TCNTL) 1977 #define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) 1978 #define pTPERIOD ((uint32_t volatile *)TPERIOD) 1979 #define bfin_read_TPERIOD() bfin_read32(TPERIOD) 1980 #define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) 1981 #define pTSCALE ((uint32_t volatile *)TSCALE) 1982 #define bfin_read_TSCALE() bfin_read32(TSCALE) 1983 #define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) 1984 #define pTCOUNT ((uint32_t volatile *)TCOUNT) 1985 #define bfin_read_TCOUNT() bfin_read32(TCOUNT) 1986 #define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) 1987 1988 #endif /* __BFIN_CDEF_ADSP_EDN_DUAL_CORE_extended__ */ 1989