1 /* 2 * (C) Copyright 2002 3 * Daniel Engstr�m, Omicron Ceti AB <daniel@omicron.se>. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #ifndef _ASM_IC_SC520_H_ 25 #define _ASM_IC_SC520_H_ 1 26 27 #ifndef __ASSEMBLY__ 28 29 void init_sc520(void); 30 unsigned long init_sc520_dram(void); 31 void sc520_udelay(unsigned long usec); 32 33 /* Memory mapped configuration registers */ 34 typedef struct sc520_mmcr { 35 u16 revid; /* ElanSC520 microcontroller revision id */ 36 u8 cpuctl; /* am5x86 CPU control */ 37 38 u8 pad_0x003[0x0d]; 39 40 u8 drcctl; /* SDRAM control */ 41 u8 pad_0x011[0x01]; 42 u8 drctmctl; /* SDRAM timing control */ 43 u8 pad_0x013[0x01]; 44 u16 drccfg; /* SDRAM bank configuration*/ 45 u8 pad_0x016[0x02]; 46 u32 drcbendadr; /* SDRAM bank 0-3 ending address*/ 47 u8 pad_0x01c[0x04]; 48 u8 eccctl; /* ECC control */ 49 u8 eccsta; /* ECC status */ 50 u8 eccckbpos; /* ECC check bit position */ 51 u8 ecccktest; /* ECC Check Code Test */ 52 u32 eccsbadd; /* ECC single-bit error address */ 53 u32 eccmbadd; /* ECC multi-bit error address */ 54 55 u8 pad_0x02c[0x14]; 56 57 u8 dbctl; /* SDRAM buffer control */ 58 59 u8 pad_0x041[0x0f]; 60 61 u16 bootcsctl; /* /BOOTCS control */ 62 u8 pad_0x052[0x02]; 63 u16 romcs1ctl; /* /ROMCS1 control */ 64 u16 romcs2ctl; /* /ROMCS2 control */ 65 66 u8 pad_0x058[0x08]; 67 68 u16 hbctl; /* host bridge control */ 69 u16 hbtgtirqctl; /* host bridge target interrupt control */ 70 u16 hbtgtirqsta; /* host bridge target interrupt status */ 71 u16 hbmstirqctl; /* host bridge target interrupt control */ 72 u16 hbmstirqsta; /* host bridge master interrupt status */ 73 u8 pad_0x06a[0x02]; 74 u32 mstintadd; /* host bridge master interrupt address */ 75 76 u8 sysarbctl; /* system arbiter control */ 77 u8 pciarbsta; /* PCI bus arbiter status */ 78 u16 sysarbmenb; /* system arbiter master enable */ 79 u32 arbprictl; /* arbiter priority control */ 80 81 u8 pad_0x078[0x08]; 82 83 u8 adddecctl; /* address decode control */ 84 u8 pad_0x081[0x01]; 85 u16 wpvsta; /* write-protect violation status */ 86 u8 pad_0x084[0x04]; 87 u32 par[16]; /* programmable address regions */ 88 89 u8 pad_0x0c8[0x0b38]; 90 91 u8 gpecho; /* GP echo mode */ 92 u8 gpcsdw; /* GP chip select data width */ 93 u16 gpcsqual; /* GP chip select qualification */ 94 u8 pad_0xc04[0x4]; 95 u8 gpcsrt; /* GP chip select recovery time */ 96 u8 gpcspw; /* GP chip select pulse width */ 97 u8 gpcsoff; /* GP chip select offset */ 98 u8 gprdw; /* GP read pulse width */ 99 u8 gprdoff; /* GP read offset */ 100 u8 gpwrw; /* GP write pulse width */ 101 u8 gpwroff; /* GP write offset */ 102 u8 gpalew; /* GP ale pulse width */ 103 u8 gpaleoff; /* GP ale offset */ 104 105 u8 pad_0xc11[0x0f]; 106 107 u16 piopfs15_0; /* PIO15-PIO0 pin function select */ 108 u16 piopfs31_16; /* PIO31-PIO16 pin function select */ 109 u8 cspfs; /* chip select pin function select */ 110 u8 pad_0xc25[0x01]; 111 u8 clksel; /* clock select */ 112 u8 pad_0xc27[0x01]; 113 u16 dsctl; /* drive strength control */ 114 u16 piodir15_0; /* PIO15-PIO0 direction */ 115 u16 piodir31_16; /* PIO31-PIO16 direction */ 116 u8 pad_0xc2e[0x02]; 117 u16 piodata15_0 ; /* PIO15-PIO0 data */ 118 u16 piodata31_16; /* PIO31-PIO16 data */ 119 u16 pioset15_0; /* PIO15-PIO0 set */ 120 u16 pioset31_16; /* PIO31-PIO16 set */ 121 u16 pioclr15_0; /* PIO15-PIO0 clear */ 122 u16 pioclr31_16; /* PIO31-PIO16 clear */ 123 124 u8 pad_0xc3c[0x24]; 125 126 u16 swtmrmilli; /* software timer millisecond count */ 127 u16 swtmrmicro; /* software timer microsecond count */ 128 u8 swtmrcfg; /* software timer configuration */ 129 130 u8 pad_0xc65[0x0b]; 131 132 u8 gptmrsta; /* GP timers status register */ 133 u8 pad_0xc71; 134 u16 gptmr0ctl; /* GP timer 0 mode/control */ 135 u16 gptmr0cnt; /* GP timer 0 count */ 136 u16 gptmr0maxcmpa; /* GP timer 0 maxcount compare A */ 137 u16 gptmr0maxcmpb; /* GP timer 0 maxcount compare B */ 138 u16 gptmr1ctl; /* GP timer 1 mode/control */ 139 u16 gptmr1cnt; /* GP timer 1 count */ 140 u16 gptmr1maxcmpa; /* GP timer 1 maxcount compare A */ 141 u16 gptmr1maxcmpb; /* GP timer 1 maxcount compare B*/ 142 u16 gptmr2ctl; /* GP timer 2 mode/control */ 143 u16 gptmr2cnt; /* GP timer 2 count */ 144 u8 pad_0xc86[0x08]; 145 u16 gptmr2maxcmpa; /* GP timer 2 maxcount compare A */ 146 147 u8 pad_0xc90[0x20]; 148 149 u16 wdtmrctl; /* watchdog timer control */ 150 u16 wdtmrcntl; /* watchdog timer count low */ 151 u16 wdtmrcnth; /* watchdog timer count high */ 152 153 u8 pad_0xcb6[0x0a]; 154 155 u8 uart1ctl; /* UART 1 general control */ 156 u8 uart1sta; /* UART 1 general status */ 157 u8 uart1fcrshad; /* UART 1 FIFO control shadow */ 158 u8 pad_0xcc3[0x01]; 159 u8 uart2ctl; /* UART 2 general control */ 160 u8 uart2sta; /* UART 2 general status */ 161 u8 uart2fcrshad; /* UART 2 FIFO control shadow */ 162 163 u8 pad_0xcc7[0x09]; 164 165 u8 ssictl; /* SSI control */ 166 u8 ssixmit; /* SSI transmit */ 167 u8 ssicmd; /* SSI command */ 168 u8 ssista; /* SSI status */ 169 u8 ssircv; /* SSI receive */ 170 171 u8 pad_0xcd5[0x2b]; 172 173 u8 picicr; /* interrupt control */ 174 u8 pad_0xd01[0x01]; 175 u8 pic_mode[3]; /* PIC interrupt mode */ 176 u8 pad_0xd05[0x03]; 177 u16 swint16_1; /* software interrupt 16-1 control */ 178 u8 swint22_17; /* software interrupt 22-17/NMI control */ 179 u8 pad_0xd0b[0x05]; 180 u16 intpinpol; /* interrupt pin polarity */ 181 u8 pad_0xd12[0x02]; 182 u16 pcihostmap; /* PCI host bridge interrupt mapping */ 183 u8 pad_0xd16[0x02]; 184 u16 eccmap; /* ECC interrupt mapping */ 185 u8 gp_tmr_int_map[3]; /* GP timer interrupt mapping */ 186 u8 pad_0xd1d[0x03]; 187 u8 pit_int_map[3]; /* PIT interrupt mapping */ 188 u8 pad_0xd23[0x05]; 189 u8 uart_int_map[2]; /* UART interrupt mapping */ 190 u8 pad_0xd2a[0x06]; 191 u8 pci_int_map[4]; /* PCI interrupt mapping (A through D)*/ 192 u8 pad_0xd34[0x0c]; 193 u8 dmabcintmap; /* DMA buffer chaining interrupt mapping */ 194 u8 ssimap; /* SSI interrupt mapping register */ 195 u8 wdtmap; /* watchdog timer interrupt mapping */ 196 u8 rtcmap; /* RTC interrupt mapping register */ 197 u8 wpvmap; /* write-protect interrupt mapping */ 198 u8 icemap; /* AMDebug JTAG Rx/Tx interrupt mapping */ 199 u8 ferrmap; /* floating point error interrupt mapping */ 200 u8 pad_0xd47[0x09]; 201 u8 gp_int_map[11]; /* GP IRQ interrupt mapping */ 202 203 u8 pad_0xd5b[0x15]; 204 205 u8 sysinfo; /* system board information */ 206 u8 pad_0xd71[0x01]; 207 u8 rescfg; /* reset configuration */ 208 u8 pad_0xd73[0x01]; 209 u8 ressta; /* reset status */ 210 211 u8 pad_0xd75[0x0b]; 212 213 u8 gpdmactl; /* GP-DMA Control */ 214 u8 gpdmammio; /* GP-DMA memory-mapped I/O */ 215 u16 gpdmaextchmapa; /* GP-DMA resource channel map a */ 216 u16 gpdmaextchmapb; /* GP-DMA resource channel map b */ 217 u8 gp_dma_ext_pg_0; /* GP-DMA channel extended page 0 */ 218 u8 gp_dma_ext_pg_1; /* GP-DMA channel extended page 0 */ 219 u8 gp_dma_ext_pg_2; /* GP-DMA channel extended page 0 */ 220 u8 gp_dma_ext_pg_3; /* GP-DMA channel extended page 0 */ 221 u8 gp_dma_ext_pg_5; /* GP-DMA channel extended page 0 */ 222 u8 gp_dma_ext_pg_6; /* GP-DMA channel extended page 0 */ 223 u8 gp_dma_ext_pg_7; /* GP-DMA channel extended page 0 */ 224 u8 pad_0xd8d[0x03]; 225 u8 gpdmaexttc3; /* GP-DMA channel 3 extender transfer count */ 226 u8 gpdmaexttc5; /* GP-DMA channel 5 extender transfer count */ 227 u8 gpdmaexttc6; /* GP-DMA channel 6 extender transfer count */ 228 u8 gpdmaexttc7; /* GP-DMA channel 7 extender transfer count */ 229 u8 pad_0xd94[0x4]; 230 u8 gpdmabcctl; /* buffer chaining control */ 231 u8 gpdmabcsta; /* buffer chaining status */ 232 u8 gpdmabsintenb; /* buffer chaining interrupt enable */ 233 u8 gpdmabcval; /* buffer chaining valid */ 234 u8 pad_0xd9c[0x04]; 235 u16 gpdmanxtaddl3; /* GP-DMA channel 3 next address low */ 236 u16 gpdmanxtaddh3; /* GP-DMA channel 3 next address high */ 237 u16 gpdmanxtaddl5; /* GP-DMA channel 5 next address low */ 238 u16 gpdmanxtaddh5; /* GP-DMA channel 5 next address high */ 239 u16 gpdmanxtaddl6; /* GP-DMA channel 6 next address low */ 240 u16 gpdmanxtaddh6; /* GP-DMA channel 6 next address high */ 241 u16 gpdmanxtaddl7; /* GP-DMA channel 7 next address low */ 242 u16 gpdmanxtaddh7; /* GP-DMA channel 7 next address high */ 243 u16 gpdmanxttcl3; /* GP-DMA channel 3 next transfer count low */ 244 u16 gpdmanxttch3; /* GP-DMA channel 3 next transfer count high */ 245 u16 gpdmanxttcl5; /* GP-DMA channel 5 next transfer count low */ 246 u16 gpdmanxttch5; /* GP-DMA channel 5 next transfer count high */ 247 u16 gpdmanxttcl6; /* GP-DMA channel 6 next transfer count low */ 248 u16 gpdmanxttch6; /* GP-DMA channel 6 next transfer count high */ 249 u16 gpdmanxttcl7; /* GP-DMA channel 7 next transfer count low */ 250 u16 gpdmanxttch7; /* GP-DMA channel 7 next transfer count high */ 251 252 u8 pad_0xdc0[0x0240]; 253 } sc520_mmcr_t; 254 255 extern volatile sc520_mmcr_t *sc520_mmcr; 256 257 #endif 258 259 /* MMCR Offsets (required for assembler code */ 260 #define SC520_DBCTL 0x0040 /* SDRAM Buffer Control Register */ 261 #define SC520_PAR14 0x00c0 /* Programmable Address Region 14 Register */ 262 #define SC520_PAR15 0x00c4 /* Programmable Address Region 15 Register */ 263 #define SC520_SWTMRMILLI 0x0c60 /* Software Timer Millisecond Count */ 264 #define SC520_SWTMRMICRO 0x0c62 /* Software Timer Microsecond Count */ 265 266 /* MMCR Register bits (not all of them :) ) */ 267 268 /* SSI Stuff */ 269 #define CTL_CLK_SEL_4 0x00 /* Nominal Bit Rate = 8 MHz */ 270 #define CTL_CLK_SEL_8 0x10 /* Nominal Bit Rate = 4 MHz */ 271 #define CTL_CLK_SEL_16 0x20 /* Nominal Bit Rate = 2 MHz */ 272 #define CTL_CLK_SEL_32 0x30 /* Nominal Bit Rate = 1 MHz */ 273 #define CTL_CLK_SEL_64 0x40 /* Nominal Bit Rate = 512 KHz */ 274 #define CTL_CLK_SEL_128 0x50 /* Nominal Bit Rate = 256 KHz */ 275 #define CTL_CLK_SEL_256 0x60 /* Nominal Bit Rate = 128 KHz */ 276 #define CTL_CLK_SEL_512 0x70 /* Nominal Bit Rate = 64 KHz */ 277 278 #define TC_INT_ENB 0x08 /* Transaction Complete Interrupt Enable */ 279 #define PHS_INV_ENB 0x04 /* SSI Inverted Phase Mode Enable */ 280 #define CLK_INV_ENB 0x02 /* SSI Inverted Clock Mode Enable */ 281 #define MSBF_ENB 0x01 /* SSI Most Significant Bit First Mode Enable */ 282 283 #define SSICMD_CMD_SEL_XMITRCV 0x03 /* Simultaneous Transmit / Receive Transaction */ 284 #define SSICMD_CMD_SEL_RCV 0x02 /* Receive Transaction */ 285 #define SSICMD_CMD_SEL_XMIT 0x01 /* Transmit Transaction */ 286 #define SSISTA_BSY 0x02 /* SSI Busy */ 287 #define SSISTA_TC_INT 0x01 /* SSI Transaction Complete Interrupt */ 288 289 /* BITS for SC520_ADDDECCTL: */ 290 #define WPV_INT_ENB 0x80 /* Write-Protect Violation Interrupt Enable */ 291 #define IO_HOLE_DEST_PCI 0x10 /* I/O Hole Access Destination */ 292 #define RTC_DIS 0x04 /* RTC Disable */ 293 #define UART2_DIS 0x02 /* UART2 Disable */ 294 #define UART1_DIS 0x01 /* UART1 Disable */ 295 296 /* 0x28000000 - 0x3fffffff is used by the flash banks */ 297 298 /* 0x40000000 - 0xffffffff is not adressable by the SC520 */ 299 300 /* priority numbers used for interrupt channel mappings */ 301 #define SC520_IRQ_DISABLED 0 302 #define SC520_IRQ0 1 303 #define SC520_IRQ1 2 304 #define SC520_IRQ2 4 /* same as IRQ9 */ 305 #define SC520_IRQ3 11 306 #define SC520_IRQ4 12 307 #define SC520_IRQ5 13 308 #define SC520_IRQ6 21 309 #define SC520_IRQ7 22 310 #define SC520_IRQ8 3 311 #define SC520_IRQ9 4 312 #define SC520_IRQ10 5 313 #define SC520_IRQ11 6 314 #define SC520_IRQ12 7 315 #define SC520_IRQ13 8 316 #define SC520_IRQ14 9 317 #define SC520_IRQ15 10 318 319 #endif 320