1 /*
2 * (C) Copyright 2000
3 * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
4 *
5 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6 * Marius Groeger <mgroeger@sysgo.de>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27 #include <common.h>
28
29 #if defined(CONFIG_HARD_I2C)
30
31 #include <asm/cpm_8260.h>
32 #include <i2c.h>
33
34 /* define to enable debug messages */
35 #undef DEBUG_I2C
36
37 DECLARE_GLOBAL_DATA_PTR;
38
39 #if defined(CONFIG_I2C_MULTI_BUS)
40 static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = 0;
41 #endif /* CONFIG_I2C_MULTI_BUS */
42
43 /* uSec to wait between polls of the i2c */
44 #define DELAY_US 100
45 /* uSec to wait for the CPM to start processing the buffer */
46 #define START_DELAY_US 1000
47
48 /*
49 * tx/rx per-byte timeout: we delay DELAY_US uSec between polls so the
50 * timeout will be (tx_length + rx_length) * DELAY_US * TOUT_LOOP
51 */
52 #define TOUT_LOOP 5
53
54 /*-----------------------------------------------------------------------
55 * Set default values
56 */
57 #ifndef CONFIG_SYS_I2C_SPEED
58 #define CONFIG_SYS_I2C_SPEED 50000
59 #endif
60
61 /*-----------------------------------------------------------------------
62 */
63
64 typedef void (*i2c_ecb_t)(int, int, void *); /* error callback function */
65
66 /* This structure keeps track of the bd and buffer space usage. */
67 typedef struct i2c_state {
68 int rx_idx; /* index to next free Rx BD */
69 int tx_idx; /* index to next free Tx BD */
70 void *rxbd; /* pointer to next free Rx BD */
71 void *txbd; /* pointer to next free Tx BD */
72 int tx_space; /* number of Tx bytes left */
73 unsigned char *tx_buf; /* pointer to free Tx area */
74 i2c_ecb_t err_cb; /* error callback function */
75 void *cb_data; /* private data to be passed */
76 } i2c_state_t;
77
78 /* flags for i2c_send() and i2c_receive() */
79 #define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */
80 #define I2CF_START_COND 0x02 /* tx: generate start condition */
81 #define I2CF_STOP_COND 0x04 /* tx: generate stop condition */
82
83 /* return codes */
84 #define I2CERR_NO_BUFFERS 1 /* no more BDs or buffer space */
85 #define I2CERR_MSG_TOO_LONG 2 /* tried to send/receive to much data */
86 #define I2CERR_TIMEOUT 3 /* timeout in i2c_doio() */
87 #define I2CERR_QUEUE_EMPTY 4 /* i2c_doio called without send/receive */
88 #define I2CERR_IO_ERROR 5 /* had an error during comms */
89
90 /* error callback flags */
91 #define I2CECB_RX_ERR 0x10 /* this is a receive error */
92 #define I2CECB_RX_OV 0x02 /* receive overrun error */
93 #define I2CECB_RX_MASK 0x0f /* mask for error bits */
94 #define I2CECB_TX_ERR 0x20 /* this is a transmit error */
95 #define I2CECB_TX_CL 0x01 /* transmit collision error */
96 #define I2CECB_TX_UN 0x02 /* transmit underflow error */
97 #define I2CECB_TX_NAK 0x04 /* transmit no ack error */
98 #define I2CECB_TX_MASK 0x0f /* mask for error bits */
99 #define I2CECB_TIMEOUT 0x40 /* this is a timeout error */
100
101 #define ERROR_I2C_NONE 0
102 #define ERROR_I2C_LENGTH 1
103
104 #define I2C_WRITE_BIT 0x00
105 #define I2C_READ_BIT 0x01
106
107 #define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
108
109
110 #define NUM_RX_BDS 4
111 #define NUM_TX_BDS 4
112 #define MAX_TX_SPACE 256
113
114 typedef struct I2C_BD
115 {
116 unsigned short status;
117 unsigned short length;
118 unsigned char *addr;
119 } I2C_BD;
120 #define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */
121
122 #define BD_I2C_TX_CL 0x0001 /* collision error */
123 #define BD_I2C_TX_UN 0x0002 /* underflow error */
124 #define BD_I2C_TX_NAK 0x0004 /* no acknowledge error */
125 #define BD_I2C_TX_ERR (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL)
126
127 #define BD_I2C_RX_ERR BD_SC_OV
128
129 #ifdef DEBUG_I2C
130 #define PRINTD(x) printf x
131 #else
132 #define PRINTD(x)
133 #endif
134
135 /*
136 * Returns the best value of I2BRG to meet desired clock speed of I2C with
137 * input parameters (clock speed, filter, and predivider value).
138 * It returns computer speed value and the difference between it and desired
139 * speed.
140 */
141 static inline int
i2c_roundrate(int hz,int speed,int filter,int modval,int * brgval,int * totspeed)142 i2c_roundrate(int hz, int speed, int filter, int modval,
143 int *brgval, int *totspeed)
144 {
145 int moddiv = 1 << (5-(modval & 3)), brgdiv, div;
146
147 PRINTD(("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n",
148 hz, speed, filter, modval));
149
150 div = moddiv * speed;
151 brgdiv = (hz + div - 1) / div;
152
153 PRINTD(("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv));
154
155 *brgval = ((brgdiv + 1) / 2) - 3 - (2*filter);
156
157 if ((*brgval < 0) || (*brgval > 255)) {
158 PRINTD(("\t\trejected brgval=%d\n", *brgval));
159 return -1;
160 }
161
162 brgdiv = 2 * (*brgval + 3 + (2 * filter));
163 div = moddiv * brgdiv ;
164 *totspeed = hz / div;
165
166 PRINTD(("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed));
167
168 return 0;
169 }
170
171 /*
172 * Sets the I2C clock predivider and divider to meet required clock speed.
173 */
i2c_setrate(int hz,int speed)174 static int i2c_setrate(int hz, int speed)
175 {
176 immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
177 volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
178 int brgval,
179 modval, /* 0-3 */
180 bestspeed_diff = speed,
181 bestspeed_brgval=0,
182 bestspeed_modval=0,
183 bestspeed_filter=0,
184 totspeed,
185 filter = 0; /* Use this fixed value */
186
187 for (modval = 0; modval < 4; modval++)
188 {
189 if (i2c_roundrate (hz, speed, filter, modval, &brgval, &totspeed) == 0)
190 {
191 int diff = speed - totspeed ;
192
193 if ((diff >= 0) && (diff < bestspeed_diff))
194 {
195 bestspeed_diff = diff ;
196 bestspeed_modval = modval;
197 bestspeed_brgval = brgval;
198 bestspeed_filter = filter;
199 }
200 }
201 }
202
203 PRINTD(("[I2C] Best is:\n"));
204 PRINTD(("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
205 hz, speed,
206 bestspeed_filter, bestspeed_modval, bestspeed_brgval,
207 bestspeed_diff));
208
209 i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3);
210 i2c->i2c_i2brg = bestspeed_brgval & 0xff;
211
212 PRINTD(("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod, i2c->i2c_i2brg));
213
214 return 1 ;
215 }
216
i2c_init(int speed,int slaveadd)217 void i2c_init(int speed, int slaveadd)
218 {
219 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
220 volatile cpm8260_t *cp = (cpm8260_t *)&immap->im_cpm;
221 volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
222 volatile iic_t *iip;
223 ulong rbase, tbase;
224 volatile I2C_BD *rxbd, *txbd;
225 uint dpaddr;
226
227 #ifdef CONFIG_SYS_I2C_INIT_BOARD
228 /* call board specific i2c bus reset routine before accessing the */
229 /* environment, which might be in a chip on that bus. For details */
230 /* about this problem see doc/I2C_Edge_Conditions. */
231 i2c_init_board();
232 #endif
233
234 dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE]));
235 if (dpaddr == 0) {
236 /* need to allocate dual port ram */
237 dpaddr = m8260_cpm_dpalloc(64 +
238 (NUM_RX_BDS * sizeof(I2C_BD)) + (NUM_TX_BDS * sizeof(I2C_BD)) +
239 MAX_TX_SPACE, 64);
240 *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE])) = dpaddr;
241 }
242
243 /*
244 * initialise data in dual port ram:
245 *
246 * dpaddr -> parameter ram (64 bytes)
247 * rbase -> rx BD (NUM_RX_BDS * sizeof(I2C_BD) bytes)
248 * tbase -> tx BD (NUM_TX_BDS * sizeof(I2C_BD) bytes)
249 * tx buffer (MAX_TX_SPACE bytes)
250 */
251
252 iip = (iic_t *)&immap->im_dprambase[dpaddr];
253 memset((void*)iip, 0, sizeof(iic_t));
254
255 rbase = dpaddr + 64;
256 tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD);
257
258 /* Disable interrupts */
259 i2c->i2c_i2mod = 0x00;
260 i2c->i2c_i2cmr = 0x00;
261 i2c->i2c_i2cer = 0xff;
262 i2c->i2c_i2add = slaveadd;
263
264 /*
265 * Set the I2C BRG Clock division factor from desired i2c rate
266 * and current CPU rate (we assume sccr dfbgr field is 0;
267 * divide BRGCLK by 1)
268 */
269 PRINTD(("[I2C] Setting rate...\n"));
270 i2c_setrate (gd->brg_clk, CONFIG_SYS_I2C_SPEED) ;
271
272 /* Set I2C controller in master mode */
273 i2c->i2c_i2com = 0x01;
274
275 /* Initialize Tx/Rx parameters */
276 iip->iic_rbase = rbase;
277 iip->iic_tbase = tbase;
278 rxbd = (I2C_BD *)((unsigned char *)&immap->im_dprambase[iip->iic_rbase]);
279 txbd = (I2C_BD *)((unsigned char *)&immap->im_dprambase[iip->iic_tbase]);
280
281 PRINTD(("[I2C] rbase = %04x\n", iip->iic_rbase));
282 PRINTD(("[I2C] tbase = %04x\n", iip->iic_tbase));
283 PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
284 PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
285
286 /* Set big endian byte order */
287 iip->iic_tfcr = 0x10;
288 iip->iic_rfcr = 0x10;
289
290 /* Set maximum receive size. */
291 iip->iic_mrblr = I2C_RXTX_LEN;
292
293 cp->cp_cpcr = mk_cr_cmd(CPM_CR_I2C_PAGE,
294 CPM_CR_I2C_SBLOCK,
295 0x00,
296 CPM_CR_INIT_TRX) | CPM_CR_FLG;
297 do {
298 __asm__ __volatile__ ("eieio");
299 } while (cp->cp_cpcr & CPM_CR_FLG);
300
301 /* Clear events and interrupts */
302 i2c->i2c_i2cer = 0xff;
303 i2c->i2c_i2cmr = 0x00;
304 }
305
306 static
i2c_newio(i2c_state_t * state)307 void i2c_newio(i2c_state_t *state)
308 {
309 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
310 volatile iic_t *iip;
311 uint dpaddr;
312
313 PRINTD(("[I2C] i2c_newio\n"));
314
315 dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE]));
316 iip = (iic_t *)&immap->im_dprambase[dpaddr];
317 state->rx_idx = 0;
318 state->tx_idx = 0;
319 state->rxbd = (void*)&immap->im_dprambase[iip->iic_rbase];
320 state->txbd = (void*)&immap->im_dprambase[iip->iic_tbase];
321 state->tx_space = MAX_TX_SPACE;
322 state->tx_buf = (uchar*)state->txbd + NUM_TX_BDS * sizeof(I2C_BD);
323 state->err_cb = NULL;
324 state->cb_data = NULL;
325
326 PRINTD(("[I2C] rxbd = %08x\n", (int)state->rxbd));
327 PRINTD(("[I2C] txbd = %08x\n", (int)state->txbd));
328 PRINTD(("[I2C] tx_buf = %08x\n", (int)state->tx_buf));
329
330 /* clear the buffer memory */
331 memset((char *)state->tx_buf, 0, MAX_TX_SPACE);
332 }
333
334 static
i2c_send(i2c_state_t * state,unsigned char address,unsigned char secondary_address,unsigned int flags,unsigned short size,unsigned char * dataout)335 int i2c_send(i2c_state_t *state,
336 unsigned char address,
337 unsigned char secondary_address,
338 unsigned int flags,
339 unsigned short size,
340 unsigned char *dataout)
341 {
342 volatile I2C_BD *txbd;
343 int i,j;
344
345 PRINTD(("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
346 address, secondary_address, flags, size));
347
348 /* trying to send message larger than BD */
349 if (size > I2C_RXTX_LEN)
350 return I2CERR_MSG_TOO_LONG;
351
352 /* no more free bds */
353 if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size))
354 return I2CERR_NO_BUFFERS;
355
356 txbd = (I2C_BD *)state->txbd;
357 txbd->addr = state->tx_buf;
358
359 PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
360
361 if (flags & I2CF_START_COND)
362 {
363 PRINTD(("[I2C] Formatting addresses...\n"));
364 if (flags & I2CF_ENABLE_SECONDARY)
365 {
366 txbd->length = size + 2; /* Length of message plus dest addresses */
367 txbd->addr[0] = address << 1;
368 txbd->addr[1] = secondary_address;
369 i = 2;
370 }
371 else
372 {
373 txbd->length = size + 1; /* Length of message plus dest address */
374 txbd->addr[0] = address << 1; /* Write destination address to BD */
375 i = 1;
376 }
377 }
378 else
379 {
380 txbd->length = size; /* Length of message */
381 i = 0;
382 }
383
384 /* set up txbd */
385 txbd->status = BD_SC_READY;
386 if (flags & I2CF_START_COND)
387 txbd->status |= BD_I2C_TX_START;
388 if (flags & I2CF_STOP_COND)
389 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
390
391 /* Copy data to send into buffer */
392 PRINTD(("[I2C] copy data...\n"));
393 for(j = 0; j < size; i++, j++)
394 txbd->addr[i] = dataout[j];
395
396 PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
397 txbd->length,
398 txbd->status,
399 txbd->addr[0],
400 txbd->addr[1]));
401
402 /* advance state */
403 state->tx_buf += txbd->length;
404 state->tx_space -= txbd->length;
405 state->tx_idx++;
406 state->txbd = (void*)(txbd + 1);
407
408 return 0;
409 }
410
411 static
i2c_receive(i2c_state_t * state,unsigned char address,unsigned char secondary_address,unsigned int flags,unsigned short size_to_expect,unsigned char * datain)412 int i2c_receive(i2c_state_t *state,
413 unsigned char address,
414 unsigned char secondary_address,
415 unsigned int flags,
416 unsigned short size_to_expect,
417 unsigned char *datain)
418 {
419 volatile I2C_BD *rxbd, *txbd;
420
421 PRINTD(("[I2C] i2c_receive %02d %02d %02d\n", address, secondary_address, flags));
422
423 /* Expected to receive too much */
424 if (size_to_expect > I2C_RXTX_LEN)
425 return I2CERR_MSG_TOO_LONG;
426
427 /* no more free bds */
428 if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS
429 || state->tx_space < 2)
430 return I2CERR_NO_BUFFERS;
431
432 rxbd = (I2C_BD *)state->rxbd;
433 txbd = (I2C_BD *)state->txbd;
434
435 PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
436 PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
437
438 txbd->addr = state->tx_buf;
439
440 /* set up TXBD for destination address */
441 if (flags & I2CF_ENABLE_SECONDARY)
442 {
443 txbd->length = 2;
444 txbd->addr[0] = address << 1; /* Write data */
445 txbd->addr[1] = secondary_address; /* Internal address */
446 txbd->status = BD_SC_READY;
447 }
448 else
449 {
450 txbd->length = 1 + size_to_expect;
451 txbd->addr[0] = (address << 1) | 0x01;
452 txbd->status = BD_SC_READY;
453 memset(&txbd->addr[1], 0, txbd->length);
454 }
455
456 /* set up rxbd for reception */
457 rxbd->status = BD_SC_EMPTY;
458 rxbd->length = size_to_expect;
459 rxbd->addr = datain;
460
461 txbd->status |= BD_I2C_TX_START;
462 if (flags & I2CF_STOP_COND)
463 {
464 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
465 rxbd->status |= BD_SC_WRAP;
466 }
467
468 PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
469 txbd->length,
470 txbd->status,
471 txbd->addr[0],
472 txbd->addr[1]));
473 PRINTD(("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
474 rxbd->length,
475 rxbd->status,
476 rxbd->addr[0],
477 rxbd->addr[1]));
478
479 /* advance state */
480 state->tx_buf += txbd->length;
481 state->tx_space -= txbd->length;
482 state->tx_idx++;
483 state->txbd = (void*)(txbd + 1);
484 state->rx_idx++;
485 state->rxbd = (void*)(rxbd + 1);
486
487 return 0;
488 }
489
490
491 static
i2c_doio(i2c_state_t * state)492 int i2c_doio(i2c_state_t *state)
493 {
494 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
495 volatile iic_t *iip;
496 volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
497 volatile I2C_BD *txbd, *rxbd;
498 int n, i, b, rxcnt = 0, rxtimeo = 0, txcnt = 0, txtimeo = 0, rc = 0;
499 uint dpaddr;
500
501 PRINTD(("[I2C] i2c_doio\n"));
502
503 if (state->tx_idx <= 0 && state->rx_idx <= 0) {
504 PRINTD(("[I2C] No I/O is queued\n"));
505 return I2CERR_QUEUE_EMPTY;
506 }
507
508 dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE]));
509 iip = (iic_t *)&immap->im_dprambase[dpaddr];
510 iip->iic_rbptr = iip->iic_rbase;
511 iip->iic_tbptr = iip->iic_tbase;
512
513 /* Enable I2C */
514 PRINTD(("[I2C] Enabling I2C...\n"));
515 i2c->i2c_i2mod |= 0x01;
516
517 /* Begin transmission */
518 i2c->i2c_i2com |= 0x80;
519
520 /* Loop until transmit & receive completed */
521
522 if ((n = state->tx_idx) > 0) {
523
524 txbd = ((I2C_BD*)state->txbd) - n;
525 for (i = 0; i < n; i++) {
526 txtimeo += TOUT_LOOP * txbd->length;
527 txbd++;
528 }
529
530 txbd--; /* wait until last in list is done */
531
532 PRINTD(("[I2C] Transmitting...(txbd=0x%08lx)\n", (ulong)txbd));
533
534 udelay(START_DELAY_US); /* give it time to start */
535 while((txbd->status & BD_SC_READY) && (++txcnt < txtimeo)) {
536 udelay(DELAY_US);
537 if (ctrlc())
538 return (-1);
539 __asm__ __volatile__ ("eieio");
540 }
541 }
542
543 if (txcnt < txtimeo && (n = state->rx_idx) > 0) {
544
545 rxbd = ((I2C_BD*)state->rxbd) - n;
546 for (i = 0; i < n; i++) {
547 rxtimeo += TOUT_LOOP * rxbd->length;
548 rxbd++;
549 }
550
551 rxbd--; /* wait until last in list is done */
552
553 PRINTD(("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong)rxbd));
554
555 udelay(START_DELAY_US); /* give it time to start */
556 while((rxbd->status & BD_SC_EMPTY) && (++rxcnt < rxtimeo)) {
557 udelay(DELAY_US);
558 if (ctrlc())
559 return (-1);
560 __asm__ __volatile__ ("eieio");
561 }
562 }
563
564 /* Turn off I2C */
565 i2c->i2c_i2mod &= ~0x01;
566
567 if ((n = state->tx_idx) > 0) {
568 for (i = 0; i < n; i++) {
569 txbd = ((I2C_BD*)state->txbd) - (n - i);
570 if ((b = txbd->status & BD_I2C_TX_ERR) != 0) {
571 if (state->err_cb != NULL)
572 (*state->err_cb)(I2CECB_TX_ERR|b, i,
573 state->cb_data);
574 if (rc == 0)
575 rc = I2CERR_IO_ERROR;
576 }
577 }
578 }
579
580 if ((n = state->rx_idx) > 0) {
581 for (i = 0; i < n; i++) {
582 rxbd = ((I2C_BD*)state->rxbd) - (n - i);
583 if ((b = rxbd->status & BD_I2C_RX_ERR) != 0) {
584 if (state->err_cb != NULL)
585 (*state->err_cb)(I2CECB_RX_ERR|b, i,
586 state->cb_data);
587 if (rc == 0)
588 rc = I2CERR_IO_ERROR;
589 }
590 }
591 }
592
593 if ((txtimeo > 0 && txcnt >= txtimeo) || \
594 (rxtimeo > 0 && rxcnt >= rxtimeo)) {
595 if (state->err_cb != NULL)
596 (*state->err_cb)(I2CECB_TIMEOUT, -1, state->cb_data);
597 if (rc == 0)
598 rc = I2CERR_TIMEOUT;
599 }
600
601 return (rc);
602 }
603
604 static void
i2c_probe_callback(int flags,int xnum,void * data)605 i2c_probe_callback(int flags, int xnum, void *data)
606 {
607 /*
608 * the only acceptable errors are a transmit NAK or a receive
609 * overrun - tx NAK means the device does not exist, rx OV
610 * means the device must have responded to the slave address
611 * even though the transfer failed
612 */
613 if (flags == (I2CECB_TX_ERR|I2CECB_TX_NAK))
614 *(int *)data |= 1;
615 if (flags == (I2CECB_RX_ERR|I2CECB_RX_OV))
616 *(int *)data |= 2;
617 }
618
619 int
i2c_probe(uchar chip)620 i2c_probe(uchar chip)
621 {
622 i2c_state_t state;
623 int rc, err_flag;
624 uchar buf[1];
625
626 i2c_newio(&state);
627
628 state.err_cb = i2c_probe_callback;
629 state.cb_data = (void *) &err_flag;
630 err_flag = 0;
631
632 rc = i2c_receive(&state, chip, 0, I2CF_START_COND|I2CF_STOP_COND, 1, buf);
633
634 if (rc != 0)
635 return (rc); /* probe failed */
636
637 rc = i2c_doio(&state);
638
639 if (rc == 0)
640 return (0); /* device exists - read succeeded */
641
642 if (rc == I2CERR_TIMEOUT)
643 return (-1); /* device does not exist - timeout */
644
645 if (rc != I2CERR_IO_ERROR || err_flag == 0)
646 return (rc); /* probe failed */
647
648 if (err_flag & 1)
649 return (-1); /* device does not exist - had transmit NAK */
650
651 return (0); /* device exists - had receive overrun */
652 }
653
654
655 int
i2c_read(uchar chip,uint addr,int alen,uchar * buffer,int len)656 i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
657 {
658 i2c_state_t state;
659 uchar xaddr[4];
660 int rc;
661
662 xaddr[0] = (addr >> 24) & 0xFF;
663 xaddr[1] = (addr >> 16) & 0xFF;
664 xaddr[2] = (addr >> 8) & 0xFF;
665 xaddr[3] = addr & 0xFF;
666
667 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
668 /*
669 * EEPROM chips that implement "address overflow" are ones
670 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
671 * and the extra bits end up in the "chip address" bit slots.
672 * This makes a 24WC08 (1Kbyte) chip look like four 256 byte
673 * chips.
674 *
675 * Note that we consider the length of the address field to still
676 * be one byte because the extra address bits are hidden in the
677 * chip address.
678 */
679 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
680 #endif
681
682 i2c_newio(&state);
683
684 rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]);
685 if (rc != 0) {
686 printf("i2c_read: i2c_send failed (%d)\n", rc);
687 return 1;
688 }
689
690 rc = i2c_receive(&state, chip, 0, I2CF_STOP_COND, len, buffer);
691 if (rc != 0) {
692 printf("i2c_read: i2c_receive failed (%d)\n", rc);
693 return 1;
694 }
695
696 rc = i2c_doio(&state);
697 if (rc != 0) {
698 printf("i2c_read: i2c_doio failed (%d)\n", rc);
699 return 1;
700 }
701 return 0;
702 }
703
704 int
i2c_write(uchar chip,uint addr,int alen,uchar * buffer,int len)705 i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
706 {
707 i2c_state_t state;
708 uchar xaddr[4];
709 int rc;
710
711 xaddr[0] = (addr >> 24) & 0xFF;
712 xaddr[1] = (addr >> 16) & 0xFF;
713 xaddr[2] = (addr >> 8) & 0xFF;
714 xaddr[3] = addr & 0xFF;
715
716 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
717 /*
718 * EEPROM chips that implement "address overflow" are ones
719 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
720 * and the extra bits end up in the "chip address" bit slots.
721 * This makes a 24WC08 (1Kbyte) chip look like four 256 byte
722 * chips.
723 *
724 * Note that we consider the length of the address field to still
725 * be one byte because the extra address bits are hidden in the
726 * chip address.
727 */
728 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
729 #endif
730
731 i2c_newio(&state);
732
733 rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]);
734 if (rc != 0) {
735 printf("i2c_write: first i2c_send failed (%d)\n", rc);
736 return 1;
737 }
738
739 rc = i2c_send(&state, 0, 0, I2CF_STOP_COND, len, buffer);
740 if (rc != 0) {
741 printf("i2c_write: second i2c_send failed (%d)\n", rc);
742 return 1;
743 }
744
745 rc = i2c_doio(&state);
746 if (rc != 0) {
747 printf("i2c_write: i2c_doio failed (%d)\n", rc);
748 return 1;
749 }
750 return 0;
751 }
752
753 #if defined(CONFIG_I2C_MULTI_BUS)
754 /*
755 * Functions for multiple I2C bus handling
756 */
i2c_get_bus_num(void)757 unsigned int i2c_get_bus_num(void)
758 {
759 return i2c_bus_num;
760 }
761
i2c_set_bus_num(unsigned int bus)762 int i2c_set_bus_num(unsigned int bus)
763 {
764 #if defined(CONFIG_I2C_MUX)
765 if (bus < CONFIG_SYS_MAX_I2C_BUS) {
766 i2c_bus_num = bus;
767 } else {
768 int ret;
769
770 ret = i2x_mux_select_mux(bus);
771 if (ret == 0)
772 i2c_bus_num = bus;
773 else
774 return ret;
775 }
776 #else
777 if (bus >= CONFIG_SYS_MAX_I2C_BUS)
778 return -1;
779 i2c_bus_num = bus;
780 #endif
781 return 0;
782 }
783
784 #endif /* CONFIG_I2C_MULTI_BUS */
785 #endif /* CONFIG_HARD_I2C */
786