1 /*
2 * R8A66597 HCD (Host Controller Driver) for u-boot
3 *
4 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 *
19 */
20
21 #ifndef __R8A66597_H__
22 #define __R8A66597_H__
23
24 #define SYSCFG0 0x00
25 #define SYSCFG1 0x02
26 #define SYSSTS0 0x04
27 #define SYSSTS1 0x06
28 #define DVSTCTR0 0x08
29 #define DVSTCTR1 0x0A
30 #define TESTMODE 0x0C
31 #define PINCFG 0x0E
32 #define DMA0CFG 0x10
33 #define DMA1CFG 0x12
34 #define CFIFO 0x14
35 #define D0FIFO 0x18
36 #define D1FIFO 0x1C
37 #define CFIFOSEL 0x20
38 #define CFIFOCTR 0x22
39 #define CFIFOSIE 0x24
40 #define D0FIFOSEL 0x28
41 #define D0FIFOCTR 0x2A
42 #define D1FIFOSEL 0x2C
43 #define D1FIFOCTR 0x2E
44 #define INTENB0 0x30
45 #define INTENB1 0x32
46 #define INTENB2 0x34
47 #define BRDYENB 0x36
48 #define NRDYENB 0x38
49 #define BEMPENB 0x3A
50 #define SOFCFG 0x3C
51 #define INTSTS0 0x40
52 #define INTSTS1 0x42
53 #define INTSTS2 0x44
54 #define BRDYSTS 0x46
55 #define NRDYSTS 0x48
56 #define BEMPSTS 0x4A
57 #define FRMNUM 0x4C
58 #define UFRMNUM 0x4E
59 #define USBADDR 0x50
60 #define USBREQ 0x54
61 #define USBVAL 0x56
62 #define USBINDX 0x58
63 #define USBLENG 0x5A
64 #define DCPCFG 0x5C
65 #define DCPMAXP 0x5E
66 #define DCPCTR 0x60
67 #define PIPESEL 0x64
68 #define PIPECFG 0x68
69 #define PIPEBUF 0x6A
70 #define PIPEMAXP 0x6C
71 #define PIPEPERI 0x6E
72 #define PIPE1CTR 0x70
73 #define PIPE2CTR 0x72
74 #define PIPE3CTR 0x74
75 #define PIPE4CTR 0x76
76 #define PIPE5CTR 0x78
77 #define PIPE6CTR 0x7A
78 #define PIPE7CTR 0x7C
79 #define PIPE8CTR 0x7E
80 #define PIPE9CTR 0x80
81 #define PIPE1TRE 0x90
82 #define PIPE1TRN 0x92
83 #define PIPE2TRE 0x94
84 #define PIPE2TRN 0x96
85 #define PIPE3TRE 0x98
86 #define PIPE3TRN 0x9A
87 #define PIPE4TRE 0x9C
88 #define PIPE4TRN 0x9E
89 #define PIPE5TRE 0xA0
90 #define PIPE5TRN 0xA2
91 #define DEVADD0 0xD0
92 #define DEVADD1 0xD2
93 #define DEVADD2 0xD4
94 #define DEVADD3 0xD6
95 #define DEVADD4 0xD8
96 #define DEVADD5 0xDA
97 #define DEVADD6 0xDC
98 #define DEVADD7 0xDE
99 #define DEVADD8 0xE0
100 #define DEVADD9 0xE2
101 #define DEVADDA 0xE4
102
103 /* System Configuration Control Register */
104 #define XTAL 0xC000 /* b15-14: Crystal selection */
105 #define XTAL48 0x8000 /* 48MHz */
106 #define XTAL24 0x4000 /* 24MHz */
107 #define XTAL12 0x0000 /* 12MHz */
108 #define XCKE 0x2000 /* b13: External clock enable */
109 #define PLLC 0x0800 /* b11: PLL control */
110 #define SCKE 0x0400 /* b10: USB clock enable */
111 #define PCSDIS 0x0200 /* b9: not CS wakeup */
112 #define LPSME 0x0100 /* b8: Low power sleep mode */
113 #define HSE 0x0080 /* b7: Hi-speed enable */
114 #define DCFM 0x0040 /* b6: Controller function select */
115 #define DRPD 0x0020 /* b5: D+/- pull down control */
116 #define DPRPU 0x0010 /* b4: D+ pull up control */
117 #define USBE 0x0001 /* b0: USB module operation enable */
118
119 /* System Configuration Status Register */
120 #define OVCBIT 0x8000 /* b15-14: Over-current bit */
121 #define OVCMON 0xC000 /* b15-14: Over-current monitor */
122 #define SOFEA 0x0020 /* b5: SOF monitor */
123 #define IDMON 0x0004 /* b3: ID-pin monitor */
124 #define LNST 0x0003 /* b1-0: D+, D- line status */
125 #define SE1 0x0003 /* SE1 */
126 #define FS_KSTS 0x0002 /* Full-Speed K State */
127 #define FS_JSTS 0x0001 /* Full-Speed J State */
128 #define LS_JSTS 0x0002 /* Low-Speed J State */
129 #define LS_KSTS 0x0001 /* Low-Speed K State */
130 #define SE0 0x0000 /* SE0 */
131
132 /* Device State Control Register */
133 #define EXTLP0 0x0400 /* b10: External port */
134 #define VBOUT 0x0200 /* b9: VBUS output */
135 #define WKUP 0x0100 /* b8: Remote wakeup */
136 #define RWUPE 0x0080 /* b7: Remote wakeup sense */
137 #define USBRST 0x0040 /* b6: USB reset enable */
138 #define RESUME 0x0020 /* b5: Resume enable */
139 #define UACT 0x0010 /* b4: USB bus enable */
140 #define RHST 0x0007 /* b1-0: Reset handshake status */
141 #define HSPROC 0x0004 /* HS handshake is processing */
142 #define HSMODE 0x0003 /* Hi-Speed mode */
143 #define FSMODE 0x0002 /* Full-Speed mode */
144 #define LSMODE 0x0001 /* Low-Speed mode */
145 #define UNDECID 0x0000 /* Undecided */
146
147 /* Test Mode Register */
148 #define UTST 0x000F /* b3-0: Test select */
149 #define H_TST_PACKET 0x000C /* HOST TEST Packet */
150 #define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
151 #define H_TST_K 0x000A /* HOST TEST K */
152 #define H_TST_J 0x0009 /* HOST TEST J */
153 #define H_TST_NORMAL 0x0000 /* HOST Normal Mode */
154 #define P_TST_PACKET 0x0004 /* PERI TEST Packet */
155 #define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
156 #define P_TST_K 0x0002 /* PERI TEST K */
157 #define P_TST_J 0x0001 /* PERI TEST J */
158 #define P_TST_NORMAL 0x0000 /* PERI Normal Mode */
159
160 /* Data Pin Configuration Register */
161 #define LDRV 0x8000 /* b15: Drive Current Adjust */
162 #define VIF1 0x0000 /* VIF = 1.8V */
163 #define VIF3 0x8000 /* VIF = 3.3V */
164 #define INTA 0x0001 /* b1: USB INT-pin active */
165
166 /* DMAx Pin Configuration Register */
167 #define DREQA 0x4000 /* b14: Dreq active select */
168 #define BURST 0x2000 /* b13: Burst mode */
169 #define DACKA 0x0400 /* b10: Dack active select */
170 #define DFORM 0x0380 /* b9-7: DMA mode select */
171 #define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
172 #define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
173 #define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
174 #define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
175 #define DENDA 0x0040 /* b6: Dend active select */
176 #define PKTM 0x0020 /* b5: Packet mode */
177 #define DENDE 0x0010 /* b4: Dend enable */
178 #define OBUS 0x0004 /* b2: OUTbus mode */
179
180 /* CFIFO/DxFIFO Port Select Register */
181 #define RCNT 0x8000 /* b15: Read count mode */
182 #define REW 0x4000 /* b14: Buffer rewind */
183 #define DCLRM 0x2000 /* b13: DMA buffer clear mode */
184 #define DREQE 0x1000 /* b12: DREQ output enable */
185 #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
186 #define MBW 0x0800
187 #else
188 #define MBW 0x0400 /* b10: Maximum bit width for FIFO access */
189 #endif
190 #define MBW_8 0x0000 /* 8bit */
191 #define MBW_16 0x0400 /* 16bit */
192 #define BIGEND 0x0100 /* b8: Big endian mode */
193 #define BYTE_LITTLE 0x0000 /* little dendian */
194 #define BYTE_BIG 0x0100 /* big endifan */
195 #define ISEL 0x0020 /* b5: DCP FIFO port direction select */
196 #define CURPIPE 0x000F /* b2-0: PIPE select */
197
198 /* CFIFO/DxFIFO Port Control Register */
199 #define BVAL 0x8000 /* b15: Buffer valid flag */
200 #define BCLR 0x4000 /* b14: Buffer clear */
201 #define FRDY 0x2000 /* b13: FIFO ready */
202 #define DTLN 0x0FFF /* b11-0: FIFO received data length */
203
204 /* Interrupt Enable Register 0 */
205 #define VBSE 0x8000 /* b15: VBUS interrupt */
206 #define RSME 0x4000 /* b14: Resume interrupt */
207 #define SOFE 0x2000 /* b13: Frame update interrupt */
208 #define DVSE 0x1000 /* b12: Device state transition interrupt */
209 #define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */
210 #define BEMPE 0x0400 /* b10: Buffer empty interrupt */
211 #define NRDYE 0x0200 /* b9: Buffer not ready interrupt */
212 #define BRDYE 0x0100 /* b8: Buffer ready interrupt */
213
214 /* Interrupt Enable Register 1 */
215 #define OVRCRE 0x8000 /* b15: Over-current interrupt */
216 #define BCHGE 0x4000 /* b14: USB us chenge interrupt */
217 #define DTCHE 0x1000 /* b12: Detach sense interrupt */
218 #define ATTCHE 0x0800 /* b11: Attach sense interrupt */
219 #define EOFERRE 0x0040 /* b6: EOF error interrupt */
220 #define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
221 #define SACKE 0x0010 /* b4: SETUP ACK interrupt */
222
223 /* BRDY Interrupt Enable/Status Register */
224 #define BRDY9 0x0200 /* b9: PIPE9 */
225 #define BRDY8 0x0100 /* b8: PIPE8 */
226 #define BRDY7 0x0080 /* b7: PIPE7 */
227 #define BRDY6 0x0040 /* b6: PIPE6 */
228 #define BRDY5 0x0020 /* b5: PIPE5 */
229 #define BRDY4 0x0010 /* b4: PIPE4 */
230 #define BRDY3 0x0008 /* b3: PIPE3 */
231 #define BRDY2 0x0004 /* b2: PIPE2 */
232 #define BRDY1 0x0002 /* b1: PIPE1 */
233 #define BRDY0 0x0001 /* b1: PIPE0 */
234
235 /* NRDY Interrupt Enable/Status Register */
236 #define NRDY9 0x0200 /* b9: PIPE9 */
237 #define NRDY8 0x0100 /* b8: PIPE8 */
238 #define NRDY7 0x0080 /* b7: PIPE7 */
239 #define NRDY6 0x0040 /* b6: PIPE6 */
240 #define NRDY5 0x0020 /* b5: PIPE5 */
241 #define NRDY4 0x0010 /* b4: PIPE4 */
242 #define NRDY3 0x0008 /* b3: PIPE3 */
243 #define NRDY2 0x0004 /* b2: PIPE2 */
244 #define NRDY1 0x0002 /* b1: PIPE1 */
245 #define NRDY0 0x0001 /* b1: PIPE0 */
246
247 /* BEMP Interrupt Enable/Status Register */
248 #define BEMP9 0x0200 /* b9: PIPE9 */
249 #define BEMP8 0x0100 /* b8: PIPE8 */
250 #define BEMP7 0x0080 /* b7: PIPE7 */
251 #define BEMP6 0x0040 /* b6: PIPE6 */
252 #define BEMP5 0x0020 /* b5: PIPE5 */
253 #define BEMP4 0x0010 /* b4: PIPE4 */
254 #define BEMP3 0x0008 /* b3: PIPE3 */
255 #define BEMP2 0x0004 /* b2: PIPE2 */
256 #define BEMP1 0x0002 /* b1: PIPE1 */
257 #define BEMP0 0x0001 /* b0: PIPE0 */
258
259 /* SOF Pin Configuration Register */
260 #define TRNENSEL 0x0100 /* b8: Select transaction enable period */
261 #define BRDYM 0x0040 /* b6: BRDY clear timing */
262 #define INTL 0x0020 /* b5: Interrupt sense select */
263 #define EDGESTS 0x0010 /* b4: */
264 #define SOFMODE 0x000C /* b3-2: SOF pin select */
265 #define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */
266 #define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
267 #define SOF_DISABLE 0x0000 /* SOF OUT Disable */
268
269 /* Interrupt Status Register 0 */
270 #define VBINT 0x8000 /* b15: VBUS interrupt */
271 #define RESM 0x4000 /* b14: Resume interrupt */
272 #define SOFR 0x2000 /* b13: SOF frame update interrupt */
273 #define DVST 0x1000 /* b12: Device state transition interrupt */
274 #define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */
275 #define BEMP 0x0400 /* b10: Buffer empty interrupt */
276 #define NRDY 0x0200 /* b9: Buffer not ready interrupt */
277 #define BRDY 0x0100 /* b8: Buffer ready interrupt */
278 #define VBSTS 0x0080 /* b7: VBUS input port */
279 #define DVSQ 0x0070 /* b6-4: Device state */
280 #define DS_SPD_CNFG 0x0070 /* Suspend Configured */
281 #define DS_SPD_ADDR 0x0060 /* Suspend Address */
282 #define DS_SPD_DFLT 0x0050 /* Suspend Default */
283 #define DS_SPD_POWR 0x0040 /* Suspend Powered */
284 #define DS_SUSP 0x0040 /* Suspend */
285 #define DS_CNFG 0x0030 /* Configured */
286 #define DS_ADDS 0x0020 /* Address */
287 #define DS_DFLT 0x0010 /* Default */
288 #define DS_POWR 0x0000 /* Powered */
289 #define DVSQS 0x0030 /* b5-4: Device state */
290 #define VALID 0x0008 /* b3: Setup packet detected flag */
291 #define CTSQ 0x0007 /* b2-0: Control transfer stage */
292 #define CS_SQER 0x0006 /* Sequence error */
293 #define CS_WRND 0x0005 /* Control write nodata status stage */
294 #define CS_WRSS 0x0004 /* Control write status stage */
295 #define CS_WRDS 0x0003 /* Control write data stage */
296 #define CS_RDSS 0x0002 /* Control read status stage */
297 #define CS_RDDS 0x0001 /* Control read data stage */
298 #define CS_IDST 0x0000 /* Idle or setup stage */
299
300 /* Interrupt Status Register 1 */
301 #define OVRCR 0x8000 /* b15: Over-current interrupt */
302 #define BCHG 0x4000 /* b14: USB bus chenge interrupt */
303 #define DTCH 0x1000 /* b12: Detach sense interrupt */
304 #define ATTCH 0x0800 /* b11: Attach sense interrupt */
305 #define EOFERR 0x0040 /* b6: EOF-error interrupt */
306 #define SIGN 0x0020 /* b5: Setup ignore interrupt */
307 #define SACK 0x0010 /* b4: Setup acknowledge interrupt */
308
309 /* Frame Number Register */
310 #define OVRN 0x8000 /* b15: Overrun error */
311 #define CRCE 0x4000 /* b14: Received data error */
312 #define FRNM 0x07FF /* b10-0: Frame number */
313
314 /* Micro Frame Number Register */
315 #define UFRNM 0x0007 /* b2-0: Micro frame number */
316
317 /* Default Control Pipe Maxpacket Size Register */
318 /* Pipe Maxpacket Size Register */
319 #define DEVSEL 0xF000 /* b15-14: Device address select */
320 #define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
321
322 /* Default Control Pipe Control Register */
323 #define BSTS 0x8000 /* b15: Buffer status */
324 #define SUREQ 0x4000 /* b14: Send USB request */
325 #define CSCLR 0x2000 /* b13: complete-split status clear */
326 #define CSSTS 0x1000 /* b12: complete-split status */
327 #define SUREQCLR 0x0800 /* b11: stop setup request */
328 #define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
329 #define SQSET 0x0080 /* b7: Sequence toggle bit set */
330 #define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
331 #define PBUSY 0x0020 /* b5: pipe busy */
332 #define PINGE 0x0010 /* b4: ping enable */
333 #define CCPL 0x0004 /* b2: Enable control transfer complete */
334 #define PID 0x0003 /* b1-0: Response PID */
335 #define PID_STALL11 0x0003 /* STALL */
336 #define PID_STALL 0x0002 /* STALL */
337 #define PID_BUF 0x0001 /* BUF */
338 #define PID_NAK 0x0000 /* NAK */
339
340 /* Pipe Window Select Register */
341 #define PIPENM 0x0007 /* b2-0: Pipe select */
342
343 /* Pipe Configuration Register */
344 #define R8A66597_TYP 0xC000 /* b15-14: Transfer type */
345 #define R8A66597_ISO 0xC000 /* Isochronous */
346 #define R8A66597_INT 0x8000 /* Interrupt */
347 #define R8A66597_BULK 0x4000 /* Bulk */
348 #define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */
349 #define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */
350 #define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */
351 #define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */
352 #define R8A66597_DIR 0x0010 /* b4: Transfer direction select */
353 #define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */
354
355 /* Pipe Buffer Configuration Register */
356 #define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
357 #define BUFNMB 0x007F /* b6-0: Pipe buffer number */
358 #define PIPE0BUF 256
359 #define PIPExBUF 64
360
361 /* Pipe Maxpacket Size Register */
362 #define MXPS 0x07FF /* b10-0: Maxpacket size */
363
364 /* Pipe Cycle Configuration Register */
365 #define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
366 #define IITV 0x0007 /* b2-0: Isochronous interval */
367
368 /* Pipex Control Register */
369 #define BSTS 0x8000 /* b15: Buffer status */
370 #define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
371 #define CSCLR 0x2000 /* b13: complete-split status clear */
372 #define CSSTS 0x1000 /* b12: complete-split status */
373 #define ATREPM 0x0400 /* b10: Auto repeat mode */
374 #define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
375 #define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
376 #define SQSET 0x0080 /* b7: Sequence toggle bit set */
377 #define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
378 #define PBUSY 0x0020 /* b5: pipe busy */
379 #define PID 0x0003 /* b1-0: Response PID */
380
381 /* PIPExTRE */
382 #define TRENB 0x0200 /* b9: Transaction counter enable */
383 #define TRCLR 0x0100 /* b8: Transaction counter clear */
384
385 /* PIPExTRN */
386 #define TRNCNT 0xFFFF /* b15-0: Transaction counter */
387
388 /* DEVADDx */
389 #define UPPHUB 0x7800
390 #define HUBPORT 0x0700
391 #define USBSPD 0x00C0
392 #define RTPORT 0x0001
393
394 #define R8A66597_MAX_NUM_PIPE 10
395 #define R8A66597_BUF_BSIZE 8
396 #define R8A66597_MAX_DEVICE 10
397 #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
398 #define R8A66597_MAX_ROOT_HUB 1
399 #else
400 #define R8A66597_MAX_ROOT_HUB 2
401 #endif
402 #define R8A66597_MAX_SAMPLING 5
403 #define R8A66597_RH_POLL_TIME 10
404
405 #define BULK_IN_PIPENUM 3
406 #define BULK_IN_BUFNUM 8
407
408 #define BULK_OUT_PIPENUM 4
409 #define BULK_OUT_BUFNUM 40
410
411 #define check_bulk_or_isoc(pipenum) ((pipenum >= 1 && pipenum <= 5))
412 #define check_interrupt(pipenum) ((pipenum >= 6 && pipenum <= 9))
413 #define make_devsel(addr) (addr << 12)
414
415 struct r8a66597 {
416 unsigned long reg;
417 unsigned short pipe_config; /* bit field */
418 unsigned short port_status;
419 unsigned short port_change;
420 u16 speed; /* HSMODE or FSMODE or LSMODE */
421 unsigned char rh_devnum;
422 };
423
r8a66597_read(struct r8a66597 * r8a66597,unsigned long offset)424 static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
425 {
426 return inw(r8a66597->reg + offset);
427 }
428
r8a66597_read_fifo(struct r8a66597 * r8a66597,unsigned long offset,void * buf,int len)429 static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
430 unsigned long offset, void *buf,
431 int len)
432 {
433 int i;
434 #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
435 unsigned long fifoaddr = r8a66597->reg + offset;
436 unsigned long count;
437 unsigned long *p = buf;
438
439 count = len / 4;
440 for (i = 0; i < count; i++)
441 inl(p[i], r8a66597->reg + offset);
442
443 if (len & 0x00000003) {
444 unsigned long tmp = inl(fifoaddr);
445 memcpy((unsigned char *)buf + count * 4, &tmp, len & 0x03);
446 }
447 #else
448 unsigned short *p = buf;
449
450 len = (len + 1) / 2;
451 for (i = 0; i < len; i++)
452 p[i] = inw(r8a66597->reg + offset);
453 #endif
454 }
455
r8a66597_write(struct r8a66597 * r8a66597,u16 val,unsigned long offset)456 static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
457 unsigned long offset)
458 {
459 outw(val, r8a66597->reg + offset);
460 }
461
r8a66597_write_fifo(struct r8a66597 * r8a66597,unsigned long offset,void * buf,int len)462 static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
463 unsigned long offset, void *buf,
464 int len)
465 {
466 int i;
467 unsigned long fifoaddr = r8a66597->reg + offset;
468 #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
469 unsigned long count;
470 unsigned char *pb;
471 unsigned long *p = buf;
472
473 count = len / 4;
474 for (i = 0; i < count; i++)
475 outl(p[i], fifoaddr);
476
477 if (len & 0x00000003) {
478 pb = (unsigned char *)buf + count * 4;
479 for (i = 0; i < (len & 0x00000003); i++) {
480 if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
481 outb(pb[i], fifoaddr + i);
482 else
483 outb(pb[i], fifoaddr + 3 - i);
484 }
485 }
486 #else
487 int odd = len & 0x0001;
488 unsigned short *p = buf;
489
490 len = len / 2;
491 for (i = 0; i < len; i++)
492 outw(p[i], fifoaddr);
493
494 if (odd) {
495 unsigned char *pb = (unsigned char *)(buf + len);
496 outb(*pb, fifoaddr);
497 }
498 #endif
499 }
500
r8a66597_mdfy(struct r8a66597 * r8a66597,u16 val,u16 pat,unsigned long offset)501 static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
502 u16 val, u16 pat, unsigned long offset)
503 {
504 u16 tmp;
505 tmp = r8a66597_read(r8a66597, offset);
506 tmp = tmp & (~pat);
507 tmp = tmp | val;
508 r8a66597_write(r8a66597, tmp, offset);
509 }
510
511 #define r8a66597_bclr(r8a66597, val, offset) \
512 r8a66597_mdfy(r8a66597, 0, val, offset)
513 #define r8a66597_bset(r8a66597, val, offset) \
514 r8a66597_mdfy(r8a66597, val, 0, offset)
515
get_syscfg_reg(int port)516 static inline unsigned long get_syscfg_reg(int port)
517 {
518 return port == 0 ? SYSCFG0 : SYSCFG1;
519 }
520
get_syssts_reg(int port)521 static inline unsigned long get_syssts_reg(int port)
522 {
523 return port == 0 ? SYSSTS0 : SYSSTS1;
524 }
525
get_dvstctr_reg(int port)526 static inline unsigned long get_dvstctr_reg(int port)
527 {
528 return port == 0 ? DVSTCTR0 : DVSTCTR1;
529 }
530
get_dmacfg_reg(int port)531 static inline unsigned long get_dmacfg_reg(int port)
532 {
533 return port == 0 ? DMA0CFG : DMA1CFG;
534 }
535
get_intenb_reg(int port)536 static inline unsigned long get_intenb_reg(int port)
537 {
538 return port == 0 ? INTENB1 : INTENB2;
539 }
540
get_intsts_reg(int port)541 static inline unsigned long get_intsts_reg(int port)
542 {
543 return port == 0 ? INTSTS1 : INTSTS2;
544 }
545
get_rh_usb_speed(struct r8a66597 * r8a66597,int port)546 static inline u16 get_rh_usb_speed(struct r8a66597 *r8a66597, int port)
547 {
548 unsigned long dvstctr_reg = get_dvstctr_reg(port);
549
550 return r8a66597_read(r8a66597, dvstctr_reg) & RHST;
551 }
552
r8a66597_port_power(struct r8a66597 * r8a66597,int port,int power)553 static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port,
554 int power)
555 {
556 unsigned long dvstctr_reg = get_dvstctr_reg(port);
557
558 if (power)
559 r8a66597_bset(r8a66597, VBOUT, dvstctr_reg);
560 else
561 r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg);
562 }
563
564 #define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
565 #define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4)
566 #define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4)
567 #define get_devadd_addr(address) (DEVADD0 + address * 2)
568
569
570 /* USB HUB CONSTANTS (not OHCI-specific; see hub.h, based on usb_ohci.h) */
571
572 /* destination of request */
573 #define RH_INTERFACE 0x01
574 #define RH_ENDPOINT 0x02
575 #define RH_OTHER 0x03
576
577 #define RH_CLASS 0x20
578 #define RH_VENDOR 0x40
579
580 /* Requests: bRequest << 8 | bmRequestType */
581 #define RH_GET_STATUS 0x0080
582 #define RH_CLEAR_FEATURE 0x0100
583 #define RH_SET_FEATURE 0x0300
584 #define RH_SET_ADDRESS 0x0500
585 #define RH_GET_DESCRIPTOR 0x0680
586 #define RH_SET_DESCRIPTOR 0x0700
587 #define RH_GET_CONFIGURATION 0x0880
588 #define RH_SET_CONFIGURATION 0x0900
589 #define RH_GET_STATE 0x0280
590 #define RH_GET_INTERFACE 0x0A80
591 #define RH_SET_INTERFACE 0x0B00
592 #define RH_SYNC_FRAME 0x0C80
593 /* Our Vendor Specific Request */
594 #define RH_SET_EP 0x2000
595
596 /* Hub port features */
597 #define RH_PORT_CONNECTION 0x00
598 #define RH_PORT_ENABLE 0x01
599 #define RH_PORT_SUSPEND 0x02
600 #define RH_PORT_OVER_CURRENT 0x03
601 #define RH_PORT_RESET 0x04
602 #define RH_PORT_POWER 0x08
603 #define RH_PORT_LOW_SPEED 0x09
604
605 #define RH_C_PORT_CONNECTION 0x10
606 #define RH_C_PORT_ENABLE 0x11
607 #define RH_C_PORT_SUSPEND 0x12
608 #define RH_C_PORT_OVER_CURRENT 0x13
609 #define RH_C_PORT_RESET 0x14
610
611 /* Hub features */
612 #define RH_C_HUB_LOCAL_POWER 0x00
613 #define RH_C_HUB_OVER_CURRENT 0x01
614
615 #define RH_DEVICE_REMOTE_WAKEUP 0x00
616 #define RH_ENDPOINT_STALL 0x01
617
618 #define RH_ACK 0x01
619 #define RH_REQ_ERR -1
620 #define RH_NACK 0x00
621
622 /* OHCI ROOT HUB REGISTER MASKS */
623
624 /* roothub.portstatus [i] bits */
625 #define RH_PS_CCS 0x00000001 /* current connect status */
626 #define RH_PS_PES 0x00000002 /* port enable status*/
627 #define RH_PS_PSS 0x00000004 /* port suspend status */
628 #define RH_PS_POCI 0x00000008 /* port over current indicator */
629 #define RH_PS_PRS 0x00000010 /* port reset status */
630 #define RH_PS_PPS 0x00000100 /* port power status */
631 #define RH_PS_LSDA 0x00000200 /* low speed device attached */
632 #define RH_PS_CSC 0x00010000 /* connect status change */
633 #define RH_PS_PESC 0x00020000 /* port enable status change */
634 #define RH_PS_PSSC 0x00040000 /* port suspend status change */
635 #define RH_PS_OCIC 0x00080000 /* over current indicator change */
636 #define RH_PS_PRSC 0x00100000 /* port reset status change */
637
638 /* roothub.status bits */
639 #define RH_HS_LPS 0x00000001 /* local power status */
640 #define RH_HS_OCI 0x00000002 /* over current indicator */
641 #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
642 #define RH_HS_LPSC 0x00010000 /* local power status change */
643 #define RH_HS_OCIC 0x00020000 /* over current indicator change */
644 #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
645
646 /* roothub.b masks */
647 #define RH_B_DR 0x0000ffff /* device removable flags */
648 #define RH_B_PPCM 0xffff0000 /* port power control mask */
649
650 /* roothub.a masks */
651 #define RH_A_NDP (0xff << 0) /* number of downstream ports */
652 #define RH_A_PSM (1 << 8) /* power switching mode */
653 #define RH_A_NPS (1 << 9) /* no power switching */
654 #define RH_A_DT (1 << 10) /* device type (mbz) */
655 #define RH_A_OCPM (1 << 11) /* over current protection mode */
656 #define RH_A_NOCP (1 << 12) /* no over current protection */
657 #define RH_A_POTPGT (0xff << 24) /* power on to power good time */
658
659 #endif /* __R8A66597_H__ */
660