1 /*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #include <common.h>
25
26 /*
27 * CPU test
28 * Shift instructions: rlwnm
29 *
30 * The test contains a pre-built table of instructions, operands and
31 * expected results. For each table entry, the test will cyclically use
32 * different sets of operand registers and result registers.
33 */
34
35 #include <post.h>
36 #include "cpu_asm.h"
37
38 #if CONFIG_POST & CONFIG_SYS_POST_CPU
39
40 extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
41 ulong op2);
42 extern ulong cpu_post_makecr (long v);
43
44 static struct cpu_post_rlwnm_s
45 {
46 ulong cmd;
47 ulong op1;
48 ulong op2;
49 uchar mb;
50 uchar me;
51 ulong res;
52 } cpu_post_rlwnm_table[] =
53 {
54 {
55 OP_RLWNM,
56 0xffff0000,
57 24,
58 16,
59 23,
60 0x0000ff00
61 },
62 };
63 static unsigned int cpu_post_rlwnm_size =
64 sizeof (cpu_post_rlwnm_table) / sizeof (struct cpu_post_rlwnm_s);
65
cpu_post_test_rlwnm(void)66 int cpu_post_test_rlwnm (void)
67 {
68 int ret = 0;
69 unsigned int i, reg;
70 int flag = disable_interrupts();
71
72 for (i = 0; i < cpu_post_rlwnm_size && ret == 0; i++)
73 {
74 struct cpu_post_rlwnm_s *test = cpu_post_rlwnm_table + i;
75
76 for (reg = 0; reg < 32 && ret == 0; reg++)
77 {
78 unsigned int reg0 = (reg + 0) % 32;
79 unsigned int reg1 = (reg + 1) % 32;
80 unsigned int reg2 = (reg + 2) % 32;
81 unsigned int stk = reg < 16 ? 31 : 15;
82 unsigned long code[] =
83 {
84 ASM_STW(stk, 1, -4),
85 ASM_ADDI(stk, 1, -24),
86 ASM_STW(3, stk, 12),
87 ASM_STW(4, stk, 16),
88 ASM_STW(reg0, stk, 8),
89 ASM_STW(reg1, stk, 4),
90 ASM_STW(reg2, stk, 0),
91 ASM_LWZ(reg1, stk, 12),
92 ASM_LWZ(reg0, stk, 16),
93 ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me),
94 ASM_STW(reg2, stk, 12),
95 ASM_LWZ(reg2, stk, 0),
96 ASM_LWZ(reg1, stk, 4),
97 ASM_LWZ(reg0, stk, 8),
98 ASM_LWZ(3, stk, 12),
99 ASM_ADDI(1, stk, 24),
100 ASM_LWZ(stk, 1, -4),
101 ASM_BLR,
102 };
103 unsigned long codecr[] =
104 {
105 ASM_STW(stk, 1, -4),
106 ASM_ADDI(stk, 1, -24),
107 ASM_STW(3, stk, 12),
108 ASM_STW(4, stk, 16),
109 ASM_STW(reg0, stk, 8),
110 ASM_STW(reg1, stk, 4),
111 ASM_STW(reg2, stk, 0),
112 ASM_LWZ(reg1, stk, 12),
113 ASM_LWZ(reg0, stk, 16),
114 ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me) |
115 BIT_C,
116 ASM_STW(reg2, stk, 12),
117 ASM_LWZ(reg2, stk, 0),
118 ASM_LWZ(reg1, stk, 4),
119 ASM_LWZ(reg0, stk, 8),
120 ASM_LWZ(3, stk, 12),
121 ASM_ADDI(1, stk, 24),
122 ASM_LWZ(stk, 1, -4),
123 ASM_BLR,
124 };
125 ulong res;
126 ulong cr;
127
128 if (ret == 0)
129 {
130 cr = 0;
131 cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
132
133 ret = res == test->res && cr == 0 ? 0 : -1;
134
135 if (ret != 0)
136 {
137 post_log ("Error at rlwnm test %d !\n", i);
138 }
139 }
140
141 if (ret == 0)
142 {
143 cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
144
145 ret = res == test->res &&
146 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
147
148 if (ret != 0)
149 {
150 post_log ("Error at rlwnm test %d !\n", i);
151 }
152 }
153 }
154 }
155
156 if (flag)
157 enable_interrupts();
158
159 return ret;
160 }
161
162 #endif
163