1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Cadence DDR Driver 4 * 5 * Copyright (C) 2012-2021 Cadence Design Systems, Inc. 6 * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ 7 */ 8 9 #ifndef LPDDR4_H 10 #define LPDDR4_H 11 12 #include "lpddr4_ctl_regs.h" 13 #include "lpddr4_sanity.h" 14 #ifdef CONFIG_K3_AM64_DDRSS 15 #include "lpddr4_16bit.h" 16 #include "lpddr4_16bit_sanity.h" 17 #else 18 #include "lpddr4_32bit.h" 19 #include "lpddr4_32bit_sanity.h" 20 #endif 21 22 #ifdef REG_WRITE_VERIF 23 #include "lpddr4_ctl_regs_rw_masks.h" 24 #endif 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 #define PRODUCT_ID (0x1046U) 30 31 #define LPDDR4_BIT_MASK (0x1U) 32 #define BYTE_MASK (0xffU) 33 #define NIBBLE_MASK (0xfU) 34 35 #define WORD_SHIFT (32U) 36 #define WORD_MASK (0xffffffffU) 37 #define SLICE_WIDTH (0x100) 38 39 #define CTL_OFFSET 0 40 #define PI_OFFSET (((u32)1) << 11) 41 #define PHY_OFFSET (((u32)1) << 12) 42 43 #define CTL_INT_MASK_ALL ((u32)LPDDR4_LOR_BITS - WORD_SHIFT) 44 45 #define PLL_READY (0x3U) 46 #define IO_CALIB_DONE ((u32)0x1U << 23U) 47 #define IO_CALIB_FIELD ((u32)NIBBLE_MASK << 28U) 48 #define IO_CALIB_STATE ((u32)0xBU << 28U) 49 #define RX_CAL_DONE ((u32)LPDDR4_BIT_MASK << 4U) 50 #define CA_TRAIN_RL (((u32)LPDDR4_BIT_MASK << 5U) | ((u32)LPDDR4_BIT_MASK << 4U)) 51 #define WR_LVL_STATE (((u32)NIBBLE_MASK) << 13U) 52 #define GATE_LVL_ERROR_FIELDS (((u32)LPDDR4_BIT_MASK << 7U) | ((u32)LPDDR4_BIT_MASK << 6U)) 53 #define READ_LVL_ERROR_FIELDS ((((u32)NIBBLE_MASK) << 28U) | (((u32)BYTE_MASK) << 16U)) 54 #define DQ_LVL_STATUS (((u32)LPDDR4_BIT_MASK << 26U) | (((u32)BYTE_MASK) << 18U)) 55 56 #define CDN_TRUE 1U 57 #define CDN_FALSE 0U 58 59 void lpddr4_setsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound); 60 volatile u32 *lpddr4_addoffset(volatile u32 *addr, u32 regoffset); 61 u32 lpddr4_pollctlirq(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt irqbit, u32 delay); 62 bool lpddr4_checklvlerrors(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo, bool errfound); 63 void lpddr4_seterrors(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, u8 *errfoundptr); 64 65 u32 lpddr4_enablepiinitiator(const lpddr4_privatedata *pd); 66 void lpddr4_checkwrlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr); 67 u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mrrstatus); 68 u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset); 69 #ifdef __cplusplus 70 } 71 #endif 72 73 #endif /* LPDDR4_H */ 74