1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2009
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 */
7
8 #include <common.h>
9 #include <log.h>
10 #include <asm/global_data.h>
11 #include <asm/io.h>
12 #include <usb.h>
13 #include <linux/delay.h>
14 #include "ehci.h"
15 #include <linux/mbus.h>
16 #include <asm/arch/cpu.h>
17 #include <dm.h>
18
19 #if defined(CONFIG_ARCH_KIRKWOOD)
20 #include <asm/arch/soc.h>
21 #elif defined(CONFIG_ARCH_ORION5X)
22 #include <asm/arch/orion5x.h>
23 #endif
24
25 DECLARE_GLOBAL_DATA_PTR;
26
27 #define USB_WINDOW_CTRL(i) (0x320 + ((i) << 4))
28 #define USB_WINDOW_BASE(i) (0x324 + ((i) << 4))
29 #define USB_TARGET_DRAM 0x0
30
31 #define USB2_SBUSCFG_OFF 0x90
32
33 #define USB_SBUSCFG_BAWR_OFF 0x6
34 #define USB_SBUSCFG_BARD_OFF 0x3
35 #define USB_SBUSCFG_AHBBRST_OFF 0x0
36
37 #define USB_SBUSCFG_BAWR_ALIGN_64B 0x4
38 #define USB_SBUSCFG_BARD_ALIGN_64B 0x4
39 #define USB_SBUSCFG_AHBBRST_INCR16 0x7
40
41 /*
42 * USB 2.0 Bridge Address Decoding registers setup
43 */
44 #if CONFIG_IS_ENABLED(DM_USB)
45
46 struct ehci_mvebu_priv {
47 struct ehci_ctrl ehci;
48 fdt_addr_t hcd_base;
49 };
50
51 /*
52 * Once all the older Marvell SoC's (Orion, Kirkwood) are converted
53 * to the common mvebu archticture including the mbus setup, this
54 * will be the only function needed to configure the access windows
55 */
usb_brg_adrdec_setup(void * base)56 static void usb_brg_adrdec_setup(void *base)
57 {
58 const struct mbus_dram_target_info *dram;
59 int i;
60
61 dram = mvebu_mbus_dram_info();
62
63 for (i = 0; i < 4; i++) {
64 writel(0, base + USB_WINDOW_CTRL(i));
65 writel(0, base + USB_WINDOW_BASE(i));
66 }
67
68 for (i = 0; i < dram->num_cs; i++) {
69 const struct mbus_dram_window *cs = dram->cs + i;
70
71 /* Write size, attributes and target id to control register */
72 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
73 (dram->mbus_dram_target_id << 4) | 1,
74 base + USB_WINDOW_CTRL(i));
75
76 /* Write base address to base register */
77 writel(cs->base, base + USB_WINDOW_BASE(i));
78 }
79 }
80
marvell_ehci_powerup_fixup(struct ehci_ctrl * ctrl,uint32_t * status_reg,uint32_t * reg)81 static void marvell_ehci_powerup_fixup(struct ehci_ctrl *ctrl,
82 uint32_t *status_reg, uint32_t *reg)
83 {
84 struct ehci_mvebu_priv *priv = ctrl->priv;
85
86 /*
87 * Set default value for reg SBUSCFG, which is Control for the AMBA
88 * system bus interface:
89 * BAWR = BARD = 4 : Align rd/wr bursts packets larger than 64 bytes
90 * AHBBRST = 7 : Align AHB burst for packets larger than 64 bytes
91 */
92 writel((USB_SBUSCFG_BAWR_ALIGN_64B << USB_SBUSCFG_BAWR_OFF) |
93 (USB_SBUSCFG_BARD_ALIGN_64B << USB_SBUSCFG_BARD_OFF) |
94 (USB_SBUSCFG_AHBBRST_INCR16 << USB_SBUSCFG_AHBBRST_OFF),
95 priv->hcd_base + USB2_SBUSCFG_OFF);
96
97 mdelay(50);
98 }
99
100 static struct ehci_ops marvell_ehci_ops = {
101 .powerup_fixup = NULL,
102 };
103
ehci_mvebu_probe(struct udevice * dev)104 static int ehci_mvebu_probe(struct udevice *dev)
105 {
106 struct ehci_mvebu_priv *priv = dev_get_priv(dev);
107 struct ehci_hccr *hccr;
108 struct ehci_hcor *hcor;
109
110 /*
111 * Get the base address for EHCI controller from the device node
112 */
113 priv->hcd_base = dev_read_addr(dev);
114 if (priv->hcd_base == FDT_ADDR_T_NONE) {
115 debug("Can't get the EHCI register base address\n");
116 return -ENXIO;
117 }
118
119 /*
120 * For SoCs without hlock like Armada3700 we need to program the sbuscfg
121 * reg to guarantee AHB master's burst will not overrun or underrun
122 * the FIFO. Otherwise all USB2 write option will fail.
123 * Also, the address decoder doesn't need to get setup with this
124 * SoC, so don't call usb_brg_adrdec_setup().
125 */
126 if (device_is_compatible(dev, "marvell,armada3700-ehci"))
127 marvell_ehci_ops.powerup_fixup = marvell_ehci_powerup_fixup;
128 else
129 usb_brg_adrdec_setup((void *)priv->hcd_base);
130
131 hccr = (struct ehci_hccr *)(priv->hcd_base + 0x100);
132 hcor = (struct ehci_hcor *)
133 ((uintptr_t)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
134
135 debug("ehci-marvell: init hccr %lx and hcor %lx hc_length %ld\n",
136 (uintptr_t)hccr, (uintptr_t)hcor,
137 (uintptr_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
138
139 return ehci_register(dev, hccr, hcor, &marvell_ehci_ops, 0,
140 USB_INIT_HOST);
141 }
142
143 static const struct udevice_id ehci_usb_ids[] = {
144 { .compatible = "marvell,orion-ehci", },
145 { .compatible = "marvell,armada3700-ehci", },
146 { }
147 };
148
149 U_BOOT_DRIVER(ehci_mvebu) = {
150 .name = "ehci_mvebu",
151 .id = UCLASS_USB,
152 .of_match = ehci_usb_ids,
153 .probe = ehci_mvebu_probe,
154 .remove = ehci_deregister,
155 .ops = &ehci_usb_ops,
156 .plat_auto = sizeof(struct usb_plat),
157 .priv_auto = sizeof(struct ehci_mvebu_priv),
158 .flags = DM_FLAG_ALLOC_PRIV_DMA,
159 };
160
161 #else
162 #define MVUSB_BASE(port) MVUSB0_BASE
163
usb_brg_adrdec_setup(int index)164 static void usb_brg_adrdec_setup(int index)
165 {
166 int i;
167 u32 size, base, attrib;
168
169 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
170
171 /* Enable DRAM bank */
172 switch (i) {
173 case 0:
174 attrib = MVUSB0_CPU_ATTR_DRAM_CS0;
175 break;
176 case 1:
177 attrib = MVUSB0_CPU_ATTR_DRAM_CS1;
178 break;
179 case 2:
180 attrib = MVUSB0_CPU_ATTR_DRAM_CS2;
181 break;
182 case 3:
183 attrib = MVUSB0_CPU_ATTR_DRAM_CS3;
184 break;
185 default:
186 /* invalide bank, disable access */
187 attrib = 0;
188 break;
189 }
190
191 size = gd->bd->bi_dram[i].size;
192 base = gd->bd->bi_dram[i].start;
193 if ((size) && (attrib))
194 writel(MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
195 attrib, MVCPU_WIN_ENABLE),
196 MVUSB0_BASE + USB_WINDOW_CTRL(i));
197 else
198 writel(MVCPU_WIN_DISABLE,
199 MVUSB0_BASE + USB_WINDOW_CTRL(i));
200
201 writel(base, MVUSB0_BASE + USB_WINDOW_BASE(i));
202 }
203 }
204
205 /*
206 * Create the appropriate control structures to manage
207 * a new EHCI host controller.
208 */
ehci_hcd_init(int index,enum usb_init_type init,struct ehci_hccr ** hccr,struct ehci_hcor ** hcor)209 int ehci_hcd_init(int index, enum usb_init_type init,
210 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
211 {
212 usb_brg_adrdec_setup(index);
213
214 *hccr = (struct ehci_hccr *)(MVUSB_BASE(index) + 0x100);
215 *hcor = (struct ehci_hcor *)((uint32_t) *hccr
216 + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
217
218 debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n",
219 (uint32_t)*hccr, (uint32_t)*hcor,
220 (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
221
222 return 0;
223 }
224
225 /*
226 * Destroy the appropriate control structures corresponding
227 * the the EHCI host controller.
228 */
ehci_hcd_stop(int index)229 int ehci_hcd_stop(int index)
230 {
231 return 0;
232 }
233
234 #endif /* CONFIG_IS_ENABLED(DM_USB) */
235