1 /* Capstone Disassembly Engine */
2 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
3
4 #ifdef CAPSTONE_HAS_MIPS
5
6 #include <stdio.h> // debug
7 #include <string.h>
8
9 #include "../../utils.h"
10
11 #include "MipsMapping.h"
12
13 #define GET_INSTRINFO_ENUM
14 #include "MipsGenInstrInfo.inc"
15
16 #ifndef CAPSTONE_DIET
17 static const name_map reg_name_maps[] = {
18 { MIPS_REG_INVALID, NULL },
19
20 //{ MIPS_REG_0, "0"},
21 { MIPS_REG_0, "zero"},
22 { MIPS_REG_1, "at"},
23 //{ MIPS_REG_1, "1"},
24 { MIPS_REG_2, "v0"},
25 //{ MIPS_REG_2, "2"},
26 { MIPS_REG_3, "v1"},
27 //{ MIPS_REG_3, "3"},
28 { MIPS_REG_4, "a0"},
29 //{ MIPS_REG_4, "4"},
30 { MIPS_REG_5, "a1"},
31 //{ MIPS_REG_5, "5"},
32 { MIPS_REG_6, "a2"},
33 //{ MIPS_REG_6, "6"},
34 { MIPS_REG_7, "a3"},
35 //{ MIPS_REG_7, "7"},
36 { MIPS_REG_8, "t0"},
37 //{ MIPS_REG_8, "8"},
38 { MIPS_REG_9, "t1"},
39 //{ MIPS_REG_9, "9"},
40 { MIPS_REG_10, "t2"},
41 //{ MIPS_REG_10, "10"},
42 { MIPS_REG_11, "t3"},
43 //{ MIPS_REG_11, "11"},
44 { MIPS_REG_12, "t4"},
45 //{ MIPS_REG_12, "12"},
46 { MIPS_REG_13, "t5"},
47 //{ MIPS_REG_13, "13"},
48 { MIPS_REG_14, "t6"},
49 //{ MIPS_REG_14, "14"},
50 { MIPS_REG_15, "t7"},
51 //{ MIPS_REG_15, "15"},
52 { MIPS_REG_16, "s0"},
53 //{ MIPS_REG_16, "16"},
54 { MIPS_REG_17, "s1"},
55 //{ MIPS_REG_17, "17"},
56 { MIPS_REG_18, "s2"},
57 //{ MIPS_REG_18, "18"},
58 { MIPS_REG_19, "s3"},
59 //{ MIPS_REG_19, "19"},
60 { MIPS_REG_20, "s4"},
61 //{ MIPS_REG_20, "20"},
62 { MIPS_REG_21, "s5"},
63 //{ MIPS_REG_21, "21"},
64 { MIPS_REG_22, "s6"},
65 //{ MIPS_REG_22, "22"},
66 { MIPS_REG_23, "s7"},
67 //{ MIPS_REG_23, "23"},
68 { MIPS_REG_24, "t8"},
69 //{ MIPS_REG_24, "24"},
70 { MIPS_REG_25, "t9"},
71 //{ MIPS_REG_25, "25"},
72 { MIPS_REG_26, "k0"},
73 //{ MIPS_REG_26, "26"},
74 { MIPS_REG_27, "k1"},
75 //{ MIPS_REG_27, "27"},
76 { MIPS_REG_28, "gp"},
77 //{ MIPS_REG_28, "28"},
78 { MIPS_REG_29, "sp"},
79 //{ MIPS_REG_29, "29"},
80 { MIPS_REG_30, "fp"},
81 //{ MIPS_REG_30, "30"},
82 { MIPS_REG_31, "ra"},
83 //{ MIPS_REG_31, "31"},
84
85 { MIPS_REG_DSPCCOND, "dspccond"},
86 { MIPS_REG_DSPCARRY, "dspcarry"},
87 { MIPS_REG_DSPEFI, "dspefi"},
88 { MIPS_REG_DSPOUTFLAG, "dspoutflag"},
89 { MIPS_REG_DSPOUTFLAG16_19, "dspoutflag16_19"},
90 { MIPS_REG_DSPOUTFLAG20, "dspoutflag20"},
91 { MIPS_REG_DSPOUTFLAG21, "dspoutflag21"},
92 { MIPS_REG_DSPOUTFLAG22, "dspoutflag22"},
93 { MIPS_REG_DSPOUTFLAG23, "dspoutflag23"},
94 { MIPS_REG_DSPPOS, "dsppos"},
95 { MIPS_REG_DSPSCOUNT, "dspscount"},
96
97 { MIPS_REG_AC0, "ac0"},
98 { MIPS_REG_AC1, "ac1"},
99 { MIPS_REG_AC2, "ac2"},
100 { MIPS_REG_AC3, "ac3"},
101
102 { MIPS_REG_CC0, "cc0"},
103 { MIPS_REG_CC1, "cc1"},
104 { MIPS_REG_CC2, "cc2"},
105 { MIPS_REG_CC3, "cc3"},
106 { MIPS_REG_CC4, "cc4"},
107 { MIPS_REG_CC5, "cc5"},
108 { MIPS_REG_CC6, "cc6"},
109 { MIPS_REG_CC7, "cc7"},
110
111 { MIPS_REG_F0, "f0"},
112 { MIPS_REG_F1, "f1"},
113 { MIPS_REG_F2, "f2"},
114 { MIPS_REG_F3, "f3"},
115 { MIPS_REG_F4, "f4"},
116 { MIPS_REG_F5, "f5"},
117 { MIPS_REG_F6, "f6"},
118 { MIPS_REG_F7, "f7"},
119 { MIPS_REG_F8, "f8"},
120 { MIPS_REG_F9, "f9"},
121 { MIPS_REG_F10, "f10"},
122 { MIPS_REG_F11, "f11"},
123 { MIPS_REG_F12, "f12"},
124 { MIPS_REG_F13, "f13"},
125 { MIPS_REG_F14, "f14"},
126 { MIPS_REG_F15, "f15"},
127 { MIPS_REG_F16, "f16"},
128 { MIPS_REG_F17, "f17"},
129 { MIPS_REG_F18, "f18"},
130 { MIPS_REG_F19, "f19"},
131 { MIPS_REG_F20, "f20"},
132 { MIPS_REG_F21, "f21"},
133 { MIPS_REG_F22, "f22"},
134 { MIPS_REG_F23, "f23"},
135 { MIPS_REG_F24, "f24"},
136 { MIPS_REG_F25, "f25"},
137 { MIPS_REG_F26, "f26"},
138 { MIPS_REG_F27, "f27"},
139 { MIPS_REG_F28, "f28"},
140 { MIPS_REG_F29, "f29"},
141 { MIPS_REG_F30, "f30"},
142 { MIPS_REG_F31, "f31"},
143
144 { MIPS_REG_FCC0, "fcc0"},
145 { MIPS_REG_FCC1, "fcc1"},
146 { MIPS_REG_FCC2, "fcc2"},
147 { MIPS_REG_FCC3, "fcc3"},
148 { MIPS_REG_FCC4, "fcc4"},
149 { MIPS_REG_FCC5, "fcc5"},
150 { MIPS_REG_FCC6, "fcc6"},
151 { MIPS_REG_FCC7, "fcc7"},
152
153 { MIPS_REG_W0, "w0"},
154 { MIPS_REG_W1, "w1"},
155 { MIPS_REG_W2, "w2"},
156 { MIPS_REG_W3, "w3"},
157 { MIPS_REG_W4, "w4"},
158 { MIPS_REG_W5, "w5"},
159 { MIPS_REG_W6, "w6"},
160 { MIPS_REG_W7, "w7"},
161 { MIPS_REG_W8, "w8"},
162 { MIPS_REG_W9, "w9"},
163 { MIPS_REG_W10, "w10"},
164 { MIPS_REG_W11, "w11"},
165 { MIPS_REG_W12, "w12"},
166 { MIPS_REG_W13, "w13"},
167 { MIPS_REG_W14, "w14"},
168 { MIPS_REG_W15, "w15"},
169 { MIPS_REG_W16, "w16"},
170 { MIPS_REG_W17, "w17"},
171 { MIPS_REG_W18, "w18"},
172 { MIPS_REG_W19, "w19"},
173 { MIPS_REG_W20, "w20"},
174 { MIPS_REG_W21, "w21"},
175 { MIPS_REG_W22, "w22"},
176 { MIPS_REG_W23, "w23"},
177 { MIPS_REG_W24, "w24"},
178 { MIPS_REG_W25, "w25"},
179 { MIPS_REG_W26, "w26"},
180 { MIPS_REG_W27, "w27"},
181 { MIPS_REG_W28, "w28"},
182 { MIPS_REG_W29, "w29"},
183 { MIPS_REG_W30, "w30"},
184 { MIPS_REG_W31, "w31"},
185
186 { MIPS_REG_HI, "hi"},
187 { MIPS_REG_LO, "lo"},
188
189 { MIPS_REG_P0, "p0"},
190 { MIPS_REG_P1, "p1"},
191 { MIPS_REG_P2, "p2"},
192
193 { MIPS_REG_MPL0, "mpl0"},
194 { MIPS_REG_MPL1, "mpl1"},
195 { MIPS_REG_MPL2, "mpl2"},
196 };
197 #endif
198
Mips_reg_name(csh handle,unsigned int reg)199 const char *Mips_reg_name(csh handle, unsigned int reg)
200 {
201 #ifndef CAPSTONE_DIET
202 if (reg >= MIPS_REG_ENDING)
203 return NULL;
204
205 return reg_name_maps[reg].name;
206 #else
207 return NULL;
208 #endif
209 }
210
211 static const insn_map insns[] = {
212 // dummy item
213 {
214 0, 0,
215 #ifndef CAPSTONE_DIET
216 { 0 }, { 0 }, { 0 }, 0, 0
217 #endif
218 },
219
220 {
221 Mips_ABSQ_S_PH, MIPS_INS_ABSQ_S,
222 #ifndef CAPSTONE_DIET
223 { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
224 #endif
225 },
226 {
227 Mips_ABSQ_S_QB, MIPS_INS_ABSQ_S,
228 #ifndef CAPSTONE_DIET
229 { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
230 #endif
231 },
232 {
233 Mips_ABSQ_S_W, MIPS_INS_ABSQ_S,
234 #ifndef CAPSTONE_DIET
235 { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
236 #endif
237 },
238 {
239 Mips_ADD, MIPS_INS_ADD,
240 #ifndef CAPSTONE_DIET
241 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
242 #endif
243 },
244 {
245 Mips_ADDIUPC, MIPS_INS_ADDIUPC,
246 #ifndef CAPSTONE_DIET
247 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
248 #endif
249 },
250 {
251 Mips_ADDQH_PH, MIPS_INS_ADDQH,
252 #ifndef CAPSTONE_DIET
253 { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
254 #endif
255 },
256 {
257 Mips_ADDQH_R_PH, MIPS_INS_ADDQH_R,
258 #ifndef CAPSTONE_DIET
259 { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
260 #endif
261 },
262 {
263 Mips_ADDQH_R_W, MIPS_INS_ADDQH_R,
264 #ifndef CAPSTONE_DIET
265 { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
266 #endif
267 },
268 {
269 Mips_ADDQH_W, MIPS_INS_ADDQH,
270 #ifndef CAPSTONE_DIET
271 { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
272 #endif
273 },
274 {
275 Mips_ADDQ_PH, MIPS_INS_ADDQ,
276 #ifndef CAPSTONE_DIET
277 { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
278 #endif
279 },
280 {
281 Mips_ADDQ_S_PH, MIPS_INS_ADDQ_S,
282 #ifndef CAPSTONE_DIET
283 { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
284 #endif
285 },
286 {
287 Mips_ADDQ_S_W, MIPS_INS_ADDQ_S,
288 #ifndef CAPSTONE_DIET
289 { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
290 #endif
291 },
292 {
293 Mips_ADDSC, MIPS_INS_ADDSC,
294 #ifndef CAPSTONE_DIET
295 { 0 }, { MIPS_REG_DSPCARRY, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
296 #endif
297 },
298 {
299 Mips_ADDS_A_B, MIPS_INS_ADDS_A,
300 #ifndef CAPSTONE_DIET
301 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
302 #endif
303 },
304 {
305 Mips_ADDS_A_D, MIPS_INS_ADDS_A,
306 #ifndef CAPSTONE_DIET
307 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
308 #endif
309 },
310 {
311 Mips_ADDS_A_H, MIPS_INS_ADDS_A,
312 #ifndef CAPSTONE_DIET
313 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
314 #endif
315 },
316 {
317 Mips_ADDS_A_W, MIPS_INS_ADDS_A,
318 #ifndef CAPSTONE_DIET
319 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
320 #endif
321 },
322 {
323 Mips_ADDS_S_B, MIPS_INS_ADDS_S,
324 #ifndef CAPSTONE_DIET
325 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
326 #endif
327 },
328 {
329 Mips_ADDS_S_D, MIPS_INS_ADDS_S,
330 #ifndef CAPSTONE_DIET
331 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
332 #endif
333 },
334 {
335 Mips_ADDS_S_H, MIPS_INS_ADDS_S,
336 #ifndef CAPSTONE_DIET
337 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
338 #endif
339 },
340 {
341 Mips_ADDS_S_W, MIPS_INS_ADDS_S,
342 #ifndef CAPSTONE_DIET
343 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
344 #endif
345 },
346 {
347 Mips_ADDS_U_B, MIPS_INS_ADDS_U,
348 #ifndef CAPSTONE_DIET
349 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
350 #endif
351 },
352 {
353 Mips_ADDS_U_D, MIPS_INS_ADDS_U,
354 #ifndef CAPSTONE_DIET
355 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
356 #endif
357 },
358 {
359 Mips_ADDS_U_H, MIPS_INS_ADDS_U,
360 #ifndef CAPSTONE_DIET
361 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
362 #endif
363 },
364 {
365 Mips_ADDS_U_W, MIPS_INS_ADDS_U,
366 #ifndef CAPSTONE_DIET
367 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
368 #endif
369 },
370 {
371 Mips_ADDUH_QB, MIPS_INS_ADDUH,
372 #ifndef CAPSTONE_DIET
373 { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
374 #endif
375 },
376 {
377 Mips_ADDUH_R_QB, MIPS_INS_ADDUH_R,
378 #ifndef CAPSTONE_DIET
379 { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
380 #endif
381 },
382 {
383 Mips_ADDU_PH, MIPS_INS_ADDU,
384 #ifndef CAPSTONE_DIET
385 { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
386 #endif
387 },
388 {
389 Mips_ADDU_QB, MIPS_INS_ADDU,
390 #ifndef CAPSTONE_DIET
391 { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
392 #endif
393 },
394 {
395 Mips_ADDU_S_PH, MIPS_INS_ADDU_S,
396 #ifndef CAPSTONE_DIET
397 { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
398 #endif
399 },
400 {
401 Mips_ADDU_S_QB, MIPS_INS_ADDU_S,
402 #ifndef CAPSTONE_DIET
403 { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
404 #endif
405 },
406 {
407 Mips_ADDVI_B, MIPS_INS_ADDVI,
408 #ifndef CAPSTONE_DIET
409 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
410 #endif
411 },
412 {
413 Mips_ADDVI_D, MIPS_INS_ADDVI,
414 #ifndef CAPSTONE_DIET
415 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
416 #endif
417 },
418 {
419 Mips_ADDVI_H, MIPS_INS_ADDVI,
420 #ifndef CAPSTONE_DIET
421 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
422 #endif
423 },
424 {
425 Mips_ADDVI_W, MIPS_INS_ADDVI,
426 #ifndef CAPSTONE_DIET
427 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
428 #endif
429 },
430 {
431 Mips_ADDV_B, MIPS_INS_ADDV,
432 #ifndef CAPSTONE_DIET
433 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
434 #endif
435 },
436 {
437 Mips_ADDV_D, MIPS_INS_ADDV,
438 #ifndef CAPSTONE_DIET
439 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
440 #endif
441 },
442 {
443 Mips_ADDV_H, MIPS_INS_ADDV,
444 #ifndef CAPSTONE_DIET
445 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
446 #endif
447 },
448 {
449 Mips_ADDV_W, MIPS_INS_ADDV,
450 #ifndef CAPSTONE_DIET
451 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
452 #endif
453 },
454 {
455 Mips_ADDWC, MIPS_INS_ADDWC,
456 #ifndef CAPSTONE_DIET
457 { MIPS_REG_DSPCARRY, 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
458 #endif
459 },
460 {
461 Mips_ADD_A_B, MIPS_INS_ADD_A,
462 #ifndef CAPSTONE_DIET
463 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
464 #endif
465 },
466 {
467 Mips_ADD_A_D, MIPS_INS_ADD_A,
468 #ifndef CAPSTONE_DIET
469 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
470 #endif
471 },
472 {
473 Mips_ADD_A_H, MIPS_INS_ADD_A,
474 #ifndef CAPSTONE_DIET
475 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
476 #endif
477 },
478 {
479 Mips_ADD_A_W, MIPS_INS_ADD_A,
480 #ifndef CAPSTONE_DIET
481 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
482 #endif
483 },
484 {
485 Mips_ADD_MM, MIPS_INS_ADD,
486 #ifndef CAPSTONE_DIET
487 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
488 #endif
489 },
490 {
491 Mips_ADDi, MIPS_INS_ADDI,
492 #ifndef CAPSTONE_DIET
493 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
494 #endif
495 },
496 {
497 Mips_ADDi_MM, MIPS_INS_ADDI,
498 #ifndef CAPSTONE_DIET
499 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
500 #endif
501 },
502 {
503 Mips_ADDiu, MIPS_INS_ADDIU,
504 #ifndef CAPSTONE_DIET
505 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
506 #endif
507 },
508 {
509 Mips_ADDiu_MM, MIPS_INS_ADDIU,
510 #ifndef CAPSTONE_DIET
511 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
512 #endif
513 },
514 {
515 Mips_ADDu, MIPS_INS_ADDU,
516 #ifndef CAPSTONE_DIET
517 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
518 #endif
519 },
520 {
521 Mips_ADDu_MM, MIPS_INS_ADDU,
522 #ifndef CAPSTONE_DIET
523 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
524 #endif
525 },
526 {
527 Mips_ALIGN, MIPS_INS_ALIGN,
528 #ifndef CAPSTONE_DIET
529 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
530 #endif
531 },
532 {
533 Mips_ALUIPC, MIPS_INS_ALUIPC,
534 #ifndef CAPSTONE_DIET
535 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
536 #endif
537 },
538 {
539 Mips_AND, MIPS_INS_AND,
540 #ifndef CAPSTONE_DIET
541 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
542 #endif
543 },
544 {
545 Mips_AND64, MIPS_INS_AND,
546 #ifndef CAPSTONE_DIET
547 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
548 #endif
549 },
550 {
551 Mips_ANDI_B, MIPS_INS_ANDI,
552 #ifndef CAPSTONE_DIET
553 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
554 #endif
555 },
556 {
557 Mips_AND_MM, MIPS_INS_AND,
558 #ifndef CAPSTONE_DIET
559 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
560 #endif
561 },
562 {
563 Mips_AND_V, MIPS_INS_AND,
564 #ifndef CAPSTONE_DIET
565 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
566 #endif
567 },
568 {
569 Mips_ANDi, MIPS_INS_ANDI,
570 #ifndef CAPSTONE_DIET
571 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
572 #endif
573 },
574 {
575 Mips_ANDi64, MIPS_INS_ANDI,
576 #ifndef CAPSTONE_DIET
577 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
578 #endif
579 },
580 {
581 Mips_ANDi_MM, MIPS_INS_ANDI,
582 #ifndef CAPSTONE_DIET
583 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
584 #endif
585 },
586 {
587 Mips_APPEND, MIPS_INS_APPEND,
588 #ifndef CAPSTONE_DIET
589 { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
590 #endif
591 },
592 {
593 Mips_ASUB_S_B, MIPS_INS_ASUB_S,
594 #ifndef CAPSTONE_DIET
595 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
596 #endif
597 },
598 {
599 Mips_ASUB_S_D, MIPS_INS_ASUB_S,
600 #ifndef CAPSTONE_DIET
601 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
602 #endif
603 },
604 {
605 Mips_ASUB_S_H, MIPS_INS_ASUB_S,
606 #ifndef CAPSTONE_DIET
607 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
608 #endif
609 },
610 {
611 Mips_ASUB_S_W, MIPS_INS_ASUB_S,
612 #ifndef CAPSTONE_DIET
613 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
614 #endif
615 },
616 {
617 Mips_ASUB_U_B, MIPS_INS_ASUB_U,
618 #ifndef CAPSTONE_DIET
619 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
620 #endif
621 },
622 {
623 Mips_ASUB_U_D, MIPS_INS_ASUB_U,
624 #ifndef CAPSTONE_DIET
625 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
626 #endif
627 },
628 {
629 Mips_ASUB_U_H, MIPS_INS_ASUB_U,
630 #ifndef CAPSTONE_DIET
631 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
632 #endif
633 },
634 {
635 Mips_ASUB_U_W, MIPS_INS_ASUB_U,
636 #ifndef CAPSTONE_DIET
637 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
638 #endif
639 },
640 {
641 Mips_AUI, MIPS_INS_AUI,
642 #ifndef CAPSTONE_DIET
643 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
644 #endif
645 },
646 {
647 Mips_AUIPC, MIPS_INS_AUIPC,
648 #ifndef CAPSTONE_DIET
649 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
650 #endif
651 },
652 {
653 Mips_AVER_S_B, MIPS_INS_AVER_S,
654 #ifndef CAPSTONE_DIET
655 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
656 #endif
657 },
658 {
659 Mips_AVER_S_D, MIPS_INS_AVER_S,
660 #ifndef CAPSTONE_DIET
661 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
662 #endif
663 },
664 {
665 Mips_AVER_S_H, MIPS_INS_AVER_S,
666 #ifndef CAPSTONE_DIET
667 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
668 #endif
669 },
670 {
671 Mips_AVER_S_W, MIPS_INS_AVER_S,
672 #ifndef CAPSTONE_DIET
673 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
674 #endif
675 },
676 {
677 Mips_AVER_U_B, MIPS_INS_AVER_U,
678 #ifndef CAPSTONE_DIET
679 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
680 #endif
681 },
682 {
683 Mips_AVER_U_D, MIPS_INS_AVER_U,
684 #ifndef CAPSTONE_DIET
685 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
686 #endif
687 },
688 {
689 Mips_AVER_U_H, MIPS_INS_AVER_U,
690 #ifndef CAPSTONE_DIET
691 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
692 #endif
693 },
694 {
695 Mips_AVER_U_W, MIPS_INS_AVER_U,
696 #ifndef CAPSTONE_DIET
697 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
698 #endif
699 },
700 {
701 Mips_AVE_S_B, MIPS_INS_AVE_S,
702 #ifndef CAPSTONE_DIET
703 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
704 #endif
705 },
706 {
707 Mips_AVE_S_D, MIPS_INS_AVE_S,
708 #ifndef CAPSTONE_DIET
709 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
710 #endif
711 },
712 {
713 Mips_AVE_S_H, MIPS_INS_AVE_S,
714 #ifndef CAPSTONE_DIET
715 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
716 #endif
717 },
718 {
719 Mips_AVE_S_W, MIPS_INS_AVE_S,
720 #ifndef CAPSTONE_DIET
721 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
722 #endif
723 },
724 {
725 Mips_AVE_U_B, MIPS_INS_AVE_U,
726 #ifndef CAPSTONE_DIET
727 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
728 #endif
729 },
730 {
731 Mips_AVE_U_D, MIPS_INS_AVE_U,
732 #ifndef CAPSTONE_DIET
733 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
734 #endif
735 },
736 {
737 Mips_AVE_U_H, MIPS_INS_AVE_U,
738 #ifndef CAPSTONE_DIET
739 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
740 #endif
741 },
742 {
743 Mips_AVE_U_W, MIPS_INS_AVE_U,
744 #ifndef CAPSTONE_DIET
745 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
746 #endif
747 },
748 {
749 Mips_AddiuRxImmX16, MIPS_INS_ADDIU,
750 #ifndef CAPSTONE_DIET
751 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
752 #endif
753 },
754 {
755 Mips_AddiuRxPcImmX16, MIPS_INS_ADDIU,
756 #ifndef CAPSTONE_DIET
757 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
758 #endif
759 },
760 {
761 Mips_AddiuRxRxImm16, MIPS_INS_ADDIU,
762 #ifndef CAPSTONE_DIET
763 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
764 #endif
765 },
766 {
767 Mips_AddiuRxRxImmX16, MIPS_INS_ADDIU,
768 #ifndef CAPSTONE_DIET
769 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
770 #endif
771 },
772 {
773 Mips_AddiuRxRyOffMemX16, MIPS_INS_ADDIU,
774 #ifndef CAPSTONE_DIET
775 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
776 #endif
777 },
778 {
779 Mips_AddiuSpImm16, MIPS_INS_ADDIU,
780 #ifndef CAPSTONE_DIET
781 { MIPS_REG_SP, 0 }, { MIPS_REG_SP, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
782 #endif
783 },
784 {
785 Mips_AddiuSpImmX16, MIPS_INS_ADDIU,
786 #ifndef CAPSTONE_DIET
787 { MIPS_REG_SP, 0 }, { MIPS_REG_SP, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
788 #endif
789 },
790 {
791 Mips_AdduRxRyRz16, MIPS_INS_ADDU,
792 #ifndef CAPSTONE_DIET
793 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
794 #endif
795 },
796 {
797 Mips_AndRxRxRy16, MIPS_INS_AND,
798 #ifndef CAPSTONE_DIET
799 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
800 #endif
801 },
802 {
803 Mips_BADDu, MIPS_INS_BADDU,
804 #ifndef CAPSTONE_DIET
805 { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
806 #endif
807 },
808 {
809 Mips_BAL, MIPS_INS_BAL,
810 #ifndef CAPSTONE_DIET
811 { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
812 #endif
813 },
814 {
815 Mips_BALC, MIPS_INS_BALC,
816 #ifndef CAPSTONE_DIET
817 { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
818 #endif
819 },
820 {
821 Mips_BALIGN, MIPS_INS_BALIGN,
822 #ifndef CAPSTONE_DIET
823 { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
824 #endif
825 },
826 {
827 Mips_BC, MIPS_INS_BC,
828 #ifndef CAPSTONE_DIET
829 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
830 #endif
831 },
832 {
833 Mips_BC0F, MIPS_INS_BC0F,
834 #ifndef CAPSTONE_DIET
835 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
836 #endif
837 },
838 {
839 Mips_BC0FL, MIPS_INS_BC0FL,
840 #ifndef CAPSTONE_DIET
841 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
842 #endif
843 },
844 {
845 Mips_BC0T, MIPS_INS_BC0T,
846 #ifndef CAPSTONE_DIET
847 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
848 #endif
849 },
850 {
851 Mips_BC0TL, MIPS_INS_BC0TL,
852 #ifndef CAPSTONE_DIET
853 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
854 #endif
855 },
856 {
857 Mips_BC1EQZ, MIPS_INS_BC1EQZ,
858 #ifndef CAPSTONE_DIET
859 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
860 #endif
861 },
862 {
863 Mips_BC1F, MIPS_INS_BC1F,
864 #ifndef CAPSTONE_DIET
865 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
866 #endif
867 },
868 {
869 Mips_BC1FL, MIPS_INS_BC1FL,
870 #ifndef CAPSTONE_DIET
871 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
872 #endif
873 },
874 {
875 Mips_BC1F_MM, MIPS_INS_BC1F,
876 #ifndef CAPSTONE_DIET
877 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
878 #endif
879 },
880 {
881 Mips_BC1NEZ, MIPS_INS_BC1NEZ,
882 #ifndef CAPSTONE_DIET
883 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
884 #endif
885 },
886 {
887 Mips_BC1T, MIPS_INS_BC1T,
888 #ifndef CAPSTONE_DIET
889 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
890 #endif
891 },
892 {
893 Mips_BC1TL, MIPS_INS_BC1TL,
894 #ifndef CAPSTONE_DIET
895 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
896 #endif
897 },
898 {
899 Mips_BC1T_MM, MIPS_INS_BC1T,
900 #ifndef CAPSTONE_DIET
901 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
902 #endif
903 },
904 {
905 Mips_BC2EQZ, MIPS_INS_BC2EQZ,
906 #ifndef CAPSTONE_DIET
907 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
908 #endif
909 },
910 {
911 Mips_BC2F, MIPS_INS_BC2F,
912 #ifndef CAPSTONE_DIET
913 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
914 #endif
915 },
916 {
917 Mips_BC2FL, MIPS_INS_BC2FL,
918 #ifndef CAPSTONE_DIET
919 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
920 #endif
921 },
922 {
923 Mips_BC2NEZ, MIPS_INS_BC2NEZ,
924 #ifndef CAPSTONE_DIET
925 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
926 #endif
927 },
928 {
929 Mips_BC2T, MIPS_INS_BC2T,
930 #ifndef CAPSTONE_DIET
931 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
932 #endif
933 },
934 {
935 Mips_BC2TL, MIPS_INS_BC2TL,
936 #ifndef CAPSTONE_DIET
937 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
938 #endif
939 },
940 {
941 Mips_BC3F, MIPS_INS_BC3F,
942 #ifndef CAPSTONE_DIET
943 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
944 #endif
945 },
946 {
947 Mips_BC3FL, MIPS_INS_BC3FL,
948 #ifndef CAPSTONE_DIET
949 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
950 #endif
951 },
952 {
953 Mips_BC3T, MIPS_INS_BC3T,
954 #ifndef CAPSTONE_DIET
955 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
956 #endif
957 },
958 {
959 Mips_BC3TL, MIPS_INS_BC3TL,
960 #ifndef CAPSTONE_DIET
961 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
962 #endif
963 },
964 {
965 Mips_BCLRI_B, MIPS_INS_BCLRI,
966 #ifndef CAPSTONE_DIET
967 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
968 #endif
969 },
970 {
971 Mips_BCLRI_D, MIPS_INS_BCLRI,
972 #ifndef CAPSTONE_DIET
973 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
974 #endif
975 },
976 {
977 Mips_BCLRI_H, MIPS_INS_BCLRI,
978 #ifndef CAPSTONE_DIET
979 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
980 #endif
981 },
982 {
983 Mips_BCLRI_W, MIPS_INS_BCLRI,
984 #ifndef CAPSTONE_DIET
985 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
986 #endif
987 },
988 {
989 Mips_BCLR_B, MIPS_INS_BCLR,
990 #ifndef CAPSTONE_DIET
991 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
992 #endif
993 },
994 {
995 Mips_BCLR_D, MIPS_INS_BCLR,
996 #ifndef CAPSTONE_DIET
997 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
998 #endif
999 },
1000 {
1001 Mips_BCLR_H, MIPS_INS_BCLR,
1002 #ifndef CAPSTONE_DIET
1003 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1004 #endif
1005 },
1006 {
1007 Mips_BCLR_W, MIPS_INS_BCLR,
1008 #ifndef CAPSTONE_DIET
1009 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1010 #endif
1011 },
1012 {
1013 Mips_BEQ, MIPS_INS_BEQ,
1014 #ifndef CAPSTONE_DIET
1015 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
1016 #endif
1017 },
1018 {
1019 Mips_BEQ64, MIPS_INS_BEQ,
1020 #ifndef CAPSTONE_DIET
1021 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
1022 #endif
1023 },
1024 {
1025 Mips_BEQC, MIPS_INS_BEQC,
1026 #ifndef CAPSTONE_DIET
1027 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1028 #endif
1029 },
1030 {
1031 Mips_BEQL, MIPS_INS_BEQL,
1032 #ifndef CAPSTONE_DIET
1033 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
1034 #endif
1035 },
1036 {
1037 Mips_BEQZALC, MIPS_INS_BEQZALC,
1038 #ifndef CAPSTONE_DIET
1039 { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1040 #endif
1041 },
1042 {
1043 Mips_BEQZC, MIPS_INS_BEQZC,
1044 #ifndef CAPSTONE_DIET
1045 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1046 #endif
1047 },
1048 {
1049 Mips_BEQZC_MM, MIPS_INS_BEQZC,
1050 #ifndef CAPSTONE_DIET
1051 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
1052 #endif
1053 },
1054 {
1055 Mips_BEQ_MM, MIPS_INS_BEQ,
1056 #ifndef CAPSTONE_DIET
1057 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
1058 #endif
1059 },
1060 {
1061 Mips_BGEC, MIPS_INS_BGEC,
1062 #ifndef CAPSTONE_DIET
1063 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1064 #endif
1065 },
1066 {
1067 Mips_BGEUC, MIPS_INS_BGEUC,
1068 #ifndef CAPSTONE_DIET
1069 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1070 #endif
1071 },
1072 {
1073 Mips_BGEZ, MIPS_INS_BGEZ,
1074 #ifndef CAPSTONE_DIET
1075 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
1076 #endif
1077 },
1078 {
1079 Mips_BGEZ64, MIPS_INS_BGEZ,
1080 #ifndef CAPSTONE_DIET
1081 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
1082 #endif
1083 },
1084 {
1085 Mips_BGEZAL, MIPS_INS_BGEZAL,
1086 #ifndef CAPSTONE_DIET
1087 { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
1088 #endif
1089 },
1090 {
1091 Mips_BGEZALC, MIPS_INS_BGEZALC,
1092 #ifndef CAPSTONE_DIET
1093 { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1094 #endif
1095 },
1096 {
1097 Mips_BGEZALL, MIPS_INS_BGEZALL,
1098 #ifndef CAPSTONE_DIET
1099 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
1100 #endif
1101 },
1102 {
1103 Mips_BGEZALS_MM, MIPS_INS_BGEZALS,
1104 #ifndef CAPSTONE_DIET
1105 { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
1106 #endif
1107 },
1108 {
1109 Mips_BGEZAL_MM, MIPS_INS_BGEZAL,
1110 #ifndef CAPSTONE_DIET
1111 { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
1112 #endif
1113 },
1114 {
1115 Mips_BGEZC, MIPS_INS_BGEZC,
1116 #ifndef CAPSTONE_DIET
1117 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1118 #endif
1119 },
1120 {
1121 Mips_BGEZL, MIPS_INS_BGEZL,
1122 #ifndef CAPSTONE_DIET
1123 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
1124 #endif
1125 },
1126 {
1127 Mips_BGEZ_MM, MIPS_INS_BGEZ,
1128 #ifndef CAPSTONE_DIET
1129 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
1130 #endif
1131 },
1132 {
1133 Mips_BGTZ, MIPS_INS_BGTZ,
1134 #ifndef CAPSTONE_DIET
1135 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
1136 #endif
1137 },
1138 {
1139 Mips_BGTZ64, MIPS_INS_BGTZ,
1140 #ifndef CAPSTONE_DIET
1141 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
1142 #endif
1143 },
1144 {
1145 Mips_BGTZALC, MIPS_INS_BGTZALC,
1146 #ifndef CAPSTONE_DIET
1147 { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1148 #endif
1149 },
1150 {
1151 Mips_BGTZC, MIPS_INS_BGTZC,
1152 #ifndef CAPSTONE_DIET
1153 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1154 #endif
1155 },
1156 {
1157 Mips_BGTZL, MIPS_INS_BGTZL,
1158 #ifndef CAPSTONE_DIET
1159 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
1160 #endif
1161 },
1162 {
1163 Mips_BGTZ_MM, MIPS_INS_BGTZ,
1164 #ifndef CAPSTONE_DIET
1165 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
1166 #endif
1167 },
1168 {
1169 Mips_BINSLI_B, MIPS_INS_BINSLI,
1170 #ifndef CAPSTONE_DIET
1171 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1172 #endif
1173 },
1174 {
1175 Mips_BINSLI_D, MIPS_INS_BINSLI,
1176 #ifndef CAPSTONE_DIET
1177 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1178 #endif
1179 },
1180 {
1181 Mips_BINSLI_H, MIPS_INS_BINSLI,
1182 #ifndef CAPSTONE_DIET
1183 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1184 #endif
1185 },
1186 {
1187 Mips_BINSLI_W, MIPS_INS_BINSLI,
1188 #ifndef CAPSTONE_DIET
1189 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1190 #endif
1191 },
1192 {
1193 Mips_BINSL_B, MIPS_INS_BINSL,
1194 #ifndef CAPSTONE_DIET
1195 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1196 #endif
1197 },
1198 {
1199 Mips_BINSL_D, MIPS_INS_BINSL,
1200 #ifndef CAPSTONE_DIET
1201 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1202 #endif
1203 },
1204 {
1205 Mips_BINSL_H, MIPS_INS_BINSL,
1206 #ifndef CAPSTONE_DIET
1207 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1208 #endif
1209 },
1210 {
1211 Mips_BINSL_W, MIPS_INS_BINSL,
1212 #ifndef CAPSTONE_DIET
1213 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1214 #endif
1215 },
1216 {
1217 Mips_BINSRI_B, MIPS_INS_BINSRI,
1218 #ifndef CAPSTONE_DIET
1219 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1220 #endif
1221 },
1222 {
1223 Mips_BINSRI_D, MIPS_INS_BINSRI,
1224 #ifndef CAPSTONE_DIET
1225 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1226 #endif
1227 },
1228 {
1229 Mips_BINSRI_H, MIPS_INS_BINSRI,
1230 #ifndef CAPSTONE_DIET
1231 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1232 #endif
1233 },
1234 {
1235 Mips_BINSRI_W, MIPS_INS_BINSRI,
1236 #ifndef CAPSTONE_DIET
1237 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1238 #endif
1239 },
1240 {
1241 Mips_BINSR_B, MIPS_INS_BINSR,
1242 #ifndef CAPSTONE_DIET
1243 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1244 #endif
1245 },
1246 {
1247 Mips_BINSR_D, MIPS_INS_BINSR,
1248 #ifndef CAPSTONE_DIET
1249 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1250 #endif
1251 },
1252 {
1253 Mips_BINSR_H, MIPS_INS_BINSR,
1254 #ifndef CAPSTONE_DIET
1255 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1256 #endif
1257 },
1258 {
1259 Mips_BINSR_W, MIPS_INS_BINSR,
1260 #ifndef CAPSTONE_DIET
1261 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1262 #endif
1263 },
1264 {
1265 Mips_BITREV, MIPS_INS_BITREV,
1266 #ifndef CAPSTONE_DIET
1267 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
1268 #endif
1269 },
1270 {
1271 Mips_BITSWAP, MIPS_INS_BITSWAP,
1272 #ifndef CAPSTONE_DIET
1273 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
1274 #endif
1275 },
1276 {
1277 Mips_BLEZ, MIPS_INS_BLEZ,
1278 #ifndef CAPSTONE_DIET
1279 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
1280 #endif
1281 },
1282 {
1283 Mips_BLEZ64, MIPS_INS_BLEZ,
1284 #ifndef CAPSTONE_DIET
1285 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
1286 #endif
1287 },
1288 {
1289 Mips_BLEZALC, MIPS_INS_BLEZALC,
1290 #ifndef CAPSTONE_DIET
1291 { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1292 #endif
1293 },
1294 {
1295 Mips_BLEZC, MIPS_INS_BLEZC,
1296 #ifndef CAPSTONE_DIET
1297 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1298 #endif
1299 },
1300 {
1301 Mips_BLEZL, MIPS_INS_BLEZL,
1302 #ifndef CAPSTONE_DIET
1303 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
1304 #endif
1305 },
1306 {
1307 Mips_BLEZ_MM, MIPS_INS_BLEZ,
1308 #ifndef CAPSTONE_DIET
1309 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
1310 #endif
1311 },
1312 {
1313 Mips_BLTC, MIPS_INS_BLTC,
1314 #ifndef CAPSTONE_DIET
1315 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1316 #endif
1317 },
1318 {
1319 Mips_BLTUC, MIPS_INS_BLTUC,
1320 #ifndef CAPSTONE_DIET
1321 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1322 #endif
1323 },
1324 {
1325 Mips_BLTZ, MIPS_INS_BLTZ,
1326 #ifndef CAPSTONE_DIET
1327 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
1328 #endif
1329 },
1330 {
1331 Mips_BLTZ64, MIPS_INS_BLTZ,
1332 #ifndef CAPSTONE_DIET
1333 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
1334 #endif
1335 },
1336 {
1337 Mips_BLTZAL, MIPS_INS_BLTZAL,
1338 #ifndef CAPSTONE_DIET
1339 { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
1340 #endif
1341 },
1342 {
1343 Mips_BLTZALC, MIPS_INS_BLTZALC,
1344 #ifndef CAPSTONE_DIET
1345 { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1346 #endif
1347 },
1348 {
1349 Mips_BLTZALL, MIPS_INS_BLTZALL,
1350 #ifndef CAPSTONE_DIET
1351 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
1352 #endif
1353 },
1354 {
1355 Mips_BLTZALS_MM, MIPS_INS_BLTZALS,
1356 #ifndef CAPSTONE_DIET
1357 { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
1358 #endif
1359 },
1360 {
1361 Mips_BLTZAL_MM, MIPS_INS_BLTZAL,
1362 #ifndef CAPSTONE_DIET
1363 { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
1364 #endif
1365 },
1366 {
1367 Mips_BLTZC, MIPS_INS_BLTZC,
1368 #ifndef CAPSTONE_DIET
1369 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1370 #endif
1371 },
1372 {
1373 Mips_BLTZL, MIPS_INS_BLTZL,
1374 #ifndef CAPSTONE_DIET
1375 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
1376 #endif
1377 },
1378 {
1379 Mips_BLTZ_MM, MIPS_INS_BLTZ,
1380 #ifndef CAPSTONE_DIET
1381 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
1382 #endif
1383 },
1384 {
1385 Mips_BMNZI_B, MIPS_INS_BMNZI,
1386 #ifndef CAPSTONE_DIET
1387 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1388 #endif
1389 },
1390 {
1391 Mips_BMNZ_V, MIPS_INS_BMNZ,
1392 #ifndef CAPSTONE_DIET
1393 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1394 #endif
1395 },
1396 {
1397 Mips_BMZI_B, MIPS_INS_BMZI,
1398 #ifndef CAPSTONE_DIET
1399 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1400 #endif
1401 },
1402 {
1403 Mips_BMZ_V, MIPS_INS_BMZ,
1404 #ifndef CAPSTONE_DIET
1405 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1406 #endif
1407 },
1408 {
1409 Mips_BNE, MIPS_INS_BNE,
1410 #ifndef CAPSTONE_DIET
1411 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
1412 #endif
1413 },
1414 {
1415 Mips_BNE64, MIPS_INS_BNE,
1416 #ifndef CAPSTONE_DIET
1417 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
1418 #endif
1419 },
1420 {
1421 Mips_BNEC, MIPS_INS_BNEC,
1422 #ifndef CAPSTONE_DIET
1423 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1424 #endif
1425 },
1426 {
1427 Mips_BNEGI_B, MIPS_INS_BNEGI,
1428 #ifndef CAPSTONE_DIET
1429 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1430 #endif
1431 },
1432 {
1433 Mips_BNEGI_D, MIPS_INS_BNEGI,
1434 #ifndef CAPSTONE_DIET
1435 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1436 #endif
1437 },
1438 {
1439 Mips_BNEGI_H, MIPS_INS_BNEGI,
1440 #ifndef CAPSTONE_DIET
1441 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1442 #endif
1443 },
1444 {
1445 Mips_BNEGI_W, MIPS_INS_BNEGI,
1446 #ifndef CAPSTONE_DIET
1447 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1448 #endif
1449 },
1450 {
1451 Mips_BNEG_B, MIPS_INS_BNEG,
1452 #ifndef CAPSTONE_DIET
1453 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1454 #endif
1455 },
1456 {
1457 Mips_BNEG_D, MIPS_INS_BNEG,
1458 #ifndef CAPSTONE_DIET
1459 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1460 #endif
1461 },
1462 {
1463 Mips_BNEG_H, MIPS_INS_BNEG,
1464 #ifndef CAPSTONE_DIET
1465 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1466 #endif
1467 },
1468 {
1469 Mips_BNEG_W, MIPS_INS_BNEG,
1470 #ifndef CAPSTONE_DIET
1471 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1472 #endif
1473 },
1474 {
1475 Mips_BNEL, MIPS_INS_BNEL,
1476 #ifndef CAPSTONE_DIET
1477 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
1478 #endif
1479 },
1480 {
1481 Mips_BNEZALC, MIPS_INS_BNEZALC,
1482 #ifndef CAPSTONE_DIET
1483 { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1484 #endif
1485 },
1486 {
1487 Mips_BNEZC, MIPS_INS_BNEZC,
1488 #ifndef CAPSTONE_DIET
1489 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1490 #endif
1491 },
1492 {
1493 Mips_BNEZC_MM, MIPS_INS_BNEZC,
1494 #ifndef CAPSTONE_DIET
1495 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
1496 #endif
1497 },
1498 {
1499 Mips_BNE_MM, MIPS_INS_BNE,
1500 #ifndef CAPSTONE_DIET
1501 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
1502 #endif
1503 },
1504 {
1505 Mips_BNVC, MIPS_INS_BNVC,
1506 #ifndef CAPSTONE_DIET
1507 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1508 #endif
1509 },
1510 {
1511 Mips_BNZ_B, MIPS_INS_BNZ,
1512 #ifndef CAPSTONE_DIET
1513 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
1514 #endif
1515 },
1516 {
1517 Mips_BNZ_D, MIPS_INS_BNZ,
1518 #ifndef CAPSTONE_DIET
1519 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
1520 #endif
1521 },
1522 {
1523 Mips_BNZ_H, MIPS_INS_BNZ,
1524 #ifndef CAPSTONE_DIET
1525 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
1526 #endif
1527 },
1528 {
1529 Mips_BNZ_V, MIPS_INS_BNZ,
1530 #ifndef CAPSTONE_DIET
1531 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
1532 #endif
1533 },
1534 {
1535 Mips_BNZ_W, MIPS_INS_BNZ,
1536 #ifndef CAPSTONE_DIET
1537 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
1538 #endif
1539 },
1540 {
1541 Mips_BOVC, MIPS_INS_BOVC,
1542 #ifndef CAPSTONE_DIET
1543 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1544 #endif
1545 },
1546 {
1547 Mips_BPOSGE32, MIPS_INS_BPOSGE32,
1548 #ifndef CAPSTONE_DIET
1549 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 1, 0
1550 #endif
1551 },
1552 {
1553 Mips_BREAK, MIPS_INS_BREAK,
1554 #ifndef CAPSTONE_DIET
1555 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
1556 #endif
1557 },
1558 {
1559 Mips_BREAK_MM, MIPS_INS_BREAK,
1560 #ifndef CAPSTONE_DIET
1561 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
1562 #endif
1563 },
1564 {
1565 Mips_BSELI_B, MIPS_INS_BSELI,
1566 #ifndef CAPSTONE_DIET
1567 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1568 #endif
1569 },
1570 {
1571 Mips_BSEL_V, MIPS_INS_BSEL,
1572 #ifndef CAPSTONE_DIET
1573 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1574 #endif
1575 },
1576 {
1577 Mips_BSETI_B, MIPS_INS_BSETI,
1578 #ifndef CAPSTONE_DIET
1579 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1580 #endif
1581 },
1582 {
1583 Mips_BSETI_D, MIPS_INS_BSETI,
1584 #ifndef CAPSTONE_DIET
1585 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1586 #endif
1587 },
1588 {
1589 Mips_BSETI_H, MIPS_INS_BSETI,
1590 #ifndef CAPSTONE_DIET
1591 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1592 #endif
1593 },
1594 {
1595 Mips_BSETI_W, MIPS_INS_BSETI,
1596 #ifndef CAPSTONE_DIET
1597 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1598 #endif
1599 },
1600 {
1601 Mips_BSET_B, MIPS_INS_BSET,
1602 #ifndef CAPSTONE_DIET
1603 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1604 #endif
1605 },
1606 {
1607 Mips_BSET_D, MIPS_INS_BSET,
1608 #ifndef CAPSTONE_DIET
1609 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1610 #endif
1611 },
1612 {
1613 Mips_BSET_H, MIPS_INS_BSET,
1614 #ifndef CAPSTONE_DIET
1615 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1616 #endif
1617 },
1618 {
1619 Mips_BSET_W, MIPS_INS_BSET,
1620 #ifndef CAPSTONE_DIET
1621 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1622 #endif
1623 },
1624 {
1625 Mips_BZ_B, MIPS_INS_BZ,
1626 #ifndef CAPSTONE_DIET
1627 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
1628 #endif
1629 },
1630 {
1631 Mips_BZ_D, MIPS_INS_BZ,
1632 #ifndef CAPSTONE_DIET
1633 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
1634 #endif
1635 },
1636 {
1637 Mips_BZ_H, MIPS_INS_BZ,
1638 #ifndef CAPSTONE_DIET
1639 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
1640 #endif
1641 },
1642 {
1643 Mips_BZ_V, MIPS_INS_BZ,
1644 #ifndef CAPSTONE_DIET
1645 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
1646 #endif
1647 },
1648 {
1649 Mips_BZ_W, MIPS_INS_BZ,
1650 #ifndef CAPSTONE_DIET
1651 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
1652 #endif
1653 },
1654 {
1655 Mips_BeqzRxImm16, MIPS_INS_BEQZ,
1656 #ifndef CAPSTONE_DIET
1657 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
1658 #endif
1659 },
1660 {
1661 Mips_BeqzRxImmX16, MIPS_INS_BEQZ,
1662 #ifndef CAPSTONE_DIET
1663 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
1664 #endif
1665 },
1666 {
1667 Mips_Bimm16, MIPS_INS_B,
1668 #ifndef CAPSTONE_DIET
1669 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
1670 #endif
1671 },
1672 {
1673 Mips_BimmX16, MIPS_INS_B,
1674 #ifndef CAPSTONE_DIET
1675 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
1676 #endif
1677 },
1678 {
1679 Mips_BnezRxImm16, MIPS_INS_BNEZ,
1680 #ifndef CAPSTONE_DIET
1681 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
1682 #endif
1683 },
1684 {
1685 Mips_BnezRxImmX16, MIPS_INS_BNEZ,
1686 #ifndef CAPSTONE_DIET
1687 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
1688 #endif
1689 },
1690 {
1691 Mips_Break16, MIPS_INS_BREAK,
1692 #ifndef CAPSTONE_DIET
1693 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
1694 #endif
1695 },
1696 {
1697 Mips_Bteqz16, MIPS_INS_BTEQZ,
1698 #ifndef CAPSTONE_DIET
1699 { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
1700 #endif
1701 },
1702 {
1703 Mips_BteqzX16, MIPS_INS_BTEQZ,
1704 #ifndef CAPSTONE_DIET
1705 { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
1706 #endif
1707 },
1708 {
1709 Mips_Btnez16, MIPS_INS_BTNEZ,
1710 #ifndef CAPSTONE_DIET
1711 { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
1712 #endif
1713 },
1714 {
1715 Mips_BtnezX16, MIPS_INS_BTNEZ,
1716 #ifndef CAPSTONE_DIET
1717 { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
1718 #endif
1719 },
1720 {
1721 Mips_CACHE, MIPS_INS_CACHE,
1722 #ifndef CAPSTONE_DIET
1723 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
1724 #endif
1725 },
1726 {
1727 Mips_CACHE_R6, MIPS_INS_CACHE,
1728 #ifndef CAPSTONE_DIET
1729 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
1730 #endif
1731 },
1732 {
1733 Mips_CEIL_L_D64, MIPS_INS_CEIL,
1734 #ifndef CAPSTONE_DIET
1735 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
1736 #endif
1737 },
1738 {
1739 Mips_CEIL_L_S, MIPS_INS_CEIL,
1740 #ifndef CAPSTONE_DIET
1741 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
1742 #endif
1743 },
1744 {
1745 Mips_CEIL_W_D32, MIPS_INS_CEIL,
1746 #ifndef CAPSTONE_DIET
1747 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
1748 #endif
1749 },
1750 {
1751 Mips_CEIL_W_D64, MIPS_INS_CEIL,
1752 #ifndef CAPSTONE_DIET
1753 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0
1754 #endif
1755 },
1756 {
1757 Mips_CEIL_W_MM, MIPS_INS_CEIL,
1758 #ifndef CAPSTONE_DIET
1759 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
1760 #endif
1761 },
1762 {
1763 Mips_CEIL_W_S, MIPS_INS_CEIL,
1764 #ifndef CAPSTONE_DIET
1765 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
1766 #endif
1767 },
1768 {
1769 Mips_CEIL_W_S_MM, MIPS_INS_CEIL,
1770 #ifndef CAPSTONE_DIET
1771 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
1772 #endif
1773 },
1774 {
1775 Mips_CEQI_B, MIPS_INS_CEQI,
1776 #ifndef CAPSTONE_DIET
1777 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1778 #endif
1779 },
1780 {
1781 Mips_CEQI_D, MIPS_INS_CEQI,
1782 #ifndef CAPSTONE_DIET
1783 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1784 #endif
1785 },
1786 {
1787 Mips_CEQI_H, MIPS_INS_CEQI,
1788 #ifndef CAPSTONE_DIET
1789 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1790 #endif
1791 },
1792 {
1793 Mips_CEQI_W, MIPS_INS_CEQI,
1794 #ifndef CAPSTONE_DIET
1795 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1796 #endif
1797 },
1798 {
1799 Mips_CEQ_B, MIPS_INS_CEQ,
1800 #ifndef CAPSTONE_DIET
1801 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1802 #endif
1803 },
1804 {
1805 Mips_CEQ_D, MIPS_INS_CEQ,
1806 #ifndef CAPSTONE_DIET
1807 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1808 #endif
1809 },
1810 {
1811 Mips_CEQ_H, MIPS_INS_CEQ,
1812 #ifndef CAPSTONE_DIET
1813 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1814 #endif
1815 },
1816 {
1817 Mips_CEQ_W, MIPS_INS_CEQ,
1818 #ifndef CAPSTONE_DIET
1819 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1820 #endif
1821 },
1822 {
1823 Mips_CFC1, MIPS_INS_CFC1,
1824 #ifndef CAPSTONE_DIET
1825 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
1826 #endif
1827 },
1828 {
1829 Mips_CFC1_MM, MIPS_INS_CFC1,
1830 #ifndef CAPSTONE_DIET
1831 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
1832 #endif
1833 },
1834 {
1835 Mips_CFCMSA, MIPS_INS_CFCMSA,
1836 #ifndef CAPSTONE_DIET
1837 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1838 #endif
1839 },
1840 {
1841 Mips_CINS, MIPS_INS_CINS,
1842 #ifndef CAPSTONE_DIET
1843 { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
1844 #endif
1845 },
1846 {
1847 Mips_CINS32, MIPS_INS_CINS32,
1848 #ifndef CAPSTONE_DIET
1849 { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
1850 #endif
1851 },
1852 {
1853 Mips_CLASS_D, MIPS_INS_CLASS,
1854 #ifndef CAPSTONE_DIET
1855 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
1856 #endif
1857 },
1858 {
1859 Mips_CLASS_S, MIPS_INS_CLASS,
1860 #ifndef CAPSTONE_DIET
1861 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
1862 #endif
1863 },
1864 {
1865 Mips_CLEI_S_B, MIPS_INS_CLEI_S,
1866 #ifndef CAPSTONE_DIET
1867 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1868 #endif
1869 },
1870 {
1871 Mips_CLEI_S_D, MIPS_INS_CLEI_S,
1872 #ifndef CAPSTONE_DIET
1873 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1874 #endif
1875 },
1876 {
1877 Mips_CLEI_S_H, MIPS_INS_CLEI_S,
1878 #ifndef CAPSTONE_DIET
1879 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1880 #endif
1881 },
1882 {
1883 Mips_CLEI_S_W, MIPS_INS_CLEI_S,
1884 #ifndef CAPSTONE_DIET
1885 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1886 #endif
1887 },
1888 {
1889 Mips_CLEI_U_B, MIPS_INS_CLEI_U,
1890 #ifndef CAPSTONE_DIET
1891 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1892 #endif
1893 },
1894 {
1895 Mips_CLEI_U_D, MIPS_INS_CLEI_U,
1896 #ifndef CAPSTONE_DIET
1897 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1898 #endif
1899 },
1900 {
1901 Mips_CLEI_U_H, MIPS_INS_CLEI_U,
1902 #ifndef CAPSTONE_DIET
1903 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1904 #endif
1905 },
1906 {
1907 Mips_CLEI_U_W, MIPS_INS_CLEI_U,
1908 #ifndef CAPSTONE_DIET
1909 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1910 #endif
1911 },
1912 {
1913 Mips_CLE_S_B, MIPS_INS_CLE_S,
1914 #ifndef CAPSTONE_DIET
1915 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1916 #endif
1917 },
1918 {
1919 Mips_CLE_S_D, MIPS_INS_CLE_S,
1920 #ifndef CAPSTONE_DIET
1921 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1922 #endif
1923 },
1924 {
1925 Mips_CLE_S_H, MIPS_INS_CLE_S,
1926 #ifndef CAPSTONE_DIET
1927 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1928 #endif
1929 },
1930 {
1931 Mips_CLE_S_W, MIPS_INS_CLE_S,
1932 #ifndef CAPSTONE_DIET
1933 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1934 #endif
1935 },
1936 {
1937 Mips_CLE_U_B, MIPS_INS_CLE_U,
1938 #ifndef CAPSTONE_DIET
1939 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1940 #endif
1941 },
1942 {
1943 Mips_CLE_U_D, MIPS_INS_CLE_U,
1944 #ifndef CAPSTONE_DIET
1945 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1946 #endif
1947 },
1948 {
1949 Mips_CLE_U_H, MIPS_INS_CLE_U,
1950 #ifndef CAPSTONE_DIET
1951 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1952 #endif
1953 },
1954 {
1955 Mips_CLE_U_W, MIPS_INS_CLE_U,
1956 #ifndef CAPSTONE_DIET
1957 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1958 #endif
1959 },
1960 {
1961 Mips_CLO, MIPS_INS_CLO,
1962 #ifndef CAPSTONE_DIET
1963 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
1964 #endif
1965 },
1966 {
1967 Mips_CLO_MM, MIPS_INS_CLO,
1968 #ifndef CAPSTONE_DIET
1969 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
1970 #endif
1971 },
1972 {
1973 Mips_CLO_R6, MIPS_INS_CLO,
1974 #ifndef CAPSTONE_DIET
1975 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
1976 #endif
1977 },
1978 {
1979 Mips_CLTI_S_B, MIPS_INS_CLTI_S,
1980 #ifndef CAPSTONE_DIET
1981 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1982 #endif
1983 },
1984 {
1985 Mips_CLTI_S_D, MIPS_INS_CLTI_S,
1986 #ifndef CAPSTONE_DIET
1987 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1988 #endif
1989 },
1990 {
1991 Mips_CLTI_S_H, MIPS_INS_CLTI_S,
1992 #ifndef CAPSTONE_DIET
1993 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1994 #endif
1995 },
1996 {
1997 Mips_CLTI_S_W, MIPS_INS_CLTI_S,
1998 #ifndef CAPSTONE_DIET
1999 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2000 #endif
2001 },
2002 {
2003 Mips_CLTI_U_B, MIPS_INS_CLTI_U,
2004 #ifndef CAPSTONE_DIET
2005 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2006 #endif
2007 },
2008 {
2009 Mips_CLTI_U_D, MIPS_INS_CLTI_U,
2010 #ifndef CAPSTONE_DIET
2011 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2012 #endif
2013 },
2014 {
2015 Mips_CLTI_U_H, MIPS_INS_CLTI_U,
2016 #ifndef CAPSTONE_DIET
2017 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2018 #endif
2019 },
2020 {
2021 Mips_CLTI_U_W, MIPS_INS_CLTI_U,
2022 #ifndef CAPSTONE_DIET
2023 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2024 #endif
2025 },
2026 {
2027 Mips_CLT_S_B, MIPS_INS_CLT_S,
2028 #ifndef CAPSTONE_DIET
2029 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2030 #endif
2031 },
2032 {
2033 Mips_CLT_S_D, MIPS_INS_CLT_S,
2034 #ifndef CAPSTONE_DIET
2035 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2036 #endif
2037 },
2038 {
2039 Mips_CLT_S_H, MIPS_INS_CLT_S,
2040 #ifndef CAPSTONE_DIET
2041 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2042 #endif
2043 },
2044 {
2045 Mips_CLT_S_W, MIPS_INS_CLT_S,
2046 #ifndef CAPSTONE_DIET
2047 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2048 #endif
2049 },
2050 {
2051 Mips_CLT_U_B, MIPS_INS_CLT_U,
2052 #ifndef CAPSTONE_DIET
2053 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2054 #endif
2055 },
2056 {
2057 Mips_CLT_U_D, MIPS_INS_CLT_U,
2058 #ifndef CAPSTONE_DIET
2059 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2060 #endif
2061 },
2062 {
2063 Mips_CLT_U_H, MIPS_INS_CLT_U,
2064 #ifndef CAPSTONE_DIET
2065 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2066 #endif
2067 },
2068 {
2069 Mips_CLT_U_W, MIPS_INS_CLT_U,
2070 #ifndef CAPSTONE_DIET
2071 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2072 #endif
2073 },
2074 {
2075 Mips_CLZ, MIPS_INS_CLZ,
2076 #ifndef CAPSTONE_DIET
2077 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2078 #endif
2079 },
2080 {
2081 Mips_CLZ_MM, MIPS_INS_CLZ,
2082 #ifndef CAPSTONE_DIET
2083 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
2084 #endif
2085 },
2086 {
2087 Mips_CLZ_R6, MIPS_INS_CLZ,
2088 #ifndef CAPSTONE_DIET
2089 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2090 #endif
2091 },
2092 {
2093 Mips_CMPGDU_EQ_QB, MIPS_INS_CMPGDU,
2094 #ifndef CAPSTONE_DIET
2095 { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
2096 #endif
2097 },
2098 {
2099 Mips_CMPGDU_LE_QB, MIPS_INS_CMPGDU,
2100 #ifndef CAPSTONE_DIET
2101 { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
2102 #endif
2103 },
2104 {
2105 Mips_CMPGDU_LT_QB, MIPS_INS_CMPGDU,
2106 #ifndef CAPSTONE_DIET
2107 { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
2108 #endif
2109 },
2110 {
2111 Mips_CMPGU_EQ_QB, MIPS_INS_CMPGU,
2112 #ifndef CAPSTONE_DIET
2113 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
2114 #endif
2115 },
2116 {
2117 Mips_CMPGU_LE_QB, MIPS_INS_CMPGU,
2118 #ifndef CAPSTONE_DIET
2119 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
2120 #endif
2121 },
2122 {
2123 Mips_CMPGU_LT_QB, MIPS_INS_CMPGU,
2124 #ifndef CAPSTONE_DIET
2125 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
2126 #endif
2127 },
2128 {
2129 Mips_CMPU_EQ_QB, MIPS_INS_CMPU,
2130 #ifndef CAPSTONE_DIET
2131 { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
2132 #endif
2133 },
2134 {
2135 Mips_CMPU_LE_QB, MIPS_INS_CMPU,
2136 #ifndef CAPSTONE_DIET
2137 { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
2138 #endif
2139 },
2140 {
2141 Mips_CMPU_LT_QB, MIPS_INS_CMPU,
2142 #ifndef CAPSTONE_DIET
2143 { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
2144 #endif
2145 },
2146 {
2147 Mips_CMP_EQ_D, MIPS_INS_CMP,
2148 #ifndef CAPSTONE_DIET
2149 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2150 #endif
2151 },
2152 {
2153 Mips_CMP_EQ_PH, MIPS_INS_CMP,
2154 #ifndef CAPSTONE_DIET
2155 { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
2156 #endif
2157 },
2158 {
2159 Mips_CMP_EQ_S, MIPS_INS_CMP,
2160 #ifndef CAPSTONE_DIET
2161 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2162 #endif
2163 },
2164 {
2165 Mips_CMP_F_D, MIPS_INS_CMP,
2166 #ifndef CAPSTONE_DIET
2167 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2168 #endif
2169 },
2170 {
2171 Mips_CMP_F_S, MIPS_INS_CMP,
2172 #ifndef CAPSTONE_DIET
2173 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2174 #endif
2175 },
2176 {
2177 Mips_CMP_LE_D, MIPS_INS_CMP,
2178 #ifndef CAPSTONE_DIET
2179 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2180 #endif
2181 },
2182 {
2183 Mips_CMP_LE_PH, MIPS_INS_CMP,
2184 #ifndef CAPSTONE_DIET
2185 { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
2186 #endif
2187 },
2188 {
2189 Mips_CMP_LE_S, MIPS_INS_CMP,
2190 #ifndef CAPSTONE_DIET
2191 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2192 #endif
2193 },
2194 {
2195 Mips_CMP_LT_D, MIPS_INS_CMP,
2196 #ifndef CAPSTONE_DIET
2197 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2198 #endif
2199 },
2200 {
2201 Mips_CMP_LT_PH, MIPS_INS_CMP,
2202 #ifndef CAPSTONE_DIET
2203 { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
2204 #endif
2205 },
2206 {
2207 Mips_CMP_LT_S, MIPS_INS_CMP,
2208 #ifndef CAPSTONE_DIET
2209 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2210 #endif
2211 },
2212 {
2213 Mips_CMP_SAF_D, MIPS_INS_CMP,
2214 #ifndef CAPSTONE_DIET
2215 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2216 #endif
2217 },
2218 {
2219 Mips_CMP_SAF_S, MIPS_INS_CMP,
2220 #ifndef CAPSTONE_DIET
2221 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2222 #endif
2223 },
2224 {
2225 Mips_CMP_SEQ_D, MIPS_INS_CMP,
2226 #ifndef CAPSTONE_DIET
2227 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2228 #endif
2229 },
2230 {
2231 Mips_CMP_SEQ_S, MIPS_INS_CMP,
2232 #ifndef CAPSTONE_DIET
2233 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2234 #endif
2235 },
2236 {
2237 Mips_CMP_SLE_D, MIPS_INS_CMP,
2238 #ifndef CAPSTONE_DIET
2239 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2240 #endif
2241 },
2242 {
2243 Mips_CMP_SLE_S, MIPS_INS_CMP,
2244 #ifndef CAPSTONE_DIET
2245 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2246 #endif
2247 },
2248 {
2249 Mips_CMP_SLT_D, MIPS_INS_CMP,
2250 #ifndef CAPSTONE_DIET
2251 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2252 #endif
2253 },
2254 {
2255 Mips_CMP_SLT_S, MIPS_INS_CMP,
2256 #ifndef CAPSTONE_DIET
2257 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2258 #endif
2259 },
2260 {
2261 Mips_CMP_SUEQ_D, MIPS_INS_CMP,
2262 #ifndef CAPSTONE_DIET
2263 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2264 #endif
2265 },
2266 {
2267 Mips_CMP_SUEQ_S, MIPS_INS_CMP,
2268 #ifndef CAPSTONE_DIET
2269 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2270 #endif
2271 },
2272 {
2273 Mips_CMP_SULE_D, MIPS_INS_CMP,
2274 #ifndef CAPSTONE_DIET
2275 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2276 #endif
2277 },
2278 {
2279 Mips_CMP_SULE_S, MIPS_INS_CMP,
2280 #ifndef CAPSTONE_DIET
2281 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2282 #endif
2283 },
2284 {
2285 Mips_CMP_SULT_D, MIPS_INS_CMP,
2286 #ifndef CAPSTONE_DIET
2287 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2288 #endif
2289 },
2290 {
2291 Mips_CMP_SULT_S, MIPS_INS_CMP,
2292 #ifndef CAPSTONE_DIET
2293 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2294 #endif
2295 },
2296 {
2297 Mips_CMP_SUN_D, MIPS_INS_CMP,
2298 #ifndef CAPSTONE_DIET
2299 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2300 #endif
2301 },
2302 {
2303 Mips_CMP_SUN_S, MIPS_INS_CMP,
2304 #ifndef CAPSTONE_DIET
2305 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2306 #endif
2307 },
2308 {
2309 Mips_CMP_UEQ_D, MIPS_INS_CMP,
2310 #ifndef CAPSTONE_DIET
2311 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2312 #endif
2313 },
2314 {
2315 Mips_CMP_UEQ_S, MIPS_INS_CMP,
2316 #ifndef CAPSTONE_DIET
2317 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2318 #endif
2319 },
2320 {
2321 Mips_CMP_ULE_D, MIPS_INS_CMP,
2322 #ifndef CAPSTONE_DIET
2323 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2324 #endif
2325 },
2326 {
2327 Mips_CMP_ULE_S, MIPS_INS_CMP,
2328 #ifndef CAPSTONE_DIET
2329 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2330 #endif
2331 },
2332 {
2333 Mips_CMP_ULT_D, MIPS_INS_CMP,
2334 #ifndef CAPSTONE_DIET
2335 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2336 #endif
2337 },
2338 {
2339 Mips_CMP_ULT_S, MIPS_INS_CMP,
2340 #ifndef CAPSTONE_DIET
2341 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2342 #endif
2343 },
2344 {
2345 Mips_CMP_UN_D, MIPS_INS_CMP,
2346 #ifndef CAPSTONE_DIET
2347 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2348 #endif
2349 },
2350 {
2351 Mips_CMP_UN_S, MIPS_INS_CMP,
2352 #ifndef CAPSTONE_DIET
2353 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2354 #endif
2355 },
2356 {
2357 Mips_COPY_S_B, MIPS_INS_COPY_S,
2358 #ifndef CAPSTONE_DIET
2359 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2360 #endif
2361 },
2362 {
2363 Mips_COPY_S_D, MIPS_INS_COPY_S,
2364 #ifndef CAPSTONE_DIET
2365 { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0
2366 #endif
2367 },
2368 {
2369 Mips_COPY_S_H, MIPS_INS_COPY_S,
2370 #ifndef CAPSTONE_DIET
2371 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2372 #endif
2373 },
2374 {
2375 Mips_COPY_S_W, MIPS_INS_COPY_S,
2376 #ifndef CAPSTONE_DIET
2377 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2378 #endif
2379 },
2380 {
2381 Mips_COPY_U_B, MIPS_INS_COPY_U,
2382 #ifndef CAPSTONE_DIET
2383 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2384 #endif
2385 },
2386 {
2387 Mips_COPY_U_D, MIPS_INS_COPY_U,
2388 #ifndef CAPSTONE_DIET
2389 { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0
2390 #endif
2391 },
2392 {
2393 Mips_COPY_U_H, MIPS_INS_COPY_U,
2394 #ifndef CAPSTONE_DIET
2395 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2396 #endif
2397 },
2398 {
2399 Mips_COPY_U_W, MIPS_INS_COPY_U,
2400 #ifndef CAPSTONE_DIET
2401 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2402 #endif
2403 },
2404 {
2405 Mips_CTC1, MIPS_INS_CTC1,
2406 #ifndef CAPSTONE_DIET
2407 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
2408 #endif
2409 },
2410 {
2411 Mips_CTC1_MM, MIPS_INS_CTC1,
2412 #ifndef CAPSTONE_DIET
2413 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
2414 #endif
2415 },
2416 {
2417 Mips_CTCMSA, MIPS_INS_CTCMSA,
2418 #ifndef CAPSTONE_DIET
2419 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2420 #endif
2421 },
2422 {
2423 Mips_CVT_D32_S, MIPS_INS_CVT,
2424 #ifndef CAPSTONE_DIET
2425 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2426 #endif
2427 },
2428 {
2429 Mips_CVT_D32_W, MIPS_INS_CVT,
2430 #ifndef CAPSTONE_DIET
2431 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2432 #endif
2433 },
2434 {
2435 Mips_CVT_D32_W_MM, MIPS_INS_CVT,
2436 #ifndef CAPSTONE_DIET
2437 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
2438 #endif
2439 },
2440 {
2441 Mips_CVT_D64_L, MIPS_INS_CVT,
2442 #ifndef CAPSTONE_DIET
2443 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
2444 #endif
2445 },
2446 {
2447 Mips_CVT_D64_S, MIPS_INS_CVT,
2448 #ifndef CAPSTONE_DIET
2449 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
2450 #endif
2451 },
2452 {
2453 Mips_CVT_D64_W, MIPS_INS_CVT,
2454 #ifndef CAPSTONE_DIET
2455 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
2456 #endif
2457 },
2458 {
2459 Mips_CVT_D_S_MM, MIPS_INS_CVT,
2460 #ifndef CAPSTONE_DIET
2461 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
2462 #endif
2463 },
2464 {
2465 Mips_CVT_L_D64, MIPS_INS_CVT,
2466 #ifndef CAPSTONE_DIET
2467 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32R2, 0 }, 0, 0
2468 #endif
2469 },
2470 {
2471 Mips_CVT_L_D64_MM, MIPS_INS_CVT,
2472 #ifndef CAPSTONE_DIET
2473 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
2474 #endif
2475 },
2476 {
2477 Mips_CVT_L_S, MIPS_INS_CVT,
2478 #ifndef CAPSTONE_DIET
2479 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32R2, 0 }, 0, 0
2480 #endif
2481 },
2482 {
2483 Mips_CVT_L_S_MM, MIPS_INS_CVT,
2484 #ifndef CAPSTONE_DIET
2485 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
2486 #endif
2487 },
2488 {
2489 Mips_CVT_S_D32, MIPS_INS_CVT,
2490 #ifndef CAPSTONE_DIET
2491 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2492 #endif
2493 },
2494 {
2495 Mips_CVT_S_D32_MM, MIPS_INS_CVT,
2496 #ifndef CAPSTONE_DIET
2497 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
2498 #endif
2499 },
2500 {
2501 Mips_CVT_S_D64, MIPS_INS_CVT,
2502 #ifndef CAPSTONE_DIET
2503 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
2504 #endif
2505 },
2506 {
2507 Mips_CVT_S_L, MIPS_INS_CVT,
2508 #ifndef CAPSTONE_DIET
2509 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
2510 #endif
2511 },
2512 {
2513 Mips_CVT_S_W, MIPS_INS_CVT,
2514 #ifndef CAPSTONE_DIET
2515 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
2516 #endif
2517 },
2518 {
2519 Mips_CVT_S_W_MM, MIPS_INS_CVT,
2520 #ifndef CAPSTONE_DIET
2521 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
2522 #endif
2523 },
2524 {
2525 Mips_CVT_W_D32, MIPS_INS_CVT,
2526 #ifndef CAPSTONE_DIET
2527 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2528 #endif
2529 },
2530 {
2531 Mips_CVT_W_D64, MIPS_INS_CVT,
2532 #ifndef CAPSTONE_DIET
2533 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
2534 #endif
2535 },
2536 {
2537 Mips_CVT_W_MM, MIPS_INS_CVT,
2538 #ifndef CAPSTONE_DIET
2539 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
2540 #endif
2541 },
2542 {
2543 Mips_CVT_W_S, MIPS_INS_CVT,
2544 #ifndef CAPSTONE_DIET
2545 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
2546 #endif
2547 },
2548 {
2549 Mips_CVT_W_S_MM, MIPS_INS_CVT,
2550 #ifndef CAPSTONE_DIET
2551 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
2552 #endif
2553 },
2554 {
2555 Mips_C_EQ_D32, MIPS_INS_C,
2556 #ifndef CAPSTONE_DIET
2557 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2558 #endif
2559 },
2560 {
2561 Mips_C_EQ_D64, MIPS_INS_C,
2562 #ifndef CAPSTONE_DIET
2563 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2564 #endif
2565 },
2566 {
2567 Mips_C_EQ_S, MIPS_INS_C,
2568 #ifndef CAPSTONE_DIET
2569 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2570 #endif
2571 },
2572 {
2573 Mips_C_F_D32, MIPS_INS_C,
2574 #ifndef CAPSTONE_DIET
2575 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2576 #endif
2577 },
2578 {
2579 Mips_C_F_D64, MIPS_INS_C,
2580 #ifndef CAPSTONE_DIET
2581 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2582 #endif
2583 },
2584 {
2585 Mips_C_F_S, MIPS_INS_C,
2586 #ifndef CAPSTONE_DIET
2587 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2588 #endif
2589 },
2590 {
2591 Mips_C_LE_D32, MIPS_INS_C,
2592 #ifndef CAPSTONE_DIET
2593 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2594 #endif
2595 },
2596 {
2597 Mips_C_LE_D64, MIPS_INS_C,
2598 #ifndef CAPSTONE_DIET
2599 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2600 #endif
2601 },
2602 {
2603 Mips_C_LE_S, MIPS_INS_C,
2604 #ifndef CAPSTONE_DIET
2605 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2606 #endif
2607 },
2608 {
2609 Mips_C_LT_D32, MIPS_INS_C,
2610 #ifndef CAPSTONE_DIET
2611 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2612 #endif
2613 },
2614 {
2615 Mips_C_LT_D64, MIPS_INS_C,
2616 #ifndef CAPSTONE_DIET
2617 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2618 #endif
2619 },
2620 {
2621 Mips_C_LT_S, MIPS_INS_C,
2622 #ifndef CAPSTONE_DIET
2623 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2624 #endif
2625 },
2626 {
2627 Mips_C_NGE_D32, MIPS_INS_C,
2628 #ifndef CAPSTONE_DIET
2629 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2630 #endif
2631 },
2632 {
2633 Mips_C_NGE_D64, MIPS_INS_C,
2634 #ifndef CAPSTONE_DIET
2635 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2636 #endif
2637 },
2638 {
2639 Mips_C_NGE_S, MIPS_INS_C,
2640 #ifndef CAPSTONE_DIET
2641 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2642 #endif
2643 },
2644 {
2645 Mips_C_NGLE_D32, MIPS_INS_C,
2646 #ifndef CAPSTONE_DIET
2647 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2648 #endif
2649 },
2650 {
2651 Mips_C_NGLE_D64, MIPS_INS_C,
2652 #ifndef CAPSTONE_DIET
2653 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2654 #endif
2655 },
2656 {
2657 Mips_C_NGLE_S, MIPS_INS_C,
2658 #ifndef CAPSTONE_DIET
2659 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2660 #endif
2661 },
2662 {
2663 Mips_C_NGL_D32, MIPS_INS_C,
2664 #ifndef CAPSTONE_DIET
2665 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2666 #endif
2667 },
2668 {
2669 Mips_C_NGL_D64, MIPS_INS_C,
2670 #ifndef CAPSTONE_DIET
2671 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2672 #endif
2673 },
2674 {
2675 Mips_C_NGL_S, MIPS_INS_C,
2676 #ifndef CAPSTONE_DIET
2677 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2678 #endif
2679 },
2680 {
2681 Mips_C_NGT_D32, MIPS_INS_C,
2682 #ifndef CAPSTONE_DIET
2683 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2684 #endif
2685 },
2686 {
2687 Mips_C_NGT_D64, MIPS_INS_C,
2688 #ifndef CAPSTONE_DIET
2689 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2690 #endif
2691 },
2692 {
2693 Mips_C_NGT_S, MIPS_INS_C,
2694 #ifndef CAPSTONE_DIET
2695 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2696 #endif
2697 },
2698 {
2699 Mips_C_OLE_D32, MIPS_INS_C,
2700 #ifndef CAPSTONE_DIET
2701 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2702 #endif
2703 },
2704 {
2705 Mips_C_OLE_D64, MIPS_INS_C,
2706 #ifndef CAPSTONE_DIET
2707 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2708 #endif
2709 },
2710 {
2711 Mips_C_OLE_S, MIPS_INS_C,
2712 #ifndef CAPSTONE_DIET
2713 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2714 #endif
2715 },
2716 {
2717 Mips_C_OLT_D32, MIPS_INS_C,
2718 #ifndef CAPSTONE_DIET
2719 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2720 #endif
2721 },
2722 {
2723 Mips_C_OLT_D64, MIPS_INS_C,
2724 #ifndef CAPSTONE_DIET
2725 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2726 #endif
2727 },
2728 {
2729 Mips_C_OLT_S, MIPS_INS_C,
2730 #ifndef CAPSTONE_DIET
2731 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2732 #endif
2733 },
2734 {
2735 Mips_C_SEQ_D32, MIPS_INS_C,
2736 #ifndef CAPSTONE_DIET
2737 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2738 #endif
2739 },
2740 {
2741 Mips_C_SEQ_D64, MIPS_INS_C,
2742 #ifndef CAPSTONE_DIET
2743 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2744 #endif
2745 },
2746 {
2747 Mips_C_SEQ_S, MIPS_INS_C,
2748 #ifndef CAPSTONE_DIET
2749 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2750 #endif
2751 },
2752 {
2753 Mips_C_SF_D32, MIPS_INS_C,
2754 #ifndef CAPSTONE_DIET
2755 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2756 #endif
2757 },
2758 {
2759 Mips_C_SF_D64, MIPS_INS_C,
2760 #ifndef CAPSTONE_DIET
2761 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2762 #endif
2763 },
2764 {
2765 Mips_C_SF_S, MIPS_INS_C,
2766 #ifndef CAPSTONE_DIET
2767 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2768 #endif
2769 },
2770 {
2771 Mips_C_UEQ_D32, MIPS_INS_C,
2772 #ifndef CAPSTONE_DIET
2773 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2774 #endif
2775 },
2776 {
2777 Mips_C_UEQ_D64, MIPS_INS_C,
2778 #ifndef CAPSTONE_DIET
2779 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2780 #endif
2781 },
2782 {
2783 Mips_C_UEQ_S, MIPS_INS_C,
2784 #ifndef CAPSTONE_DIET
2785 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2786 #endif
2787 },
2788 {
2789 Mips_C_ULE_D32, MIPS_INS_C,
2790 #ifndef CAPSTONE_DIET
2791 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2792 #endif
2793 },
2794 {
2795 Mips_C_ULE_D64, MIPS_INS_C,
2796 #ifndef CAPSTONE_DIET
2797 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2798 #endif
2799 },
2800 {
2801 Mips_C_ULE_S, MIPS_INS_C,
2802 #ifndef CAPSTONE_DIET
2803 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2804 #endif
2805 },
2806 {
2807 Mips_C_ULT_D32, MIPS_INS_C,
2808 #ifndef CAPSTONE_DIET
2809 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2810 #endif
2811 },
2812 {
2813 Mips_C_ULT_D64, MIPS_INS_C,
2814 #ifndef CAPSTONE_DIET
2815 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2816 #endif
2817 },
2818 {
2819 Mips_C_ULT_S, MIPS_INS_C,
2820 #ifndef CAPSTONE_DIET
2821 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2822 #endif
2823 },
2824 {
2825 Mips_C_UN_D32, MIPS_INS_C,
2826 #ifndef CAPSTONE_DIET
2827 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2828 #endif
2829 },
2830 {
2831 Mips_C_UN_D64, MIPS_INS_C,
2832 #ifndef CAPSTONE_DIET
2833 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2834 #endif
2835 },
2836 {
2837 Mips_C_UN_S, MIPS_INS_C,
2838 #ifndef CAPSTONE_DIET
2839 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2840 #endif
2841 },
2842 {
2843 Mips_CmpRxRy16, MIPS_INS_CMP,
2844 #ifndef CAPSTONE_DIET
2845 { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
2846 #endif
2847 },
2848 {
2849 Mips_CmpiRxImm16, MIPS_INS_CMPI,
2850 #ifndef CAPSTONE_DIET
2851 { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
2852 #endif
2853 },
2854 {
2855 Mips_CmpiRxImmX16, MIPS_INS_CMPI,
2856 #ifndef CAPSTONE_DIET
2857 { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
2858 #endif
2859 },
2860 {
2861 Mips_DADD, MIPS_INS_DADD,
2862 #ifndef CAPSTONE_DIET
2863 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
2864 #endif
2865 },
2866 {
2867 Mips_DADDi, MIPS_INS_DADDI,
2868 #ifndef CAPSTONE_DIET
2869 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2870 #endif
2871 },
2872 {
2873 Mips_DADDiu, MIPS_INS_DADDIU,
2874 #ifndef CAPSTONE_DIET
2875 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
2876 #endif
2877 },
2878 {
2879 Mips_DADDu, MIPS_INS_DADDU,
2880 #ifndef CAPSTONE_DIET
2881 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
2882 #endif
2883 },
2884 {
2885 Mips_DAHI, MIPS_INS_DAHI,
2886 #ifndef CAPSTONE_DIET
2887 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
2888 #endif
2889 },
2890 {
2891 Mips_DALIGN, MIPS_INS_DALIGN,
2892 #ifndef CAPSTONE_DIET
2893 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
2894 #endif
2895 },
2896 {
2897 Mips_DATI, MIPS_INS_DATI,
2898 #ifndef CAPSTONE_DIET
2899 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
2900 #endif
2901 },
2902 {
2903 Mips_DAUI, MIPS_INS_DAUI,
2904 #ifndef CAPSTONE_DIET
2905 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
2906 #endif
2907 },
2908 {
2909 Mips_DBITSWAP, MIPS_INS_DBITSWAP,
2910 #ifndef CAPSTONE_DIET
2911 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
2912 #endif
2913 },
2914 {
2915 Mips_DCLO, MIPS_INS_DCLO,
2916 #ifndef CAPSTONE_DIET
2917 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2918 #endif
2919 },
2920 {
2921 Mips_DCLO_R6, MIPS_INS_DCLO,
2922 #ifndef CAPSTONE_DIET
2923 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
2924 #endif
2925 },
2926 {
2927 Mips_DCLZ, MIPS_INS_DCLZ,
2928 #ifndef CAPSTONE_DIET
2929 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2930 #endif
2931 },
2932 {
2933 Mips_DCLZ_R6, MIPS_INS_DCLZ,
2934 #ifndef CAPSTONE_DIET
2935 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
2936 #endif
2937 },
2938 {
2939 Mips_DDIV, MIPS_INS_DDIV,
2940 #ifndef CAPSTONE_DIET
2941 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
2942 #endif
2943 },
2944 {
2945 Mips_DDIVU, MIPS_INS_DDIVU,
2946 #ifndef CAPSTONE_DIET
2947 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
2948 #endif
2949 },
2950 {
2951 Mips_DERET, MIPS_INS_DERET,
2952 #ifndef CAPSTONE_DIET
2953 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0
2954 #endif
2955 },
2956 {
2957 Mips_DERET_MM, MIPS_INS_DERET,
2958 #ifndef CAPSTONE_DIET
2959 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
2960 #endif
2961 },
2962 {
2963 Mips_DEXT, MIPS_INS_DEXT,
2964 #ifndef CAPSTONE_DIET
2965 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
2966 #endif
2967 },
2968 {
2969 Mips_DEXTM, MIPS_INS_DEXTM,
2970 #ifndef CAPSTONE_DIET
2971 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
2972 #endif
2973 },
2974 {
2975 Mips_DEXTU, MIPS_INS_DEXTU,
2976 #ifndef CAPSTONE_DIET
2977 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
2978 #endif
2979 },
2980 {
2981 Mips_DI, MIPS_INS_DI,
2982 #ifndef CAPSTONE_DIET
2983 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
2984 #endif
2985 },
2986 {
2987 Mips_DINS, MIPS_INS_DINS,
2988 #ifndef CAPSTONE_DIET
2989 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
2990 #endif
2991 },
2992 {
2993 Mips_DINSM, MIPS_INS_DINSM,
2994 #ifndef CAPSTONE_DIET
2995 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
2996 #endif
2997 },
2998 {
2999 Mips_DINSU, MIPS_INS_DINSU,
3000 #ifndef CAPSTONE_DIET
3001 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
3002 #endif
3003 },
3004 {
3005 Mips_DIV, MIPS_INS_DIV,
3006 #ifndef CAPSTONE_DIET
3007 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
3008 #endif
3009 },
3010 {
3011 Mips_DIVU, MIPS_INS_DIVU,
3012 #ifndef CAPSTONE_DIET
3013 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
3014 #endif
3015 },
3016 {
3017 Mips_DIV_S_B, MIPS_INS_DIV_S,
3018 #ifndef CAPSTONE_DIET
3019 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3020 #endif
3021 },
3022 {
3023 Mips_DIV_S_D, MIPS_INS_DIV_S,
3024 #ifndef CAPSTONE_DIET
3025 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3026 #endif
3027 },
3028 {
3029 Mips_DIV_S_H, MIPS_INS_DIV_S,
3030 #ifndef CAPSTONE_DIET
3031 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3032 #endif
3033 },
3034 {
3035 Mips_DIV_S_W, MIPS_INS_DIV_S,
3036 #ifndef CAPSTONE_DIET
3037 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3038 #endif
3039 },
3040 {
3041 Mips_DIV_U_B, MIPS_INS_DIV_U,
3042 #ifndef CAPSTONE_DIET
3043 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3044 #endif
3045 },
3046 {
3047 Mips_DIV_U_D, MIPS_INS_DIV_U,
3048 #ifndef CAPSTONE_DIET
3049 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3050 #endif
3051 },
3052 {
3053 Mips_DIV_U_H, MIPS_INS_DIV_U,
3054 #ifndef CAPSTONE_DIET
3055 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3056 #endif
3057 },
3058 {
3059 Mips_DIV_U_W, MIPS_INS_DIV_U,
3060 #ifndef CAPSTONE_DIET
3061 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3062 #endif
3063 },
3064 {
3065 Mips_DI_MM, MIPS_INS_DI,
3066 #ifndef CAPSTONE_DIET
3067 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
3068 #endif
3069 },
3070 {
3071 Mips_DLSA, MIPS_INS_DLSA,
3072 #ifndef CAPSTONE_DIET
3073 { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0
3074 #endif
3075 },
3076 {
3077 Mips_DLSA_R6, MIPS_INS_DLSA,
3078 #ifndef CAPSTONE_DIET
3079 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
3080 #endif
3081 },
3082 {
3083 Mips_DMFC0, MIPS_INS_DMFC0,
3084 #ifndef CAPSTONE_DIET
3085 { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0
3086 #endif
3087 },
3088 {
3089 Mips_DMFC1, MIPS_INS_DMFC1,
3090 #ifndef CAPSTONE_DIET
3091 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
3092 #endif
3093 },
3094 {
3095 Mips_DMFC2, MIPS_INS_DMFC2,
3096 #ifndef CAPSTONE_DIET
3097 { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0
3098 #endif
3099 },
3100 {
3101 Mips_DMOD, MIPS_INS_DMOD,
3102 #ifndef CAPSTONE_DIET
3103 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
3104 #endif
3105 },
3106 {
3107 Mips_DMODU, MIPS_INS_DMODU,
3108 #ifndef CAPSTONE_DIET
3109 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
3110 #endif
3111 },
3112 {
3113 Mips_DMTC0, MIPS_INS_DMTC0,
3114 #ifndef CAPSTONE_DIET
3115 { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0
3116 #endif
3117 },
3118 {
3119 Mips_DMTC1, MIPS_INS_DMTC1,
3120 #ifndef CAPSTONE_DIET
3121 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
3122 #endif
3123 },
3124 {
3125 Mips_DMTC2, MIPS_INS_DMTC2,
3126 #ifndef CAPSTONE_DIET
3127 { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0
3128 #endif
3129 },
3130 {
3131 Mips_DMUH, MIPS_INS_DMUH,
3132 #ifndef CAPSTONE_DIET
3133 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
3134 #endif
3135 },
3136 {
3137 Mips_DMUHU, MIPS_INS_DMUHU,
3138 #ifndef CAPSTONE_DIET
3139 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
3140 #endif
3141 },
3142 {
3143 Mips_DMUL, MIPS_INS_DMUL,
3144 #ifndef CAPSTONE_DIET
3145 { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
3146 #endif
3147 },
3148 {
3149 Mips_DMULT, MIPS_INS_DMULT,
3150 #ifndef CAPSTONE_DIET
3151 { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
3152 #endif
3153 },
3154 {
3155 Mips_DMULTu, MIPS_INS_DMULTU,
3156 #ifndef CAPSTONE_DIET
3157 { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
3158 #endif
3159 },
3160 {
3161 Mips_DMULU, MIPS_INS_DMULU,
3162 #ifndef CAPSTONE_DIET
3163 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
3164 #endif
3165 },
3166 {
3167 Mips_DMUL_R6, MIPS_INS_DMUL,
3168 #ifndef CAPSTONE_DIET
3169 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
3170 #endif
3171 },
3172 {
3173 Mips_DOTP_S_D, MIPS_INS_DOTP_S,
3174 #ifndef CAPSTONE_DIET
3175 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3176 #endif
3177 },
3178 {
3179 Mips_DOTP_S_H, MIPS_INS_DOTP_S,
3180 #ifndef CAPSTONE_DIET
3181 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3182 #endif
3183 },
3184 {
3185 Mips_DOTP_S_W, MIPS_INS_DOTP_S,
3186 #ifndef CAPSTONE_DIET
3187 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3188 #endif
3189 },
3190 {
3191 Mips_DOTP_U_D, MIPS_INS_DOTP_U,
3192 #ifndef CAPSTONE_DIET
3193 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3194 #endif
3195 },
3196 {
3197 Mips_DOTP_U_H, MIPS_INS_DOTP_U,
3198 #ifndef CAPSTONE_DIET
3199 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3200 #endif
3201 },
3202 {
3203 Mips_DOTP_U_W, MIPS_INS_DOTP_U,
3204 #ifndef CAPSTONE_DIET
3205 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3206 #endif
3207 },
3208 {
3209 Mips_DPADD_S_D, MIPS_INS_DPADD_S,
3210 #ifndef CAPSTONE_DIET
3211 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3212 #endif
3213 },
3214 {
3215 Mips_DPADD_S_H, MIPS_INS_DPADD_S,
3216 #ifndef CAPSTONE_DIET
3217 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3218 #endif
3219 },
3220 {
3221 Mips_DPADD_S_W, MIPS_INS_DPADD_S,
3222 #ifndef CAPSTONE_DIET
3223 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3224 #endif
3225 },
3226 {
3227 Mips_DPADD_U_D, MIPS_INS_DPADD_U,
3228 #ifndef CAPSTONE_DIET
3229 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3230 #endif
3231 },
3232 {
3233 Mips_DPADD_U_H, MIPS_INS_DPADD_U,
3234 #ifndef CAPSTONE_DIET
3235 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3236 #endif
3237 },
3238 {
3239 Mips_DPADD_U_W, MIPS_INS_DPADD_U,
3240 #ifndef CAPSTONE_DIET
3241 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3242 #endif
3243 },
3244 {
3245 Mips_DPAQX_SA_W_PH, MIPS_INS_DPAQX_SA,
3246 #ifndef CAPSTONE_DIET
3247 { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
3248 #endif
3249 },
3250 {
3251 Mips_DPAQX_S_W_PH, MIPS_INS_DPAQX_S,
3252 #ifndef CAPSTONE_DIET
3253 { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
3254 #endif
3255 },
3256 {
3257 Mips_DPAQ_SA_L_W, MIPS_INS_DPAQ_SA,
3258 #ifndef CAPSTONE_DIET
3259 { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3260 #endif
3261 },
3262 {
3263 Mips_DPAQ_S_W_PH, MIPS_INS_DPAQ_S,
3264 #ifndef CAPSTONE_DIET
3265 { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3266 #endif
3267 },
3268 {
3269 Mips_DPAU_H_QBL, MIPS_INS_DPAU,
3270 #ifndef CAPSTONE_DIET
3271 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3272 #endif
3273 },
3274 {
3275 Mips_DPAU_H_QBR, MIPS_INS_DPAU,
3276 #ifndef CAPSTONE_DIET
3277 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3278 #endif
3279 },
3280 {
3281 Mips_DPAX_W_PH, MIPS_INS_DPAX,
3282 #ifndef CAPSTONE_DIET
3283 { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
3284 #endif
3285 },
3286 {
3287 Mips_DPA_W_PH, MIPS_INS_DPA,
3288 #ifndef CAPSTONE_DIET
3289 { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
3290 #endif
3291 },
3292 {
3293 Mips_DPOP, MIPS_INS_DPOP,
3294 #ifndef CAPSTONE_DIET
3295 { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
3296 #endif
3297 },
3298 {
3299 Mips_DPSQX_SA_W_PH, MIPS_INS_DPSQX_SA,
3300 #ifndef CAPSTONE_DIET
3301 { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
3302 #endif
3303 },
3304 {
3305 Mips_DPSQX_S_W_PH, MIPS_INS_DPSQX_S,
3306 #ifndef CAPSTONE_DIET
3307 { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
3308 #endif
3309 },
3310 {
3311 Mips_DPSQ_SA_L_W, MIPS_INS_DPSQ_SA,
3312 #ifndef CAPSTONE_DIET
3313 { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3314 #endif
3315 },
3316 {
3317 Mips_DPSQ_S_W_PH, MIPS_INS_DPSQ_S,
3318 #ifndef CAPSTONE_DIET
3319 { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3320 #endif
3321 },
3322 {
3323 Mips_DPSUB_S_D, MIPS_INS_DPSUB_S,
3324 #ifndef CAPSTONE_DIET
3325 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3326 #endif
3327 },
3328 {
3329 Mips_DPSUB_S_H, MIPS_INS_DPSUB_S,
3330 #ifndef CAPSTONE_DIET
3331 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3332 #endif
3333 },
3334 {
3335 Mips_DPSUB_S_W, MIPS_INS_DPSUB_S,
3336 #ifndef CAPSTONE_DIET
3337 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3338 #endif
3339 },
3340 {
3341 Mips_DPSUB_U_D, MIPS_INS_DPSUB_U,
3342 #ifndef CAPSTONE_DIET
3343 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3344 #endif
3345 },
3346 {
3347 Mips_DPSUB_U_H, MIPS_INS_DPSUB_U,
3348 #ifndef CAPSTONE_DIET
3349 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3350 #endif
3351 },
3352 {
3353 Mips_DPSUB_U_W, MIPS_INS_DPSUB_U,
3354 #ifndef CAPSTONE_DIET
3355 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3356 #endif
3357 },
3358 {
3359 Mips_DPSU_H_QBL, MIPS_INS_DPSU,
3360 #ifndef CAPSTONE_DIET
3361 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3362 #endif
3363 },
3364 {
3365 Mips_DPSU_H_QBR, MIPS_INS_DPSU,
3366 #ifndef CAPSTONE_DIET
3367 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3368 #endif
3369 },
3370 {
3371 Mips_DPSX_W_PH, MIPS_INS_DPSX,
3372 #ifndef CAPSTONE_DIET
3373 { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
3374 #endif
3375 },
3376 {
3377 Mips_DPS_W_PH, MIPS_INS_DPS,
3378 #ifndef CAPSTONE_DIET
3379 { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
3380 #endif
3381 },
3382 {
3383 Mips_DROTR, MIPS_INS_DROTR,
3384 #ifndef CAPSTONE_DIET
3385 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0
3386 #endif
3387 },
3388 {
3389 Mips_DROTR32, MIPS_INS_DROTR32,
3390 #ifndef CAPSTONE_DIET
3391 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0
3392 #endif
3393 },
3394 {
3395 Mips_DROTRV, MIPS_INS_DROTRV,
3396 #ifndef CAPSTONE_DIET
3397 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0
3398 #endif
3399 },
3400 {
3401 Mips_DSBH, MIPS_INS_DSBH,
3402 #ifndef CAPSTONE_DIET
3403 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0
3404 #endif
3405 },
3406 {
3407 Mips_DSDIV, MIPS_INS_DDIV,
3408 #ifndef CAPSTONE_DIET
3409 { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
3410 #endif
3411 },
3412 {
3413 Mips_DSHD, MIPS_INS_DSHD,
3414 #ifndef CAPSTONE_DIET
3415 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0
3416 #endif
3417 },
3418 {
3419 Mips_DSLL, MIPS_INS_DSLL,
3420 #ifndef CAPSTONE_DIET
3421 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
3422 #endif
3423 },
3424 {
3425 Mips_DSLL32, MIPS_INS_DSLL32,
3426 #ifndef CAPSTONE_DIET
3427 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
3428 #endif
3429 },
3430 {
3431 Mips_DSLL64_32, MIPS_INS_DSLL,
3432 #ifndef CAPSTONE_DIET
3433 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
3434 #endif
3435 },
3436 {
3437 Mips_DSLLV, MIPS_INS_DSLLV,
3438 #ifndef CAPSTONE_DIET
3439 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
3440 #endif
3441 },
3442 {
3443 Mips_DSRA, MIPS_INS_DSRA,
3444 #ifndef CAPSTONE_DIET
3445 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
3446 #endif
3447 },
3448 {
3449 Mips_DSRA32, MIPS_INS_DSRA32,
3450 #ifndef CAPSTONE_DIET
3451 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
3452 #endif
3453 },
3454 {
3455 Mips_DSRAV, MIPS_INS_DSRAV,
3456 #ifndef CAPSTONE_DIET
3457 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
3458 #endif
3459 },
3460 {
3461 Mips_DSRL, MIPS_INS_DSRL,
3462 #ifndef CAPSTONE_DIET
3463 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
3464 #endif
3465 },
3466 {
3467 Mips_DSRL32, MIPS_INS_DSRL32,
3468 #ifndef CAPSTONE_DIET
3469 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
3470 #endif
3471 },
3472 {
3473 Mips_DSRLV, MIPS_INS_DSRLV,
3474 #ifndef CAPSTONE_DIET
3475 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
3476 #endif
3477 },
3478 {
3479 Mips_DSUB, MIPS_INS_DSUB,
3480 #ifndef CAPSTONE_DIET
3481 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
3482 #endif
3483 },
3484 {
3485 Mips_DSUBu, MIPS_INS_DSUBU,
3486 #ifndef CAPSTONE_DIET
3487 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
3488 #endif
3489 },
3490 {
3491 Mips_DUDIV, MIPS_INS_DDIVU,
3492 #ifndef CAPSTONE_DIET
3493 { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
3494 #endif
3495 },
3496 {
3497 Mips_DivRxRy16, MIPS_INS_DIV,
3498 #ifndef CAPSTONE_DIET
3499 { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
3500 #endif
3501 },
3502 {
3503 Mips_DivuRxRy16, MIPS_INS_DIVU,
3504 #ifndef CAPSTONE_DIET
3505 { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
3506 #endif
3507 },
3508 {
3509 Mips_EHB, MIPS_INS_EHB,
3510 #ifndef CAPSTONE_DIET
3511 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
3512 #endif
3513 },
3514 {
3515 Mips_EI, MIPS_INS_EI,
3516 #ifndef CAPSTONE_DIET
3517 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
3518 #endif
3519 },
3520 {
3521 Mips_EI_MM, MIPS_INS_EI,
3522 #ifndef CAPSTONE_DIET
3523 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
3524 #endif
3525 },
3526 {
3527 Mips_ERET, MIPS_INS_ERET,
3528 #ifndef CAPSTONE_DIET
3529 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, 0 }, 0, 0
3530 #endif
3531 },
3532 {
3533 Mips_ERET_MM, MIPS_INS_ERET,
3534 #ifndef CAPSTONE_DIET
3535 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
3536 #endif
3537 },
3538 {
3539 Mips_EXT, MIPS_INS_EXT,
3540 #ifndef CAPSTONE_DIET
3541 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
3542 #endif
3543 },
3544 {
3545 Mips_EXTP, MIPS_INS_EXTP,
3546 #ifndef CAPSTONE_DIET
3547 { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3548 #endif
3549 },
3550 {
3551 Mips_EXTPDP, MIPS_INS_EXTPDP,
3552 #ifndef CAPSTONE_DIET
3553 { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3554 #endif
3555 },
3556 {
3557 Mips_EXTPDPV, MIPS_INS_EXTPDPV,
3558 #ifndef CAPSTONE_DIET
3559 { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3560 #endif
3561 },
3562 {
3563 Mips_EXTPV, MIPS_INS_EXTPV,
3564 #ifndef CAPSTONE_DIET
3565 { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3566 #endif
3567 },
3568 {
3569 Mips_EXTRV_RS_W, MIPS_INS_EXTRV_RS,
3570 #ifndef CAPSTONE_DIET
3571 { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3572 #endif
3573 },
3574 {
3575 Mips_EXTRV_R_W, MIPS_INS_EXTRV_R,
3576 #ifndef CAPSTONE_DIET
3577 { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3578 #endif
3579 },
3580 {
3581 Mips_EXTRV_S_H, MIPS_INS_EXTRV_S,
3582 #ifndef CAPSTONE_DIET
3583 { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3584 #endif
3585 },
3586 {
3587 Mips_EXTRV_W, MIPS_INS_EXTRV,
3588 #ifndef CAPSTONE_DIET
3589 { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3590 #endif
3591 },
3592 {
3593 Mips_EXTR_RS_W, MIPS_INS_EXTR_RS,
3594 #ifndef CAPSTONE_DIET
3595 { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3596 #endif
3597 },
3598 {
3599 Mips_EXTR_R_W, MIPS_INS_EXTR_R,
3600 #ifndef CAPSTONE_DIET
3601 { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3602 #endif
3603 },
3604 {
3605 Mips_EXTR_S_H, MIPS_INS_EXTR_S,
3606 #ifndef CAPSTONE_DIET
3607 { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3608 #endif
3609 },
3610 {
3611 Mips_EXTR_W, MIPS_INS_EXTR,
3612 #ifndef CAPSTONE_DIET
3613 { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3614 #endif
3615 },
3616 {
3617 Mips_EXTS, MIPS_INS_EXTS,
3618 #ifndef CAPSTONE_DIET
3619 { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
3620 #endif
3621 },
3622 {
3623 Mips_EXTS32, MIPS_INS_EXTS32,
3624 #ifndef CAPSTONE_DIET
3625 { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
3626 #endif
3627 },
3628 {
3629 Mips_EXT_MM, MIPS_INS_EXT,
3630 #ifndef CAPSTONE_DIET
3631 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
3632 #endif
3633 },
3634 {
3635 Mips_FABS_D32, MIPS_INS_ABS,
3636 #ifndef CAPSTONE_DIET
3637 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
3638 #endif
3639 },
3640 {
3641 Mips_FABS_D64, MIPS_INS_ABS,
3642 #ifndef CAPSTONE_DIET
3643 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
3644 #endif
3645 },
3646 {
3647 Mips_FABS_MM, MIPS_INS_ABS,
3648 #ifndef CAPSTONE_DIET
3649 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
3650 #endif
3651 },
3652 {
3653 Mips_FABS_S, MIPS_INS_ABS,
3654 #ifndef CAPSTONE_DIET
3655 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
3656 #endif
3657 },
3658 {
3659 Mips_FABS_S_MM, MIPS_INS_ABS,
3660 #ifndef CAPSTONE_DIET
3661 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
3662 #endif
3663 },
3664 {
3665 Mips_FADD_D, MIPS_INS_FADD,
3666 #ifndef CAPSTONE_DIET
3667 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3668 #endif
3669 },
3670 {
3671 Mips_FADD_D32, MIPS_INS_ADD,
3672 #ifndef CAPSTONE_DIET
3673 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
3674 #endif
3675 },
3676 {
3677 Mips_FADD_D64, MIPS_INS_ADD,
3678 #ifndef CAPSTONE_DIET
3679 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
3680 #endif
3681 },
3682 {
3683 Mips_FADD_MM, MIPS_INS_ADD,
3684 #ifndef CAPSTONE_DIET
3685 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
3686 #endif
3687 },
3688 {
3689 Mips_FADD_S, MIPS_INS_ADD,
3690 #ifndef CAPSTONE_DIET
3691 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
3692 #endif
3693 },
3694 {
3695 Mips_FADD_S_MM, MIPS_INS_ADD,
3696 #ifndef CAPSTONE_DIET
3697 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
3698 #endif
3699 },
3700 {
3701 Mips_FADD_W, MIPS_INS_FADD,
3702 #ifndef CAPSTONE_DIET
3703 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3704 #endif
3705 },
3706 {
3707 Mips_FCAF_D, MIPS_INS_FCAF,
3708 #ifndef CAPSTONE_DIET
3709 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3710 #endif
3711 },
3712 {
3713 Mips_FCAF_W, MIPS_INS_FCAF,
3714 #ifndef CAPSTONE_DIET
3715 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3716 #endif
3717 },
3718 {
3719 Mips_FCEQ_D, MIPS_INS_FCEQ,
3720 #ifndef CAPSTONE_DIET
3721 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3722 #endif
3723 },
3724 {
3725 Mips_FCEQ_W, MIPS_INS_FCEQ,
3726 #ifndef CAPSTONE_DIET
3727 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3728 #endif
3729 },
3730 {
3731 Mips_FCLASS_D, MIPS_INS_FCLASS,
3732 #ifndef CAPSTONE_DIET
3733 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3734 #endif
3735 },
3736 {
3737 Mips_FCLASS_W, MIPS_INS_FCLASS,
3738 #ifndef CAPSTONE_DIET
3739 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3740 #endif
3741 },
3742 {
3743 Mips_FCLE_D, MIPS_INS_FCLE,
3744 #ifndef CAPSTONE_DIET
3745 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3746 #endif
3747 },
3748 {
3749 Mips_FCLE_W, MIPS_INS_FCLE,
3750 #ifndef CAPSTONE_DIET
3751 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3752 #endif
3753 },
3754 {
3755 Mips_FCLT_D, MIPS_INS_FCLT,
3756 #ifndef CAPSTONE_DIET
3757 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3758 #endif
3759 },
3760 {
3761 Mips_FCLT_W, MIPS_INS_FCLT,
3762 #ifndef CAPSTONE_DIET
3763 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3764 #endif
3765 },
3766 {
3767 Mips_FCMP_D32, MIPS_INS_C,
3768 #ifndef CAPSTONE_DIET
3769 { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
3770 #endif
3771 },
3772 {
3773 Mips_FCMP_D32_MM, MIPS_INS_C,
3774 #ifndef CAPSTONE_DIET
3775 { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
3776 #endif
3777 },
3778 {
3779 Mips_FCMP_D64, MIPS_INS_C,
3780 #ifndef CAPSTONE_DIET
3781 { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
3782 #endif
3783 },
3784 {
3785 Mips_FCMP_S32, MIPS_INS_C,
3786 #ifndef CAPSTONE_DIET
3787 { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
3788 #endif
3789 },
3790 {
3791 Mips_FCMP_S32_MM, MIPS_INS_C,
3792 #ifndef CAPSTONE_DIET
3793 { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
3794 #endif
3795 },
3796 {
3797 Mips_FCNE_D, MIPS_INS_FCNE,
3798 #ifndef CAPSTONE_DIET
3799 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3800 #endif
3801 },
3802 {
3803 Mips_FCNE_W, MIPS_INS_FCNE,
3804 #ifndef CAPSTONE_DIET
3805 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3806 #endif
3807 },
3808 {
3809 Mips_FCOR_D, MIPS_INS_FCOR,
3810 #ifndef CAPSTONE_DIET
3811 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3812 #endif
3813 },
3814 {
3815 Mips_FCOR_W, MIPS_INS_FCOR,
3816 #ifndef CAPSTONE_DIET
3817 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3818 #endif
3819 },
3820 {
3821 Mips_FCUEQ_D, MIPS_INS_FCUEQ,
3822 #ifndef CAPSTONE_DIET
3823 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3824 #endif
3825 },
3826 {
3827 Mips_FCUEQ_W, MIPS_INS_FCUEQ,
3828 #ifndef CAPSTONE_DIET
3829 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3830 #endif
3831 },
3832 {
3833 Mips_FCULE_D, MIPS_INS_FCULE,
3834 #ifndef CAPSTONE_DIET
3835 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3836 #endif
3837 },
3838 {
3839 Mips_FCULE_W, MIPS_INS_FCULE,
3840 #ifndef CAPSTONE_DIET
3841 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3842 #endif
3843 },
3844 {
3845 Mips_FCULT_D, MIPS_INS_FCULT,
3846 #ifndef CAPSTONE_DIET
3847 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3848 #endif
3849 },
3850 {
3851 Mips_FCULT_W, MIPS_INS_FCULT,
3852 #ifndef CAPSTONE_DIET
3853 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3854 #endif
3855 },
3856 {
3857 Mips_FCUNE_D, MIPS_INS_FCUNE,
3858 #ifndef CAPSTONE_DIET
3859 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3860 #endif
3861 },
3862 {
3863 Mips_FCUNE_W, MIPS_INS_FCUNE,
3864 #ifndef CAPSTONE_DIET
3865 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3866 #endif
3867 },
3868 {
3869 Mips_FCUN_D, MIPS_INS_FCUN,
3870 #ifndef CAPSTONE_DIET
3871 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3872 #endif
3873 },
3874 {
3875 Mips_FCUN_W, MIPS_INS_FCUN,
3876 #ifndef CAPSTONE_DIET
3877 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3878 #endif
3879 },
3880 {
3881 Mips_FDIV_D, MIPS_INS_FDIV,
3882 #ifndef CAPSTONE_DIET
3883 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3884 #endif
3885 },
3886 {
3887 Mips_FDIV_D32, MIPS_INS_DIV,
3888 #ifndef CAPSTONE_DIET
3889 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
3890 #endif
3891 },
3892 {
3893 Mips_FDIV_D64, MIPS_INS_DIV,
3894 #ifndef CAPSTONE_DIET
3895 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
3896 #endif
3897 },
3898 {
3899 Mips_FDIV_MM, MIPS_INS_DIV,
3900 #ifndef CAPSTONE_DIET
3901 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
3902 #endif
3903 },
3904 {
3905 Mips_FDIV_S, MIPS_INS_DIV,
3906 #ifndef CAPSTONE_DIET
3907 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
3908 #endif
3909 },
3910 {
3911 Mips_FDIV_S_MM, MIPS_INS_DIV,
3912 #ifndef CAPSTONE_DIET
3913 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
3914 #endif
3915 },
3916 {
3917 Mips_FDIV_W, MIPS_INS_FDIV,
3918 #ifndef CAPSTONE_DIET
3919 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3920 #endif
3921 },
3922 {
3923 Mips_FEXDO_H, MIPS_INS_FEXDO,
3924 #ifndef CAPSTONE_DIET
3925 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3926 #endif
3927 },
3928 {
3929 Mips_FEXDO_W, MIPS_INS_FEXDO,
3930 #ifndef CAPSTONE_DIET
3931 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3932 #endif
3933 },
3934 {
3935 Mips_FEXP2_D, MIPS_INS_FEXP2,
3936 #ifndef CAPSTONE_DIET
3937 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3938 #endif
3939 },
3940 {
3941 Mips_FEXP2_W, MIPS_INS_FEXP2,
3942 #ifndef CAPSTONE_DIET
3943 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3944 #endif
3945 },
3946 {
3947 Mips_FEXUPL_D, MIPS_INS_FEXUPL,
3948 #ifndef CAPSTONE_DIET
3949 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3950 #endif
3951 },
3952 {
3953 Mips_FEXUPL_W, MIPS_INS_FEXUPL,
3954 #ifndef CAPSTONE_DIET
3955 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3956 #endif
3957 },
3958 {
3959 Mips_FEXUPR_D, MIPS_INS_FEXUPR,
3960 #ifndef CAPSTONE_DIET
3961 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3962 #endif
3963 },
3964 {
3965 Mips_FEXUPR_W, MIPS_INS_FEXUPR,
3966 #ifndef CAPSTONE_DIET
3967 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3968 #endif
3969 },
3970 {
3971 Mips_FFINT_S_D, MIPS_INS_FFINT_S,
3972 #ifndef CAPSTONE_DIET
3973 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3974 #endif
3975 },
3976 {
3977 Mips_FFINT_S_W, MIPS_INS_FFINT_S,
3978 #ifndef CAPSTONE_DIET
3979 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3980 #endif
3981 },
3982 {
3983 Mips_FFINT_U_D, MIPS_INS_FFINT_U,
3984 #ifndef CAPSTONE_DIET
3985 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3986 #endif
3987 },
3988 {
3989 Mips_FFINT_U_W, MIPS_INS_FFINT_U,
3990 #ifndef CAPSTONE_DIET
3991 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3992 #endif
3993 },
3994 {
3995 Mips_FFQL_D, MIPS_INS_FFQL,
3996 #ifndef CAPSTONE_DIET
3997 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3998 #endif
3999 },
4000 {
4001 Mips_FFQL_W, MIPS_INS_FFQL,
4002 #ifndef CAPSTONE_DIET
4003 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4004 #endif
4005 },
4006 {
4007 Mips_FFQR_D, MIPS_INS_FFQR,
4008 #ifndef CAPSTONE_DIET
4009 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4010 #endif
4011 },
4012 {
4013 Mips_FFQR_W, MIPS_INS_FFQR,
4014 #ifndef CAPSTONE_DIET
4015 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4016 #endif
4017 },
4018 {
4019 Mips_FILL_B, MIPS_INS_FILL,
4020 #ifndef CAPSTONE_DIET
4021 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4022 #endif
4023 },
4024 {
4025 Mips_FILL_D, MIPS_INS_FILL,
4026 #ifndef CAPSTONE_DIET
4027 { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0
4028 #endif
4029 },
4030 {
4031 Mips_FILL_H, MIPS_INS_FILL,
4032 #ifndef CAPSTONE_DIET
4033 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4034 #endif
4035 },
4036 {
4037 Mips_FILL_W, MIPS_INS_FILL,
4038 #ifndef CAPSTONE_DIET
4039 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4040 #endif
4041 },
4042 {
4043 Mips_FLOG2_D, MIPS_INS_FLOG2,
4044 #ifndef CAPSTONE_DIET
4045 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4046 #endif
4047 },
4048 {
4049 Mips_FLOG2_W, MIPS_INS_FLOG2,
4050 #ifndef CAPSTONE_DIET
4051 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4052 #endif
4053 },
4054 {
4055 Mips_FLOOR_L_D64, MIPS_INS_FLOOR,
4056 #ifndef CAPSTONE_DIET
4057 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
4058 #endif
4059 },
4060 {
4061 Mips_FLOOR_L_S, MIPS_INS_FLOOR,
4062 #ifndef CAPSTONE_DIET
4063 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
4064 #endif
4065 },
4066 {
4067 Mips_FLOOR_W_D32, MIPS_INS_FLOOR,
4068 #ifndef CAPSTONE_DIET
4069 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
4070 #endif
4071 },
4072 {
4073 Mips_FLOOR_W_D64, MIPS_INS_FLOOR,
4074 #ifndef CAPSTONE_DIET
4075 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0
4076 #endif
4077 },
4078 {
4079 Mips_FLOOR_W_MM, MIPS_INS_FLOOR,
4080 #ifndef CAPSTONE_DIET
4081 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4082 #endif
4083 },
4084 {
4085 Mips_FLOOR_W_S, MIPS_INS_FLOOR,
4086 #ifndef CAPSTONE_DIET
4087 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
4088 #endif
4089 },
4090 {
4091 Mips_FLOOR_W_S_MM, MIPS_INS_FLOOR,
4092 #ifndef CAPSTONE_DIET
4093 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4094 #endif
4095 },
4096 {
4097 Mips_FMADD_D, MIPS_INS_FMADD,
4098 #ifndef CAPSTONE_DIET
4099 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4100 #endif
4101 },
4102 {
4103 Mips_FMADD_W, MIPS_INS_FMADD,
4104 #ifndef CAPSTONE_DIET
4105 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4106 #endif
4107 },
4108 {
4109 Mips_FMAX_A_D, MIPS_INS_FMAX_A,
4110 #ifndef CAPSTONE_DIET
4111 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4112 #endif
4113 },
4114 {
4115 Mips_FMAX_A_W, MIPS_INS_FMAX_A,
4116 #ifndef CAPSTONE_DIET
4117 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4118 #endif
4119 },
4120 {
4121 Mips_FMAX_D, MIPS_INS_FMAX,
4122 #ifndef CAPSTONE_DIET
4123 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4124 #endif
4125 },
4126 {
4127 Mips_FMAX_W, MIPS_INS_FMAX,
4128 #ifndef CAPSTONE_DIET
4129 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4130 #endif
4131 },
4132 {
4133 Mips_FMIN_A_D, MIPS_INS_FMIN_A,
4134 #ifndef CAPSTONE_DIET
4135 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4136 #endif
4137 },
4138 {
4139 Mips_FMIN_A_W, MIPS_INS_FMIN_A,
4140 #ifndef CAPSTONE_DIET
4141 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4142 #endif
4143 },
4144 {
4145 Mips_FMIN_D, MIPS_INS_FMIN,
4146 #ifndef CAPSTONE_DIET
4147 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4148 #endif
4149 },
4150 {
4151 Mips_FMIN_W, MIPS_INS_FMIN,
4152 #ifndef CAPSTONE_DIET
4153 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4154 #endif
4155 },
4156 {
4157 Mips_FMOV_D32, MIPS_INS_MOV,
4158 #ifndef CAPSTONE_DIET
4159 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
4160 #endif
4161 },
4162 {
4163 Mips_FMOV_D32_MM, MIPS_INS_MOV,
4164 #ifndef CAPSTONE_DIET
4165 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4166 #endif
4167 },
4168 {
4169 Mips_FMOV_D64, MIPS_INS_MOV,
4170 #ifndef CAPSTONE_DIET
4171 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
4172 #endif
4173 },
4174 {
4175 Mips_FMOV_S, MIPS_INS_MOV,
4176 #ifndef CAPSTONE_DIET
4177 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
4178 #endif
4179 },
4180 {
4181 Mips_FMOV_S_MM, MIPS_INS_MOV,
4182 #ifndef CAPSTONE_DIET
4183 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4184 #endif
4185 },
4186 {
4187 Mips_FMSUB_D, MIPS_INS_FMSUB,
4188 #ifndef CAPSTONE_DIET
4189 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4190 #endif
4191 },
4192 {
4193 Mips_FMSUB_W, MIPS_INS_FMSUB,
4194 #ifndef CAPSTONE_DIET
4195 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4196 #endif
4197 },
4198 {
4199 Mips_FMUL_D, MIPS_INS_FMUL,
4200 #ifndef CAPSTONE_DIET
4201 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4202 #endif
4203 },
4204 {
4205 Mips_FMUL_D32, MIPS_INS_MUL,
4206 #ifndef CAPSTONE_DIET
4207 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
4208 #endif
4209 },
4210 {
4211 Mips_FMUL_D64, MIPS_INS_MUL,
4212 #ifndef CAPSTONE_DIET
4213 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
4214 #endif
4215 },
4216 {
4217 Mips_FMUL_MM, MIPS_INS_MUL,
4218 #ifndef CAPSTONE_DIET
4219 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4220 #endif
4221 },
4222 {
4223 Mips_FMUL_S, MIPS_INS_MUL,
4224 #ifndef CAPSTONE_DIET
4225 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
4226 #endif
4227 },
4228 {
4229 Mips_FMUL_S_MM, MIPS_INS_MUL,
4230 #ifndef CAPSTONE_DIET
4231 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4232 #endif
4233 },
4234 {
4235 Mips_FMUL_W, MIPS_INS_FMUL,
4236 #ifndef CAPSTONE_DIET
4237 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4238 #endif
4239 },
4240 {
4241 Mips_FNEG_D32, MIPS_INS_NEG,
4242 #ifndef CAPSTONE_DIET
4243 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
4244 #endif
4245 },
4246 {
4247 Mips_FNEG_D64, MIPS_INS_NEG,
4248 #ifndef CAPSTONE_DIET
4249 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
4250 #endif
4251 },
4252 {
4253 Mips_FNEG_MM, MIPS_INS_NEG,
4254 #ifndef CAPSTONE_DIET
4255 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4256 #endif
4257 },
4258 {
4259 Mips_FNEG_S, MIPS_INS_NEG,
4260 #ifndef CAPSTONE_DIET
4261 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
4262 #endif
4263 },
4264 {
4265 Mips_FNEG_S_MM, MIPS_INS_NEG,
4266 #ifndef CAPSTONE_DIET
4267 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4268 #endif
4269 },
4270 {
4271 Mips_FRCP_D, MIPS_INS_FRCP,
4272 #ifndef CAPSTONE_DIET
4273 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4274 #endif
4275 },
4276 {
4277 Mips_FRCP_W, MIPS_INS_FRCP,
4278 #ifndef CAPSTONE_DIET
4279 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4280 #endif
4281 },
4282 {
4283 Mips_FRINT_D, MIPS_INS_FRINT,
4284 #ifndef CAPSTONE_DIET
4285 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4286 #endif
4287 },
4288 {
4289 Mips_FRINT_W, MIPS_INS_FRINT,
4290 #ifndef CAPSTONE_DIET
4291 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4292 #endif
4293 },
4294 {
4295 Mips_FRSQRT_D, MIPS_INS_FRSQRT,
4296 #ifndef CAPSTONE_DIET
4297 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4298 #endif
4299 },
4300 {
4301 Mips_FRSQRT_W, MIPS_INS_FRSQRT,
4302 #ifndef CAPSTONE_DIET
4303 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4304 #endif
4305 },
4306 {
4307 Mips_FSAF_D, MIPS_INS_FSAF,
4308 #ifndef CAPSTONE_DIET
4309 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4310 #endif
4311 },
4312 {
4313 Mips_FSAF_W, MIPS_INS_FSAF,
4314 #ifndef CAPSTONE_DIET
4315 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4316 #endif
4317 },
4318 {
4319 Mips_FSEQ_D, MIPS_INS_FSEQ,
4320 #ifndef CAPSTONE_DIET
4321 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4322 #endif
4323 },
4324 {
4325 Mips_FSEQ_W, MIPS_INS_FSEQ,
4326 #ifndef CAPSTONE_DIET
4327 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4328 #endif
4329 },
4330 {
4331 Mips_FSLE_D, MIPS_INS_FSLE,
4332 #ifndef CAPSTONE_DIET
4333 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4334 #endif
4335 },
4336 {
4337 Mips_FSLE_W, MIPS_INS_FSLE,
4338 #ifndef CAPSTONE_DIET
4339 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4340 #endif
4341 },
4342 {
4343 Mips_FSLT_D, MIPS_INS_FSLT,
4344 #ifndef CAPSTONE_DIET
4345 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4346 #endif
4347 },
4348 {
4349 Mips_FSLT_W, MIPS_INS_FSLT,
4350 #ifndef CAPSTONE_DIET
4351 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4352 #endif
4353 },
4354 {
4355 Mips_FSNE_D, MIPS_INS_FSNE,
4356 #ifndef CAPSTONE_DIET
4357 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4358 #endif
4359 },
4360 {
4361 Mips_FSNE_W, MIPS_INS_FSNE,
4362 #ifndef CAPSTONE_DIET
4363 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4364 #endif
4365 },
4366 {
4367 Mips_FSOR_D, MIPS_INS_FSOR,
4368 #ifndef CAPSTONE_DIET
4369 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4370 #endif
4371 },
4372 {
4373 Mips_FSOR_W, MIPS_INS_FSOR,
4374 #ifndef CAPSTONE_DIET
4375 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4376 #endif
4377 },
4378 {
4379 Mips_FSQRT_D, MIPS_INS_FSQRT,
4380 #ifndef CAPSTONE_DIET
4381 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4382 #endif
4383 },
4384 {
4385 Mips_FSQRT_D32, MIPS_INS_SQRT,
4386 #ifndef CAPSTONE_DIET
4387 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
4388 #endif
4389 },
4390 {
4391 Mips_FSQRT_D64, MIPS_INS_SQRT,
4392 #ifndef CAPSTONE_DIET
4393 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0
4394 #endif
4395 },
4396 {
4397 Mips_FSQRT_MM, MIPS_INS_SQRT,
4398 #ifndef CAPSTONE_DIET
4399 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4400 #endif
4401 },
4402 {
4403 Mips_FSQRT_S, MIPS_INS_SQRT,
4404 #ifndef CAPSTONE_DIET
4405 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
4406 #endif
4407 },
4408 {
4409 Mips_FSQRT_S_MM, MIPS_INS_SQRT,
4410 #ifndef CAPSTONE_DIET
4411 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4412 #endif
4413 },
4414 {
4415 Mips_FSQRT_W, MIPS_INS_FSQRT,
4416 #ifndef CAPSTONE_DIET
4417 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4418 #endif
4419 },
4420 {
4421 Mips_FSUB_D, MIPS_INS_FSUB,
4422 #ifndef CAPSTONE_DIET
4423 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4424 #endif
4425 },
4426 {
4427 Mips_FSUB_D32, MIPS_INS_SUB,
4428 #ifndef CAPSTONE_DIET
4429 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
4430 #endif
4431 },
4432 {
4433 Mips_FSUB_D64, MIPS_INS_SUB,
4434 #ifndef CAPSTONE_DIET
4435 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
4436 #endif
4437 },
4438 {
4439 Mips_FSUB_MM, MIPS_INS_SUB,
4440 #ifndef CAPSTONE_DIET
4441 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4442 #endif
4443 },
4444 {
4445 Mips_FSUB_S, MIPS_INS_SUB,
4446 #ifndef CAPSTONE_DIET
4447 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
4448 #endif
4449 },
4450 {
4451 Mips_FSUB_S_MM, MIPS_INS_SUB,
4452 #ifndef CAPSTONE_DIET
4453 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4454 #endif
4455 },
4456 {
4457 Mips_FSUB_W, MIPS_INS_FSUB,
4458 #ifndef CAPSTONE_DIET
4459 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4460 #endif
4461 },
4462 {
4463 Mips_FSUEQ_D, MIPS_INS_FSUEQ,
4464 #ifndef CAPSTONE_DIET
4465 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4466 #endif
4467 },
4468 {
4469 Mips_FSUEQ_W, MIPS_INS_FSUEQ,
4470 #ifndef CAPSTONE_DIET
4471 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4472 #endif
4473 },
4474 {
4475 Mips_FSULE_D, MIPS_INS_FSULE,
4476 #ifndef CAPSTONE_DIET
4477 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4478 #endif
4479 },
4480 {
4481 Mips_FSULE_W, MIPS_INS_FSULE,
4482 #ifndef CAPSTONE_DIET
4483 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4484 #endif
4485 },
4486 {
4487 Mips_FSULT_D, MIPS_INS_FSULT,
4488 #ifndef CAPSTONE_DIET
4489 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4490 #endif
4491 },
4492 {
4493 Mips_FSULT_W, MIPS_INS_FSULT,
4494 #ifndef CAPSTONE_DIET
4495 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4496 #endif
4497 },
4498 {
4499 Mips_FSUNE_D, MIPS_INS_FSUNE,
4500 #ifndef CAPSTONE_DIET
4501 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4502 #endif
4503 },
4504 {
4505 Mips_FSUNE_W, MIPS_INS_FSUNE,
4506 #ifndef CAPSTONE_DIET
4507 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4508 #endif
4509 },
4510 {
4511 Mips_FSUN_D, MIPS_INS_FSUN,
4512 #ifndef CAPSTONE_DIET
4513 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4514 #endif
4515 },
4516 {
4517 Mips_FSUN_W, MIPS_INS_FSUN,
4518 #ifndef CAPSTONE_DIET
4519 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4520 #endif
4521 },
4522 {
4523 Mips_FTINT_S_D, MIPS_INS_FTINT_S,
4524 #ifndef CAPSTONE_DIET
4525 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4526 #endif
4527 },
4528 {
4529 Mips_FTINT_S_W, MIPS_INS_FTINT_S,
4530 #ifndef CAPSTONE_DIET
4531 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4532 #endif
4533 },
4534 {
4535 Mips_FTINT_U_D, MIPS_INS_FTINT_U,
4536 #ifndef CAPSTONE_DIET
4537 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4538 #endif
4539 },
4540 {
4541 Mips_FTINT_U_W, MIPS_INS_FTINT_U,
4542 #ifndef CAPSTONE_DIET
4543 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4544 #endif
4545 },
4546 {
4547 Mips_FTQ_H, MIPS_INS_FTQ,
4548 #ifndef CAPSTONE_DIET
4549 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4550 #endif
4551 },
4552 {
4553 Mips_FTQ_W, MIPS_INS_FTQ,
4554 #ifndef CAPSTONE_DIET
4555 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4556 #endif
4557 },
4558 {
4559 Mips_FTRUNC_S_D, MIPS_INS_FTRUNC_S,
4560 #ifndef CAPSTONE_DIET
4561 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4562 #endif
4563 },
4564 {
4565 Mips_FTRUNC_S_W, MIPS_INS_FTRUNC_S,
4566 #ifndef CAPSTONE_DIET
4567 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4568 #endif
4569 },
4570 {
4571 Mips_FTRUNC_U_D, MIPS_INS_FTRUNC_U,
4572 #ifndef CAPSTONE_DIET
4573 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4574 #endif
4575 },
4576 {
4577 Mips_FTRUNC_U_W, MIPS_INS_FTRUNC_U,
4578 #ifndef CAPSTONE_DIET
4579 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4580 #endif
4581 },
4582 {
4583 Mips_HADD_S_D, MIPS_INS_HADD_S,
4584 #ifndef CAPSTONE_DIET
4585 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4586 #endif
4587 },
4588 {
4589 Mips_HADD_S_H, MIPS_INS_HADD_S,
4590 #ifndef CAPSTONE_DIET
4591 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4592 #endif
4593 },
4594 {
4595 Mips_HADD_S_W, MIPS_INS_HADD_S,
4596 #ifndef CAPSTONE_DIET
4597 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4598 #endif
4599 },
4600 {
4601 Mips_HADD_U_D, MIPS_INS_HADD_U,
4602 #ifndef CAPSTONE_DIET
4603 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4604 #endif
4605 },
4606 {
4607 Mips_HADD_U_H, MIPS_INS_HADD_U,
4608 #ifndef CAPSTONE_DIET
4609 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4610 #endif
4611 },
4612 {
4613 Mips_HADD_U_W, MIPS_INS_HADD_U,
4614 #ifndef CAPSTONE_DIET
4615 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4616 #endif
4617 },
4618 {
4619 Mips_HSUB_S_D, MIPS_INS_HSUB_S,
4620 #ifndef CAPSTONE_DIET
4621 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4622 #endif
4623 },
4624 {
4625 Mips_HSUB_S_H, MIPS_INS_HSUB_S,
4626 #ifndef CAPSTONE_DIET
4627 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4628 #endif
4629 },
4630 {
4631 Mips_HSUB_S_W, MIPS_INS_HSUB_S,
4632 #ifndef CAPSTONE_DIET
4633 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4634 #endif
4635 },
4636 {
4637 Mips_HSUB_U_D, MIPS_INS_HSUB_U,
4638 #ifndef CAPSTONE_DIET
4639 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4640 #endif
4641 },
4642 {
4643 Mips_HSUB_U_H, MIPS_INS_HSUB_U,
4644 #ifndef CAPSTONE_DIET
4645 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4646 #endif
4647 },
4648 {
4649 Mips_HSUB_U_W, MIPS_INS_HSUB_U,
4650 #ifndef CAPSTONE_DIET
4651 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4652 #endif
4653 },
4654 {
4655 Mips_ILVEV_B, MIPS_INS_ILVEV,
4656 #ifndef CAPSTONE_DIET
4657 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4658 #endif
4659 },
4660 {
4661 Mips_ILVEV_D, MIPS_INS_ILVEV,
4662 #ifndef CAPSTONE_DIET
4663 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4664 #endif
4665 },
4666 {
4667 Mips_ILVEV_H, MIPS_INS_ILVEV,
4668 #ifndef CAPSTONE_DIET
4669 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4670 #endif
4671 },
4672 {
4673 Mips_ILVEV_W, MIPS_INS_ILVEV,
4674 #ifndef CAPSTONE_DIET
4675 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4676 #endif
4677 },
4678 {
4679 Mips_ILVL_B, MIPS_INS_ILVL,
4680 #ifndef CAPSTONE_DIET
4681 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4682 #endif
4683 },
4684 {
4685 Mips_ILVL_D, MIPS_INS_ILVL,
4686 #ifndef CAPSTONE_DIET
4687 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4688 #endif
4689 },
4690 {
4691 Mips_ILVL_H, MIPS_INS_ILVL,
4692 #ifndef CAPSTONE_DIET
4693 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4694 #endif
4695 },
4696 {
4697 Mips_ILVL_W, MIPS_INS_ILVL,
4698 #ifndef CAPSTONE_DIET
4699 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4700 #endif
4701 },
4702 {
4703 Mips_ILVOD_B, MIPS_INS_ILVOD,
4704 #ifndef CAPSTONE_DIET
4705 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4706 #endif
4707 },
4708 {
4709 Mips_ILVOD_D, MIPS_INS_ILVOD,
4710 #ifndef CAPSTONE_DIET
4711 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4712 #endif
4713 },
4714 {
4715 Mips_ILVOD_H, MIPS_INS_ILVOD,
4716 #ifndef CAPSTONE_DIET
4717 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4718 #endif
4719 },
4720 {
4721 Mips_ILVOD_W, MIPS_INS_ILVOD,
4722 #ifndef CAPSTONE_DIET
4723 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4724 #endif
4725 },
4726 {
4727 Mips_ILVR_B, MIPS_INS_ILVR,
4728 #ifndef CAPSTONE_DIET
4729 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4730 #endif
4731 },
4732 {
4733 Mips_ILVR_D, MIPS_INS_ILVR,
4734 #ifndef CAPSTONE_DIET
4735 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4736 #endif
4737 },
4738 {
4739 Mips_ILVR_H, MIPS_INS_ILVR,
4740 #ifndef CAPSTONE_DIET
4741 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4742 #endif
4743 },
4744 {
4745 Mips_ILVR_W, MIPS_INS_ILVR,
4746 #ifndef CAPSTONE_DIET
4747 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4748 #endif
4749 },
4750 {
4751 Mips_INS, MIPS_INS_INS,
4752 #ifndef CAPSTONE_DIET
4753 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
4754 #endif
4755 },
4756 {
4757 Mips_INSERT_B, MIPS_INS_INSERT,
4758 #ifndef CAPSTONE_DIET
4759 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4760 #endif
4761 },
4762 {
4763 Mips_INSERT_D, MIPS_INS_INSERT,
4764 #ifndef CAPSTONE_DIET
4765 { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0
4766 #endif
4767 },
4768 {
4769 Mips_INSERT_H, MIPS_INS_INSERT,
4770 #ifndef CAPSTONE_DIET
4771 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4772 #endif
4773 },
4774 {
4775 Mips_INSERT_W, MIPS_INS_INSERT,
4776 #ifndef CAPSTONE_DIET
4777 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4778 #endif
4779 },
4780 {
4781 Mips_INSV, MIPS_INS_INSV,
4782 #ifndef CAPSTONE_DIET
4783 { MIPS_REG_DSPPOS, MIPS_REG_DSPSCOUNT, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
4784 #endif
4785 },
4786 {
4787 Mips_INSVE_B, MIPS_INS_INSVE,
4788 #ifndef CAPSTONE_DIET
4789 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4790 #endif
4791 },
4792 {
4793 Mips_INSVE_D, MIPS_INS_INSVE,
4794 #ifndef CAPSTONE_DIET
4795 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4796 #endif
4797 },
4798 {
4799 Mips_INSVE_H, MIPS_INS_INSVE,
4800 #ifndef CAPSTONE_DIET
4801 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4802 #endif
4803 },
4804 {
4805 Mips_INSVE_W, MIPS_INS_INSVE,
4806 #ifndef CAPSTONE_DIET
4807 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4808 #endif
4809 },
4810 {
4811 Mips_INS_MM, MIPS_INS_INS,
4812 #ifndef CAPSTONE_DIET
4813 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4814 #endif
4815 },
4816 {
4817 Mips_J, MIPS_INS_J,
4818 #ifndef CAPSTONE_DIET
4819 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
4820 #endif
4821 },
4822 {
4823 Mips_JAL, MIPS_INS_JAL,
4824 #ifndef CAPSTONE_DIET
4825 { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
4826 #endif
4827 },
4828 {
4829 Mips_JALR, MIPS_INS_JALR,
4830 #ifndef CAPSTONE_DIET
4831 { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
4832 #endif
4833 },
4834 {
4835 Mips_JALR16_MM, MIPS_INS_JALR,
4836 #ifndef CAPSTONE_DIET
4837 { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4838 #endif
4839 },
4840 {
4841 Mips_JALR64, MIPS_INS_JALR,
4842 #ifndef CAPSTONE_DIET
4843 { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
4844 #endif
4845 },
4846 {
4847 Mips_JALRS_MM, MIPS_INS_JALRS,
4848 #ifndef CAPSTONE_DIET
4849 { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4850 #endif
4851 },
4852 {
4853 Mips_JALR_HB, MIPS_INS_JALR_HB,
4854 #ifndef CAPSTONE_DIET
4855 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 1
4856 #endif
4857 },
4858 {
4859 Mips_JALR_MM, MIPS_INS_JALR,
4860 #ifndef CAPSTONE_DIET
4861 { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4862 #endif
4863 },
4864 {
4865 Mips_JALS_MM, MIPS_INS_JALS,
4866 #ifndef CAPSTONE_DIET
4867 { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4868 #endif
4869 },
4870 {
4871 Mips_JALX, MIPS_INS_JALX,
4872 #ifndef CAPSTONE_DIET
4873 { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
4874 #endif
4875 },
4876 {
4877 Mips_JAL_MM, MIPS_INS_JAL,
4878 #ifndef CAPSTONE_DIET
4879 { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4880 #endif
4881 },
4882 {
4883 Mips_JIALC, MIPS_INS_JIALC,
4884 #ifndef CAPSTONE_DIET
4885 { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
4886 #endif
4887 },
4888 {
4889 Mips_JIC, MIPS_INS_JIC,
4890 #ifndef CAPSTONE_DIET
4891 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
4892 #endif
4893 },
4894 {
4895 Mips_JR, MIPS_INS_JR,
4896 #ifndef CAPSTONE_DIET
4897 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 1, 1
4898 #endif
4899 },
4900 {
4901 Mips_JR64, MIPS_INS_JR,
4902 #ifndef CAPSTONE_DIET
4903 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 1, 1
4904 #endif
4905 },
4906 {
4907 Mips_JRADDIUSP, MIPS_INS_JRADDIUSP,
4908 #ifndef CAPSTONE_DIET
4909 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1
4910 #endif
4911 },
4912 {
4913 Mips_JR_HB, MIPS_INS_JR_HB,
4914 #ifndef CAPSTONE_DIET
4915 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 1
4916 #endif
4917 },
4918 {
4919 Mips_JR_HB_R6, MIPS_INS_JR_HB,
4920 #ifndef CAPSTONE_DIET
4921 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 1
4922 #endif
4923 },
4924 {
4925 Mips_JR_MM, MIPS_INS_JR,
4926 #ifndef CAPSTONE_DIET
4927 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1
4928 #endif
4929 },
4930 {
4931 Mips_J_MM, MIPS_INS_J,
4932 #ifndef CAPSTONE_DIET
4933 { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4934 #endif
4935 },
4936 {
4937 Mips_Jal16, MIPS_INS_JAL,
4938 #ifndef CAPSTONE_DIET
4939 { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
4940 #endif
4941 },
4942 {
4943 Mips_JrRa16, MIPS_INS_JR,
4944 #ifndef CAPSTONE_DIET
4945 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1
4946 #endif
4947 },
4948 {
4949 Mips_JrcRa16, MIPS_INS_JRC,
4950 #ifndef CAPSTONE_DIET
4951 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1
4952 #endif
4953 },
4954 {
4955 Mips_JrcRx16, MIPS_INS_JRC,
4956 #ifndef CAPSTONE_DIET
4957 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1
4958 #endif
4959 },
4960 {
4961 Mips_JumpLinkReg16, MIPS_INS_JALRC,
4962 #ifndef CAPSTONE_DIET
4963 { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
4964 #endif
4965 },
4966 {
4967 Mips_LB, MIPS_INS_LB,
4968 #ifndef CAPSTONE_DIET
4969 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
4970 #endif
4971 },
4972 {
4973 Mips_LB64, MIPS_INS_LB,
4974 #ifndef CAPSTONE_DIET
4975 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
4976 #endif
4977 },
4978 {
4979 Mips_LBUX, MIPS_INS_LBUX,
4980 #ifndef CAPSTONE_DIET
4981 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
4982 #endif
4983 },
4984 {
4985 Mips_LB_MM, MIPS_INS_LB,
4986 #ifndef CAPSTONE_DIET
4987 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4988 #endif
4989 },
4990 {
4991 Mips_LBu, MIPS_INS_LBU,
4992 #ifndef CAPSTONE_DIET
4993 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
4994 #endif
4995 },
4996 {
4997 Mips_LBu64, MIPS_INS_LBU,
4998 #ifndef CAPSTONE_DIET
4999 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5000 #endif
5001 },
5002 {
5003 Mips_LBu_MM, MIPS_INS_LBU,
5004 #ifndef CAPSTONE_DIET
5005 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5006 #endif
5007 },
5008 {
5009 Mips_LD, MIPS_INS_LD,
5010 #ifndef CAPSTONE_DIET
5011 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
5012 #endif
5013 },
5014 {
5015 Mips_LDC1, MIPS_INS_LDC1,
5016 #ifndef CAPSTONE_DIET
5017 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0
5018 #endif
5019 },
5020 {
5021 Mips_LDC164, MIPS_INS_LDC1,
5022 #ifndef CAPSTONE_DIET
5023 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0
5024 #endif
5025 },
5026 {
5027 Mips_LDC1_MM, MIPS_INS_LDC1,
5028 #ifndef CAPSTONE_DIET
5029 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5030 #endif
5031 },
5032 {
5033 Mips_LDC2, MIPS_INS_LDC2,
5034 #ifndef CAPSTONE_DIET
5035 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
5036 #endif
5037 },
5038 {
5039 Mips_LDC2_R6, MIPS_INS_LDC2,
5040 #ifndef CAPSTONE_DIET
5041 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5042 #endif
5043 },
5044 {
5045 Mips_LDC3, MIPS_INS_LDC3,
5046 #ifndef CAPSTONE_DIET
5047 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
5048 #endif
5049 },
5050 {
5051 Mips_LDI_B, MIPS_INS_LDI,
5052 #ifndef CAPSTONE_DIET
5053 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5054 #endif
5055 },
5056 {
5057 Mips_LDI_D, MIPS_INS_LDI,
5058 #ifndef CAPSTONE_DIET
5059 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5060 #endif
5061 },
5062 {
5063 Mips_LDI_H, MIPS_INS_LDI,
5064 #ifndef CAPSTONE_DIET
5065 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5066 #endif
5067 },
5068 {
5069 Mips_LDI_W, MIPS_INS_LDI,
5070 #ifndef CAPSTONE_DIET
5071 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5072 #endif
5073 },
5074 {
5075 Mips_LDL, MIPS_INS_LDL,
5076 #ifndef CAPSTONE_DIET
5077 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
5078 #endif
5079 },
5080 {
5081 Mips_LDPC, MIPS_INS_LDPC,
5082 #ifndef CAPSTONE_DIET
5083 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
5084 #endif
5085 },
5086 {
5087 Mips_LDR, MIPS_INS_LDR,
5088 #ifndef CAPSTONE_DIET
5089 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
5090 #endif
5091 },
5092 {
5093 Mips_LDXC1, MIPS_INS_LDXC1,
5094 #ifndef CAPSTONE_DIET
5095 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_NOTNACL, 0 }, 0, 0
5096 #endif
5097 },
5098 {
5099 Mips_LDXC164, MIPS_INS_LDXC1,
5100 #ifndef CAPSTONE_DIET
5101 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
5102 #endif
5103 },
5104 {
5105 Mips_LD_B, MIPS_INS_LD,
5106 #ifndef CAPSTONE_DIET
5107 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5108 #endif
5109 },
5110 {
5111 Mips_LD_D, MIPS_INS_LD,
5112 #ifndef CAPSTONE_DIET
5113 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5114 #endif
5115 },
5116 {
5117 Mips_LD_H, MIPS_INS_LD,
5118 #ifndef CAPSTONE_DIET
5119 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5120 #endif
5121 },
5122 {
5123 Mips_LD_W, MIPS_INS_LD,
5124 #ifndef CAPSTONE_DIET
5125 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5126 #endif
5127 },
5128 {
5129 Mips_LEA_ADDiu, MIPS_INS_ADDIU,
5130 #ifndef CAPSTONE_DIET
5131 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5132 #endif
5133 },
5134 {
5135 Mips_LEA_ADDiu64, MIPS_INS_DADDIU,
5136 #ifndef CAPSTONE_DIET
5137 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5138 #endif
5139 },
5140 {
5141 Mips_LEA_ADDiu_MM, MIPS_INS_ADDIU,
5142 #ifndef CAPSTONE_DIET
5143 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5144 #endif
5145 },
5146 {
5147 Mips_LH, MIPS_INS_LH,
5148 #ifndef CAPSTONE_DIET
5149 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5150 #endif
5151 },
5152 {
5153 Mips_LH64, MIPS_INS_LH,
5154 #ifndef CAPSTONE_DIET
5155 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5156 #endif
5157 },
5158 {
5159 Mips_LHX, MIPS_INS_LHX,
5160 #ifndef CAPSTONE_DIET
5161 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
5162 #endif
5163 },
5164 {
5165 Mips_LH_MM, MIPS_INS_LH,
5166 #ifndef CAPSTONE_DIET
5167 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5168 #endif
5169 },
5170 {
5171 Mips_LHu, MIPS_INS_LHU,
5172 #ifndef CAPSTONE_DIET
5173 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5174 #endif
5175 },
5176 {
5177 Mips_LHu64, MIPS_INS_LHU,
5178 #ifndef CAPSTONE_DIET
5179 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5180 #endif
5181 },
5182 {
5183 Mips_LHu_MM, MIPS_INS_LHU,
5184 #ifndef CAPSTONE_DIET
5185 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5186 #endif
5187 },
5188 {
5189 Mips_LL, MIPS_INS_LL,
5190 #ifndef CAPSTONE_DIET
5191 { 0 }, { 0 }, { MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
5192 #endif
5193 },
5194 {
5195 Mips_LLD, MIPS_INS_LLD,
5196 #ifndef CAPSTONE_DIET
5197 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
5198 #endif
5199 },
5200 {
5201 Mips_LLD_R6, MIPS_INS_LLD,
5202 #ifndef CAPSTONE_DIET
5203 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5204 #endif
5205 },
5206 {
5207 Mips_LL_MM, MIPS_INS_LL,
5208 #ifndef CAPSTONE_DIET
5209 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5210 #endif
5211 },
5212 {
5213 Mips_LL_R6, MIPS_INS_LL,
5214 #ifndef CAPSTONE_DIET
5215 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5216 #endif
5217 },
5218 {
5219 Mips_LSA, MIPS_INS_LSA,
5220 #ifndef CAPSTONE_DIET
5221 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5222 #endif
5223 },
5224 {
5225 Mips_LSA_R6, MIPS_INS_LSA,
5226 #ifndef CAPSTONE_DIET
5227 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5228 #endif
5229 },
5230 {
5231 Mips_LUXC1, MIPS_INS_LUXC1,
5232 #ifndef CAPSTONE_DIET
5233 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0
5234 #endif
5235 },
5236 {
5237 Mips_LUXC164, MIPS_INS_LUXC1,
5238 #ifndef CAPSTONE_DIET
5239 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
5240 #endif
5241 },
5242 {
5243 Mips_LUXC1_MM, MIPS_INS_LUXC1,
5244 #ifndef CAPSTONE_DIET
5245 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5246 #endif
5247 },
5248 {
5249 Mips_LUi, MIPS_INS_LUI,
5250 #ifndef CAPSTONE_DIET
5251 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5252 #endif
5253 },
5254 {
5255 Mips_LUi64, MIPS_INS_LUI,
5256 #ifndef CAPSTONE_DIET
5257 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5258 #endif
5259 },
5260 {
5261 Mips_LUi_MM, MIPS_INS_LUI,
5262 #ifndef CAPSTONE_DIET
5263 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5264 #endif
5265 },
5266 {
5267 Mips_LW, MIPS_INS_LW,
5268 #ifndef CAPSTONE_DIET
5269 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5270 #endif
5271 },
5272 {
5273 Mips_LW64, MIPS_INS_LW,
5274 #ifndef CAPSTONE_DIET
5275 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5276 #endif
5277 },
5278 {
5279 Mips_LWC1, MIPS_INS_LWC1,
5280 #ifndef CAPSTONE_DIET
5281 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5282 #endif
5283 },
5284 {
5285 Mips_LWC1_MM, MIPS_INS_LWC1,
5286 #ifndef CAPSTONE_DIET
5287 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5288 #endif
5289 },
5290 {
5291 Mips_LWC2, MIPS_INS_LWC2,
5292 #ifndef CAPSTONE_DIET
5293 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
5294 #endif
5295 },
5296 {
5297 Mips_LWC2_R6, MIPS_INS_LWC2,
5298 #ifndef CAPSTONE_DIET
5299 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5300 #endif
5301 },
5302 {
5303 Mips_LWC3, MIPS_INS_LWC3,
5304 #ifndef CAPSTONE_DIET
5305 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5306 #endif
5307 },
5308 {
5309 Mips_LWL, MIPS_INS_LWL,
5310 #ifndef CAPSTONE_DIET
5311 { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
5312 #endif
5313 },
5314 {
5315 Mips_LWL64, MIPS_INS_LWL,
5316 #ifndef CAPSTONE_DIET
5317 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5318 #endif
5319 },
5320 {
5321 Mips_LWL_MM, MIPS_INS_LWL,
5322 #ifndef CAPSTONE_DIET
5323 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5324 #endif
5325 },
5326 {
5327 Mips_LWPC, MIPS_INS_LWPC,
5328 #ifndef CAPSTONE_DIET
5329 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5330 #endif
5331 },
5332 {
5333 Mips_LWR, MIPS_INS_LWR,
5334 #ifndef CAPSTONE_DIET
5335 { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
5336 #endif
5337 },
5338 {
5339 Mips_LWR64, MIPS_INS_LWR,
5340 #ifndef CAPSTONE_DIET
5341 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5342 #endif
5343 },
5344 {
5345 Mips_LWR_MM, MIPS_INS_LWR,
5346 #ifndef CAPSTONE_DIET
5347 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5348 #endif
5349 },
5350 {
5351 Mips_LWUPC, MIPS_INS_LWUPC,
5352 #ifndef CAPSTONE_DIET
5353 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5354 #endif
5355 },
5356 {
5357 Mips_LWU_MM, MIPS_INS_LWU,
5358 #ifndef CAPSTONE_DIET
5359 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5360 #endif
5361 },
5362 {
5363 Mips_LWX, MIPS_INS_LWX,
5364 #ifndef CAPSTONE_DIET
5365 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
5366 #endif
5367 },
5368 {
5369 Mips_LWXC1, MIPS_INS_LWXC1,
5370 #ifndef CAPSTONE_DIET
5371 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0
5372 #endif
5373 },
5374 {
5375 Mips_LWXC1_MM, MIPS_INS_LWXC1,
5376 #ifndef CAPSTONE_DIET
5377 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5378 #endif
5379 },
5380 {
5381 Mips_LW_MM, MIPS_INS_LW,
5382 #ifndef CAPSTONE_DIET
5383 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5384 #endif
5385 },
5386 {
5387 Mips_LWu, MIPS_INS_LWU,
5388 #ifndef CAPSTONE_DIET
5389 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
5390 #endif
5391 },
5392 {
5393 Mips_LbRxRyOffMemX16, MIPS_INS_LB,
5394 #ifndef CAPSTONE_DIET
5395 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
5396 #endif
5397 },
5398 {
5399 Mips_LbuRxRyOffMemX16, MIPS_INS_LBU,
5400 #ifndef CAPSTONE_DIET
5401 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
5402 #endif
5403 },
5404 {
5405 Mips_LhRxRyOffMemX16, MIPS_INS_LH,
5406 #ifndef CAPSTONE_DIET
5407 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
5408 #endif
5409 },
5410 {
5411 Mips_LhuRxRyOffMemX16, MIPS_INS_LHU,
5412 #ifndef CAPSTONE_DIET
5413 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
5414 #endif
5415 },
5416 {
5417 Mips_LiRxImm16, MIPS_INS_LI,
5418 #ifndef CAPSTONE_DIET
5419 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
5420 #endif
5421 },
5422 {
5423 Mips_LiRxImmX16, MIPS_INS_LI,
5424 #ifndef CAPSTONE_DIET
5425 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
5426 #endif
5427 },
5428 {
5429 Mips_LwRxPcTcp16, MIPS_INS_LW,
5430 #ifndef CAPSTONE_DIET
5431 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
5432 #endif
5433 },
5434 {
5435 Mips_LwRxPcTcpX16, MIPS_INS_LW,
5436 #ifndef CAPSTONE_DIET
5437 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
5438 #endif
5439 },
5440 {
5441 Mips_LwRxRyOffMemX16, MIPS_INS_LW,
5442 #ifndef CAPSTONE_DIET
5443 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
5444 #endif
5445 },
5446 {
5447 Mips_LwRxSpImmX16, MIPS_INS_LW,
5448 #ifndef CAPSTONE_DIET
5449 { MIPS_REG_SP, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
5450 #endif
5451 },
5452 {
5453 Mips_MADD, MIPS_INS_MADD,
5454 #ifndef CAPSTONE_DIET
5455 { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
5456 #endif
5457 },
5458 {
5459 Mips_MADDF_D, MIPS_INS_MADDF,
5460 #ifndef CAPSTONE_DIET
5461 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5462 #endif
5463 },
5464 {
5465 Mips_MADDF_S, MIPS_INS_MADDF,
5466 #ifndef CAPSTONE_DIET
5467 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5468 #endif
5469 },
5470 {
5471 Mips_MADDR_Q_H, MIPS_INS_MADDR_Q,
5472 #ifndef CAPSTONE_DIET
5473 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5474 #endif
5475 },
5476 {
5477 Mips_MADDR_Q_W, MIPS_INS_MADDR_Q,
5478 #ifndef CAPSTONE_DIET
5479 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5480 #endif
5481 },
5482 {
5483 Mips_MADDU, MIPS_INS_MADDU,
5484 #ifndef CAPSTONE_DIET
5485 { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
5486 #endif
5487 },
5488 {
5489 Mips_MADDU_DSP, MIPS_INS_MADDU,
5490 #ifndef CAPSTONE_DIET
5491 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
5492 #endif
5493 },
5494 {
5495 Mips_MADDU_MM, MIPS_INS_MADDU,
5496 #ifndef CAPSTONE_DIET
5497 { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5498 #endif
5499 },
5500 {
5501 Mips_MADDV_B, MIPS_INS_MADDV,
5502 #ifndef CAPSTONE_DIET
5503 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5504 #endif
5505 },
5506 {
5507 Mips_MADDV_D, MIPS_INS_MADDV,
5508 #ifndef CAPSTONE_DIET
5509 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5510 #endif
5511 },
5512 {
5513 Mips_MADDV_H, MIPS_INS_MADDV,
5514 #ifndef CAPSTONE_DIET
5515 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5516 #endif
5517 },
5518 {
5519 Mips_MADDV_W, MIPS_INS_MADDV,
5520 #ifndef CAPSTONE_DIET
5521 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5522 #endif
5523 },
5524 {
5525 Mips_MADD_D32, MIPS_INS_MADD,
5526 #ifndef CAPSTONE_DIET
5527 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
5528 #endif
5529 },
5530 {
5531 Mips_MADD_D32_MM, MIPS_INS_MADD,
5532 #ifndef CAPSTONE_DIET
5533 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5534 #endif
5535 },
5536 {
5537 Mips_MADD_D64, MIPS_INS_MADD,
5538 #ifndef CAPSTONE_DIET
5539 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
5540 #endif
5541 },
5542 {
5543 Mips_MADD_DSP, MIPS_INS_MADD,
5544 #ifndef CAPSTONE_DIET
5545 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
5546 #endif
5547 },
5548 {
5549 Mips_MADD_MM, MIPS_INS_MADD,
5550 #ifndef CAPSTONE_DIET
5551 { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5552 #endif
5553 },
5554 {
5555 Mips_MADD_Q_H, MIPS_INS_MADD_Q,
5556 #ifndef CAPSTONE_DIET
5557 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5558 #endif
5559 },
5560 {
5561 Mips_MADD_Q_W, MIPS_INS_MADD_Q,
5562 #ifndef CAPSTONE_DIET
5563 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5564 #endif
5565 },
5566 {
5567 Mips_MADD_S, MIPS_INS_MADD,
5568 #ifndef CAPSTONE_DIET
5569 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
5570 #endif
5571 },
5572 {
5573 Mips_MADD_S_MM, MIPS_INS_MADD,
5574 #ifndef CAPSTONE_DIET
5575 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5576 #endif
5577 },
5578 {
5579 Mips_MAQ_SA_W_PHL, MIPS_INS_MAQ_SA,
5580 #ifndef CAPSTONE_DIET
5581 { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
5582 #endif
5583 },
5584 {
5585 Mips_MAQ_SA_W_PHR, MIPS_INS_MAQ_SA,
5586 #ifndef CAPSTONE_DIET
5587 { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
5588 #endif
5589 },
5590 {
5591 Mips_MAQ_S_W_PHL, MIPS_INS_MAQ_S,
5592 #ifndef CAPSTONE_DIET
5593 { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
5594 #endif
5595 },
5596 {
5597 Mips_MAQ_S_W_PHR, MIPS_INS_MAQ_S,
5598 #ifndef CAPSTONE_DIET
5599 { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
5600 #endif
5601 },
5602 {
5603 Mips_MAXA_D, MIPS_INS_MAXA,
5604 #ifndef CAPSTONE_DIET
5605 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5606 #endif
5607 },
5608 {
5609 Mips_MAXA_S, MIPS_INS_MAXA,
5610 #ifndef CAPSTONE_DIET
5611 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5612 #endif
5613 },
5614 {
5615 Mips_MAXI_S_B, MIPS_INS_MAXI_S,
5616 #ifndef CAPSTONE_DIET
5617 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5618 #endif
5619 },
5620 {
5621 Mips_MAXI_S_D, MIPS_INS_MAXI_S,
5622 #ifndef CAPSTONE_DIET
5623 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5624 #endif
5625 },
5626 {
5627 Mips_MAXI_S_H, MIPS_INS_MAXI_S,
5628 #ifndef CAPSTONE_DIET
5629 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5630 #endif
5631 },
5632 {
5633 Mips_MAXI_S_W, MIPS_INS_MAXI_S,
5634 #ifndef CAPSTONE_DIET
5635 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5636 #endif
5637 },
5638 {
5639 Mips_MAXI_U_B, MIPS_INS_MAXI_U,
5640 #ifndef CAPSTONE_DIET
5641 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5642 #endif
5643 },
5644 {
5645 Mips_MAXI_U_D, MIPS_INS_MAXI_U,
5646 #ifndef CAPSTONE_DIET
5647 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5648 #endif
5649 },
5650 {
5651 Mips_MAXI_U_H, MIPS_INS_MAXI_U,
5652 #ifndef CAPSTONE_DIET
5653 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5654 #endif
5655 },
5656 {
5657 Mips_MAXI_U_W, MIPS_INS_MAXI_U,
5658 #ifndef CAPSTONE_DIET
5659 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5660 #endif
5661 },
5662 {
5663 Mips_MAX_A_B, MIPS_INS_MAX_A,
5664 #ifndef CAPSTONE_DIET
5665 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5666 #endif
5667 },
5668 {
5669 Mips_MAX_A_D, MIPS_INS_MAX_A,
5670 #ifndef CAPSTONE_DIET
5671 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5672 #endif
5673 },
5674 {
5675 Mips_MAX_A_H, MIPS_INS_MAX_A,
5676 #ifndef CAPSTONE_DIET
5677 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5678 #endif
5679 },
5680 {
5681 Mips_MAX_A_W, MIPS_INS_MAX_A,
5682 #ifndef CAPSTONE_DIET
5683 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5684 #endif
5685 },
5686 {
5687 Mips_MAX_D, MIPS_INS_MAX,
5688 #ifndef CAPSTONE_DIET
5689 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5690 #endif
5691 },
5692 {
5693 Mips_MAX_S, MIPS_INS_MAX,
5694 #ifndef CAPSTONE_DIET
5695 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5696 #endif
5697 },
5698 {
5699 Mips_MAX_S_B, MIPS_INS_MAX_S,
5700 #ifndef CAPSTONE_DIET
5701 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5702 #endif
5703 },
5704 {
5705 Mips_MAX_S_D, MIPS_INS_MAX_S,
5706 #ifndef CAPSTONE_DIET
5707 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5708 #endif
5709 },
5710 {
5711 Mips_MAX_S_H, MIPS_INS_MAX_S,
5712 #ifndef CAPSTONE_DIET
5713 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5714 #endif
5715 },
5716 {
5717 Mips_MAX_S_W, MIPS_INS_MAX_S,
5718 #ifndef CAPSTONE_DIET
5719 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5720 #endif
5721 },
5722 {
5723 Mips_MAX_U_B, MIPS_INS_MAX_U,
5724 #ifndef CAPSTONE_DIET
5725 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5726 #endif
5727 },
5728 {
5729 Mips_MAX_U_D, MIPS_INS_MAX_U,
5730 #ifndef CAPSTONE_DIET
5731 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5732 #endif
5733 },
5734 {
5735 Mips_MAX_U_H, MIPS_INS_MAX_U,
5736 #ifndef CAPSTONE_DIET
5737 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5738 #endif
5739 },
5740 {
5741 Mips_MAX_U_W, MIPS_INS_MAX_U,
5742 #ifndef CAPSTONE_DIET
5743 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5744 #endif
5745 },
5746 {
5747 Mips_MFC0, MIPS_INS_MFC0,
5748 #ifndef CAPSTONE_DIET
5749 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0
5750 #endif
5751 },
5752 {
5753 Mips_MFC1, MIPS_INS_MFC1,
5754 #ifndef CAPSTONE_DIET
5755 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5756 #endif
5757 },
5758 {
5759 Mips_MFC1_MM, MIPS_INS_MFC1,
5760 #ifndef CAPSTONE_DIET
5761 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5762 #endif
5763 },
5764 {
5765 Mips_MFC2, MIPS_INS_MFC2,
5766 #ifndef CAPSTONE_DIET
5767 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5768 #endif
5769 },
5770 {
5771 Mips_MFHC1_D32, MIPS_INS_MFHC1,
5772 #ifndef CAPSTONE_DIET
5773 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
5774 #endif
5775 },
5776 {
5777 Mips_MFHC1_D64, MIPS_INS_MFHC1,
5778 #ifndef CAPSTONE_DIET
5779 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_FP64BIT, 0 }, 0, 0
5780 #endif
5781 },
5782 {
5783 Mips_MFHC1_MM, MIPS_INS_MFHC1,
5784 #ifndef CAPSTONE_DIET
5785 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5786 #endif
5787 },
5788 {
5789 Mips_MFHI, MIPS_INS_MFHI,
5790 #ifndef CAPSTONE_DIET
5791 { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
5792 #endif
5793 },
5794 {
5795 Mips_MFHI16_MM, MIPS_INS_MFHI,
5796 #ifndef CAPSTONE_DIET
5797 { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5798 #endif
5799 },
5800 {
5801 Mips_MFHI64, MIPS_INS_MFHI,
5802 #ifndef CAPSTONE_DIET
5803 { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
5804 #endif
5805 },
5806 {
5807 Mips_MFHI_DSP, MIPS_INS_MFHI,
5808 #ifndef CAPSTONE_DIET
5809 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
5810 #endif
5811 },
5812 {
5813 Mips_MFHI_MM, MIPS_INS_MFHI,
5814 #ifndef CAPSTONE_DIET
5815 { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5816 #endif
5817 },
5818 {
5819 Mips_MFLO, MIPS_INS_MFLO,
5820 #ifndef CAPSTONE_DIET
5821 { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
5822 #endif
5823 },
5824 {
5825 Mips_MFLO16_MM, MIPS_INS_MFLO,
5826 #ifndef CAPSTONE_DIET
5827 { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5828 #endif
5829 },
5830 {
5831 Mips_MFLO64, MIPS_INS_MFLO,
5832 #ifndef CAPSTONE_DIET
5833 { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
5834 #endif
5835 },
5836 {
5837 Mips_MFLO_DSP, MIPS_INS_MFLO,
5838 #ifndef CAPSTONE_DIET
5839 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
5840 #endif
5841 },
5842 {
5843 Mips_MFLO_MM, MIPS_INS_MFLO,
5844 #ifndef CAPSTONE_DIET
5845 { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5846 #endif
5847 },
5848 {
5849 Mips_MINA_D, MIPS_INS_MINA,
5850 #ifndef CAPSTONE_DIET
5851 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5852 #endif
5853 },
5854 {
5855 Mips_MINA_S, MIPS_INS_MINA,
5856 #ifndef CAPSTONE_DIET
5857 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5858 #endif
5859 },
5860 {
5861 Mips_MINI_S_B, MIPS_INS_MINI_S,
5862 #ifndef CAPSTONE_DIET
5863 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5864 #endif
5865 },
5866 {
5867 Mips_MINI_S_D, MIPS_INS_MINI_S,
5868 #ifndef CAPSTONE_DIET
5869 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5870 #endif
5871 },
5872 {
5873 Mips_MINI_S_H, MIPS_INS_MINI_S,
5874 #ifndef CAPSTONE_DIET
5875 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5876 #endif
5877 },
5878 {
5879 Mips_MINI_S_W, MIPS_INS_MINI_S,
5880 #ifndef CAPSTONE_DIET
5881 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5882 #endif
5883 },
5884 {
5885 Mips_MINI_U_B, MIPS_INS_MINI_U,
5886 #ifndef CAPSTONE_DIET
5887 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5888 #endif
5889 },
5890 {
5891 Mips_MINI_U_D, MIPS_INS_MINI_U,
5892 #ifndef CAPSTONE_DIET
5893 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5894 #endif
5895 },
5896 {
5897 Mips_MINI_U_H, MIPS_INS_MINI_U,
5898 #ifndef CAPSTONE_DIET
5899 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5900 #endif
5901 },
5902 {
5903 Mips_MINI_U_W, MIPS_INS_MINI_U,
5904 #ifndef CAPSTONE_DIET
5905 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5906 #endif
5907 },
5908 {
5909 Mips_MIN_A_B, MIPS_INS_MIN_A,
5910 #ifndef CAPSTONE_DIET
5911 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5912 #endif
5913 },
5914 {
5915 Mips_MIN_A_D, MIPS_INS_MIN_A,
5916 #ifndef CAPSTONE_DIET
5917 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5918 #endif
5919 },
5920 {
5921 Mips_MIN_A_H, MIPS_INS_MIN_A,
5922 #ifndef CAPSTONE_DIET
5923 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5924 #endif
5925 },
5926 {
5927 Mips_MIN_A_W, MIPS_INS_MIN_A,
5928 #ifndef CAPSTONE_DIET
5929 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5930 #endif
5931 },
5932 {
5933 Mips_MIN_D, MIPS_INS_MIN,
5934 #ifndef CAPSTONE_DIET
5935 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5936 #endif
5937 },
5938 {
5939 Mips_MIN_S, MIPS_INS_MIN,
5940 #ifndef CAPSTONE_DIET
5941 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5942 #endif
5943 },
5944 {
5945 Mips_MIN_S_B, MIPS_INS_MIN_S,
5946 #ifndef CAPSTONE_DIET
5947 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5948 #endif
5949 },
5950 {
5951 Mips_MIN_S_D, MIPS_INS_MIN_S,
5952 #ifndef CAPSTONE_DIET
5953 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5954 #endif
5955 },
5956 {
5957 Mips_MIN_S_H, MIPS_INS_MIN_S,
5958 #ifndef CAPSTONE_DIET
5959 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5960 #endif
5961 },
5962 {
5963 Mips_MIN_S_W, MIPS_INS_MIN_S,
5964 #ifndef CAPSTONE_DIET
5965 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5966 #endif
5967 },
5968 {
5969 Mips_MIN_U_B, MIPS_INS_MIN_U,
5970 #ifndef CAPSTONE_DIET
5971 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5972 #endif
5973 },
5974 {
5975 Mips_MIN_U_D, MIPS_INS_MIN_U,
5976 #ifndef CAPSTONE_DIET
5977 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5978 #endif
5979 },
5980 {
5981 Mips_MIN_U_H, MIPS_INS_MIN_U,
5982 #ifndef CAPSTONE_DIET
5983 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5984 #endif
5985 },
5986 {
5987 Mips_MIN_U_W, MIPS_INS_MIN_U,
5988 #ifndef CAPSTONE_DIET
5989 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5990 #endif
5991 },
5992 {
5993 Mips_MOD, MIPS_INS_MOD,
5994 #ifndef CAPSTONE_DIET
5995 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5996 #endif
5997 },
5998 {
5999 Mips_MODSUB, MIPS_INS_MODSUB,
6000 #ifndef CAPSTONE_DIET
6001 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
6002 #endif
6003 },
6004 {
6005 Mips_MODU, MIPS_INS_MODU,
6006 #ifndef CAPSTONE_DIET
6007 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
6008 #endif
6009 },
6010 {
6011 Mips_MOD_S_B, MIPS_INS_MOD_S,
6012 #ifndef CAPSTONE_DIET
6013 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6014 #endif
6015 },
6016 {
6017 Mips_MOD_S_D, MIPS_INS_MOD_S,
6018 #ifndef CAPSTONE_DIET
6019 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6020 #endif
6021 },
6022 {
6023 Mips_MOD_S_H, MIPS_INS_MOD_S,
6024 #ifndef CAPSTONE_DIET
6025 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6026 #endif
6027 },
6028 {
6029 Mips_MOD_S_W, MIPS_INS_MOD_S,
6030 #ifndef CAPSTONE_DIET
6031 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6032 #endif
6033 },
6034 {
6035 Mips_MOD_U_B, MIPS_INS_MOD_U,
6036 #ifndef CAPSTONE_DIET
6037 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6038 #endif
6039 },
6040 {
6041 Mips_MOD_U_D, MIPS_INS_MOD_U,
6042 #ifndef CAPSTONE_DIET
6043 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6044 #endif
6045 },
6046 {
6047 Mips_MOD_U_H, MIPS_INS_MOD_U,
6048 #ifndef CAPSTONE_DIET
6049 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6050 #endif
6051 },
6052 {
6053 Mips_MOD_U_W, MIPS_INS_MOD_U,
6054 #ifndef CAPSTONE_DIET
6055 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6056 #endif
6057 },
6058 {
6059 Mips_MOVE16_MM, MIPS_INS_MOVE,
6060 #ifndef CAPSTONE_DIET
6061 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6062 #endif
6063 },
6064 {
6065 Mips_MOVE_V, MIPS_INS_MOVE,
6066 #ifndef CAPSTONE_DIET
6067 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6068 #endif
6069 },
6070 {
6071 Mips_MOVF_D32, MIPS_INS_MOVF,
6072 #ifndef CAPSTONE_DIET
6073 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6074 #endif
6075 },
6076 {
6077 Mips_MOVF_D32_MM, MIPS_INS_MOVF,
6078 #ifndef CAPSTONE_DIET
6079 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6080 #endif
6081 },
6082 {
6083 Mips_MOVF_D64, MIPS_INS_MOVF,
6084 #ifndef CAPSTONE_DIET
6085 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6086 #endif
6087 },
6088 {
6089 Mips_MOVF_I, MIPS_INS_MOVF,
6090 #ifndef CAPSTONE_DIET
6091 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6092 #endif
6093 },
6094 {
6095 Mips_MOVF_I64, MIPS_INS_MOVF,
6096 #ifndef CAPSTONE_DIET
6097 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_GP64BIT, 0 }, 0, 0
6098 #endif
6099 },
6100 {
6101 Mips_MOVF_I_MM, MIPS_INS_MOVF,
6102 #ifndef CAPSTONE_DIET
6103 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6104 #endif
6105 },
6106 {
6107 Mips_MOVF_S, MIPS_INS_MOVF,
6108 #ifndef CAPSTONE_DIET
6109 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6110 #endif
6111 },
6112 {
6113 Mips_MOVF_S_MM, MIPS_INS_MOVF,
6114 #ifndef CAPSTONE_DIET
6115 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6116 #endif
6117 },
6118 {
6119 Mips_MOVN_I64_D64, MIPS_INS_MOVN,
6120 #ifndef CAPSTONE_DIET
6121 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6122 #endif
6123 },
6124 {
6125 Mips_MOVN_I64_I, MIPS_INS_MOVN,
6126 #ifndef CAPSTONE_DIET
6127 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6128 #endif
6129 },
6130 {
6131 Mips_MOVN_I64_I64, MIPS_INS_MOVN,
6132 #ifndef CAPSTONE_DIET
6133 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6134 #endif
6135 },
6136 {
6137 Mips_MOVN_I64_S, MIPS_INS_MOVN,
6138 #ifndef CAPSTONE_DIET
6139 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_GP64BIT, 0 }, 0, 0
6140 #endif
6141 },
6142 {
6143 Mips_MOVN_I_D32, MIPS_INS_MOVN,
6144 #ifndef CAPSTONE_DIET
6145 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6146 #endif
6147 },
6148 {
6149 Mips_MOVN_I_D32_MM, MIPS_INS_MOVN,
6150 #ifndef CAPSTONE_DIET
6151 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6152 #endif
6153 },
6154 {
6155 Mips_MOVN_I_D64, MIPS_INS_MOVN,
6156 #ifndef CAPSTONE_DIET
6157 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6158 #endif
6159 },
6160 {
6161 Mips_MOVN_I_I, MIPS_INS_MOVN,
6162 #ifndef CAPSTONE_DIET
6163 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6164 #endif
6165 },
6166 {
6167 Mips_MOVN_I_I64, MIPS_INS_MOVN,
6168 #ifndef CAPSTONE_DIET
6169 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6170 #endif
6171 },
6172 {
6173 Mips_MOVN_I_MM, MIPS_INS_MOVN,
6174 #ifndef CAPSTONE_DIET
6175 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6176 #endif
6177 },
6178 {
6179 Mips_MOVN_I_S, MIPS_INS_MOVN,
6180 #ifndef CAPSTONE_DIET
6181 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6182 #endif
6183 },
6184 {
6185 Mips_MOVN_I_S_MM, MIPS_INS_MOVN,
6186 #ifndef CAPSTONE_DIET
6187 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6188 #endif
6189 },
6190 {
6191 Mips_MOVT_D32, MIPS_INS_MOVT,
6192 #ifndef CAPSTONE_DIET
6193 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6194 #endif
6195 },
6196 {
6197 Mips_MOVT_D32_MM, MIPS_INS_MOVT,
6198 #ifndef CAPSTONE_DIET
6199 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6200 #endif
6201 },
6202 {
6203 Mips_MOVT_D64, MIPS_INS_MOVT,
6204 #ifndef CAPSTONE_DIET
6205 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6206 #endif
6207 },
6208 {
6209 Mips_MOVT_I, MIPS_INS_MOVT,
6210 #ifndef CAPSTONE_DIET
6211 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6212 #endif
6213 },
6214 {
6215 Mips_MOVT_I64, MIPS_INS_MOVT,
6216 #ifndef CAPSTONE_DIET
6217 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_GP64BIT, 0 }, 0, 0
6218 #endif
6219 },
6220 {
6221 Mips_MOVT_I_MM, MIPS_INS_MOVT,
6222 #ifndef CAPSTONE_DIET
6223 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6224 #endif
6225 },
6226 {
6227 Mips_MOVT_S, MIPS_INS_MOVT,
6228 #ifndef CAPSTONE_DIET
6229 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6230 #endif
6231 },
6232 {
6233 Mips_MOVT_S_MM, MIPS_INS_MOVT,
6234 #ifndef CAPSTONE_DIET
6235 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6236 #endif
6237 },
6238 {
6239 Mips_MOVZ_I64_D64, MIPS_INS_MOVZ,
6240 #ifndef CAPSTONE_DIET
6241 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6242 #endif
6243 },
6244 {
6245 Mips_MOVZ_I64_I, MIPS_INS_MOVZ,
6246 #ifndef CAPSTONE_DIET
6247 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6248 #endif
6249 },
6250 {
6251 Mips_MOVZ_I64_I64, MIPS_INS_MOVZ,
6252 #ifndef CAPSTONE_DIET
6253 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6254 #endif
6255 },
6256 {
6257 Mips_MOVZ_I64_S, MIPS_INS_MOVZ,
6258 #ifndef CAPSTONE_DIET
6259 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_MIPS64, 0 }, 0, 0
6260 #endif
6261 },
6262 {
6263 Mips_MOVZ_I_D32, MIPS_INS_MOVZ,
6264 #ifndef CAPSTONE_DIET
6265 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6266 #endif
6267 },
6268 {
6269 Mips_MOVZ_I_D32_MM, MIPS_INS_MOVZ,
6270 #ifndef CAPSTONE_DIET
6271 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6272 #endif
6273 },
6274 {
6275 Mips_MOVZ_I_D64, MIPS_INS_MOVZ,
6276 #ifndef CAPSTONE_DIET
6277 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6278 #endif
6279 },
6280 {
6281 Mips_MOVZ_I_I, MIPS_INS_MOVZ,
6282 #ifndef CAPSTONE_DIET
6283 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6284 #endif
6285 },
6286 {
6287 Mips_MOVZ_I_I64, MIPS_INS_MOVZ,
6288 #ifndef CAPSTONE_DIET
6289 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6290 #endif
6291 },
6292 {
6293 Mips_MOVZ_I_MM, MIPS_INS_MOVZ,
6294 #ifndef CAPSTONE_DIET
6295 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6296 #endif
6297 },
6298 {
6299 Mips_MOVZ_I_S, MIPS_INS_MOVZ,
6300 #ifndef CAPSTONE_DIET
6301 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6302 #endif
6303 },
6304 {
6305 Mips_MOVZ_I_S_MM, MIPS_INS_MOVZ,
6306 #ifndef CAPSTONE_DIET
6307 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6308 #endif
6309 },
6310 {
6311 Mips_MSUB, MIPS_INS_MSUB,
6312 #ifndef CAPSTONE_DIET
6313 { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6314 #endif
6315 },
6316 {
6317 Mips_MSUBF_D, MIPS_INS_MSUBF,
6318 #ifndef CAPSTONE_DIET
6319 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
6320 #endif
6321 },
6322 {
6323 Mips_MSUBF_S, MIPS_INS_MSUBF,
6324 #ifndef CAPSTONE_DIET
6325 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
6326 #endif
6327 },
6328 {
6329 Mips_MSUBR_Q_H, MIPS_INS_MSUBR_Q,
6330 #ifndef CAPSTONE_DIET
6331 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6332 #endif
6333 },
6334 {
6335 Mips_MSUBR_Q_W, MIPS_INS_MSUBR_Q,
6336 #ifndef CAPSTONE_DIET
6337 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6338 #endif
6339 },
6340 {
6341 Mips_MSUBU, MIPS_INS_MSUBU,
6342 #ifndef CAPSTONE_DIET
6343 { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6344 #endif
6345 },
6346 {
6347 Mips_MSUBU_DSP, MIPS_INS_MSUBU,
6348 #ifndef CAPSTONE_DIET
6349 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
6350 #endif
6351 },
6352 {
6353 Mips_MSUBU_MM, MIPS_INS_MSUBU,
6354 #ifndef CAPSTONE_DIET
6355 { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6356 #endif
6357 },
6358 {
6359 Mips_MSUBV_B, MIPS_INS_MSUBV,
6360 #ifndef CAPSTONE_DIET
6361 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6362 #endif
6363 },
6364 {
6365 Mips_MSUBV_D, MIPS_INS_MSUBV,
6366 #ifndef CAPSTONE_DIET
6367 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6368 #endif
6369 },
6370 {
6371 Mips_MSUBV_H, MIPS_INS_MSUBV,
6372 #ifndef CAPSTONE_DIET
6373 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6374 #endif
6375 },
6376 {
6377 Mips_MSUBV_W, MIPS_INS_MSUBV,
6378 #ifndef CAPSTONE_DIET
6379 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6380 #endif
6381 },
6382 {
6383 Mips_MSUB_D32, MIPS_INS_MSUB,
6384 #ifndef CAPSTONE_DIET
6385 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6386 #endif
6387 },
6388 {
6389 Mips_MSUB_D32_MM, MIPS_INS_MSUB,
6390 #ifndef CAPSTONE_DIET
6391 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6392 #endif
6393 },
6394 {
6395 Mips_MSUB_D64, MIPS_INS_MSUB,
6396 #ifndef CAPSTONE_DIET
6397 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6398 #endif
6399 },
6400 {
6401 Mips_MSUB_DSP, MIPS_INS_MSUB,
6402 #ifndef CAPSTONE_DIET
6403 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
6404 #endif
6405 },
6406 {
6407 Mips_MSUB_MM, MIPS_INS_MSUB,
6408 #ifndef CAPSTONE_DIET
6409 { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6410 #endif
6411 },
6412 {
6413 Mips_MSUB_Q_H, MIPS_INS_MSUB_Q,
6414 #ifndef CAPSTONE_DIET
6415 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6416 #endif
6417 },
6418 {
6419 Mips_MSUB_Q_W, MIPS_INS_MSUB_Q,
6420 #ifndef CAPSTONE_DIET
6421 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6422 #endif
6423 },
6424 {
6425 Mips_MSUB_S, MIPS_INS_MSUB,
6426 #ifndef CAPSTONE_DIET
6427 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6428 #endif
6429 },
6430 {
6431 Mips_MSUB_S_MM, MIPS_INS_MSUB,
6432 #ifndef CAPSTONE_DIET
6433 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6434 #endif
6435 },
6436 {
6437 Mips_MTC0, MIPS_INS_MTC0,
6438 #ifndef CAPSTONE_DIET
6439 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0
6440 #endif
6441 },
6442 {
6443 Mips_MTC1, MIPS_INS_MTC1,
6444 #ifndef CAPSTONE_DIET
6445 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
6446 #endif
6447 },
6448 {
6449 Mips_MTC1_MM, MIPS_INS_MTC1,
6450 #ifndef CAPSTONE_DIET
6451 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6452 #endif
6453 },
6454 {
6455 Mips_MTC2, MIPS_INS_MTC2,
6456 #ifndef CAPSTONE_DIET
6457 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
6458 #endif
6459 },
6460 {
6461 Mips_MTHC1_D32, MIPS_INS_MTHC1,
6462 #ifndef CAPSTONE_DIET
6463 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
6464 #endif
6465 },
6466 {
6467 Mips_MTHC1_D64, MIPS_INS_MTHC1,
6468 #ifndef CAPSTONE_DIET
6469 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_FP64BIT, 0 }, 0, 0
6470 #endif
6471 },
6472 {
6473 Mips_MTHC1_MM, MIPS_INS_MTHC1,
6474 #ifndef CAPSTONE_DIET
6475 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6476 #endif
6477 },
6478 {
6479 Mips_MTHI, MIPS_INS_MTHI,
6480 #ifndef CAPSTONE_DIET
6481 { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6482 #endif
6483 },
6484 {
6485 Mips_MTHI64, MIPS_INS_MTHI,
6486 #ifndef CAPSTONE_DIET
6487 { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6488 #endif
6489 },
6490 {
6491 Mips_MTHI_DSP, MIPS_INS_MTHI,
6492 #ifndef CAPSTONE_DIET
6493 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
6494 #endif
6495 },
6496 {
6497 Mips_MTHI_MM, MIPS_INS_MTHI,
6498 #ifndef CAPSTONE_DIET
6499 { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6500 #endif
6501 },
6502 {
6503 Mips_MTHLIP, MIPS_INS_MTHLIP,
6504 #ifndef CAPSTONE_DIET
6505 { 0 }, { MIPS_REG_DSPPOS, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
6506 #endif
6507 },
6508 {
6509 Mips_MTLO, MIPS_INS_MTLO,
6510 #ifndef CAPSTONE_DIET
6511 { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6512 #endif
6513 },
6514 {
6515 Mips_MTLO64, MIPS_INS_MTLO,
6516 #ifndef CAPSTONE_DIET
6517 { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6518 #endif
6519 },
6520 {
6521 Mips_MTLO_DSP, MIPS_INS_MTLO,
6522 #ifndef CAPSTONE_DIET
6523 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
6524 #endif
6525 },
6526 {
6527 Mips_MTLO_MM, MIPS_INS_MTLO,
6528 #ifndef CAPSTONE_DIET
6529 { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6530 #endif
6531 },
6532 {
6533 Mips_MTM0, MIPS_INS_MTM0,
6534 #ifndef CAPSTONE_DIET
6535 { 0 }, { MIPS_REG_MPL0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
6536 #endif
6537 },
6538 {
6539 Mips_MTM1, MIPS_INS_MTM1,
6540 #ifndef CAPSTONE_DIET
6541 { 0 }, { MIPS_REG_MPL1, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
6542 #endif
6543 },
6544 {
6545 Mips_MTM2, MIPS_INS_MTM2,
6546 #ifndef CAPSTONE_DIET
6547 { 0 }, { MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
6548 #endif
6549 },
6550 {
6551 Mips_MTP0, MIPS_INS_MTP0,
6552 #ifndef CAPSTONE_DIET
6553 { 0 }, { MIPS_REG_P0, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
6554 #endif
6555 },
6556 {
6557 Mips_MTP1, MIPS_INS_MTP1,
6558 #ifndef CAPSTONE_DIET
6559 { 0 }, { MIPS_REG_P1, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
6560 #endif
6561 },
6562 {
6563 Mips_MTP2, MIPS_INS_MTP2,
6564 #ifndef CAPSTONE_DIET
6565 { 0 }, { MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
6566 #endif
6567 },
6568 {
6569 Mips_MUH, MIPS_INS_MUH,
6570 #ifndef CAPSTONE_DIET
6571 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
6572 #endif
6573 },
6574 {
6575 Mips_MUHU, MIPS_INS_MUHU,
6576 #ifndef CAPSTONE_DIET
6577 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
6578 #endif
6579 },
6580 {
6581 Mips_MUL, MIPS_INS_MUL,
6582 #ifndef CAPSTONE_DIET
6583 { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6584 #endif
6585 },
6586 {
6587 Mips_MULEQ_S_W_PHL, MIPS_INS_MULEQ_S,
6588 #ifndef CAPSTONE_DIET
6589 { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
6590 #endif
6591 },
6592 {
6593 Mips_MULEQ_S_W_PHR, MIPS_INS_MULEQ_S,
6594 #ifndef CAPSTONE_DIET
6595 { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
6596 #endif
6597 },
6598 {
6599 Mips_MULEU_S_PH_QBL, MIPS_INS_MULEU_S,
6600 #ifndef CAPSTONE_DIET
6601 { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
6602 #endif
6603 },
6604 {
6605 Mips_MULEU_S_PH_QBR, MIPS_INS_MULEU_S,
6606 #ifndef CAPSTONE_DIET
6607 { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
6608 #endif
6609 },
6610 {
6611 Mips_MULQ_RS_PH, MIPS_INS_MULQ_RS,
6612 #ifndef CAPSTONE_DIET
6613 { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
6614 #endif
6615 },
6616 {
6617 Mips_MULQ_RS_W, MIPS_INS_MULQ_RS,
6618 #ifndef CAPSTONE_DIET
6619 { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
6620 #endif
6621 },
6622 {
6623 Mips_MULQ_S_PH, MIPS_INS_MULQ_S,
6624 #ifndef CAPSTONE_DIET
6625 { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
6626 #endif
6627 },
6628 {
6629 Mips_MULQ_S_W, MIPS_INS_MULQ_S,
6630 #ifndef CAPSTONE_DIET
6631 { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
6632 #endif
6633 },
6634 {
6635 Mips_MULR_Q_H, MIPS_INS_MULR_Q,
6636 #ifndef CAPSTONE_DIET
6637 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6638 #endif
6639 },
6640 {
6641 Mips_MULR_Q_W, MIPS_INS_MULR_Q,
6642 #ifndef CAPSTONE_DIET
6643 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6644 #endif
6645 },
6646 {
6647 Mips_MULSAQ_S_W_PH, MIPS_INS_MULSAQ_S,
6648 #ifndef CAPSTONE_DIET
6649 { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
6650 #endif
6651 },
6652 {
6653 Mips_MULSA_W_PH, MIPS_INS_MULSA,
6654 #ifndef CAPSTONE_DIET
6655 { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
6656 #endif
6657 },
6658 {
6659 Mips_MULT, MIPS_INS_MULT,
6660 #ifndef CAPSTONE_DIET
6661 { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6662 #endif
6663 },
6664 {
6665 Mips_MULTU_DSP, MIPS_INS_MULTU,
6666 #ifndef CAPSTONE_DIET
6667 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
6668 #endif
6669 },
6670 {
6671 Mips_MULT_DSP, MIPS_INS_MULT,
6672 #ifndef CAPSTONE_DIET
6673 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
6674 #endif
6675 },
6676 {
6677 Mips_MULT_MM, MIPS_INS_MULT,
6678 #ifndef CAPSTONE_DIET
6679 { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6680 #endif
6681 },
6682 {
6683 Mips_MULTu, MIPS_INS_MULTU,
6684 #ifndef CAPSTONE_DIET
6685 { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6686 #endif
6687 },
6688 {
6689 Mips_MULTu_MM, MIPS_INS_MULTU,
6690 #ifndef CAPSTONE_DIET
6691 { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6692 #endif
6693 },
6694 {
6695 Mips_MULU, MIPS_INS_MULU,
6696 #ifndef CAPSTONE_DIET
6697 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
6698 #endif
6699 },
6700 {
6701 Mips_MULV_B, MIPS_INS_MULV,
6702 #ifndef CAPSTONE_DIET
6703 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6704 #endif
6705 },
6706 {
6707 Mips_MULV_D, MIPS_INS_MULV,
6708 #ifndef CAPSTONE_DIET
6709 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6710 #endif
6711 },
6712 {
6713 Mips_MULV_H, MIPS_INS_MULV,
6714 #ifndef CAPSTONE_DIET
6715 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6716 #endif
6717 },
6718 {
6719 Mips_MULV_W, MIPS_INS_MULV,
6720 #ifndef CAPSTONE_DIET
6721 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6722 #endif
6723 },
6724 {
6725 Mips_MUL_MM, MIPS_INS_MUL,
6726 #ifndef CAPSTONE_DIET
6727 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6728 #endif
6729 },
6730 {
6731 Mips_MUL_PH, MIPS_INS_MUL,
6732 #ifndef CAPSTONE_DIET
6733 { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
6734 #endif
6735 },
6736 {
6737 Mips_MUL_Q_H, MIPS_INS_MUL_Q,
6738 #ifndef CAPSTONE_DIET
6739 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6740 #endif
6741 },
6742 {
6743 Mips_MUL_Q_W, MIPS_INS_MUL_Q,
6744 #ifndef CAPSTONE_DIET
6745 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6746 #endif
6747 },
6748 {
6749 Mips_MUL_R6, MIPS_INS_MUL,
6750 #ifndef CAPSTONE_DIET
6751 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
6752 #endif
6753 },
6754 {
6755 Mips_MUL_S_PH, MIPS_INS_MUL_S,
6756 #ifndef CAPSTONE_DIET
6757 { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
6758 #endif
6759 },
6760 {
6761 Mips_Mfhi16, MIPS_INS_MFHI,
6762 #ifndef CAPSTONE_DIET
6763 { MIPS_REG_HI0, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
6764 #endif
6765 },
6766 {
6767 Mips_Mflo16, MIPS_INS_MFLO,
6768 #ifndef CAPSTONE_DIET
6769 { MIPS_REG_LO0, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
6770 #endif
6771 },
6772 {
6773 Mips_Move32R16, MIPS_INS_MOVE,
6774 #ifndef CAPSTONE_DIET
6775 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
6776 #endif
6777 },
6778 {
6779 Mips_MoveR3216, MIPS_INS_MOVE,
6780 #ifndef CAPSTONE_DIET
6781 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
6782 #endif
6783 },
6784 {
6785 Mips_NLOC_B, MIPS_INS_NLOC,
6786 #ifndef CAPSTONE_DIET
6787 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6788 #endif
6789 },
6790 {
6791 Mips_NLOC_D, MIPS_INS_NLOC,
6792 #ifndef CAPSTONE_DIET
6793 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6794 #endif
6795 },
6796 {
6797 Mips_NLOC_H, MIPS_INS_NLOC,
6798 #ifndef CAPSTONE_DIET
6799 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6800 #endif
6801 },
6802 {
6803 Mips_NLOC_W, MIPS_INS_NLOC,
6804 #ifndef CAPSTONE_DIET
6805 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6806 #endif
6807 },
6808 {
6809 Mips_NLZC_B, MIPS_INS_NLZC,
6810 #ifndef CAPSTONE_DIET
6811 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6812 #endif
6813 },
6814 {
6815 Mips_NLZC_D, MIPS_INS_NLZC,
6816 #ifndef CAPSTONE_DIET
6817 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6818 #endif
6819 },
6820 {
6821 Mips_NLZC_H, MIPS_INS_NLZC,
6822 #ifndef CAPSTONE_DIET
6823 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6824 #endif
6825 },
6826 {
6827 Mips_NLZC_W, MIPS_INS_NLZC,
6828 #ifndef CAPSTONE_DIET
6829 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6830 #endif
6831 },
6832 {
6833 Mips_NMADD_D32, MIPS_INS_NMADD,
6834 #ifndef CAPSTONE_DIET
6835 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0
6836 #endif
6837 },
6838 {
6839 Mips_NMADD_D32_MM, MIPS_INS_NMADD,
6840 #ifndef CAPSTONE_DIET
6841 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6842 #endif
6843 },
6844 {
6845 Mips_NMADD_D64, MIPS_INS_NMADD,
6846 #ifndef CAPSTONE_DIET
6847 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0
6848 #endif
6849 },
6850 {
6851 Mips_NMADD_S, MIPS_INS_NMADD,
6852 #ifndef CAPSTONE_DIET
6853 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0
6854 #endif
6855 },
6856 {
6857 Mips_NMADD_S_MM, MIPS_INS_NMADD,
6858 #ifndef CAPSTONE_DIET
6859 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6860 #endif
6861 },
6862 {
6863 Mips_NMSUB_D32, MIPS_INS_NMSUB,
6864 #ifndef CAPSTONE_DIET
6865 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0
6866 #endif
6867 },
6868 {
6869 Mips_NMSUB_D32_MM, MIPS_INS_NMSUB,
6870 #ifndef CAPSTONE_DIET
6871 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6872 #endif
6873 },
6874 {
6875 Mips_NMSUB_D64, MIPS_INS_NMSUB,
6876 #ifndef CAPSTONE_DIET
6877 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0
6878 #endif
6879 },
6880 {
6881 Mips_NMSUB_S, MIPS_INS_NMSUB,
6882 #ifndef CAPSTONE_DIET
6883 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0
6884 #endif
6885 },
6886 {
6887 Mips_NMSUB_S_MM, MIPS_INS_NMSUB,
6888 #ifndef CAPSTONE_DIET
6889 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6890 #endif
6891 },
6892 {
6893 Mips_NOR, MIPS_INS_NOR,
6894 #ifndef CAPSTONE_DIET
6895 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
6896 #endif
6897 },
6898 {
6899 Mips_NOR64, MIPS_INS_NOR,
6900 #ifndef CAPSTONE_DIET
6901 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
6902 #endif
6903 },
6904 {
6905 Mips_NORI_B, MIPS_INS_NORI,
6906 #ifndef CAPSTONE_DIET
6907 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6908 #endif
6909 },
6910 {
6911 Mips_NOR_MM, MIPS_INS_NOR,
6912 #ifndef CAPSTONE_DIET
6913 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6914 #endif
6915 },
6916 {
6917 Mips_NOR_V, MIPS_INS_NOR,
6918 #ifndef CAPSTONE_DIET
6919 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6920 #endif
6921 },
6922 {
6923 Mips_NegRxRy16, MIPS_INS_NEG,
6924 #ifndef CAPSTONE_DIET
6925 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
6926 #endif
6927 },
6928 {
6929 Mips_NotRxRy16, MIPS_INS_NOT,
6930 #ifndef CAPSTONE_DIET
6931 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
6932 #endif
6933 },
6934 {
6935 Mips_OR, MIPS_INS_OR,
6936 #ifndef CAPSTONE_DIET
6937 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
6938 #endif
6939 },
6940 {
6941 Mips_OR64, MIPS_INS_OR,
6942 #ifndef CAPSTONE_DIET
6943 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
6944 #endif
6945 },
6946 {
6947 Mips_ORI_B, MIPS_INS_ORI,
6948 #ifndef CAPSTONE_DIET
6949 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6950 #endif
6951 },
6952 {
6953 Mips_OR_MM, MIPS_INS_OR,
6954 #ifndef CAPSTONE_DIET
6955 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6956 #endif
6957 },
6958 {
6959 Mips_OR_V, MIPS_INS_OR,
6960 #ifndef CAPSTONE_DIET
6961 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6962 #endif
6963 },
6964 {
6965 Mips_ORi, MIPS_INS_ORI,
6966 #ifndef CAPSTONE_DIET
6967 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
6968 #endif
6969 },
6970 {
6971 Mips_ORi64, MIPS_INS_ORI,
6972 #ifndef CAPSTONE_DIET
6973 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
6974 #endif
6975 },
6976 {
6977 Mips_ORi_MM, MIPS_INS_ORI,
6978 #ifndef CAPSTONE_DIET
6979 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6980 #endif
6981 },
6982 {
6983 Mips_OrRxRxRy16, MIPS_INS_OR,
6984 #ifndef CAPSTONE_DIET
6985 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
6986 #endif
6987 },
6988 {
6989 Mips_PACKRL_PH, MIPS_INS_PACKRL,
6990 #ifndef CAPSTONE_DIET
6991 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
6992 #endif
6993 },
6994 {
6995 Mips_PAUSE, MIPS_INS_PAUSE,
6996 #ifndef CAPSTONE_DIET
6997 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
6998 #endif
6999 },
7000 {
7001 Mips_PCKEV_B, MIPS_INS_PCKEV,
7002 #ifndef CAPSTONE_DIET
7003 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7004 #endif
7005 },
7006 {
7007 Mips_PCKEV_D, MIPS_INS_PCKEV,
7008 #ifndef CAPSTONE_DIET
7009 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7010 #endif
7011 },
7012 {
7013 Mips_PCKEV_H, MIPS_INS_PCKEV,
7014 #ifndef CAPSTONE_DIET
7015 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7016 #endif
7017 },
7018 {
7019 Mips_PCKEV_W, MIPS_INS_PCKEV,
7020 #ifndef CAPSTONE_DIET
7021 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7022 #endif
7023 },
7024 {
7025 Mips_PCKOD_B, MIPS_INS_PCKOD,
7026 #ifndef CAPSTONE_DIET
7027 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7028 #endif
7029 },
7030 {
7031 Mips_PCKOD_D, MIPS_INS_PCKOD,
7032 #ifndef CAPSTONE_DIET
7033 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7034 #endif
7035 },
7036 {
7037 Mips_PCKOD_H, MIPS_INS_PCKOD,
7038 #ifndef CAPSTONE_DIET
7039 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7040 #endif
7041 },
7042 {
7043 Mips_PCKOD_W, MIPS_INS_PCKOD,
7044 #ifndef CAPSTONE_DIET
7045 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7046 #endif
7047 },
7048 {
7049 Mips_PCNT_B, MIPS_INS_PCNT,
7050 #ifndef CAPSTONE_DIET
7051 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7052 #endif
7053 },
7054 {
7055 Mips_PCNT_D, MIPS_INS_PCNT,
7056 #ifndef CAPSTONE_DIET
7057 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7058 #endif
7059 },
7060 {
7061 Mips_PCNT_H, MIPS_INS_PCNT,
7062 #ifndef CAPSTONE_DIET
7063 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7064 #endif
7065 },
7066 {
7067 Mips_PCNT_W, MIPS_INS_PCNT,
7068 #ifndef CAPSTONE_DIET
7069 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7070 #endif
7071 },
7072 {
7073 Mips_PICK_PH, MIPS_INS_PICK,
7074 #ifndef CAPSTONE_DIET
7075 { MIPS_REG_DSPCCOND, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7076 #endif
7077 },
7078 {
7079 Mips_PICK_QB, MIPS_INS_PICK,
7080 #ifndef CAPSTONE_DIET
7081 { MIPS_REG_DSPCCOND, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7082 #endif
7083 },
7084 {
7085 Mips_POP, MIPS_INS_POP,
7086 #ifndef CAPSTONE_DIET
7087 { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
7088 #endif
7089 },
7090 {
7091 Mips_PRECEQU_PH_QBL, MIPS_INS_PRECEQU,
7092 #ifndef CAPSTONE_DIET
7093 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7094 #endif
7095 },
7096 {
7097 Mips_PRECEQU_PH_QBLA, MIPS_INS_PRECEQU,
7098 #ifndef CAPSTONE_DIET
7099 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7100 #endif
7101 },
7102 {
7103 Mips_PRECEQU_PH_QBR, MIPS_INS_PRECEQU,
7104 #ifndef CAPSTONE_DIET
7105 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7106 #endif
7107 },
7108 {
7109 Mips_PRECEQU_PH_QBRA, MIPS_INS_PRECEQU,
7110 #ifndef CAPSTONE_DIET
7111 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7112 #endif
7113 },
7114 {
7115 Mips_PRECEQ_W_PHL, MIPS_INS_PRECEQ,
7116 #ifndef CAPSTONE_DIET
7117 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7118 #endif
7119 },
7120 {
7121 Mips_PRECEQ_W_PHR, MIPS_INS_PRECEQ,
7122 #ifndef CAPSTONE_DIET
7123 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7124 #endif
7125 },
7126 {
7127 Mips_PRECEU_PH_QBL, MIPS_INS_PRECEU,
7128 #ifndef CAPSTONE_DIET
7129 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7130 #endif
7131 },
7132 {
7133 Mips_PRECEU_PH_QBLA, MIPS_INS_PRECEU,
7134 #ifndef CAPSTONE_DIET
7135 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7136 #endif
7137 },
7138 {
7139 Mips_PRECEU_PH_QBR, MIPS_INS_PRECEU,
7140 #ifndef CAPSTONE_DIET
7141 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7142 #endif
7143 },
7144 {
7145 Mips_PRECEU_PH_QBRA, MIPS_INS_PRECEU,
7146 #ifndef CAPSTONE_DIET
7147 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7148 #endif
7149 },
7150 {
7151 Mips_PRECRQU_S_QB_PH, MIPS_INS_PRECRQU_S,
7152 #ifndef CAPSTONE_DIET
7153 { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7154 #endif
7155 },
7156 {
7157 Mips_PRECRQ_PH_W, MIPS_INS_PRECRQ,
7158 #ifndef CAPSTONE_DIET
7159 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7160 #endif
7161 },
7162 {
7163 Mips_PRECRQ_QB_PH, MIPS_INS_PRECRQ,
7164 #ifndef CAPSTONE_DIET
7165 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7166 #endif
7167 },
7168 {
7169 Mips_PRECRQ_RS_PH_W, MIPS_INS_PRECRQ_RS,
7170 #ifndef CAPSTONE_DIET
7171 { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7172 #endif
7173 },
7174 {
7175 Mips_PRECR_QB_PH, MIPS_INS_PRECR,
7176 #ifndef CAPSTONE_DIET
7177 { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
7178 #endif
7179 },
7180 {
7181 Mips_PRECR_SRA_PH_W, MIPS_INS_PRECR_SRA,
7182 #ifndef CAPSTONE_DIET
7183 { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
7184 #endif
7185 },
7186 {
7187 Mips_PRECR_SRA_R_PH_W, MIPS_INS_PRECR_SRA_R,
7188 #ifndef CAPSTONE_DIET
7189 { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
7190 #endif
7191 },
7192 {
7193 Mips_PREF, MIPS_INS_PREF,
7194 #ifndef CAPSTONE_DIET
7195 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
7196 #endif
7197 },
7198 {
7199 Mips_PREF_R6, MIPS_INS_PREF,
7200 #ifndef CAPSTONE_DIET
7201 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7202 #endif
7203 },
7204 {
7205 Mips_PREPEND, MIPS_INS_PREPEND,
7206 #ifndef CAPSTONE_DIET
7207 { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
7208 #endif
7209 },
7210 {
7211 Mips_RADDU_W_QB, MIPS_INS_RADDU,
7212 #ifndef CAPSTONE_DIET
7213 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7214 #endif
7215 },
7216 {
7217 Mips_RDDSP, MIPS_INS_RDDSP,
7218 #ifndef CAPSTONE_DIET
7219 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7220 #endif
7221 },
7222 {
7223 Mips_RDHWR, MIPS_INS_RDHWR,
7224 #ifndef CAPSTONE_DIET
7225 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
7226 #endif
7227 },
7228 {
7229 Mips_RDHWR64, MIPS_INS_RDHWR,
7230 #ifndef CAPSTONE_DIET
7231 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
7232 #endif
7233 },
7234 {
7235 Mips_REPLV_PH, MIPS_INS_REPLV,
7236 #ifndef CAPSTONE_DIET
7237 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7238 #endif
7239 },
7240 {
7241 Mips_REPLV_QB, MIPS_INS_REPLV,
7242 #ifndef CAPSTONE_DIET
7243 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7244 #endif
7245 },
7246 {
7247 Mips_REPL_PH, MIPS_INS_REPL,
7248 #ifndef CAPSTONE_DIET
7249 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7250 #endif
7251 },
7252 {
7253 Mips_REPL_QB, MIPS_INS_REPL,
7254 #ifndef CAPSTONE_DIET
7255 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7256 #endif
7257 },
7258 {
7259 Mips_RINT_D, MIPS_INS_RINT,
7260 #ifndef CAPSTONE_DIET
7261 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7262 #endif
7263 },
7264 {
7265 Mips_RINT_S, MIPS_INS_RINT,
7266 #ifndef CAPSTONE_DIET
7267 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7268 #endif
7269 },
7270 {
7271 Mips_ROTR, MIPS_INS_ROTR,
7272 #ifndef CAPSTONE_DIET
7273 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
7274 #endif
7275 },
7276 {
7277 Mips_ROTRV, MIPS_INS_ROTRV,
7278 #ifndef CAPSTONE_DIET
7279 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
7280 #endif
7281 },
7282 {
7283 Mips_ROTRV_MM, MIPS_INS_ROTRV,
7284 #ifndef CAPSTONE_DIET
7285 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7286 #endif
7287 },
7288 {
7289 Mips_ROTR_MM, MIPS_INS_ROTR,
7290 #ifndef CAPSTONE_DIET
7291 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7292 #endif
7293 },
7294 {
7295 Mips_ROUND_L_D64, MIPS_INS_ROUND,
7296 #ifndef CAPSTONE_DIET
7297 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
7298 #endif
7299 },
7300 {
7301 Mips_ROUND_L_S, MIPS_INS_ROUND,
7302 #ifndef CAPSTONE_DIET
7303 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
7304 #endif
7305 },
7306 {
7307 Mips_ROUND_W_D32, MIPS_INS_ROUND,
7308 #ifndef CAPSTONE_DIET
7309 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
7310 #endif
7311 },
7312 {
7313 Mips_ROUND_W_D64, MIPS_INS_ROUND,
7314 #ifndef CAPSTONE_DIET
7315 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0
7316 #endif
7317 },
7318 {
7319 Mips_ROUND_W_MM, MIPS_INS_ROUND,
7320 #ifndef CAPSTONE_DIET
7321 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7322 #endif
7323 },
7324 {
7325 Mips_ROUND_W_S, MIPS_INS_ROUND,
7326 #ifndef CAPSTONE_DIET
7327 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
7328 #endif
7329 },
7330 {
7331 Mips_ROUND_W_S_MM, MIPS_INS_ROUND,
7332 #ifndef CAPSTONE_DIET
7333 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7334 #endif
7335 },
7336 {
7337 Mips_SAT_S_B, MIPS_INS_SAT_S,
7338 #ifndef CAPSTONE_DIET
7339 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7340 #endif
7341 },
7342 {
7343 Mips_SAT_S_D, MIPS_INS_SAT_S,
7344 #ifndef CAPSTONE_DIET
7345 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7346 #endif
7347 },
7348 {
7349 Mips_SAT_S_H, MIPS_INS_SAT_S,
7350 #ifndef CAPSTONE_DIET
7351 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7352 #endif
7353 },
7354 {
7355 Mips_SAT_S_W, MIPS_INS_SAT_S,
7356 #ifndef CAPSTONE_DIET
7357 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7358 #endif
7359 },
7360 {
7361 Mips_SAT_U_B, MIPS_INS_SAT_U,
7362 #ifndef CAPSTONE_DIET
7363 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7364 #endif
7365 },
7366 {
7367 Mips_SAT_U_D, MIPS_INS_SAT_U,
7368 #ifndef CAPSTONE_DIET
7369 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7370 #endif
7371 },
7372 {
7373 Mips_SAT_U_H, MIPS_INS_SAT_U,
7374 #ifndef CAPSTONE_DIET
7375 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7376 #endif
7377 },
7378 {
7379 Mips_SAT_U_W, MIPS_INS_SAT_U,
7380 #ifndef CAPSTONE_DIET
7381 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7382 #endif
7383 },
7384 {
7385 Mips_SB, MIPS_INS_SB,
7386 #ifndef CAPSTONE_DIET
7387 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
7388 #endif
7389 },
7390 {
7391 Mips_SB64, MIPS_INS_SB,
7392 #ifndef CAPSTONE_DIET
7393 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
7394 #endif
7395 },
7396 {
7397 Mips_SB_MM, MIPS_INS_SB,
7398 #ifndef CAPSTONE_DIET
7399 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7400 #endif
7401 },
7402 {
7403 Mips_SC, MIPS_INS_SC,
7404 #ifndef CAPSTONE_DIET
7405 { 0 }, { 0 }, { MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
7406 #endif
7407 },
7408 {
7409 Mips_SCD, MIPS_INS_SCD,
7410 #ifndef CAPSTONE_DIET
7411 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
7412 #endif
7413 },
7414 {
7415 Mips_SCD_R6, MIPS_INS_SCD,
7416 #ifndef CAPSTONE_DIET
7417 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7418 #endif
7419 },
7420 {
7421 Mips_SC_MM, MIPS_INS_SC,
7422 #ifndef CAPSTONE_DIET
7423 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7424 #endif
7425 },
7426 {
7427 Mips_SC_R6, MIPS_INS_SC,
7428 #ifndef CAPSTONE_DIET
7429 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7430 #endif
7431 },
7432 {
7433 Mips_SD, MIPS_INS_SD,
7434 #ifndef CAPSTONE_DIET
7435 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
7436 #endif
7437 },
7438 {
7439 Mips_SDBBP, MIPS_INS_SDBBP,
7440 #ifndef CAPSTONE_DIET
7441 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
7442 #endif
7443 },
7444 {
7445 Mips_SDBBP_R6, MIPS_INS_SDBBP,
7446 #ifndef CAPSTONE_DIET
7447 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7448 #endif
7449 },
7450 {
7451 Mips_SDC1, MIPS_INS_SDC1,
7452 #ifndef CAPSTONE_DIET
7453 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0
7454 #endif
7455 },
7456 {
7457 Mips_SDC164, MIPS_INS_SDC1,
7458 #ifndef CAPSTONE_DIET
7459 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0
7460 #endif
7461 },
7462 {
7463 Mips_SDC1_MM, MIPS_INS_SDC1,
7464 #ifndef CAPSTONE_DIET
7465 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7466 #endif
7467 },
7468 {
7469 Mips_SDC2, MIPS_INS_SDC2,
7470 #ifndef CAPSTONE_DIET
7471 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
7472 #endif
7473 },
7474 {
7475 Mips_SDC2_R6, MIPS_INS_SDC2,
7476 #ifndef CAPSTONE_DIET
7477 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7478 #endif
7479 },
7480 {
7481 Mips_SDC3, MIPS_INS_SDC3,
7482 #ifndef CAPSTONE_DIET
7483 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
7484 #endif
7485 },
7486 {
7487 Mips_SDIV, MIPS_INS_DIV,
7488 #ifndef CAPSTONE_DIET
7489 { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
7490 #endif
7491 },
7492 {
7493 Mips_SDIV_MM, MIPS_INS_DIV,
7494 #ifndef CAPSTONE_DIET
7495 { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7496 #endif
7497 },
7498 {
7499 Mips_SDL, MIPS_INS_SDL,
7500 #ifndef CAPSTONE_DIET
7501 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
7502 #endif
7503 },
7504 {
7505 Mips_SDR, MIPS_INS_SDR,
7506 #ifndef CAPSTONE_DIET
7507 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
7508 #endif
7509 },
7510 {
7511 Mips_SDXC1, MIPS_INS_SDXC1,
7512 #ifndef CAPSTONE_DIET
7513 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_NOTNACL, 0 }, 0, 0
7514 #endif
7515 },
7516 {
7517 Mips_SDXC164, MIPS_INS_SDXC1,
7518 #ifndef CAPSTONE_DIET
7519 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
7520 #endif
7521 },
7522 {
7523 Mips_SEB, MIPS_INS_SEB,
7524 #ifndef CAPSTONE_DIET
7525 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
7526 #endif
7527 },
7528 {
7529 Mips_SEB64, MIPS_INS_SEB,
7530 #ifndef CAPSTONE_DIET
7531 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
7532 #endif
7533 },
7534 {
7535 Mips_SEB_MM, MIPS_INS_SEB,
7536 #ifndef CAPSTONE_DIET
7537 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7538 #endif
7539 },
7540 {
7541 Mips_SEH, MIPS_INS_SEH,
7542 #ifndef CAPSTONE_DIET
7543 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
7544 #endif
7545 },
7546 {
7547 Mips_SEH64, MIPS_INS_SEH,
7548 #ifndef CAPSTONE_DIET
7549 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
7550 #endif
7551 },
7552 {
7553 Mips_SEH_MM, MIPS_INS_SEH,
7554 #ifndef CAPSTONE_DIET
7555 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7556 #endif
7557 },
7558 {
7559 Mips_SELEQZ, MIPS_INS_SELEQZ,
7560 #ifndef CAPSTONE_DIET
7561 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7562 #endif
7563 },
7564 {
7565 Mips_SELEQZ64, MIPS_INS_SELEQZ,
7566 #ifndef CAPSTONE_DIET
7567 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7568 #endif
7569 },
7570 {
7571 Mips_SELEQZ_D, MIPS_INS_SELEQZ,
7572 #ifndef CAPSTONE_DIET
7573 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7574 #endif
7575 },
7576 {
7577 Mips_SELEQZ_S, MIPS_INS_SELEQZ,
7578 #ifndef CAPSTONE_DIET
7579 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7580 #endif
7581 },
7582 {
7583 Mips_SELNEZ, MIPS_INS_SELNEZ,
7584 #ifndef CAPSTONE_DIET
7585 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7586 #endif
7587 },
7588 {
7589 Mips_SELNEZ64, MIPS_INS_SELNEZ,
7590 #ifndef CAPSTONE_DIET
7591 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7592 #endif
7593 },
7594 {
7595 Mips_SELNEZ_D, MIPS_INS_SELNEZ,
7596 #ifndef CAPSTONE_DIET
7597 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7598 #endif
7599 },
7600 {
7601 Mips_SELNEZ_S, MIPS_INS_SELNEZ,
7602 #ifndef CAPSTONE_DIET
7603 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7604 #endif
7605 },
7606 {
7607 Mips_SEL_D, MIPS_INS_SEL,
7608 #ifndef CAPSTONE_DIET
7609 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7610 #endif
7611 },
7612 {
7613 Mips_SEL_S, MIPS_INS_SEL,
7614 #ifndef CAPSTONE_DIET
7615 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7616 #endif
7617 },
7618 {
7619 Mips_SEQ, MIPS_INS_SEQ,
7620 #ifndef CAPSTONE_DIET
7621 { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
7622 #endif
7623 },
7624 {
7625 Mips_SEQi, MIPS_INS_SEQI,
7626 #ifndef CAPSTONE_DIET
7627 { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
7628 #endif
7629 },
7630 {
7631 Mips_SH, MIPS_INS_SH,
7632 #ifndef CAPSTONE_DIET
7633 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
7634 #endif
7635 },
7636 {
7637 Mips_SH64, MIPS_INS_SH,
7638 #ifndef CAPSTONE_DIET
7639 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
7640 #endif
7641 },
7642 {
7643 Mips_SHF_B, MIPS_INS_SHF,
7644 #ifndef CAPSTONE_DIET
7645 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7646 #endif
7647 },
7648 {
7649 Mips_SHF_H, MIPS_INS_SHF,
7650 #ifndef CAPSTONE_DIET
7651 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7652 #endif
7653 },
7654 {
7655 Mips_SHF_W, MIPS_INS_SHF,
7656 #ifndef CAPSTONE_DIET
7657 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7658 #endif
7659 },
7660 {
7661 Mips_SHILO, MIPS_INS_SHILO,
7662 #ifndef CAPSTONE_DIET
7663 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7664 #endif
7665 },
7666 {
7667 Mips_SHILOV, MIPS_INS_SHILOV,
7668 #ifndef CAPSTONE_DIET
7669 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7670 #endif
7671 },
7672 {
7673 Mips_SHLLV_PH, MIPS_INS_SHLLV,
7674 #ifndef CAPSTONE_DIET
7675 { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7676 #endif
7677 },
7678 {
7679 Mips_SHLLV_QB, MIPS_INS_SHLLV,
7680 #ifndef CAPSTONE_DIET
7681 { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7682 #endif
7683 },
7684 {
7685 Mips_SHLLV_S_PH, MIPS_INS_SHLLV_S,
7686 #ifndef CAPSTONE_DIET
7687 { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7688 #endif
7689 },
7690 {
7691 Mips_SHLLV_S_W, MIPS_INS_SHLLV_S,
7692 #ifndef CAPSTONE_DIET
7693 { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7694 #endif
7695 },
7696 {
7697 Mips_SHLL_PH, MIPS_INS_SHLL,
7698 #ifndef CAPSTONE_DIET
7699 { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7700 #endif
7701 },
7702 {
7703 Mips_SHLL_QB, MIPS_INS_SHLL,
7704 #ifndef CAPSTONE_DIET
7705 { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7706 #endif
7707 },
7708 {
7709 Mips_SHLL_S_PH, MIPS_INS_SHLL_S,
7710 #ifndef CAPSTONE_DIET
7711 { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7712 #endif
7713 },
7714 {
7715 Mips_SHLL_S_W, MIPS_INS_SHLL_S,
7716 #ifndef CAPSTONE_DIET
7717 { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7718 #endif
7719 },
7720 {
7721 Mips_SHRAV_PH, MIPS_INS_SHRAV,
7722 #ifndef CAPSTONE_DIET
7723 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7724 #endif
7725 },
7726 {
7727 Mips_SHRAV_QB, MIPS_INS_SHRAV,
7728 #ifndef CAPSTONE_DIET
7729 { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
7730 #endif
7731 },
7732 {
7733 Mips_SHRAV_R_PH, MIPS_INS_SHRAV_R,
7734 #ifndef CAPSTONE_DIET
7735 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7736 #endif
7737 },
7738 {
7739 Mips_SHRAV_R_QB, MIPS_INS_SHRAV_R,
7740 #ifndef CAPSTONE_DIET
7741 { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
7742 #endif
7743 },
7744 {
7745 Mips_SHRAV_R_W, MIPS_INS_SHRAV_R,
7746 #ifndef CAPSTONE_DIET
7747 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7748 #endif
7749 },
7750 {
7751 Mips_SHRA_PH, MIPS_INS_SHRA,
7752 #ifndef CAPSTONE_DIET
7753 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7754 #endif
7755 },
7756 {
7757 Mips_SHRA_QB, MIPS_INS_SHRA,
7758 #ifndef CAPSTONE_DIET
7759 { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
7760 #endif
7761 },
7762 {
7763 Mips_SHRA_R_PH, MIPS_INS_SHRA_R,
7764 #ifndef CAPSTONE_DIET
7765 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7766 #endif
7767 },
7768 {
7769 Mips_SHRA_R_QB, MIPS_INS_SHRA_R,
7770 #ifndef CAPSTONE_DIET
7771 { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
7772 #endif
7773 },
7774 {
7775 Mips_SHRA_R_W, MIPS_INS_SHRA_R,
7776 #ifndef CAPSTONE_DIET
7777 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7778 #endif
7779 },
7780 {
7781 Mips_SHRLV_PH, MIPS_INS_SHRLV,
7782 #ifndef CAPSTONE_DIET
7783 { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
7784 #endif
7785 },
7786 {
7787 Mips_SHRLV_QB, MIPS_INS_SHRLV,
7788 #ifndef CAPSTONE_DIET
7789 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7790 #endif
7791 },
7792 {
7793 Mips_SHRL_PH, MIPS_INS_SHRL,
7794 #ifndef CAPSTONE_DIET
7795 { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
7796 #endif
7797 },
7798 {
7799 Mips_SHRL_QB, MIPS_INS_SHRL,
7800 #ifndef CAPSTONE_DIET
7801 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7802 #endif
7803 },
7804 {
7805 Mips_SH_MM, MIPS_INS_SH,
7806 #ifndef CAPSTONE_DIET
7807 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7808 #endif
7809 },
7810 {
7811 Mips_SLDI_B, MIPS_INS_SLDI,
7812 #ifndef CAPSTONE_DIET
7813 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7814 #endif
7815 },
7816 {
7817 Mips_SLDI_D, MIPS_INS_SLDI,
7818 #ifndef CAPSTONE_DIET
7819 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7820 #endif
7821 },
7822 {
7823 Mips_SLDI_H, MIPS_INS_SLDI,
7824 #ifndef CAPSTONE_DIET
7825 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7826 #endif
7827 },
7828 {
7829 Mips_SLDI_W, MIPS_INS_SLDI,
7830 #ifndef CAPSTONE_DIET
7831 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7832 #endif
7833 },
7834 {
7835 Mips_SLD_B, MIPS_INS_SLD,
7836 #ifndef CAPSTONE_DIET
7837 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7838 #endif
7839 },
7840 {
7841 Mips_SLD_D, MIPS_INS_SLD,
7842 #ifndef CAPSTONE_DIET
7843 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7844 #endif
7845 },
7846 {
7847 Mips_SLD_H, MIPS_INS_SLD,
7848 #ifndef CAPSTONE_DIET
7849 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7850 #endif
7851 },
7852 {
7853 Mips_SLD_W, MIPS_INS_SLD,
7854 #ifndef CAPSTONE_DIET
7855 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7856 #endif
7857 },
7858 {
7859 Mips_SLL, MIPS_INS_SLL,
7860 #ifndef CAPSTONE_DIET
7861 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
7862 #endif
7863 },
7864 {
7865 Mips_SLL64_32, MIPS_INS_SLL,
7866 #ifndef CAPSTONE_DIET
7867 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
7868 #endif
7869 },
7870 {
7871 Mips_SLL64_64, MIPS_INS_SLL,
7872 #ifndef CAPSTONE_DIET
7873 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
7874 #endif
7875 },
7876 {
7877 Mips_SLLI_B, MIPS_INS_SLLI,
7878 #ifndef CAPSTONE_DIET
7879 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7880 #endif
7881 },
7882 {
7883 Mips_SLLI_D, MIPS_INS_SLLI,
7884 #ifndef CAPSTONE_DIET
7885 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7886 #endif
7887 },
7888 {
7889 Mips_SLLI_H, MIPS_INS_SLLI,
7890 #ifndef CAPSTONE_DIET
7891 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7892 #endif
7893 },
7894 {
7895 Mips_SLLI_W, MIPS_INS_SLLI,
7896 #ifndef CAPSTONE_DIET
7897 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7898 #endif
7899 },
7900 {
7901 Mips_SLLV, MIPS_INS_SLLV,
7902 #ifndef CAPSTONE_DIET
7903 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
7904 #endif
7905 },
7906 {
7907 Mips_SLLV_MM, MIPS_INS_SLLV,
7908 #ifndef CAPSTONE_DIET
7909 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7910 #endif
7911 },
7912 {
7913 Mips_SLL_B, MIPS_INS_SLL,
7914 #ifndef CAPSTONE_DIET
7915 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7916 #endif
7917 },
7918 {
7919 Mips_SLL_D, MIPS_INS_SLL,
7920 #ifndef CAPSTONE_DIET
7921 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7922 #endif
7923 },
7924 {
7925 Mips_SLL_H, MIPS_INS_SLL,
7926 #ifndef CAPSTONE_DIET
7927 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7928 #endif
7929 },
7930 {
7931 Mips_SLL_MM, MIPS_INS_SLL,
7932 #ifndef CAPSTONE_DIET
7933 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7934 #endif
7935 },
7936 {
7937 Mips_SLL_W, MIPS_INS_SLL,
7938 #ifndef CAPSTONE_DIET
7939 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7940 #endif
7941 },
7942 {
7943 Mips_SLT, MIPS_INS_SLT,
7944 #ifndef CAPSTONE_DIET
7945 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
7946 #endif
7947 },
7948 {
7949 Mips_SLT64, MIPS_INS_SLT,
7950 #ifndef CAPSTONE_DIET
7951 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
7952 #endif
7953 },
7954 {
7955 Mips_SLT_MM, MIPS_INS_SLT,
7956 #ifndef CAPSTONE_DIET
7957 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7958 #endif
7959 },
7960 {
7961 Mips_SLTi, MIPS_INS_SLTI,
7962 #ifndef CAPSTONE_DIET
7963 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
7964 #endif
7965 },
7966 {
7967 Mips_SLTi64, MIPS_INS_SLTI,
7968 #ifndef CAPSTONE_DIET
7969 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
7970 #endif
7971 },
7972 {
7973 Mips_SLTi_MM, MIPS_INS_SLTI,
7974 #ifndef CAPSTONE_DIET
7975 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7976 #endif
7977 },
7978 {
7979 Mips_SLTiu, MIPS_INS_SLTIU,
7980 #ifndef CAPSTONE_DIET
7981 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
7982 #endif
7983 },
7984 {
7985 Mips_SLTiu64, MIPS_INS_SLTIU,
7986 #ifndef CAPSTONE_DIET
7987 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
7988 #endif
7989 },
7990 {
7991 Mips_SLTiu_MM, MIPS_INS_SLTIU,
7992 #ifndef CAPSTONE_DIET
7993 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7994 #endif
7995 },
7996 {
7997 Mips_SLTu, MIPS_INS_SLTU,
7998 #ifndef CAPSTONE_DIET
7999 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8000 #endif
8001 },
8002 {
8003 Mips_SLTu64, MIPS_INS_SLTU,
8004 #ifndef CAPSTONE_DIET
8005 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8006 #endif
8007 },
8008 {
8009 Mips_SLTu_MM, MIPS_INS_SLTU,
8010 #ifndef CAPSTONE_DIET
8011 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8012 #endif
8013 },
8014 {
8015 Mips_SNE, MIPS_INS_SNE,
8016 #ifndef CAPSTONE_DIET
8017 { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
8018 #endif
8019 },
8020 {
8021 Mips_SNEi, MIPS_INS_SNEI,
8022 #ifndef CAPSTONE_DIET
8023 { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
8024 #endif
8025 },
8026 {
8027 Mips_SPLATI_B, MIPS_INS_SPLATI,
8028 #ifndef CAPSTONE_DIET
8029 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8030 #endif
8031 },
8032 {
8033 Mips_SPLATI_D, MIPS_INS_SPLATI,
8034 #ifndef CAPSTONE_DIET
8035 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8036 #endif
8037 },
8038 {
8039 Mips_SPLATI_H, MIPS_INS_SPLATI,
8040 #ifndef CAPSTONE_DIET
8041 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8042 #endif
8043 },
8044 {
8045 Mips_SPLATI_W, MIPS_INS_SPLATI,
8046 #ifndef CAPSTONE_DIET
8047 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8048 #endif
8049 },
8050 {
8051 Mips_SPLAT_B, MIPS_INS_SPLAT,
8052 #ifndef CAPSTONE_DIET
8053 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8054 #endif
8055 },
8056 {
8057 Mips_SPLAT_D, MIPS_INS_SPLAT,
8058 #ifndef CAPSTONE_DIET
8059 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8060 #endif
8061 },
8062 {
8063 Mips_SPLAT_H, MIPS_INS_SPLAT,
8064 #ifndef CAPSTONE_DIET
8065 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8066 #endif
8067 },
8068 {
8069 Mips_SPLAT_W, MIPS_INS_SPLAT,
8070 #ifndef CAPSTONE_DIET
8071 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8072 #endif
8073 },
8074 {
8075 Mips_SRA, MIPS_INS_SRA,
8076 #ifndef CAPSTONE_DIET
8077 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8078 #endif
8079 },
8080 {
8081 Mips_SRAI_B, MIPS_INS_SRAI,
8082 #ifndef CAPSTONE_DIET
8083 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8084 #endif
8085 },
8086 {
8087 Mips_SRAI_D, MIPS_INS_SRAI,
8088 #ifndef CAPSTONE_DIET
8089 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8090 #endif
8091 },
8092 {
8093 Mips_SRAI_H, MIPS_INS_SRAI,
8094 #ifndef CAPSTONE_DIET
8095 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8096 #endif
8097 },
8098 {
8099 Mips_SRAI_W, MIPS_INS_SRAI,
8100 #ifndef CAPSTONE_DIET
8101 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8102 #endif
8103 },
8104 {
8105 Mips_SRARI_B, MIPS_INS_SRARI,
8106 #ifndef CAPSTONE_DIET
8107 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8108 #endif
8109 },
8110 {
8111 Mips_SRARI_D, MIPS_INS_SRARI,
8112 #ifndef CAPSTONE_DIET
8113 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8114 #endif
8115 },
8116 {
8117 Mips_SRARI_H, MIPS_INS_SRARI,
8118 #ifndef CAPSTONE_DIET
8119 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8120 #endif
8121 },
8122 {
8123 Mips_SRARI_W, MIPS_INS_SRARI,
8124 #ifndef CAPSTONE_DIET
8125 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8126 #endif
8127 },
8128 {
8129 Mips_SRAR_B, MIPS_INS_SRAR,
8130 #ifndef CAPSTONE_DIET
8131 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8132 #endif
8133 },
8134 {
8135 Mips_SRAR_D, MIPS_INS_SRAR,
8136 #ifndef CAPSTONE_DIET
8137 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8138 #endif
8139 },
8140 {
8141 Mips_SRAR_H, MIPS_INS_SRAR,
8142 #ifndef CAPSTONE_DIET
8143 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8144 #endif
8145 },
8146 {
8147 Mips_SRAR_W, MIPS_INS_SRAR,
8148 #ifndef CAPSTONE_DIET
8149 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8150 #endif
8151 },
8152 {
8153 Mips_SRAV, MIPS_INS_SRAV,
8154 #ifndef CAPSTONE_DIET
8155 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8156 #endif
8157 },
8158 {
8159 Mips_SRAV_MM, MIPS_INS_SRAV,
8160 #ifndef CAPSTONE_DIET
8161 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8162 #endif
8163 },
8164 {
8165 Mips_SRA_B, MIPS_INS_SRA,
8166 #ifndef CAPSTONE_DIET
8167 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8168 #endif
8169 },
8170 {
8171 Mips_SRA_D, MIPS_INS_SRA,
8172 #ifndef CAPSTONE_DIET
8173 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8174 #endif
8175 },
8176 {
8177 Mips_SRA_H, MIPS_INS_SRA,
8178 #ifndef CAPSTONE_DIET
8179 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8180 #endif
8181 },
8182 {
8183 Mips_SRA_MM, MIPS_INS_SRA,
8184 #ifndef CAPSTONE_DIET
8185 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8186 #endif
8187 },
8188 {
8189 Mips_SRA_W, MIPS_INS_SRA,
8190 #ifndef CAPSTONE_DIET
8191 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8192 #endif
8193 },
8194 {
8195 Mips_SRL, MIPS_INS_SRL,
8196 #ifndef CAPSTONE_DIET
8197 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8198 #endif
8199 },
8200 {
8201 Mips_SRLI_B, MIPS_INS_SRLI,
8202 #ifndef CAPSTONE_DIET
8203 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8204 #endif
8205 },
8206 {
8207 Mips_SRLI_D, MIPS_INS_SRLI,
8208 #ifndef CAPSTONE_DIET
8209 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8210 #endif
8211 },
8212 {
8213 Mips_SRLI_H, MIPS_INS_SRLI,
8214 #ifndef CAPSTONE_DIET
8215 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8216 #endif
8217 },
8218 {
8219 Mips_SRLI_W, MIPS_INS_SRLI,
8220 #ifndef CAPSTONE_DIET
8221 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8222 #endif
8223 },
8224 {
8225 Mips_SRLRI_B, MIPS_INS_SRLRI,
8226 #ifndef CAPSTONE_DIET
8227 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8228 #endif
8229 },
8230 {
8231 Mips_SRLRI_D, MIPS_INS_SRLRI,
8232 #ifndef CAPSTONE_DIET
8233 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8234 #endif
8235 },
8236 {
8237 Mips_SRLRI_H, MIPS_INS_SRLRI,
8238 #ifndef CAPSTONE_DIET
8239 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8240 #endif
8241 },
8242 {
8243 Mips_SRLRI_W, MIPS_INS_SRLRI,
8244 #ifndef CAPSTONE_DIET
8245 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8246 #endif
8247 },
8248 {
8249 Mips_SRLR_B, MIPS_INS_SRLR,
8250 #ifndef CAPSTONE_DIET
8251 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8252 #endif
8253 },
8254 {
8255 Mips_SRLR_D, MIPS_INS_SRLR,
8256 #ifndef CAPSTONE_DIET
8257 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8258 #endif
8259 },
8260 {
8261 Mips_SRLR_H, MIPS_INS_SRLR,
8262 #ifndef CAPSTONE_DIET
8263 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8264 #endif
8265 },
8266 {
8267 Mips_SRLR_W, MIPS_INS_SRLR,
8268 #ifndef CAPSTONE_DIET
8269 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8270 #endif
8271 },
8272 {
8273 Mips_SRLV, MIPS_INS_SRLV,
8274 #ifndef CAPSTONE_DIET
8275 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8276 #endif
8277 },
8278 {
8279 Mips_SRLV_MM, MIPS_INS_SRLV,
8280 #ifndef CAPSTONE_DIET
8281 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8282 #endif
8283 },
8284 {
8285 Mips_SRL_B, MIPS_INS_SRL,
8286 #ifndef CAPSTONE_DIET
8287 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8288 #endif
8289 },
8290 {
8291 Mips_SRL_D, MIPS_INS_SRL,
8292 #ifndef CAPSTONE_DIET
8293 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8294 #endif
8295 },
8296 {
8297 Mips_SRL_H, MIPS_INS_SRL,
8298 #ifndef CAPSTONE_DIET
8299 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8300 #endif
8301 },
8302 {
8303 Mips_SRL_MM, MIPS_INS_SRL,
8304 #ifndef CAPSTONE_DIET
8305 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8306 #endif
8307 },
8308 {
8309 Mips_SRL_W, MIPS_INS_SRL,
8310 #ifndef CAPSTONE_DIET
8311 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8312 #endif
8313 },
8314 {
8315 Mips_SSNOP, MIPS_INS_SSNOP,
8316 #ifndef CAPSTONE_DIET
8317 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8318 #endif
8319 },
8320 {
8321 Mips_ST_B, MIPS_INS_ST,
8322 #ifndef CAPSTONE_DIET
8323 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8324 #endif
8325 },
8326 {
8327 Mips_ST_D, MIPS_INS_ST,
8328 #ifndef CAPSTONE_DIET
8329 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8330 #endif
8331 },
8332 {
8333 Mips_ST_H, MIPS_INS_ST,
8334 #ifndef CAPSTONE_DIET
8335 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8336 #endif
8337 },
8338 {
8339 Mips_ST_W, MIPS_INS_ST,
8340 #ifndef CAPSTONE_DIET
8341 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8342 #endif
8343 },
8344 {
8345 Mips_SUB, MIPS_INS_SUB,
8346 #ifndef CAPSTONE_DIET
8347 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8348 #endif
8349 },
8350 {
8351 Mips_SUBQH_PH, MIPS_INS_SUBQH,
8352 #ifndef CAPSTONE_DIET
8353 { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
8354 #endif
8355 },
8356 {
8357 Mips_SUBQH_R_PH, MIPS_INS_SUBQH_R,
8358 #ifndef CAPSTONE_DIET
8359 { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
8360 #endif
8361 },
8362 {
8363 Mips_SUBQH_R_W, MIPS_INS_SUBQH_R,
8364 #ifndef CAPSTONE_DIET
8365 { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
8366 #endif
8367 },
8368 {
8369 Mips_SUBQH_W, MIPS_INS_SUBQH,
8370 #ifndef CAPSTONE_DIET
8371 { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
8372 #endif
8373 },
8374 {
8375 Mips_SUBQ_PH, MIPS_INS_SUBQ,
8376 #ifndef CAPSTONE_DIET
8377 { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
8378 #endif
8379 },
8380 {
8381 Mips_SUBQ_S_PH, MIPS_INS_SUBQ_S,
8382 #ifndef CAPSTONE_DIET
8383 { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
8384 #endif
8385 },
8386 {
8387 Mips_SUBQ_S_W, MIPS_INS_SUBQ_S,
8388 #ifndef CAPSTONE_DIET
8389 { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
8390 #endif
8391 },
8392 {
8393 Mips_SUBSUS_U_B, MIPS_INS_SUBSUS_U,
8394 #ifndef CAPSTONE_DIET
8395 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8396 #endif
8397 },
8398 {
8399 Mips_SUBSUS_U_D, MIPS_INS_SUBSUS_U,
8400 #ifndef CAPSTONE_DIET
8401 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8402 #endif
8403 },
8404 {
8405 Mips_SUBSUS_U_H, MIPS_INS_SUBSUS_U,
8406 #ifndef CAPSTONE_DIET
8407 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8408 #endif
8409 },
8410 {
8411 Mips_SUBSUS_U_W, MIPS_INS_SUBSUS_U,
8412 #ifndef CAPSTONE_DIET
8413 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8414 #endif
8415 },
8416 {
8417 Mips_SUBSUU_S_B, MIPS_INS_SUBSUU_S,
8418 #ifndef CAPSTONE_DIET
8419 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8420 #endif
8421 },
8422 {
8423 Mips_SUBSUU_S_D, MIPS_INS_SUBSUU_S,
8424 #ifndef CAPSTONE_DIET
8425 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8426 #endif
8427 },
8428 {
8429 Mips_SUBSUU_S_H, MIPS_INS_SUBSUU_S,
8430 #ifndef CAPSTONE_DIET
8431 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8432 #endif
8433 },
8434 {
8435 Mips_SUBSUU_S_W, MIPS_INS_SUBSUU_S,
8436 #ifndef CAPSTONE_DIET
8437 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8438 #endif
8439 },
8440 {
8441 Mips_SUBS_S_B, MIPS_INS_SUBS_S,
8442 #ifndef CAPSTONE_DIET
8443 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8444 #endif
8445 },
8446 {
8447 Mips_SUBS_S_D, MIPS_INS_SUBS_S,
8448 #ifndef CAPSTONE_DIET
8449 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8450 #endif
8451 },
8452 {
8453 Mips_SUBS_S_H, MIPS_INS_SUBS_S,
8454 #ifndef CAPSTONE_DIET
8455 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8456 #endif
8457 },
8458 {
8459 Mips_SUBS_S_W, MIPS_INS_SUBS_S,
8460 #ifndef CAPSTONE_DIET
8461 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8462 #endif
8463 },
8464 {
8465 Mips_SUBS_U_B, MIPS_INS_SUBS_U,
8466 #ifndef CAPSTONE_DIET
8467 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8468 #endif
8469 },
8470 {
8471 Mips_SUBS_U_D, MIPS_INS_SUBS_U,
8472 #ifndef CAPSTONE_DIET
8473 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8474 #endif
8475 },
8476 {
8477 Mips_SUBS_U_H, MIPS_INS_SUBS_U,
8478 #ifndef CAPSTONE_DIET
8479 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8480 #endif
8481 },
8482 {
8483 Mips_SUBS_U_W, MIPS_INS_SUBS_U,
8484 #ifndef CAPSTONE_DIET
8485 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8486 #endif
8487 },
8488 {
8489 Mips_SUBUH_QB, MIPS_INS_SUBUH,
8490 #ifndef CAPSTONE_DIET
8491 { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
8492 #endif
8493 },
8494 {
8495 Mips_SUBUH_R_QB, MIPS_INS_SUBUH_R,
8496 #ifndef CAPSTONE_DIET
8497 { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
8498 #endif
8499 },
8500 {
8501 Mips_SUBU_PH, MIPS_INS_SUBU,
8502 #ifndef CAPSTONE_DIET
8503 { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
8504 #endif
8505 },
8506 {
8507 Mips_SUBU_QB, MIPS_INS_SUBU,
8508 #ifndef CAPSTONE_DIET
8509 { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
8510 #endif
8511 },
8512 {
8513 Mips_SUBU_S_PH, MIPS_INS_SUBU_S,
8514 #ifndef CAPSTONE_DIET
8515 { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
8516 #endif
8517 },
8518 {
8519 Mips_SUBU_S_QB, MIPS_INS_SUBU_S,
8520 #ifndef CAPSTONE_DIET
8521 { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
8522 #endif
8523 },
8524 {
8525 Mips_SUBVI_B, MIPS_INS_SUBVI,
8526 #ifndef CAPSTONE_DIET
8527 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8528 #endif
8529 },
8530 {
8531 Mips_SUBVI_D, MIPS_INS_SUBVI,
8532 #ifndef CAPSTONE_DIET
8533 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8534 #endif
8535 },
8536 {
8537 Mips_SUBVI_H, MIPS_INS_SUBVI,
8538 #ifndef CAPSTONE_DIET
8539 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8540 #endif
8541 },
8542 {
8543 Mips_SUBVI_W, MIPS_INS_SUBVI,
8544 #ifndef CAPSTONE_DIET
8545 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8546 #endif
8547 },
8548 {
8549 Mips_SUBV_B, MIPS_INS_SUBV,
8550 #ifndef CAPSTONE_DIET
8551 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8552 #endif
8553 },
8554 {
8555 Mips_SUBV_D, MIPS_INS_SUBV,
8556 #ifndef CAPSTONE_DIET
8557 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8558 #endif
8559 },
8560 {
8561 Mips_SUBV_H, MIPS_INS_SUBV,
8562 #ifndef CAPSTONE_DIET
8563 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8564 #endif
8565 },
8566 {
8567 Mips_SUBV_W, MIPS_INS_SUBV,
8568 #ifndef CAPSTONE_DIET
8569 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8570 #endif
8571 },
8572 {
8573 Mips_SUB_MM, MIPS_INS_SUB,
8574 #ifndef CAPSTONE_DIET
8575 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8576 #endif
8577 },
8578 {
8579 Mips_SUBu, MIPS_INS_SUBU,
8580 #ifndef CAPSTONE_DIET
8581 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8582 #endif
8583 },
8584 {
8585 Mips_SUBu_MM, MIPS_INS_SUBU,
8586 #ifndef CAPSTONE_DIET
8587 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8588 #endif
8589 },
8590 {
8591 Mips_SUXC1, MIPS_INS_SUXC1,
8592 #ifndef CAPSTONE_DIET
8593 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0
8594 #endif
8595 },
8596 {
8597 Mips_SUXC164, MIPS_INS_SUXC1,
8598 #ifndef CAPSTONE_DIET
8599 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
8600 #endif
8601 },
8602 {
8603 Mips_SUXC1_MM, MIPS_INS_SUXC1,
8604 #ifndef CAPSTONE_DIET
8605 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8606 #endif
8607 },
8608 {
8609 Mips_SW, MIPS_INS_SW,
8610 #ifndef CAPSTONE_DIET
8611 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8612 #endif
8613 },
8614 {
8615 Mips_SW64, MIPS_INS_SW,
8616 #ifndef CAPSTONE_DIET
8617 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8618 #endif
8619 },
8620 {
8621 Mips_SWC1, MIPS_INS_SWC1,
8622 #ifndef CAPSTONE_DIET
8623 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8624 #endif
8625 },
8626 {
8627 Mips_SWC1_MM, MIPS_INS_SWC1,
8628 #ifndef CAPSTONE_DIET
8629 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8630 #endif
8631 },
8632 {
8633 Mips_SWC2, MIPS_INS_SWC2,
8634 #ifndef CAPSTONE_DIET
8635 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
8636 #endif
8637 },
8638 {
8639 Mips_SWC2_R6, MIPS_INS_SWC2,
8640 #ifndef CAPSTONE_DIET
8641 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
8642 #endif
8643 },
8644 {
8645 Mips_SWC3, MIPS_INS_SWC3,
8646 #ifndef CAPSTONE_DIET
8647 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8648 #endif
8649 },
8650 {
8651 Mips_SWL, MIPS_INS_SWL,
8652 #ifndef CAPSTONE_DIET
8653 { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
8654 #endif
8655 },
8656 {
8657 Mips_SWL64, MIPS_INS_SWL,
8658 #ifndef CAPSTONE_DIET
8659 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8660 #endif
8661 },
8662 {
8663 Mips_SWL_MM, MIPS_INS_SWL,
8664 #ifndef CAPSTONE_DIET
8665 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8666 #endif
8667 },
8668 {
8669 Mips_SWR, MIPS_INS_SWR,
8670 #ifndef CAPSTONE_DIET
8671 { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
8672 #endif
8673 },
8674 {
8675 Mips_SWR64, MIPS_INS_SWR,
8676 #ifndef CAPSTONE_DIET
8677 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8678 #endif
8679 },
8680 {
8681 Mips_SWR_MM, MIPS_INS_SWR,
8682 #ifndef CAPSTONE_DIET
8683 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8684 #endif
8685 },
8686 {
8687 Mips_SWXC1, MIPS_INS_SWXC1,
8688 #ifndef CAPSTONE_DIET
8689 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0
8690 #endif
8691 },
8692 {
8693 Mips_SWXC1_MM, MIPS_INS_SWXC1,
8694 #ifndef CAPSTONE_DIET
8695 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8696 #endif
8697 },
8698 {
8699 Mips_SW_MM, MIPS_INS_SW,
8700 #ifndef CAPSTONE_DIET
8701 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8702 #endif
8703 },
8704 {
8705 Mips_SYNC, MIPS_INS_SYNC,
8706 #ifndef CAPSTONE_DIET
8707 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0
8708 #endif
8709 },
8710 {
8711 Mips_SYNC_MM, MIPS_INS_SYNC,
8712 #ifndef CAPSTONE_DIET
8713 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8714 #endif
8715 },
8716 {
8717 Mips_SYSCALL, MIPS_INS_SYSCALL,
8718 #ifndef CAPSTONE_DIET
8719 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8720 #endif
8721 },
8722 {
8723 Mips_SYSCALL_MM, MIPS_INS_SYSCALL,
8724 #ifndef CAPSTONE_DIET
8725 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8726 #endif
8727 },
8728 {
8729 Mips_SbRxRyOffMemX16, MIPS_INS_SB,
8730 #ifndef CAPSTONE_DIET
8731 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8732 #endif
8733 },
8734 {
8735 Mips_SebRx16, MIPS_INS_SEB,
8736 #ifndef CAPSTONE_DIET
8737 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8738 #endif
8739 },
8740 {
8741 Mips_SehRx16, MIPS_INS_SEH,
8742 #ifndef CAPSTONE_DIET
8743 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8744 #endif
8745 },
8746 {
8747 Mips_ShRxRyOffMemX16, MIPS_INS_SH,
8748 #ifndef CAPSTONE_DIET
8749 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8750 #endif
8751 },
8752 {
8753 Mips_SllX16, MIPS_INS_SLL,
8754 #ifndef CAPSTONE_DIET
8755 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8756 #endif
8757 },
8758 {
8759 Mips_SllvRxRy16, MIPS_INS_SLLV,
8760 #ifndef CAPSTONE_DIET
8761 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8762 #endif
8763 },
8764 {
8765 Mips_SltRxRy16, MIPS_INS_SLT,
8766 #ifndef CAPSTONE_DIET
8767 { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8768 #endif
8769 },
8770 {
8771 Mips_SltiRxImm16, MIPS_INS_SLTI,
8772 #ifndef CAPSTONE_DIET
8773 { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8774 #endif
8775 },
8776 {
8777 Mips_SltiRxImmX16, MIPS_INS_SLTI,
8778 #ifndef CAPSTONE_DIET
8779 { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8780 #endif
8781 },
8782 {
8783 Mips_SltiuRxImm16, MIPS_INS_SLTIU,
8784 #ifndef CAPSTONE_DIET
8785 { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8786 #endif
8787 },
8788 {
8789 Mips_SltiuRxImmX16, MIPS_INS_SLTIU,
8790 #ifndef CAPSTONE_DIET
8791 { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8792 #endif
8793 },
8794 {
8795 Mips_SltuRxRy16, MIPS_INS_SLTU,
8796 #ifndef CAPSTONE_DIET
8797 { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8798 #endif
8799 },
8800 {
8801 Mips_SraX16, MIPS_INS_SRA,
8802 #ifndef CAPSTONE_DIET
8803 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8804 #endif
8805 },
8806 {
8807 Mips_SravRxRy16, MIPS_INS_SRAV,
8808 #ifndef CAPSTONE_DIET
8809 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8810 #endif
8811 },
8812 {
8813 Mips_SrlX16, MIPS_INS_SRL,
8814 #ifndef CAPSTONE_DIET
8815 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8816 #endif
8817 },
8818 {
8819 Mips_SrlvRxRy16, MIPS_INS_SRLV,
8820 #ifndef CAPSTONE_DIET
8821 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8822 #endif
8823 },
8824 {
8825 Mips_SubuRxRyRz16, MIPS_INS_SUBU,
8826 #ifndef CAPSTONE_DIET
8827 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8828 #endif
8829 },
8830 {
8831 Mips_SwRxRyOffMemX16, MIPS_INS_SW,
8832 #ifndef CAPSTONE_DIET
8833 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8834 #endif
8835 },
8836 {
8837 Mips_SwRxSpImmX16, MIPS_INS_SW,
8838 #ifndef CAPSTONE_DIET
8839 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8840 #endif
8841 },
8842 {
8843 Mips_TEQ, MIPS_INS_TEQ,
8844 #ifndef CAPSTONE_DIET
8845 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
8846 #endif
8847 },
8848 {
8849 Mips_TEQI, MIPS_INS_TEQI,
8850 #ifndef CAPSTONE_DIET
8851 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
8852 #endif
8853 },
8854 {
8855 Mips_TEQI_MM, MIPS_INS_TEQI,
8856 #ifndef CAPSTONE_DIET
8857 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8858 #endif
8859 },
8860 {
8861 Mips_TEQ_MM, MIPS_INS_TEQ,
8862 #ifndef CAPSTONE_DIET
8863 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8864 #endif
8865 },
8866 {
8867 Mips_TGE, MIPS_INS_TGE,
8868 #ifndef CAPSTONE_DIET
8869 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
8870 #endif
8871 },
8872 {
8873 Mips_TGEI, MIPS_INS_TGEI,
8874 #ifndef CAPSTONE_DIET
8875 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
8876 #endif
8877 },
8878 {
8879 Mips_TGEIU, MIPS_INS_TGEIU,
8880 #ifndef CAPSTONE_DIET
8881 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
8882 #endif
8883 },
8884 {
8885 Mips_TGEIU_MM, MIPS_INS_TGEIU,
8886 #ifndef CAPSTONE_DIET
8887 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8888 #endif
8889 },
8890 {
8891 Mips_TGEI_MM, MIPS_INS_TGEI,
8892 #ifndef CAPSTONE_DIET
8893 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8894 #endif
8895 },
8896 {
8897 Mips_TGEU, MIPS_INS_TGEU,
8898 #ifndef CAPSTONE_DIET
8899 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
8900 #endif
8901 },
8902 {
8903 Mips_TGEU_MM, MIPS_INS_TGEU,
8904 #ifndef CAPSTONE_DIET
8905 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8906 #endif
8907 },
8908 {
8909 Mips_TGE_MM, MIPS_INS_TGE,
8910 #ifndef CAPSTONE_DIET
8911 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8912 #endif
8913 },
8914 {
8915 Mips_TLBP, MIPS_INS_TLBP,
8916 #ifndef CAPSTONE_DIET
8917 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8918 #endif
8919 },
8920 {
8921 Mips_TLBP_MM, MIPS_INS_TLBP,
8922 #ifndef CAPSTONE_DIET
8923 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8924 #endif
8925 },
8926 {
8927 Mips_TLBR, MIPS_INS_TLBR,
8928 #ifndef CAPSTONE_DIET
8929 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8930 #endif
8931 },
8932 {
8933 Mips_TLBR_MM, MIPS_INS_TLBR,
8934 #ifndef CAPSTONE_DIET
8935 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8936 #endif
8937 },
8938 {
8939 Mips_TLBWI, MIPS_INS_TLBWI,
8940 #ifndef CAPSTONE_DIET
8941 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8942 #endif
8943 },
8944 {
8945 Mips_TLBWI_MM, MIPS_INS_TLBWI,
8946 #ifndef CAPSTONE_DIET
8947 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8948 #endif
8949 },
8950 {
8951 Mips_TLBWR, MIPS_INS_TLBWR,
8952 #ifndef CAPSTONE_DIET
8953 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8954 #endif
8955 },
8956 {
8957 Mips_TLBWR_MM, MIPS_INS_TLBWR,
8958 #ifndef CAPSTONE_DIET
8959 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8960 #endif
8961 },
8962 {
8963 Mips_TLT, MIPS_INS_TLT,
8964 #ifndef CAPSTONE_DIET
8965 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
8966 #endif
8967 },
8968 {
8969 Mips_TLTI, MIPS_INS_TLTI,
8970 #ifndef CAPSTONE_DIET
8971 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
8972 #endif
8973 },
8974 {
8975 Mips_TLTIU_MM, MIPS_INS_TLTIU,
8976 #ifndef CAPSTONE_DIET
8977 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8978 #endif
8979 },
8980 {
8981 Mips_TLTI_MM, MIPS_INS_TLTI,
8982 #ifndef CAPSTONE_DIET
8983 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8984 #endif
8985 },
8986 {
8987 Mips_TLTU, MIPS_INS_TLTU,
8988 #ifndef CAPSTONE_DIET
8989 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
8990 #endif
8991 },
8992 {
8993 Mips_TLTU_MM, MIPS_INS_TLTU,
8994 #ifndef CAPSTONE_DIET
8995 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8996 #endif
8997 },
8998 {
8999 Mips_TLT_MM, MIPS_INS_TLT,
9000 #ifndef CAPSTONE_DIET
9001 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
9002 #endif
9003 },
9004 {
9005 Mips_TNE, MIPS_INS_TNE,
9006 #ifndef CAPSTONE_DIET
9007 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
9008 #endif
9009 },
9010 {
9011 Mips_TNEI, MIPS_INS_TNEI,
9012 #ifndef CAPSTONE_DIET
9013 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
9014 #endif
9015 },
9016 {
9017 Mips_TNEI_MM, MIPS_INS_TNEI,
9018 #ifndef CAPSTONE_DIET
9019 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
9020 #endif
9021 },
9022 {
9023 Mips_TNE_MM, MIPS_INS_TNE,
9024 #ifndef CAPSTONE_DIET
9025 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
9026 #endif
9027 },
9028 {
9029 Mips_TRUNC_L_D64, MIPS_INS_TRUNC,
9030 #ifndef CAPSTONE_DIET
9031 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
9032 #endif
9033 },
9034 {
9035 Mips_TRUNC_L_S, MIPS_INS_TRUNC,
9036 #ifndef CAPSTONE_DIET
9037 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
9038 #endif
9039 },
9040 {
9041 Mips_TRUNC_W_D32, MIPS_INS_TRUNC,
9042 #ifndef CAPSTONE_DIET
9043 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
9044 #endif
9045 },
9046 {
9047 Mips_TRUNC_W_D64, MIPS_INS_TRUNC,
9048 #ifndef CAPSTONE_DIET
9049 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0
9050 #endif
9051 },
9052 {
9053 Mips_TRUNC_W_MM, MIPS_INS_TRUNC,
9054 #ifndef CAPSTONE_DIET
9055 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
9056 #endif
9057 },
9058 {
9059 Mips_TRUNC_W_S, MIPS_INS_TRUNC,
9060 #ifndef CAPSTONE_DIET
9061 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
9062 #endif
9063 },
9064 {
9065 Mips_TRUNC_W_S_MM, MIPS_INS_TRUNC,
9066 #ifndef CAPSTONE_DIET
9067 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
9068 #endif
9069 },
9070 {
9071 Mips_TTLTIU, MIPS_INS_TLTIU,
9072 #ifndef CAPSTONE_DIET
9073 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
9074 #endif
9075 },
9076 {
9077 Mips_UDIV, MIPS_INS_DIVU,
9078 #ifndef CAPSTONE_DIET
9079 { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
9080 #endif
9081 },
9082 {
9083 Mips_UDIV_MM, MIPS_INS_DIVU,
9084 #ifndef CAPSTONE_DIET
9085 { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
9086 #endif
9087 },
9088 {
9089 Mips_V3MULU, MIPS_INS_V3MULU,
9090 #ifndef CAPSTONE_DIET
9091 { 0 }, { MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
9092 #endif
9093 },
9094 {
9095 Mips_VMM0, MIPS_INS_VMM0,
9096 #ifndef CAPSTONE_DIET
9097 { 0 }, { MIPS_REG_MPL0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
9098 #endif
9099 },
9100 {
9101 Mips_VMULU, MIPS_INS_VMULU,
9102 #ifndef CAPSTONE_DIET
9103 { 0 }, { MIPS_REG_MPL1, MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
9104 #endif
9105 },
9106 {
9107 Mips_VSHF_B, MIPS_INS_VSHF,
9108 #ifndef CAPSTONE_DIET
9109 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
9110 #endif
9111 },
9112 {
9113 Mips_VSHF_D, MIPS_INS_VSHF,
9114 #ifndef CAPSTONE_DIET
9115 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
9116 #endif
9117 },
9118 {
9119 Mips_VSHF_H, MIPS_INS_VSHF,
9120 #ifndef CAPSTONE_DIET
9121 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
9122 #endif
9123 },
9124 {
9125 Mips_VSHF_W, MIPS_INS_VSHF,
9126 #ifndef CAPSTONE_DIET
9127 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
9128 #endif
9129 },
9130 {
9131 Mips_WAIT, MIPS_INS_WAIT,
9132 #ifndef CAPSTONE_DIET
9133 { 0 }, { 0 }, { MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
9134 #endif
9135 },
9136 {
9137 Mips_WAIT_MM, MIPS_INS_WAIT,
9138 #ifndef CAPSTONE_DIET
9139 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
9140 #endif
9141 },
9142 {
9143 Mips_WRDSP, MIPS_INS_WRDSP,
9144 #ifndef CAPSTONE_DIET
9145 { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
9146 #endif
9147 },
9148 {
9149 Mips_WSBH, MIPS_INS_WSBH,
9150 #ifndef CAPSTONE_DIET
9151 { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
9152 #endif
9153 },
9154 {
9155 Mips_WSBH_MM, MIPS_INS_WSBH,
9156 #ifndef CAPSTONE_DIET
9157 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
9158 #endif
9159 },
9160 {
9161 Mips_XOR, MIPS_INS_XOR,
9162 #ifndef CAPSTONE_DIET
9163 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
9164 #endif
9165 },
9166 {
9167 Mips_XOR64, MIPS_INS_XOR,
9168 #ifndef CAPSTONE_DIET
9169 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
9170 #endif
9171 },
9172 {
9173 Mips_XORI_B, MIPS_INS_XORI,
9174 #ifndef CAPSTONE_DIET
9175 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
9176 #endif
9177 },
9178 {
9179 Mips_XOR_MM, MIPS_INS_XOR,
9180 #ifndef CAPSTONE_DIET
9181 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
9182 #endif
9183 },
9184 {
9185 Mips_XOR_V, MIPS_INS_XOR,
9186 #ifndef CAPSTONE_DIET
9187 { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
9188 #endif
9189 },
9190 {
9191 Mips_XORi, MIPS_INS_XORI,
9192 #ifndef CAPSTONE_DIET
9193 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
9194 #endif
9195 },
9196 {
9197 Mips_XORi64, MIPS_INS_XORI,
9198 #ifndef CAPSTONE_DIET
9199 { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
9200 #endif
9201 },
9202 {
9203 Mips_XORi_MM, MIPS_INS_XORI,
9204 #ifndef CAPSTONE_DIET
9205 { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
9206 #endif
9207 },
9208 {
9209 Mips_XorRxRxRy16, MIPS_INS_XOR,
9210 #ifndef CAPSTONE_DIET
9211 { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
9212 #endif
9213 },
9214 };
9215
9216 // given internal insn id, return public instruction info
Mips_get_insn_id(cs_struct * h,cs_insn * insn,unsigned int id)9217 void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
9218 {
9219 unsigned int i;
9220
9221 i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
9222 if (i != 0) {
9223 insn->id = insns[i].mapid;
9224
9225 if (h->detail) {
9226 #ifndef CAPSTONE_DIET
9227 memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
9228 insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);
9229
9230 memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
9231 insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod);
9232
9233 memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups));
9234 insn->detail->groups_count = (uint8_t)count_positive(insns[i].groups);
9235
9236 if (insns[i].branch || insns[i].indirect_branch) {
9237 // this insn also belongs to JUMP group. add JUMP group
9238 insn->detail->groups[insn->detail->groups_count] = MIPS_GRP_JUMP;
9239 insn->detail->groups_count++;
9240 }
9241 #endif
9242 }
9243 }
9244 }
9245
9246 static const name_map insn_name_maps[] = {
9247 { MIPS_INS_INVALID, NULL },
9248
9249 { MIPS_INS_ABSQ_S, "absq_s" },
9250 { MIPS_INS_ADD, "add" },
9251 { MIPS_INS_ADDIUPC, "addiupc" },
9252 { MIPS_INS_ADDQH, "addqh" },
9253 { MIPS_INS_ADDQH_R, "addqh_r" },
9254 { MIPS_INS_ADDQ, "addq" },
9255 { MIPS_INS_ADDQ_S, "addq_s" },
9256 { MIPS_INS_ADDSC, "addsc" },
9257 { MIPS_INS_ADDS_A, "adds_a" },
9258 { MIPS_INS_ADDS_S, "adds_s" },
9259 { MIPS_INS_ADDS_U, "adds_u" },
9260 { MIPS_INS_ADDUH, "adduh" },
9261 { MIPS_INS_ADDUH_R, "adduh_r" },
9262 { MIPS_INS_ADDU, "addu" },
9263 { MIPS_INS_ADDU_S, "addu_s" },
9264 { MIPS_INS_ADDVI, "addvi" },
9265 { MIPS_INS_ADDV, "addv" },
9266 { MIPS_INS_ADDWC, "addwc" },
9267 { MIPS_INS_ADD_A, "add_a" },
9268 { MIPS_INS_ADDI, "addi" },
9269 { MIPS_INS_ADDIU, "addiu" },
9270 { MIPS_INS_ALIGN, "align" },
9271 { MIPS_INS_ALUIPC, "aluipc" },
9272 { MIPS_INS_AND, "and" },
9273 { MIPS_INS_ANDI, "andi" },
9274 { MIPS_INS_APPEND, "append" },
9275 { MIPS_INS_ASUB_S, "asub_s" },
9276 { MIPS_INS_ASUB_U, "asub_u" },
9277 { MIPS_INS_AUI, "aui" },
9278 { MIPS_INS_AUIPC, "auipc" },
9279 { MIPS_INS_AVER_S, "aver_s" },
9280 { MIPS_INS_AVER_U, "aver_u" },
9281 { MIPS_INS_AVE_S, "ave_s" },
9282 { MIPS_INS_AVE_U, "ave_u" },
9283 { MIPS_INS_BADDU, "baddu" },
9284 { MIPS_INS_BAL, "bal" },
9285 { MIPS_INS_BALC, "balc" },
9286 { MIPS_INS_BALIGN, "balign" },
9287 { MIPS_INS_BC, "bc" },
9288 { MIPS_INS_BC0F, "bc0f" },
9289 { MIPS_INS_BC0FL, "bc0fl" },
9290 { MIPS_INS_BC0T, "bc0t" },
9291 { MIPS_INS_BC0TL, "bc0tl" },
9292 { MIPS_INS_BC1EQZ, "bc1eqz" },
9293 { MIPS_INS_BC1F, "bc1f" },
9294 { MIPS_INS_BC1FL, "bc1fl" },
9295 { MIPS_INS_BC1NEZ, "bc1nez" },
9296 { MIPS_INS_BC1T, "bc1t" },
9297 { MIPS_INS_BC1TL, "bc1tl" },
9298 { MIPS_INS_BC2EQZ, "bc2eqz" },
9299 { MIPS_INS_BC2F, "bc2f" },
9300 { MIPS_INS_BC2FL, "bc2fl" },
9301 { MIPS_INS_BC2NEZ, "bc2nez" },
9302 { MIPS_INS_BC2T, "bc2t" },
9303 { MIPS_INS_BC2TL, "bc2tl" },
9304 { MIPS_INS_BC3F, "bc3f" },
9305 { MIPS_INS_BC3FL, "bc3fl" },
9306 { MIPS_INS_BC3T, "bc3t" },
9307 { MIPS_INS_BC3TL, "bc3tl" },
9308 { MIPS_INS_BCLRI, "bclri" },
9309 { MIPS_INS_BCLR, "bclr" },
9310 { MIPS_INS_BEQ, "beq" },
9311 { MIPS_INS_BEQC, "beqc" },
9312 { MIPS_INS_BEQL, "beql" },
9313 { MIPS_INS_BEQZALC, "beqzalc" },
9314 { MIPS_INS_BEQZC, "beqzc" },
9315 { MIPS_INS_BGEC, "bgec" },
9316 { MIPS_INS_BGEUC, "bgeuc" },
9317 { MIPS_INS_BGEZ, "bgez" },
9318 { MIPS_INS_BGEZAL, "bgezal" },
9319 { MIPS_INS_BGEZALC, "bgezalc" },
9320 { MIPS_INS_BGEZALL, "bgezall" },
9321 { MIPS_INS_BGEZALS, "bgezals" },
9322 { MIPS_INS_BGEZC, "bgezc" },
9323 { MIPS_INS_BGEZL, "bgezl" },
9324 { MIPS_INS_BGTZ, "bgtz" },
9325 { MIPS_INS_BGTZALC, "bgtzalc" },
9326 { MIPS_INS_BGTZC, "bgtzc" },
9327 { MIPS_INS_BGTZL, "bgtzl" },
9328 { MIPS_INS_BINSLI, "binsli" },
9329 { MIPS_INS_BINSL, "binsl" },
9330 { MIPS_INS_BINSRI, "binsri" },
9331 { MIPS_INS_BINSR, "binsr" },
9332 { MIPS_INS_BITREV, "bitrev" },
9333 { MIPS_INS_BITSWAP, "bitswap" },
9334 { MIPS_INS_BLEZ, "blez" },
9335 { MIPS_INS_BLEZALC, "blezalc" },
9336 { MIPS_INS_BLEZC, "blezc" },
9337 { MIPS_INS_BLEZL, "blezl" },
9338 { MIPS_INS_BLTC, "bltc" },
9339 { MIPS_INS_BLTUC, "bltuc" },
9340 { MIPS_INS_BLTZ, "bltz" },
9341 { MIPS_INS_BLTZAL, "bltzal" },
9342 { MIPS_INS_BLTZALC, "bltzalc" },
9343 { MIPS_INS_BLTZALL, "bltzall" },
9344 { MIPS_INS_BLTZALS, "bltzals" },
9345 { MIPS_INS_BLTZC, "bltzc" },
9346 { MIPS_INS_BLTZL, "bltzl" },
9347 { MIPS_INS_BMNZI, "bmnzi" },
9348 { MIPS_INS_BMNZ, "bmnz" },
9349 { MIPS_INS_BMZI, "bmzi" },
9350 { MIPS_INS_BMZ, "bmz" },
9351 { MIPS_INS_BNE, "bne" },
9352 { MIPS_INS_BNEC, "bnec" },
9353 { MIPS_INS_BNEGI, "bnegi" },
9354 { MIPS_INS_BNEG, "bneg" },
9355 { MIPS_INS_BNEL, "bnel" },
9356 { MIPS_INS_BNEZALC, "bnezalc" },
9357 { MIPS_INS_BNEZC, "bnezc" },
9358 { MIPS_INS_BNVC, "bnvc" },
9359 { MIPS_INS_BNZ, "bnz" },
9360 { MIPS_INS_BOVC, "bovc" },
9361 { MIPS_INS_BPOSGE32, "bposge32" },
9362 { MIPS_INS_BREAK, "break" },
9363 { MIPS_INS_BSELI, "bseli" },
9364 { MIPS_INS_BSEL, "bsel" },
9365 { MIPS_INS_BSETI, "bseti" },
9366 { MIPS_INS_BSET, "bset" },
9367 { MIPS_INS_BZ, "bz" },
9368 { MIPS_INS_BEQZ, "beqz" },
9369 { MIPS_INS_B, "b" },
9370 { MIPS_INS_BNEZ, "bnez" },
9371 { MIPS_INS_BTEQZ, "bteqz" },
9372 { MIPS_INS_BTNEZ, "btnez" },
9373 { MIPS_INS_CACHE, "cache" },
9374 { MIPS_INS_CEIL, "ceil" },
9375 { MIPS_INS_CEQI, "ceqi" },
9376 { MIPS_INS_CEQ, "ceq" },
9377 { MIPS_INS_CFC1, "cfc1" },
9378 { MIPS_INS_CFCMSA, "cfcmsa" },
9379 { MIPS_INS_CINS, "cins" },
9380 { MIPS_INS_CINS32, "cins32" },
9381 { MIPS_INS_CLASS, "class" },
9382 { MIPS_INS_CLEI_S, "clei_s" },
9383 { MIPS_INS_CLEI_U, "clei_u" },
9384 { MIPS_INS_CLE_S, "cle_s" },
9385 { MIPS_INS_CLE_U, "cle_u" },
9386 { MIPS_INS_CLO, "clo" },
9387 { MIPS_INS_CLTI_S, "clti_s" },
9388 { MIPS_INS_CLTI_U, "clti_u" },
9389 { MIPS_INS_CLT_S, "clt_s" },
9390 { MIPS_INS_CLT_U, "clt_u" },
9391 { MIPS_INS_CLZ, "clz" },
9392 { MIPS_INS_CMPGDU, "cmpgdu" },
9393 { MIPS_INS_CMPGU, "cmpgu" },
9394 { MIPS_INS_CMPU, "cmpu" },
9395 { MIPS_INS_CMP, "cmp" },
9396 { MIPS_INS_COPY_S, "copy_s" },
9397 { MIPS_INS_COPY_U, "copy_u" },
9398 { MIPS_INS_CTC1, "ctc1" },
9399 { MIPS_INS_CTCMSA, "ctcmsa" },
9400 { MIPS_INS_CVT, "cvt" },
9401 { MIPS_INS_C, "c" },
9402 { MIPS_INS_CMPI, "cmpi" },
9403 { MIPS_INS_DADD, "dadd" },
9404 { MIPS_INS_DADDI, "daddi" },
9405 { MIPS_INS_DADDIU, "daddiu" },
9406 { MIPS_INS_DADDU, "daddu" },
9407 { MIPS_INS_DAHI, "dahi" },
9408 { MIPS_INS_DALIGN, "dalign" },
9409 { MIPS_INS_DATI, "dati" },
9410 { MIPS_INS_DAUI, "daui" },
9411 { MIPS_INS_DBITSWAP, "dbitswap" },
9412 { MIPS_INS_DCLO, "dclo" },
9413 { MIPS_INS_DCLZ, "dclz" },
9414 { MIPS_INS_DDIV, "ddiv" },
9415 { MIPS_INS_DDIVU, "ddivu" },
9416 { MIPS_INS_DERET, "deret" },
9417 { MIPS_INS_DEXT, "dext" },
9418 { MIPS_INS_DEXTM, "dextm" },
9419 { MIPS_INS_DEXTU, "dextu" },
9420 { MIPS_INS_DI, "di" },
9421 { MIPS_INS_DINS, "dins" },
9422 { MIPS_INS_DINSM, "dinsm" },
9423 { MIPS_INS_DINSU, "dinsu" },
9424 { MIPS_INS_DIV, "div" },
9425 { MIPS_INS_DIVU, "divu" },
9426 { MIPS_INS_DIV_S, "div_s" },
9427 { MIPS_INS_DIV_U, "div_u" },
9428 { MIPS_INS_DLSA, "dlsa" },
9429 { MIPS_INS_DMFC0, "dmfc0" },
9430 { MIPS_INS_DMFC1, "dmfc1" },
9431 { MIPS_INS_DMFC2, "dmfc2" },
9432 { MIPS_INS_DMOD, "dmod" },
9433 { MIPS_INS_DMODU, "dmodu" },
9434 { MIPS_INS_DMTC0, "dmtc0" },
9435 { MIPS_INS_DMTC1, "dmtc1" },
9436 { MIPS_INS_DMTC2, "dmtc2" },
9437 { MIPS_INS_DMUH, "dmuh" },
9438 { MIPS_INS_DMUHU, "dmuhu" },
9439 { MIPS_INS_DMUL, "dmul" },
9440 { MIPS_INS_DMULT, "dmult" },
9441 { MIPS_INS_DMULTU, "dmultu" },
9442 { MIPS_INS_DMULU, "dmulu" },
9443 { MIPS_INS_DOTP_S, "dotp_s" },
9444 { MIPS_INS_DOTP_U, "dotp_u" },
9445 { MIPS_INS_DPADD_S, "dpadd_s" },
9446 { MIPS_INS_DPADD_U, "dpadd_u" },
9447 { MIPS_INS_DPAQX_SA, "dpaqx_sa" },
9448 { MIPS_INS_DPAQX_S, "dpaqx_s" },
9449 { MIPS_INS_DPAQ_SA, "dpaq_sa" },
9450 { MIPS_INS_DPAQ_S, "dpaq_s" },
9451 { MIPS_INS_DPAU, "dpau" },
9452 { MIPS_INS_DPAX, "dpax" },
9453 { MIPS_INS_DPA, "dpa" },
9454 { MIPS_INS_DPOP, "dpop" },
9455 { MIPS_INS_DPSQX_SA, "dpsqx_sa" },
9456 { MIPS_INS_DPSQX_S, "dpsqx_s" },
9457 { MIPS_INS_DPSQ_SA, "dpsq_sa" },
9458 { MIPS_INS_DPSQ_S, "dpsq_s" },
9459 { MIPS_INS_DPSUB_S, "dpsub_s" },
9460 { MIPS_INS_DPSUB_U, "dpsub_u" },
9461 { MIPS_INS_DPSU, "dpsu" },
9462 { MIPS_INS_DPSX, "dpsx" },
9463 { MIPS_INS_DPS, "dps" },
9464 { MIPS_INS_DROTR, "drotr" },
9465 { MIPS_INS_DROTR32, "drotr32" },
9466 { MIPS_INS_DROTRV, "drotrv" },
9467 { MIPS_INS_DSBH, "dsbh" },
9468 { MIPS_INS_DSHD, "dshd" },
9469 { MIPS_INS_DSLL, "dsll" },
9470 { MIPS_INS_DSLL32, "dsll32" },
9471 { MIPS_INS_DSLLV, "dsllv" },
9472 { MIPS_INS_DSRA, "dsra" },
9473 { MIPS_INS_DSRA32, "dsra32" },
9474 { MIPS_INS_DSRAV, "dsrav" },
9475 { MIPS_INS_DSRL, "dsrl" },
9476 { MIPS_INS_DSRL32, "dsrl32" },
9477 { MIPS_INS_DSRLV, "dsrlv" },
9478 { MIPS_INS_DSUB, "dsub" },
9479 { MIPS_INS_DSUBU, "dsubu" },
9480 { MIPS_INS_EHB, "ehb" },
9481 { MIPS_INS_EI, "ei" },
9482 { MIPS_INS_ERET, "eret" },
9483 { MIPS_INS_EXT, "ext" },
9484 { MIPS_INS_EXTP, "extp" },
9485 { MIPS_INS_EXTPDP, "extpdp" },
9486 { MIPS_INS_EXTPDPV, "extpdpv" },
9487 { MIPS_INS_EXTPV, "extpv" },
9488 { MIPS_INS_EXTRV_RS, "extrv_rs" },
9489 { MIPS_INS_EXTRV_R, "extrv_r" },
9490 { MIPS_INS_EXTRV_S, "extrv_s" },
9491 { MIPS_INS_EXTRV, "extrv" },
9492 { MIPS_INS_EXTR_RS, "extr_rs" },
9493 { MIPS_INS_EXTR_R, "extr_r" },
9494 { MIPS_INS_EXTR_S, "extr_s" },
9495 { MIPS_INS_EXTR, "extr" },
9496 { MIPS_INS_EXTS, "exts" },
9497 { MIPS_INS_EXTS32, "exts32" },
9498 { MIPS_INS_ABS, "abs" },
9499 { MIPS_INS_FADD, "fadd" },
9500 { MIPS_INS_FCAF, "fcaf" },
9501 { MIPS_INS_FCEQ, "fceq" },
9502 { MIPS_INS_FCLASS, "fclass" },
9503 { MIPS_INS_FCLE, "fcle" },
9504 { MIPS_INS_FCLT, "fclt" },
9505 { MIPS_INS_FCNE, "fcne" },
9506 { MIPS_INS_FCOR, "fcor" },
9507 { MIPS_INS_FCUEQ, "fcueq" },
9508 { MIPS_INS_FCULE, "fcule" },
9509 { MIPS_INS_FCULT, "fcult" },
9510 { MIPS_INS_FCUNE, "fcune" },
9511 { MIPS_INS_FCUN, "fcun" },
9512 { MIPS_INS_FDIV, "fdiv" },
9513 { MIPS_INS_FEXDO, "fexdo" },
9514 { MIPS_INS_FEXP2, "fexp2" },
9515 { MIPS_INS_FEXUPL, "fexupl" },
9516 { MIPS_INS_FEXUPR, "fexupr" },
9517 { MIPS_INS_FFINT_S, "ffint_s" },
9518 { MIPS_INS_FFINT_U, "ffint_u" },
9519 { MIPS_INS_FFQL, "ffql" },
9520 { MIPS_INS_FFQR, "ffqr" },
9521 { MIPS_INS_FILL, "fill" },
9522 { MIPS_INS_FLOG2, "flog2" },
9523 { MIPS_INS_FLOOR, "floor" },
9524 { MIPS_INS_FMADD, "fmadd" },
9525 { MIPS_INS_FMAX_A, "fmax_a" },
9526 { MIPS_INS_FMAX, "fmax" },
9527 { MIPS_INS_FMIN_A, "fmin_a" },
9528 { MIPS_INS_FMIN, "fmin" },
9529 { MIPS_INS_MOV, "mov" },
9530 { MIPS_INS_FMSUB, "fmsub" },
9531 { MIPS_INS_FMUL, "fmul" },
9532 { MIPS_INS_MUL, "mul" },
9533 { MIPS_INS_NEG, "neg" },
9534 { MIPS_INS_FRCP, "frcp" },
9535 { MIPS_INS_FRINT, "frint" },
9536 { MIPS_INS_FRSQRT, "frsqrt" },
9537 { MIPS_INS_FSAF, "fsaf" },
9538 { MIPS_INS_FSEQ, "fseq" },
9539 { MIPS_INS_FSLE, "fsle" },
9540 { MIPS_INS_FSLT, "fslt" },
9541 { MIPS_INS_FSNE, "fsne" },
9542 { MIPS_INS_FSOR, "fsor" },
9543 { MIPS_INS_FSQRT, "fsqrt" },
9544 { MIPS_INS_SQRT, "sqrt" },
9545 { MIPS_INS_FSUB, "fsub" },
9546 { MIPS_INS_SUB, "sub" },
9547 { MIPS_INS_FSUEQ, "fsueq" },
9548 { MIPS_INS_FSULE, "fsule" },
9549 { MIPS_INS_FSULT, "fsult" },
9550 { MIPS_INS_FSUNE, "fsune" },
9551 { MIPS_INS_FSUN, "fsun" },
9552 { MIPS_INS_FTINT_S, "ftint_s" },
9553 { MIPS_INS_FTINT_U, "ftint_u" },
9554 { MIPS_INS_FTQ, "ftq" },
9555 { MIPS_INS_FTRUNC_S, "ftrunc_s" },
9556 { MIPS_INS_FTRUNC_U, "ftrunc_u" },
9557 { MIPS_INS_HADD_S, "hadd_s" },
9558 { MIPS_INS_HADD_U, "hadd_u" },
9559 { MIPS_INS_HSUB_S, "hsub_s" },
9560 { MIPS_INS_HSUB_U, "hsub_u" },
9561 { MIPS_INS_ILVEV, "ilvev" },
9562 { MIPS_INS_ILVL, "ilvl" },
9563 { MIPS_INS_ILVOD, "ilvod" },
9564 { MIPS_INS_ILVR, "ilvr" },
9565 { MIPS_INS_INS, "ins" },
9566 { MIPS_INS_INSERT, "insert" },
9567 { MIPS_INS_INSV, "insv" },
9568 { MIPS_INS_INSVE, "insve" },
9569 { MIPS_INS_J, "j" },
9570 { MIPS_INS_JAL, "jal" },
9571 { MIPS_INS_JALR, "jalr" },
9572 { MIPS_INS_JALRS, "jalrs" },
9573 { MIPS_INS_JALS, "jals" },
9574 { MIPS_INS_JALX, "jalx" },
9575 { MIPS_INS_JIALC, "jialc" },
9576 { MIPS_INS_JIC, "jic" },
9577 { MIPS_INS_JR, "jr" },
9578 { MIPS_INS_JRADDIUSP, "jraddiusp" },
9579 { MIPS_INS_JRC, "jrc" },
9580 { MIPS_INS_JALRC, "jalrc" },
9581 { MIPS_INS_LB, "lb" },
9582 { MIPS_INS_LBUX, "lbux" },
9583 { MIPS_INS_LBU, "lbu" },
9584 { MIPS_INS_LD, "ld" },
9585 { MIPS_INS_LDC1, "ldc1" },
9586 { MIPS_INS_LDC2, "ldc2" },
9587 { MIPS_INS_LDC3, "ldc3" },
9588 { MIPS_INS_LDI, "ldi" },
9589 { MIPS_INS_LDL, "ldl" },
9590 { MIPS_INS_LDPC, "ldpc" },
9591 { MIPS_INS_LDR, "ldr" },
9592 { MIPS_INS_LDXC1, "ldxc1" },
9593 { MIPS_INS_LH, "lh" },
9594 { MIPS_INS_LHX, "lhx" },
9595 { MIPS_INS_LHU, "lhu" },
9596 { MIPS_INS_LL, "ll" },
9597 { MIPS_INS_LLD, "lld" },
9598 { MIPS_INS_LSA, "lsa" },
9599 { MIPS_INS_LUXC1, "luxc1" },
9600 { MIPS_INS_LUI, "lui" },
9601 { MIPS_INS_LW, "lw" },
9602 { MIPS_INS_LWC1, "lwc1" },
9603 { MIPS_INS_LWC2, "lwc2" },
9604 { MIPS_INS_LWC3, "lwc3" },
9605 { MIPS_INS_LWL, "lwl" },
9606 { MIPS_INS_LWPC, "lwpc" },
9607 { MIPS_INS_LWR, "lwr" },
9608 { MIPS_INS_LWUPC, "lwupc" },
9609 { MIPS_INS_LWU, "lwu" },
9610 { MIPS_INS_LWX, "lwx" },
9611 { MIPS_INS_LWXC1, "lwxc1" },
9612 { MIPS_INS_LI, "li" },
9613 { MIPS_INS_MADD, "madd" },
9614 { MIPS_INS_MADDF, "maddf" },
9615 { MIPS_INS_MADDR_Q, "maddr_q" },
9616 { MIPS_INS_MADDU, "maddu" },
9617 { MIPS_INS_MADDV, "maddv" },
9618 { MIPS_INS_MADD_Q, "madd_q" },
9619 { MIPS_INS_MAQ_SA, "maq_sa" },
9620 { MIPS_INS_MAQ_S, "maq_s" },
9621 { MIPS_INS_MAXA, "maxa" },
9622 { MIPS_INS_MAXI_S, "maxi_s" },
9623 { MIPS_INS_MAXI_U, "maxi_u" },
9624 { MIPS_INS_MAX_A, "max_a" },
9625 { MIPS_INS_MAX, "max" },
9626 { MIPS_INS_MAX_S, "max_s" },
9627 { MIPS_INS_MAX_U, "max_u" },
9628 { MIPS_INS_MFC0, "mfc0" },
9629 { MIPS_INS_MFC1, "mfc1" },
9630 { MIPS_INS_MFC2, "mfc2" },
9631 { MIPS_INS_MFHC1, "mfhc1" },
9632 { MIPS_INS_MFHI, "mfhi" },
9633 { MIPS_INS_MFLO, "mflo" },
9634 { MIPS_INS_MINA, "mina" },
9635 { MIPS_INS_MINI_S, "mini_s" },
9636 { MIPS_INS_MINI_U, "mini_u" },
9637 { MIPS_INS_MIN_A, "min_a" },
9638 { MIPS_INS_MIN, "min" },
9639 { MIPS_INS_MIN_S, "min_s" },
9640 { MIPS_INS_MIN_U, "min_u" },
9641 { MIPS_INS_MOD, "mod" },
9642 { MIPS_INS_MODSUB, "modsub" },
9643 { MIPS_INS_MODU, "modu" },
9644 { MIPS_INS_MOD_S, "mod_s" },
9645 { MIPS_INS_MOD_U, "mod_u" },
9646 { MIPS_INS_MOVE, "move" },
9647 { MIPS_INS_MOVF, "movf" },
9648 { MIPS_INS_MOVN, "movn" },
9649 { MIPS_INS_MOVT, "movt" },
9650 { MIPS_INS_MOVZ, "movz" },
9651 { MIPS_INS_MSUB, "msub" },
9652 { MIPS_INS_MSUBF, "msubf" },
9653 { MIPS_INS_MSUBR_Q, "msubr_q" },
9654 { MIPS_INS_MSUBU, "msubu" },
9655 { MIPS_INS_MSUBV, "msubv" },
9656 { MIPS_INS_MSUB_Q, "msub_q" },
9657 { MIPS_INS_MTC0, "mtc0" },
9658 { MIPS_INS_MTC1, "mtc1" },
9659 { MIPS_INS_MTC2, "mtc2" },
9660 { MIPS_INS_MTHC1, "mthc1" },
9661 { MIPS_INS_MTHI, "mthi" },
9662 { MIPS_INS_MTHLIP, "mthlip" },
9663 { MIPS_INS_MTLO, "mtlo" },
9664 { MIPS_INS_MTM0, "mtm0" },
9665 { MIPS_INS_MTM1, "mtm1" },
9666 { MIPS_INS_MTM2, "mtm2" },
9667 { MIPS_INS_MTP0, "mtp0" },
9668 { MIPS_INS_MTP1, "mtp1" },
9669 { MIPS_INS_MTP2, "mtp2" },
9670 { MIPS_INS_MUH, "muh" },
9671 { MIPS_INS_MUHU, "muhu" },
9672 { MIPS_INS_MULEQ_S, "muleq_s" },
9673 { MIPS_INS_MULEU_S, "muleu_s" },
9674 { MIPS_INS_MULQ_RS, "mulq_rs" },
9675 { MIPS_INS_MULQ_S, "mulq_s" },
9676 { MIPS_INS_MULR_Q, "mulr_q" },
9677 { MIPS_INS_MULSAQ_S, "mulsaq_s" },
9678 { MIPS_INS_MULSA, "mulsa" },
9679 { MIPS_INS_MULT, "mult" },
9680 { MIPS_INS_MULTU, "multu" },
9681 { MIPS_INS_MULU, "mulu" },
9682 { MIPS_INS_MULV, "mulv" },
9683 { MIPS_INS_MUL_Q, "mul_q" },
9684 { MIPS_INS_MUL_S, "mul_s" },
9685 { MIPS_INS_NLOC, "nloc" },
9686 { MIPS_INS_NLZC, "nlzc" },
9687 { MIPS_INS_NMADD, "nmadd" },
9688 { MIPS_INS_NMSUB, "nmsub" },
9689 { MIPS_INS_NOR, "nor" },
9690 { MIPS_INS_NORI, "nori" },
9691 { MIPS_INS_NOT, "not" },
9692 { MIPS_INS_OR, "or" },
9693 { MIPS_INS_ORI, "ori" },
9694 { MIPS_INS_PACKRL, "packrl" },
9695 { MIPS_INS_PAUSE, "pause" },
9696 { MIPS_INS_PCKEV, "pckev" },
9697 { MIPS_INS_PCKOD, "pckod" },
9698 { MIPS_INS_PCNT, "pcnt" },
9699 { MIPS_INS_PICK, "pick" },
9700 { MIPS_INS_POP, "pop" },
9701 { MIPS_INS_PRECEQU, "precequ" },
9702 { MIPS_INS_PRECEQ, "preceq" },
9703 { MIPS_INS_PRECEU, "preceu" },
9704 { MIPS_INS_PRECRQU_S, "precrqu_s" },
9705 { MIPS_INS_PRECRQ, "precrq" },
9706 { MIPS_INS_PRECRQ_RS, "precrq_rs" },
9707 { MIPS_INS_PRECR, "precr" },
9708 { MIPS_INS_PRECR_SRA, "precr_sra" },
9709 { MIPS_INS_PRECR_SRA_R, "precr_sra_r" },
9710 { MIPS_INS_PREF, "pref" },
9711 { MIPS_INS_PREPEND, "prepend" },
9712 { MIPS_INS_RADDU, "raddu" },
9713 { MIPS_INS_RDDSP, "rddsp" },
9714 { MIPS_INS_RDHWR, "rdhwr" },
9715 { MIPS_INS_REPLV, "replv" },
9716 { MIPS_INS_REPL, "repl" },
9717 { MIPS_INS_RINT, "rint" },
9718 { MIPS_INS_ROTR, "rotr" },
9719 { MIPS_INS_ROTRV, "rotrv" },
9720 { MIPS_INS_ROUND, "round" },
9721 { MIPS_INS_SAT_S, "sat_s" },
9722 { MIPS_INS_SAT_U, "sat_u" },
9723 { MIPS_INS_SB, "sb" },
9724 { MIPS_INS_SC, "sc" },
9725 { MIPS_INS_SCD, "scd" },
9726 { MIPS_INS_SD, "sd" },
9727 { MIPS_INS_SDBBP, "sdbbp" },
9728 { MIPS_INS_SDC1, "sdc1" },
9729 { MIPS_INS_SDC2, "sdc2" },
9730 { MIPS_INS_SDC3, "sdc3" },
9731 { MIPS_INS_SDL, "sdl" },
9732 { MIPS_INS_SDR, "sdr" },
9733 { MIPS_INS_SDXC1, "sdxc1" },
9734 { MIPS_INS_SEB, "seb" },
9735 { MIPS_INS_SEH, "seh" },
9736 { MIPS_INS_SELEQZ, "seleqz" },
9737 { MIPS_INS_SELNEZ, "selnez" },
9738 { MIPS_INS_SEL, "sel" },
9739 { MIPS_INS_SEQ, "seq" },
9740 { MIPS_INS_SEQI, "seqi" },
9741 { MIPS_INS_SH, "sh" },
9742 { MIPS_INS_SHF, "shf" },
9743 { MIPS_INS_SHILO, "shilo" },
9744 { MIPS_INS_SHILOV, "shilov" },
9745 { MIPS_INS_SHLLV, "shllv" },
9746 { MIPS_INS_SHLLV_S, "shllv_s" },
9747 { MIPS_INS_SHLL, "shll" },
9748 { MIPS_INS_SHLL_S, "shll_s" },
9749 { MIPS_INS_SHRAV, "shrav" },
9750 { MIPS_INS_SHRAV_R, "shrav_r" },
9751 { MIPS_INS_SHRA, "shra" },
9752 { MIPS_INS_SHRA_R, "shra_r" },
9753 { MIPS_INS_SHRLV, "shrlv" },
9754 { MIPS_INS_SHRL, "shrl" },
9755 { MIPS_INS_SLDI, "sldi" },
9756 { MIPS_INS_SLD, "sld" },
9757 { MIPS_INS_SLL, "sll" },
9758 { MIPS_INS_SLLI, "slli" },
9759 { MIPS_INS_SLLV, "sllv" },
9760 { MIPS_INS_SLT, "slt" },
9761 { MIPS_INS_SLTI, "slti" },
9762 { MIPS_INS_SLTIU, "sltiu" },
9763 { MIPS_INS_SLTU, "sltu" },
9764 { MIPS_INS_SNE, "sne" },
9765 { MIPS_INS_SNEI, "snei" },
9766 { MIPS_INS_SPLATI, "splati" },
9767 { MIPS_INS_SPLAT, "splat" },
9768 { MIPS_INS_SRA, "sra" },
9769 { MIPS_INS_SRAI, "srai" },
9770 { MIPS_INS_SRARI, "srari" },
9771 { MIPS_INS_SRAR, "srar" },
9772 { MIPS_INS_SRAV, "srav" },
9773 { MIPS_INS_SRL, "srl" },
9774 { MIPS_INS_SRLI, "srli" },
9775 { MIPS_INS_SRLRI, "srlri" },
9776 { MIPS_INS_SRLR, "srlr" },
9777 { MIPS_INS_SRLV, "srlv" },
9778 { MIPS_INS_SSNOP, "ssnop" },
9779 { MIPS_INS_ST, "st" },
9780 { MIPS_INS_SUBQH, "subqh" },
9781 { MIPS_INS_SUBQH_R, "subqh_r" },
9782 { MIPS_INS_SUBQ, "subq" },
9783 { MIPS_INS_SUBQ_S, "subq_s" },
9784 { MIPS_INS_SUBSUS_U, "subsus_u" },
9785 { MIPS_INS_SUBSUU_S, "subsuu_s" },
9786 { MIPS_INS_SUBS_S, "subs_s" },
9787 { MIPS_INS_SUBS_U, "subs_u" },
9788 { MIPS_INS_SUBUH, "subuh" },
9789 { MIPS_INS_SUBUH_R, "subuh_r" },
9790 { MIPS_INS_SUBU, "subu" },
9791 { MIPS_INS_SUBU_S, "subu_s" },
9792 { MIPS_INS_SUBVI, "subvi" },
9793 { MIPS_INS_SUBV, "subv" },
9794 { MIPS_INS_SUXC1, "suxc1" },
9795 { MIPS_INS_SW, "sw" },
9796 { MIPS_INS_SWC1, "swc1" },
9797 { MIPS_INS_SWC2, "swc2" },
9798 { MIPS_INS_SWC3, "swc3" },
9799 { MIPS_INS_SWL, "swl" },
9800 { MIPS_INS_SWR, "swr" },
9801 { MIPS_INS_SWXC1, "swxc1" },
9802 { MIPS_INS_SYNC, "sync" },
9803 { MIPS_INS_SYSCALL, "syscall" },
9804 { MIPS_INS_TEQ, "teq" },
9805 { MIPS_INS_TEQI, "teqi" },
9806 { MIPS_INS_TGE, "tge" },
9807 { MIPS_INS_TGEI, "tgei" },
9808 { MIPS_INS_TGEIU, "tgeiu" },
9809 { MIPS_INS_TGEU, "tgeu" },
9810 { MIPS_INS_TLBP, "tlbp" },
9811 { MIPS_INS_TLBR, "tlbr" },
9812 { MIPS_INS_TLBWI, "tlbwi" },
9813 { MIPS_INS_TLBWR, "tlbwr" },
9814 { MIPS_INS_TLT, "tlt" },
9815 { MIPS_INS_TLTI, "tlti" },
9816 { MIPS_INS_TLTIU, "tltiu" },
9817 { MIPS_INS_TLTU, "tltu" },
9818 { MIPS_INS_TNE, "tne" },
9819 { MIPS_INS_TNEI, "tnei" },
9820 { MIPS_INS_TRUNC, "trunc" },
9821 { MIPS_INS_V3MULU, "v3mulu" },
9822 { MIPS_INS_VMM0, "vmm0" },
9823 { MIPS_INS_VMULU, "vmulu" },
9824 { MIPS_INS_VSHF, "vshf" },
9825 { MIPS_INS_WAIT, "wait" },
9826 { MIPS_INS_WRDSP, "wrdsp" },
9827 { MIPS_INS_WSBH, "wsbh" },
9828 { MIPS_INS_XOR, "xor" },
9829 { MIPS_INS_XORI, "xori" },
9830
9831 // alias instructions
9832 { MIPS_INS_NOP, "nop" },
9833 { MIPS_INS_NEGU, "negu" },
9834
9835 { MIPS_INS_JALR_HB, "jalr.hb" },
9836 { MIPS_INS_JR_HB, "jr.hb" },
9837 };
9838
Mips_insn_name(csh handle,unsigned int id)9839 const char *Mips_insn_name(csh handle, unsigned int id)
9840 {
9841 #ifndef CAPSTONE_DIET
9842 if (id >= MIPS_INS_ENDING)
9843 return NULL;
9844
9845 return insn_name_maps[id].name;
9846 #else
9847 return NULL;
9848 #endif
9849 }
9850
9851 #ifndef CAPSTONE_DIET
9852 static const name_map group_name_maps[] = {
9853 // generic groups
9854 { MIPS_GRP_INVALID, NULL },
9855 { MIPS_GRP_JUMP, "jump" },
9856
9857 // architecture-specific groups
9858 { MIPS_GRP_BITCOUNT, "bitcount" },
9859 { MIPS_GRP_DSP, "dsp" },
9860 { MIPS_GRP_DSPR2, "dspr2" },
9861 { MIPS_GRP_FPIDX, "fpidx" },
9862 { MIPS_GRP_MSA, "msa" },
9863 { MIPS_GRP_MIPS32R2, "mips32r2" },
9864 { MIPS_GRP_MIPS64, "mips64" },
9865 { MIPS_GRP_MIPS64R2, "mips64r2" },
9866 { MIPS_GRP_SEINREG, "seinreg" },
9867 { MIPS_GRP_STDENC, "stdenc" },
9868 { MIPS_GRP_SWAP, "swap" },
9869 { MIPS_GRP_MICROMIPS, "micromips" },
9870 { MIPS_GRP_MIPS16MODE, "mips16mode" },
9871 { MIPS_GRP_FP64BIT, "fp64bit" },
9872 { MIPS_GRP_NONANSFPMATH, "nonansfpmath" },
9873 { MIPS_GRP_NOTFP64BIT, "notfp64bit" },
9874 { MIPS_GRP_NOTINMICROMIPS, "notinmicromips" },
9875 { MIPS_GRP_NOTNACL, "notnacl" },
9876
9877 { MIPS_GRP_NOTMIPS32R6, "notmips32r6" },
9878 { MIPS_GRP_NOTMIPS64R6, "notmips64r6" },
9879 { MIPS_GRP_CNMIPS, "cnmips" },
9880
9881 { MIPS_GRP_MIPS32, "mips32" },
9882 { MIPS_GRP_MIPS32R6, "mips32r6" },
9883 { MIPS_GRP_MIPS64R6, "mips64r6" },
9884
9885 { MIPS_GRP_MIPS2, "mips2" },
9886 { MIPS_GRP_MIPS3, "mips3" },
9887 { MIPS_GRP_MIPS3_32, "mips3_32"},
9888 { MIPS_GRP_MIPS3_32R2, "mips3_32r2" },
9889
9890 { MIPS_GRP_MIPS4_32, "mips4_32" },
9891 { MIPS_GRP_MIPS4_32R2, "mips4_32r2" },
9892 { MIPS_GRP_MIPS5_32R2, "mips5_32r2" },
9893
9894 { MIPS_GRP_GP32BIT, "gp32bit" },
9895 { MIPS_GRP_GP64BIT, "gp64bit" },
9896 };
9897 #endif
9898
Mips_group_name(csh handle,unsigned int id)9899 const char *Mips_group_name(csh handle, unsigned int id)
9900 {
9901 #ifndef CAPSTONE_DIET
9902 // verify group id
9903 if (id >= MIPS_GRP_ENDING || (id > MIPS_GRP_JUMP && id < MIPS_GRP_BITCOUNT))
9904 return NULL;
9905
9906 // NOTE: when new generic groups are added, 2 must be changed accordingly
9907 if (id >= 128)
9908 return group_name_maps[id - 128 + 2].name;
9909 else
9910 return group_name_maps[id].name;
9911 #else
9912 return NULL;
9913 #endif
9914 }
9915
9916 // map instruction name to public instruction ID
Mips_map_insn(const char * name)9917 mips_reg Mips_map_insn(const char *name)
9918 {
9919 // handle special alias first
9920 unsigned int i;
9921
9922 // NOTE: skip first NULL name in insn_name_maps
9923 i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name);
9924
9925 return (i != -1)? i : MIPS_REG_INVALID;
9926 }
9927
9928 // map internal raw register to 'public' register
Mips_map_register(unsigned int r)9929 mips_reg Mips_map_register(unsigned int r)
9930 {
9931 // for some reasons different Mips modes can map different register number to
9932 // the same Mips register. this function handles the issue for exposing Mips
9933 // operands by mapping internal registers to 'public' register.
9934 static const unsigned int map[] = { 0,
9935 MIPS_REG_AT, MIPS_REG_DSPCCOND, MIPS_REG_DSPCARRY, MIPS_REG_DSPEFI, MIPS_REG_DSPOUTFLAG,
9936 MIPS_REG_DSPPOS, MIPS_REG_DSPSCOUNT, MIPS_REG_FP, MIPS_REG_GP, MIPS_REG_2,
9937 MIPS_REG_1, MIPS_REG_0, MIPS_REG_6, MIPS_REG_4, MIPS_REG_5,
9938 MIPS_REG_3, MIPS_REG_7, 0, MIPS_REG_RA, MIPS_REG_SP,
9939 MIPS_REG_ZERO, MIPS_REG_A0, MIPS_REG_A1, MIPS_REG_A2, MIPS_REG_A3,
9940 MIPS_REG_AC0, MIPS_REG_AC1, MIPS_REG_AC2, MIPS_REG_AC3, MIPS_REG_AT,
9941 MIPS_REG_CC0, MIPS_REG_CC1, MIPS_REG_CC2, MIPS_REG_CC3, MIPS_REG_CC4,
9942 MIPS_REG_CC5, MIPS_REG_CC6, MIPS_REG_CC7, MIPS_REG_0, MIPS_REG_1,
9943 MIPS_REG_2, MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6,
9944 MIPS_REG_7, MIPS_REG_8, MIPS_REG_9, MIPS_REG_0, MIPS_REG_1,
9945 MIPS_REG_2, MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6,
9946 MIPS_REG_7, MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11,
9947 MIPS_REG_12, MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16,
9948 MIPS_REG_17, MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21,
9949 MIPS_REG_22, MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26,
9950 MIPS_REG_27, MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31,
9951 MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, MIPS_REG_13, MIPS_REG_14,
9952 MIPS_REG_15, MIPS_REG_16, MIPS_REG_17, MIPS_REG_18, MIPS_REG_19,
9953 MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, MIPS_REG_23, MIPS_REG_24,
9954 MIPS_REG_25, MIPS_REG_26, MIPS_REG_27, MIPS_REG_28, MIPS_REG_29,
9955 MIPS_REG_30, MIPS_REG_31, MIPS_REG_F0, MIPS_REG_F2, MIPS_REG_F4,
9956 MIPS_REG_F6, MIPS_REG_F8, MIPS_REG_F10, MIPS_REG_F12, MIPS_REG_F14,
9957 MIPS_REG_F16, MIPS_REG_F18, MIPS_REG_F20, MIPS_REG_F22, MIPS_REG_F24,
9958 MIPS_REG_F26, MIPS_REG_F28, MIPS_REG_F30, MIPS_REG_DSPOUTFLAG20, MIPS_REG_DSPOUTFLAG21,
9959 MIPS_REG_DSPOUTFLAG22, MIPS_REG_DSPOUTFLAG23, MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2,
9960 MIPS_REG_F3, MIPS_REG_F4, MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7,
9961 MIPS_REG_F8, MIPS_REG_F9, MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12,
9962 MIPS_REG_F13, MIPS_REG_F14, MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17,
9963 MIPS_REG_F18, MIPS_REG_F19, MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22,
9964 MIPS_REG_F23, MIPS_REG_F24, MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27,
9965 MIPS_REG_F28, MIPS_REG_F29, MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_FCC0,
9966 MIPS_REG_FCC1, MIPS_REG_FCC2, MIPS_REG_FCC3, MIPS_REG_FCC4, MIPS_REG_FCC5,
9967 MIPS_REG_FCC6, MIPS_REG_FCC7, MIPS_REG_0, MIPS_REG_1, MIPS_REG_2,
9968 MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, MIPS_REG_7,
9969 MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, MIPS_REG_12,
9970 MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, MIPS_REG_17,
9971 MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, MIPS_REG_22,
9972 MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, MIPS_REG_27,
9973 MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, MIPS_REG_FP,
9974 MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, MIPS_REG_F3, MIPS_REG_F4,
9975 MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, MIPS_REG_F8, MIPS_REG_F9,
9976 MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, MIPS_REG_F13, MIPS_REG_F14,
9977 MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, MIPS_REG_F18, MIPS_REG_F19,
9978 MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, MIPS_REG_F23, MIPS_REG_F24,
9979 MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, MIPS_REG_F28, MIPS_REG_F29,
9980 MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_GP, MIPS_REG_AC0, MIPS_REG_AC1,
9981 MIPS_REG_AC2, MIPS_REG_AC3, MIPS_REG_0, MIPS_REG_1, MIPS_REG_2,
9982 MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, MIPS_REG_7,
9983 MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, MIPS_REG_12,
9984 MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, MIPS_REG_17,
9985 MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, MIPS_REG_22,
9986 MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, MIPS_REG_27,
9987 MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, MIPS_REG_K0,
9988 MIPS_REG_K1, MIPS_REG_AC0, MIPS_REG_AC1, MIPS_REG_AC2, MIPS_REG_AC3,
9989 MIPS_REG_MPL0, MIPS_REG_MPL1, MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1,
9990 MIPS_REG_P2, MIPS_REG_RA, MIPS_REG_S0, MIPS_REG_S1, MIPS_REG_S2,
9991 MIPS_REG_S3, MIPS_REG_S4, MIPS_REG_S5, MIPS_REG_S6, MIPS_REG_S7,
9992 MIPS_REG_SP, MIPS_REG_T0, MIPS_REG_T1, MIPS_REG_T2, MIPS_REG_T3,
9993 MIPS_REG_T4, MIPS_REG_T5, MIPS_REG_T6, MIPS_REG_T7, MIPS_REG_T8,
9994 MIPS_REG_T9, MIPS_REG_V0, MIPS_REG_V1, MIPS_REG_W0, MIPS_REG_W1,
9995 MIPS_REG_W2, MIPS_REG_W3, MIPS_REG_W4, MIPS_REG_W5, MIPS_REG_W6,
9996 MIPS_REG_W7, MIPS_REG_W8, MIPS_REG_W9, MIPS_REG_W10, MIPS_REG_W11,
9997 MIPS_REG_W12, MIPS_REG_W13, MIPS_REG_W14, MIPS_REG_W15, MIPS_REG_W16,
9998 MIPS_REG_W17, MIPS_REG_W18, MIPS_REG_W19, MIPS_REG_W20, MIPS_REG_W21,
9999 MIPS_REG_W22, MIPS_REG_W23, MIPS_REG_W24, MIPS_REG_W25, MIPS_REG_W26,
10000 MIPS_REG_W27, MIPS_REG_W28, MIPS_REG_W29, MIPS_REG_W30, MIPS_REG_W31,
10001 MIPS_REG_ZERO, MIPS_REG_A0, MIPS_REG_A1, MIPS_REG_A2, MIPS_REG_A3,
10002 MIPS_REG_AC0, MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, MIPS_REG_F3,
10003 MIPS_REG_F4, MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, MIPS_REG_F8,
10004 MIPS_REG_F9, MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, MIPS_REG_F13,
10005 MIPS_REG_F14, MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, MIPS_REG_F18,
10006 MIPS_REG_F19, MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, MIPS_REG_F23,
10007 MIPS_REG_F24, MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, MIPS_REG_F28,
10008 MIPS_REG_F29, MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_DSPOUTFLAG16_19, MIPS_REG_HI,
10009 MIPS_REG_K0, MIPS_REG_K1, MIPS_REG_LO, MIPS_REG_S0, MIPS_REG_S1,
10010 MIPS_REG_S2, MIPS_REG_S3, MIPS_REG_S4, MIPS_REG_S5, MIPS_REG_S6,
10011 MIPS_REG_S7, MIPS_REG_T0, MIPS_REG_T1, MIPS_REG_T2, MIPS_REG_T3,
10012 MIPS_REG_T4, MIPS_REG_T5, MIPS_REG_T6, MIPS_REG_T7, MIPS_REG_T8,
10013 MIPS_REG_T9, MIPS_REG_V0, MIPS_REG_V1,
10014 };
10015
10016 if (r < ARR_SIZE(map))
10017 return map[r];
10018
10019 // cannot find this register
10020 return 0;
10021 }
10022
10023 #endif
10024