1 /*
2  * QEMU 16550A multi UART emulation
3  *
4  * SPDX-License-Identifier: MIT
5  *
6  * Copyright (c) 2003-2004 Fabrice Bellard
7  * Copyright (c) 2008 Citrix Systems, Inc.
8  *
9  * Permission is hereby granted, free of charge, to any person obtaining a copy
10  * of this software and associated documentation files (the "Software"), to deal
11  * in the Software without restriction, including without limitation the rights
12  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13  * copies of the Software, and to permit persons to whom the Software is
14  * furnished to do so, subject to the following conditions:
15  *
16  * The above copyright notice and this permission notice shall be included in
17  * all copies or substantial portions of the Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25  * THE SOFTWARE.
26  */
27 
28 /* see docs/specs/pci-serial.txt */
29 
30 #include "qemu/osdep.h"
31 #include "qapi/error.h"
32 #include "hw/char/serial.h"
33 #include "hw/irq.h"
34 #include "hw/pci/pci.h"
35 #include "hw/qdev-properties.h"
36 #include "migration/vmstate.h"
37 
38 #define PCI_SERIAL_MAX_PORTS 4
39 
40 typedef struct PCIMultiSerialState {
41     PCIDevice    dev;
42     MemoryRegion iobar;
43     uint32_t     ports;
44     char         *name[PCI_SERIAL_MAX_PORTS];
45     SerialState  state[PCI_SERIAL_MAX_PORTS];
46     uint32_t     level[PCI_SERIAL_MAX_PORTS];
47     qemu_irq     *irqs;
48     uint8_t      prog_if;
49 } PCIMultiSerialState;
50 
multi_serial_pci_exit(PCIDevice * dev)51 static void multi_serial_pci_exit(PCIDevice *dev)
52 {
53     PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
54     SerialState *s;
55     int i;
56 
57     for (i = 0; i < pci->ports; i++) {
58         s = pci->state + i;
59         serial_exit_core(s);
60         memory_region_del_subregion(&pci->iobar, &s->io);
61         g_free(pci->name[i]);
62     }
63     qemu_free_irqs(pci->irqs, pci->ports);
64 }
65 
multi_serial_irq_mux(void * opaque,int n,int level)66 static void multi_serial_irq_mux(void *opaque, int n, int level)
67 {
68     PCIMultiSerialState *pci = opaque;
69     int i, pending = 0;
70 
71     pci->level[n] = level;
72     for (i = 0; i < pci->ports; i++) {
73         if (pci->level[i]) {
74             pending = 1;
75         }
76     }
77     pci_set_irq(&pci->dev, pending);
78 }
79 
multi_serial_pci_realize(PCIDevice * dev,Error ** errp)80 static void multi_serial_pci_realize(PCIDevice *dev, Error **errp)
81 {
82     PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
83     PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
84     SerialState *s;
85     Error *err = NULL;
86     int i, nr_ports = 0;
87 
88     switch (pc->device_id) {
89     case 0x0003:
90         nr_ports = 2;
91         break;
92     case 0x0004:
93         nr_ports = 4;
94         break;
95     }
96     assert(nr_ports > 0);
97     assert(nr_ports <= PCI_SERIAL_MAX_PORTS);
98 
99     pci->dev.config[PCI_CLASS_PROG] = pci->prog_if;
100     pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
101     memory_region_init(&pci->iobar, OBJECT(pci), "multiserial", 8 * nr_ports);
102     pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->iobar);
103     pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci,
104                                    nr_ports);
105 
106     for (i = 0; i < nr_ports; i++) {
107         s = pci->state + i;
108         s->baudbase = 115200;
109         serial_realize_core(s, &err);
110         if (err != NULL) {
111             error_propagate(errp, err);
112             multi_serial_pci_exit(dev);
113             return;
114         }
115         s->irq = pci->irqs[i];
116         pci->name[i] = g_strdup_printf("uart #%d", i + 1);
117         memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s,
118                               pci->name[i], 8);
119         memory_region_add_subregion(&pci->iobar, 8 * i, &s->io);
120         pci->ports++;
121     }
122 }
123 
124 static const VMStateDescription vmstate_pci_multi_serial = {
125     .name = "pci-serial-multi",
126     .version_id = 1,
127     .minimum_version_id = 1,
128     .fields = (VMStateField[]) {
129         VMSTATE_PCI_DEVICE(dev, PCIMultiSerialState),
130         VMSTATE_STRUCT_ARRAY(state, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS,
131                              0, vmstate_serial, SerialState),
132         VMSTATE_UINT32_ARRAY(level, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS),
133         VMSTATE_END_OF_LIST()
134     }
135 };
136 
137 static Property multi_2x_serial_pci_properties[] = {
138     DEFINE_PROP_CHR("chardev1",  PCIMultiSerialState, state[0].chr),
139     DEFINE_PROP_CHR("chardev2",  PCIMultiSerialState, state[1].chr),
140     DEFINE_PROP_UINT8("prog_if",  PCIMultiSerialState, prog_if, 0x02),
141     DEFINE_PROP_END_OF_LIST(),
142 };
143 
144 static Property multi_4x_serial_pci_properties[] = {
145     DEFINE_PROP_CHR("chardev1",  PCIMultiSerialState, state[0].chr),
146     DEFINE_PROP_CHR("chardev2",  PCIMultiSerialState, state[1].chr),
147     DEFINE_PROP_CHR("chardev3",  PCIMultiSerialState, state[2].chr),
148     DEFINE_PROP_CHR("chardev4",  PCIMultiSerialState, state[3].chr),
149     DEFINE_PROP_UINT8("prog_if",  PCIMultiSerialState, prog_if, 0x02),
150     DEFINE_PROP_END_OF_LIST(),
151 };
152 
multi_2x_serial_pci_class_initfn(ObjectClass * klass,void * data)153 static void multi_2x_serial_pci_class_initfn(ObjectClass *klass, void *data)
154 {
155     DeviceClass *dc = DEVICE_CLASS(klass);
156     PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
157     pc->realize = multi_serial_pci_realize;
158     pc->exit = multi_serial_pci_exit;
159     pc->vendor_id = PCI_VENDOR_ID_REDHAT;
160     pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL2;
161     pc->revision = 1;
162     pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
163     dc->vmsd = &vmstate_pci_multi_serial;
164     dc->props = multi_2x_serial_pci_properties;
165     set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
166 }
167 
multi_4x_serial_pci_class_initfn(ObjectClass * klass,void * data)168 static void multi_4x_serial_pci_class_initfn(ObjectClass *klass, void *data)
169 {
170     DeviceClass *dc = DEVICE_CLASS(klass);
171     PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
172     pc->realize = multi_serial_pci_realize;
173     pc->exit = multi_serial_pci_exit;
174     pc->vendor_id = PCI_VENDOR_ID_REDHAT;
175     pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL4;
176     pc->revision = 1;
177     pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
178     dc->vmsd = &vmstate_pci_multi_serial;
179     dc->props = multi_4x_serial_pci_properties;
180     set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
181 }
182 
183 static const TypeInfo multi_2x_serial_pci_info = {
184     .name          = "pci-serial-2x",
185     .parent        = TYPE_PCI_DEVICE,
186     .instance_size = sizeof(PCIMultiSerialState),
187     .class_init    = multi_2x_serial_pci_class_initfn,
188     .interfaces = (InterfaceInfo[]) {
189         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
190         { },
191     },
192 };
193 
194 static const TypeInfo multi_4x_serial_pci_info = {
195     .name          = "pci-serial-4x",
196     .parent        = TYPE_PCI_DEVICE,
197     .instance_size = sizeof(PCIMultiSerialState),
198     .class_init    = multi_4x_serial_pci_class_initfn,
199     .interfaces = (InterfaceInfo[]) {
200         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
201         { },
202     },
203 };
204 
multi_serial_pci_register_types(void)205 static void multi_serial_pci_register_types(void)
206 {
207     type_register_static(&multi_2x_serial_pci_info);
208     type_register_static(&multi_4x_serial_pci_info);
209 }
210 
211 type_init(multi_serial_pci_register_types)
212