1 #ifndef _IPXE_PCIEA_H 2 #define _IPXE_PCIEA_H 3 4 /** @file 5 * 6 * PCI Enhanced Allocation 7 * 8 */ 9 10 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); 11 12 #include <ipxe/pci.h> 13 14 /** Number of entries */ 15 #define PCIEA_ENTRIES 2 16 #define PCIEA_ENTRIES_MASK 0x3f 17 18 /** First entry */ 19 #define PCIEA_FIRST 4 20 21 /** Entry descriptor */ 22 #define PCIEA_DESC 0 23 24 /** Entry size */ 25 #define PCIEA_DESC_SIZE(desc) ( ( (desc) >> 0 ) & 0x7 ) 26 27 /** BAR equivalent indicator */ 28 #define PCIEA_DESC_BEI(desc) ( ( (desc) >> 4 ) & 0xf ) 29 30 /** BAR equivalent indicators */ 31 enum pciea_bei { 32 PCIEA_BEI_BAR_0 = 0, /**< Standard BAR 0 */ 33 PCIEA_BEI_BAR_1 = 1, /**< Standard BAR 1 */ 34 PCIEA_BEI_BAR_2 = 2, /**< Standard BAR 2 */ 35 PCIEA_BEI_BAR_3 = 3, /**< Standard BAR 3 */ 36 PCIEA_BEI_BAR_4 = 4, /**< Standard BAR 4 */ 37 PCIEA_BEI_BAR_5 = 5, /**< Standard BAR 5 */ 38 PCIEA_BEI_ROM = 8, /**< Expansion ROM BAR */ 39 PCIEA_BEI_VF_BAR_0 = 9, /**< Virtual function BAR 0 */ 40 PCIEA_BEI_VF_BAR_1 = 10, /**< Virtual function BAR 1 */ 41 PCIEA_BEI_VF_BAR_2 = 11, /**< Virtual function BAR 2 */ 42 PCIEA_BEI_VF_BAR_3 = 12, /**< Virtual function BAR 3 */ 43 PCIEA_BEI_VF_BAR_4 = 13, /**< Virtual function BAR 4 */ 44 PCIEA_BEI_VF_BAR_5 = 14, /**< Virtual function BAR 5 */ 45 }; 46 47 /** Entry is enabled */ 48 #define PCIEA_DESC_ENABLED 0x80000000UL 49 50 /** Base address low dword */ 51 #define PCIEA_LOW_BASE 4 52 53 /** Limit low dword */ 54 #define PCIEA_LOW_LIMIT 8 55 56 /** BAR is 64-bit */ 57 #define PCIEA_LOW_ATTR_64BIT 0x00000002UL 58 59 /** Low dword attribute bit mask */ 60 #define PCIEA_LOW_ATTR_MASK 0x00000003UL 61 62 /** Offset to high dwords */ 63 #define PCIEA_LOW_HIGH 8 64 65 extern unsigned long pciea_bar_start ( struct pci_device *pci, 66 unsigned int bei ); 67 extern unsigned long pciea_bar_size ( struct pci_device *pci, 68 unsigned int bei ); 69 70 #endif /* _IPXE_PCIEA_H */ 71