1 // Initialize PCI devices (on emulators)
2 //
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
5 //
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
7
8 #include "byteorder.h" // le64_to_cpu
9 #include "config.h" // CONFIG_*
10 #include "dev-q35.h" // Q35_HOST_BRIDGE_PCIEXBAR_ADDR
11 #include "dev-piix.h" // PIIX_*
12 #include "e820map.h" // e820_add
13 #include "hw/ata.h" // PORT_ATA1_CMD_BASE
14 #include "hw/pci.h" // pci_config_readl
15 #include "hw/pcidevice.h" // pci_probe_devices
16 #include "hw/pci_ids.h" // PCI_VENDOR_ID_INTEL
17 #include "hw/pci_regs.h" // PCI_COMMAND
18 #include "fw/dev-pci.h" // REDHAT_CAP_RESOURCE_RESERVE
19 #include "list.h" // struct hlist_node
20 #include "malloc.h" // free
21 #include "output.h" // dprintf
22 #include "paravirt.h" // RamSize
23 #include "romfile.h" // romfile_loadint
24 #include "string.h" // memset
25 #include "util.h" // pci_setup
26 #include "x86.h" // outb
27
28 #define PCI_DEVICE_MEM_MIN (1<<12) // 4k == page size
29 #define PCI_BRIDGE_MEM_MIN (1<<21) // 2M == hugepage size
30 #define PCI_BRIDGE_IO_MIN 0x1000 // mandated by pci bridge spec
31
32 #define PCI_ROM_SLOT 6
33 #define PCI_NUM_REGIONS 7
34 #define PCI_BRIDGE_NUM_REGIONS 2
35
36 enum pci_region_type {
37 PCI_REGION_TYPE_IO,
38 PCI_REGION_TYPE_MEM,
39 PCI_REGION_TYPE_PREFMEM,
40 PCI_REGION_TYPE_COUNT,
41 };
42
43 static const char *region_type_name[] = {
44 [ PCI_REGION_TYPE_IO ] = "io",
45 [ PCI_REGION_TYPE_MEM ] = "mem",
46 [ PCI_REGION_TYPE_PREFMEM ] = "prefmem",
47 };
48
49 u64 pcimem_start = BUILD_PCIMEM_START;
50 u64 pcimem_end = BUILD_PCIMEM_END;
51 u64 pcimem64_start = BUILD_PCIMEM64_START;
52 u64 pcimem64_end = BUILD_PCIMEM64_END;
53 u64 pci_io_low_end = 0xa000;
54
55 struct pci_region_entry {
56 struct pci_device *dev;
57 int bar;
58 u64 size;
59 u64 align;
60 int is64;
61 enum pci_region_type type;
62 struct hlist_node node;
63 };
64
65 struct pci_region {
66 /* pci region assignments */
67 u64 base;
68 struct hlist_head list;
69 };
70
71 struct pci_bus {
72 struct pci_region r[PCI_REGION_TYPE_COUNT];
73 struct pci_device *bus_dev;
74 };
75
pci_bar(struct pci_device * pci,int region_num)76 static u32 pci_bar(struct pci_device *pci, int region_num)
77 {
78 if (region_num != PCI_ROM_SLOT) {
79 return PCI_BASE_ADDRESS_0 + region_num * 4;
80 }
81
82 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
83 u8 type = pci->header_type & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
84 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
85 }
86
87 static void
pci_set_io_region_addr(struct pci_device * pci,int bar,u64 addr,int is64)88 pci_set_io_region_addr(struct pci_device *pci, int bar, u64 addr, int is64)
89 {
90 u32 ofs = pci_bar(pci, bar);
91 pci_config_writel(pci->bdf, ofs, addr);
92 if (is64)
93 pci_config_writel(pci->bdf, ofs + 4, addr >> 32);
94 }
95
96
97 /****************************************************************
98 * Misc. device init
99 ****************************************************************/
100
101 /* host irqs corresponding to PCI irqs A-D */
102 const u8 pci_irqs[4] = {
103 10, 10, 11, 11
104 };
105
dummy_pci_slot_get_irq(struct pci_device * pci,int pin)106 static int dummy_pci_slot_get_irq(struct pci_device *pci, int pin)
107 {
108 dprintf(1, "pci_slot_get_irq called with unknown routing\n");
109
110 return 0xff; /* PCI defined "unknown" or "no connection" for x86 */
111 }
112
113 static int (*pci_slot_get_irq)(struct pci_device *pci, int pin) =
114 dummy_pci_slot_get_irq;
115
116 // Return the global irq number corresponding to a host bus device irq pin.
piix_pci_slot_get_irq(struct pci_device * pci,int pin)117 static int piix_pci_slot_get_irq(struct pci_device *pci, int pin)
118 {
119 int slot_addend = 0;
120
121 while (pci->parent != NULL) {
122 slot_addend += pci_bdf_to_dev(pci->bdf);
123 pci = pci->parent;
124 }
125 slot_addend += pci_bdf_to_dev(pci->bdf) - 1;
126 return pci_irqs[(pin - 1 + slot_addend) & 3];
127 }
128
mch_pci_slot_get_irq(struct pci_device * pci,int pin)129 static int mch_pci_slot_get_irq(struct pci_device *pci, int pin)
130 {
131 int pin_addend = 0;
132 while (pci->parent != NULL) {
133 pin_addend += pci_bdf_to_dev(pci->bdf);
134 pci = pci->parent;
135 }
136 u8 slot = pci_bdf_to_dev(pci->bdf);
137 if (slot <= 24)
138 /* Slots 0-24 rotate slot:pin mapping similar to piix above, but
139 with a different starting index - see q35-acpi-dsdt.dsl */
140 return pci_irqs[(pin - 1 + pin_addend + slot) & 3];
141 /* Slots 25-31 all use LNKA mapping (or LNKE, but A:D = E:H) */
142 return pci_irqs[(pin - 1 + pin_addend) & 3];
143 }
144
145 /* PIIX3/PIIX4 PCI to ISA bridge */
piix_isa_bridge_setup(struct pci_device * pci,void * arg)146 static void piix_isa_bridge_setup(struct pci_device *pci, void *arg)
147 {
148 int i, irq;
149 u8 elcr[2];
150
151 elcr[0] = 0x00;
152 elcr[1] = 0x00;
153 for (i = 0; i < 4; i++) {
154 irq = pci_irqs[i];
155 /* set to trigger level */
156 elcr[irq >> 3] |= (1 << (irq & 7));
157 /* activate irq remapping in PIIX */
158 pci_config_writeb(pci->bdf, 0x60 + i, irq);
159 }
160 outb(elcr[0], PIIX_PORT_ELCR1);
161 outb(elcr[1], PIIX_PORT_ELCR2);
162 dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]);
163 }
164
mch_isa_lpc_setup(u16 bdf)165 static void mch_isa_lpc_setup(u16 bdf)
166 {
167 /* pm io base */
168 pci_config_writel(bdf, ICH9_LPC_PMBASE,
169 acpi_pm_base | ICH9_LPC_PMBASE_RTE);
170
171 /* acpi enable, SCI: IRQ9 000b = irq9*/
172 pci_config_writeb(bdf, ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_ACPI_EN);
173
174 /* set root complex register block BAR */
175 pci_config_writel(bdf, ICH9_LPC_RCBA,
176 ICH9_LPC_RCBA_ADDR | ICH9_LPC_RCBA_EN);
177 }
178
179 static int ICH9LpcBDF = -1;
180
181 /* ICH9 LPC PCI to ISA bridge */
182 /* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_LPC */
mch_isa_bridge_setup(struct pci_device * dev,void * arg)183 static void mch_isa_bridge_setup(struct pci_device *dev, void *arg)
184 {
185 u16 bdf = dev->bdf;
186 int i, irq;
187 u8 elcr[2];
188
189 elcr[0] = 0x00;
190 elcr[1] = 0x00;
191
192 for (i = 0; i < 4; i++) {
193 irq = pci_irqs[i];
194 /* set to trigger level */
195 elcr[irq >> 3] |= (1 << (irq & 7));
196
197 /* activate irq remapping in LPC */
198
199 /* PIRQ[A-D] routing */
200 pci_config_writeb(bdf, ICH9_LPC_PIRQA_ROUT + i, irq);
201 /* PIRQ[E-H] routing */
202 pci_config_writeb(bdf, ICH9_LPC_PIRQE_ROUT + i, irq);
203 }
204 outb(elcr[0], ICH9_LPC_PORT_ELCR1);
205 outb(elcr[1], ICH9_LPC_PORT_ELCR2);
206 dprintf(1, "Q35 LPC init: elcr=%02x %02x\n", elcr[0], elcr[1]);
207
208 ICH9LpcBDF = bdf;
209
210 mch_isa_lpc_setup(bdf);
211
212 e820_add(ICH9_LPC_RCBA_ADDR, 16*1024, E820_RESERVED);
213
214 acpi_pm1a_cnt = acpi_pm_base + 0x04;
215 pmtimer_setup(acpi_pm_base + 0x08);
216 }
217
storage_ide_setup(struct pci_device * pci,void * arg)218 static void storage_ide_setup(struct pci_device *pci, void *arg)
219 {
220 /* IDE: we map it as in ISA mode */
221 pci_set_io_region_addr(pci, 0, PORT_ATA1_CMD_BASE, 0);
222 pci_set_io_region_addr(pci, 1, PORT_ATA1_CTRL_BASE, 0);
223 pci_set_io_region_addr(pci, 2, PORT_ATA2_CMD_BASE, 0);
224 pci_set_io_region_addr(pci, 3, PORT_ATA2_CTRL_BASE, 0);
225 }
226
227 /* PIIX3/PIIX4 IDE */
piix_ide_setup(struct pci_device * pci,void * arg)228 static void piix_ide_setup(struct pci_device *pci, void *arg)
229 {
230 u16 bdf = pci->bdf;
231 pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
232 pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
233 }
234
pic_ibm_setup(struct pci_device * pci,void * arg)235 static void pic_ibm_setup(struct pci_device *pci, void *arg)
236 {
237 /* PIC, IBM, MPIC & MPIC2 */
238 pci_set_io_region_addr(pci, 0, 0x80800000 + 0x00040000, 0);
239 }
240
apple_macio_setup(struct pci_device * pci,void * arg)241 static void apple_macio_setup(struct pci_device *pci, void *arg)
242 {
243 /* macio bridge */
244 pci_set_io_region_addr(pci, 0, 0x80800000, 0);
245 }
246
piix4_pm_config_setup(u16 bdf)247 static void piix4_pm_config_setup(u16 bdf)
248 {
249 // acpi sci is hardwired to 9
250 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
251
252 pci_config_writel(bdf, PIIX_PMBASE, acpi_pm_base | 1);
253 pci_config_writeb(bdf, PIIX_PMREGMISC, 0x01); /* enable PM io space */
254 pci_config_writel(bdf, PIIX_SMBHSTBASE, (acpi_pm_base + 0x100) | 1);
255 pci_config_writeb(bdf, PIIX_SMBHSTCFG, 0x09); /* enable SMBus io space */
256 }
257
258 static int PiixPmBDF = -1;
259
260 /* PIIX4 Power Management device (for ACPI) */
piix4_pm_setup(struct pci_device * pci,void * arg)261 static void piix4_pm_setup(struct pci_device *pci, void *arg)
262 {
263 PiixPmBDF = pci->bdf;
264 piix4_pm_config_setup(pci->bdf);
265
266 acpi_pm1a_cnt = acpi_pm_base + 0x04;
267 pmtimer_setup(acpi_pm_base + 0x08);
268 }
269
ich9_smbus_enable(u16 bdf)270 static void ich9_smbus_enable(u16 bdf)
271 {
272 /* map smbus into io space */
273 pci_config_writel(bdf, ICH9_SMB_SMB_BASE,
274 (acpi_pm_base + 0x100) | PCI_BASE_ADDRESS_SPACE_IO);
275
276 /* enable SMBus */
277 pci_config_writeb(bdf, ICH9_SMB_HOSTC, ICH9_SMB_HOSTC_HST_EN);
278 }
279
280 static int ICH9SmbusBDF = -1;
281
282 /* ICH9 SMBUS */
283 /* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_SMBUS */
ich9_smbus_setup(struct pci_device * dev,void * arg)284 static void ich9_smbus_setup(struct pci_device *dev, void *arg)
285 {
286 ICH9SmbusBDF = dev->bdf;
287
288 ich9_smbus_enable(dev->bdf);
289 }
290
intel_igd_setup(struct pci_device * dev,void * arg)291 static void intel_igd_setup(struct pci_device *dev, void *arg)
292 {
293 struct romfile_s *opregion = romfile_find("etc/igd-opregion");
294 u64 bdsm_size = le64_to_cpu(romfile_loadint("etc/igd-bdsm-size", 0));
295
296 /* Apply OpRegion to any Intel VGA device, more than one is undefined */
297 if (opregion && opregion->size) {
298 void *addr = memalign_high(PAGE_SIZE, opregion->size);
299 if (!addr) {
300 warn_noalloc();
301 return;
302 }
303
304 if (opregion->copy(opregion, addr, opregion->size) < 0) {
305 free(addr);
306 return;
307 }
308
309 pci_config_writel(dev->bdf, 0xFC, cpu_to_le32((u32)addr));
310
311 dprintf(1, "Intel IGD OpRegion enabled at 0x%08x, size %dKB, dev %pP\n"
312 , (u32)addr, opregion->size >> 10, dev);
313 }
314
315 /* Apply BDSM only to Intel VGA at 00:02.0 */
316 if (bdsm_size && (dev->bdf == pci_to_bdf(0, 2, 0))) {
317 void *addr = memalign_tmphigh(1024 * 1024, bdsm_size);
318 if (!addr) {
319 warn_noalloc();
320 return;
321 }
322
323 e820_add((u32)addr, bdsm_size, E820_RESERVED);
324
325 pci_config_writel(dev->bdf, 0x5C, cpu_to_le32((u32)addr));
326
327 dprintf(1, "Intel IGD BDSM enabled at 0x%08x, size %lldMB, dev %pP\n"
328 , (u32)addr, bdsm_size >> 20, dev);
329 }
330 }
331
332 static const struct pci_device_id pci_device_tbl[] = {
333 /* PIIX3/PIIX4 PCI to ISA bridge */
334 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0,
335 piix_isa_bridge_setup),
336 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
337 piix_isa_bridge_setup),
338 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_LPC,
339 mch_isa_bridge_setup),
340
341 /* STORAGE IDE */
342 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1,
343 PCI_CLASS_STORAGE_IDE, piix_ide_setup),
344 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
345 PCI_CLASS_STORAGE_IDE, piix_ide_setup),
346 PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
347 storage_ide_setup),
348
349 /* PIC, IBM, MPIC & MPIC2 */
350 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0x0046, PCI_CLASS_SYSTEM_PIC,
351 pic_ibm_setup),
352 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0xFFFF, PCI_CLASS_SYSTEM_PIC,
353 pic_ibm_setup),
354
355 /* PIIX4 Power Management device (for ACPI) */
356 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
357 piix4_pm_setup),
358 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_SMBUS,
359 ich9_smbus_setup),
360
361 /* 0xff00 */
362 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_setup),
363 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0022, 0xff00, apple_macio_setup),
364
365 /* Intel IGD OpRegion setup */
366 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
367 intel_igd_setup),
368
369 PCI_DEVICE_END,
370 };
371
372 static int MCHMmcfgBDF = -1;
373 static void mch_mmconfig_setup(u16 bdf);
374
pci_resume(void)375 void pci_resume(void)
376 {
377 if (!CONFIG_QEMU) {
378 return;
379 }
380
381 if (PiixPmBDF >= 0) {
382 piix4_pm_config_setup(PiixPmBDF);
383 }
384
385 if (ICH9LpcBDF >= 0) {
386 mch_isa_lpc_setup(ICH9LpcBDF);
387 }
388
389 if (ICH9SmbusBDF >= 0) {
390 ich9_smbus_enable(ICH9SmbusBDF);
391 }
392
393 if(MCHMmcfgBDF >= 0) {
394 mch_mmconfig_setup(MCHMmcfgBDF);
395 }
396 }
397
pci_bios_init_device(struct pci_device * pci)398 static void pci_bios_init_device(struct pci_device *pci)
399 {
400 dprintf(1, "PCI: init bdf=%pP id=%04x:%04x\n"
401 , pci, pci->vendor, pci->device);
402
403 /* map the interrupt */
404 u16 bdf = pci->bdf;
405 int pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
406 if (pin != 0)
407 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pci_slot_get_irq(pci, pin));
408
409 pci_init_device(pci_device_tbl, pci, NULL);
410
411 /* enable memory mappings */
412 pci_config_maskw(bdf, PCI_COMMAND, 0,
413 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_SERR);
414 /* enable SERR# for forwarding */
415 if (pci->header_type & PCI_HEADER_TYPE_BRIDGE)
416 pci_config_maskw(bdf, PCI_BRIDGE_CONTROL, 0,
417 PCI_BRIDGE_CTL_SERR);
418 }
419
pci_bios_init_devices(void)420 static void pci_bios_init_devices(void)
421 {
422 struct pci_device *pci;
423 foreachpci(pci) {
424 pci_bios_init_device(pci);
425 }
426 }
427
pci_enable_default_vga(void)428 static void pci_enable_default_vga(void)
429 {
430 struct pci_device *pci;
431
432 foreachpci(pci) {
433 if (is_pci_vga(pci)) {
434 dprintf(1, "PCI: Using %pP for primary VGA\n", pci);
435 return;
436 }
437 }
438
439 pci = pci_find_class(PCI_CLASS_DISPLAY_VGA);
440 if (!pci) {
441 dprintf(1, "PCI: No VGA devices found\n");
442 return;
443 }
444
445 dprintf(1, "PCI: Enabling %pP for primary VGA\n", pci);
446
447 pci_config_maskw(pci->bdf, PCI_COMMAND, 0,
448 PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
449
450 while (pci->parent) {
451 pci = pci->parent;
452
453 dprintf(1, "PCI: Setting VGA enable on bridge %pP\n", pci);
454
455 pci_config_maskw(pci->bdf, PCI_BRIDGE_CONTROL, 0, PCI_BRIDGE_CTL_VGA);
456 pci_config_maskw(pci->bdf, PCI_COMMAND, 0,
457 PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
458 }
459 }
460
461 /****************************************************************
462 * Platform device initialization
463 ****************************************************************/
464
i440fx_mem_addr_setup(struct pci_device * dev,void * arg)465 static void i440fx_mem_addr_setup(struct pci_device *dev, void *arg)
466 {
467 if (RamSize <= 0x80000000)
468 pcimem_start = 0x80000000;
469 else if (RamSize <= 0xc0000000)
470 pcimem_start = 0xc0000000;
471
472 pci_slot_get_irq = piix_pci_slot_get_irq;
473 }
474
mch_mmconfig_setup(u16 bdf)475 static void mch_mmconfig_setup(u16 bdf)
476 {
477 u64 addr = Q35_HOST_BRIDGE_PCIEXBAR_ADDR;
478 u32 upper = addr >> 32;
479 u32 lower = (addr & 0xffffffff) | Q35_HOST_BRIDGE_PCIEXBAREN;
480 pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, 0);
481 pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR + 4, upper);
482 pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, lower);
483 }
484
mch_mem_addr_setup(struct pci_device * dev,void * arg)485 static void mch_mem_addr_setup(struct pci_device *dev, void *arg)
486 {
487 u64 addr = Q35_HOST_BRIDGE_PCIEXBAR_ADDR;
488 u32 size = Q35_HOST_BRIDGE_PCIEXBAR_SIZE;
489
490 /* setup mmconfig */
491 MCHMmcfgBDF = dev->bdf;
492 mch_mmconfig_setup(dev->bdf);
493 e820_add(addr, size, E820_RESERVED);
494
495 /* setup pci i/o window (above mmconfig) */
496 pcimem_start = addr + size;
497
498 pci_slot_get_irq = mch_pci_slot_get_irq;
499
500 /* setup io address space */
501 if (acpi_pm_base < 0x1000)
502 pci_io_low_end = 0x10000;
503 else
504 pci_io_low_end = acpi_pm_base;
505 }
506
507 static const struct pci_device_id pci_platform_tbl[] = {
508 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441,
509 i440fx_mem_addr_setup),
510 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q35_MCH,
511 mch_mem_addr_setup),
512 PCI_DEVICE_END
513 };
514
pci_bios_init_platform(void)515 static void pci_bios_init_platform(void)
516 {
517 struct pci_device *pci;
518 foreachpci(pci) {
519 pci_init_device(pci_platform_tbl, pci, NULL);
520 }
521 }
522
pci_find_resource_reserve_capability(u16 bdf)523 static u8 pci_find_resource_reserve_capability(u16 bdf)
524 {
525 u16 device_id;
526
527 if (pci_config_readw(bdf, PCI_VENDOR_ID) != PCI_VENDOR_ID_REDHAT) {
528 dprintf(3, "PCI: This is non-QEMU bridge.\n");
529 return 0;
530 }
531
532 device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
533
534 if (device_id != PCI_DEVICE_ID_REDHAT_ROOT_PORT &&
535 device_id != PCI_DEVICE_ID_REDHAT_BRIDGE) {
536 dprintf(1, "PCI: QEMU resource reserve cap device ID doesn't match.\n");
537 return 0;
538 }
539 u8 cap = 0;
540
541 do {
542 cap = pci_find_capability(bdf, PCI_CAP_ID_VNDR, cap);
543 } while (cap &&
544 pci_config_readb(bdf, cap + PCI_CAP_REDHAT_TYPE_OFFSET) !=
545 REDHAT_CAP_RESOURCE_RESERVE);
546 if (cap) {
547 u8 cap_len = pci_config_readb(bdf, cap + PCI_CAP_FLAGS);
548 if (cap_len < RES_RESERVE_CAP_SIZE) {
549 dprintf(1, "PCI: QEMU resource reserve cap length %d is invalid\n",
550 cap_len);
551 return 0;
552 }
553 } else {
554 dprintf(1, "PCI: QEMU resource reserve cap not found\n");
555 }
556 return cap;
557 }
558
559 /****************************************************************
560 * Bus initialization
561 ****************************************************************/
562
563 static void
pci_bios_init_bus_rec(int bus,u8 * pci_bus)564 pci_bios_init_bus_rec(int bus, u8 *pci_bus)
565 {
566 int bdf;
567 u16 class;
568
569 dprintf(1, "PCI: %s bus = 0x%x\n", __func__, bus);
570
571 /* prevent accidental access to unintended devices */
572 foreachbdf(bdf, bus) {
573 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
574 if (class == PCI_CLASS_BRIDGE_PCI) {
575 pci_config_writeb(bdf, PCI_SECONDARY_BUS, 255);
576 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 0);
577 }
578 }
579
580 foreachbdf(bdf, bus) {
581 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
582 if (class != PCI_CLASS_BRIDGE_PCI) {
583 continue;
584 }
585 dprintf(1, "PCI: %s bdf = 0x%x\n", __func__, bdf);
586
587 u8 pribus = pci_config_readb(bdf, PCI_PRIMARY_BUS);
588 if (pribus != bus) {
589 dprintf(1, "PCI: primary bus = 0x%x -> 0x%x\n", pribus, bus);
590 pci_config_writeb(bdf, PCI_PRIMARY_BUS, bus);
591 } else {
592 dprintf(1, "PCI: primary bus = 0x%x\n", pribus);
593 }
594
595 u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
596 (*pci_bus)++;
597 if (*pci_bus != secbus) {
598 dprintf(1, "PCI: secondary bus = 0x%x -> 0x%x\n",
599 secbus, *pci_bus);
600 secbus = *pci_bus;
601 pci_config_writeb(bdf, PCI_SECONDARY_BUS, secbus);
602 } else {
603 dprintf(1, "PCI: secondary bus = 0x%x\n", secbus);
604 }
605
606 /* set to max for access to all subordinate buses.
607 later set it to accurate value */
608 u8 subbus = pci_config_readb(bdf, PCI_SUBORDINATE_BUS);
609 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 255);
610
611 pci_bios_init_bus_rec(secbus, pci_bus);
612
613 if (subbus != *pci_bus) {
614 u8 res_bus = *pci_bus;
615 u8 cap = pci_find_resource_reserve_capability(bdf);
616
617 if (cap) {
618 u32 tmp_res_bus = pci_config_readl(bdf,
619 cap + RES_RESERVE_BUS_RES);
620 if (tmp_res_bus != (u32)-1) {
621 res_bus = tmp_res_bus & 0xFF;
622 if ((u8)(res_bus + secbus) < secbus ||
623 (u8)(res_bus + secbus) < res_bus) {
624 dprintf(1, "PCI: bus_reserve value %d is invalid\n",
625 res_bus);
626 res_bus = 0;
627 }
628 if (secbus + res_bus > *pci_bus) {
629 dprintf(1, "PCI: QEMU resource reserve cap: bus = %u\n",
630 res_bus);
631 res_bus = secbus + res_bus;
632 }
633 }
634 }
635 dprintf(1, "PCI: subordinate bus = 0x%x -> 0x%x\n",
636 subbus, res_bus);
637 subbus = res_bus;
638 *pci_bus = res_bus;
639 } else {
640 dprintf(1, "PCI: subordinate bus = 0x%x\n", subbus);
641 }
642 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, subbus);
643 }
644 }
645
646 static void
pci_bios_init_bus(void)647 pci_bios_init_bus(void)
648 {
649 u8 extraroots = romfile_loadint("etc/extra-pci-roots", 0);
650 u8 pci_bus = 0;
651
652 pci_bios_init_bus_rec(0 /* host bus */, &pci_bus);
653
654 if (extraroots) {
655 while (pci_bus < 0xff) {
656 pci_bus++;
657 pci_bios_init_bus_rec(pci_bus, &pci_bus);
658 }
659 }
660 }
661
662
663 /****************************************************************
664 * Bus sizing
665 ****************************************************************/
666
667 static void
pci_bios_get_bar(struct pci_device * pci,int bar,int * ptype,u64 * psize,int * pis64)668 pci_bios_get_bar(struct pci_device *pci, int bar,
669 int *ptype, u64 *psize, int *pis64)
670 {
671 u32 ofs = pci_bar(pci, bar);
672 u16 bdf = pci->bdf;
673 u32 old = pci_config_readl(bdf, ofs);
674 int is64 = 0, type = PCI_REGION_TYPE_MEM;
675 u64 mask;
676
677 if (bar == PCI_ROM_SLOT) {
678 mask = PCI_ROM_ADDRESS_MASK;
679 pci_config_writel(bdf, ofs, mask);
680 } else {
681 if (old & PCI_BASE_ADDRESS_SPACE_IO) {
682 mask = PCI_BASE_ADDRESS_IO_MASK;
683 type = PCI_REGION_TYPE_IO;
684 } else {
685 mask = PCI_BASE_ADDRESS_MEM_MASK;
686 if (old & PCI_BASE_ADDRESS_MEM_PREFETCH)
687 type = PCI_REGION_TYPE_PREFMEM;
688 is64 = ((old & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
689 == PCI_BASE_ADDRESS_MEM_TYPE_64);
690 }
691 pci_config_writel(bdf, ofs, ~0);
692 }
693 u64 val = pci_config_readl(bdf, ofs);
694 pci_config_writel(bdf, ofs, old);
695 if (is64) {
696 u32 hold = pci_config_readl(bdf, ofs + 4);
697 pci_config_writel(bdf, ofs + 4, ~0);
698 u32 high = pci_config_readl(bdf, ofs + 4);
699 pci_config_writel(bdf, ofs + 4, hold);
700 val |= ((u64)high << 32);
701 mask |= ((u64)0xffffffff << 32);
702 *psize = (~(val & mask)) + 1;
703 } else {
704 *psize = ((~(val & mask)) + 1) & 0xffffffff;
705 }
706 *ptype = type;
707 *pis64 = is64;
708 }
709
pci_bios_bridge_region_is64(struct pci_region * r,struct pci_device * pci,int type)710 static int pci_bios_bridge_region_is64(struct pci_region *r,
711 struct pci_device *pci, int type)
712 {
713 if (type != PCI_REGION_TYPE_PREFMEM)
714 return 0;
715 u32 pmem = pci_config_readl(pci->bdf, PCI_PREF_MEMORY_BASE);
716 if (!pmem) {
717 pci_config_writel(pci->bdf, PCI_PREF_MEMORY_BASE, 0xfff0fff0);
718 pmem = pci_config_readl(pci->bdf, PCI_PREF_MEMORY_BASE);
719 pci_config_writel(pci->bdf, PCI_PREF_MEMORY_BASE, 0x0);
720 }
721 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) != PCI_PREF_RANGE_TYPE_64)
722 return 0;
723 struct pci_region_entry *entry;
724 hlist_for_each_entry(entry, &r->list, node) {
725 if (!entry->is64)
726 return 0;
727 }
728 return 1;
729 }
730
pci_region_align(struct pci_region * r)731 static u64 pci_region_align(struct pci_region *r)
732 {
733 struct pci_region_entry *entry;
734 hlist_for_each_entry(entry, &r->list, node) {
735 // The first entry in the sorted list has the largest alignment
736 return entry->align;
737 }
738 return 1;
739 }
740
pci_region_sum(struct pci_region * r)741 static u64 pci_region_sum(struct pci_region *r)
742 {
743 u64 sum = 0;
744 struct pci_region_entry *entry;
745 hlist_for_each_entry(entry, &r->list, node) {
746 sum += entry->size;
747 }
748 return sum;
749 }
750
pci_region_migrate_64bit_entries(struct pci_region * from,struct pci_region * to)751 static void pci_region_migrate_64bit_entries(struct pci_region *from,
752 struct pci_region *to)
753 {
754 struct hlist_node *n, **last = &to->list.first;
755 struct pci_region_entry *entry;
756 hlist_for_each_entry_safe(entry, n, &from->list, node) {
757 if (!entry->is64)
758 continue;
759 if (entry->dev->class == PCI_CLASS_SERIAL_USB)
760 continue;
761 // Move from source list to destination list.
762 hlist_del(&entry->node);
763 hlist_add(&entry->node, last);
764 last = &entry->node.next;
765 }
766 }
767
768 static struct pci_region_entry *
pci_region_create_entry(struct pci_bus * bus,struct pci_device * dev,int bar,u64 size,u64 align,int type,int is64)769 pci_region_create_entry(struct pci_bus *bus, struct pci_device *dev,
770 int bar, u64 size, u64 align, int type, int is64)
771 {
772 struct pci_region_entry *entry = malloc_tmp(sizeof(*entry));
773 if (!entry) {
774 warn_noalloc();
775 return NULL;
776 }
777 memset(entry, 0, sizeof(*entry));
778 entry->dev = dev;
779 entry->bar = bar;
780 entry->size = size;
781 entry->align = align;
782 entry->is64 = is64;
783 entry->type = type;
784 // Insert into list in sorted order.
785 struct hlist_node **pprev;
786 struct pci_region_entry *pos;
787 hlist_for_each_entry_pprev(pos, pprev, &bus->r[type].list, node) {
788 if (pos->align < align || (pos->align == align && pos->size < size))
789 break;
790 }
791 hlist_add(&entry->node, pprev);
792 return entry;
793 }
794
pci_bus_hotplug_support(struct pci_bus * bus,u8 pcie_cap)795 static int pci_bus_hotplug_support(struct pci_bus *bus, u8 pcie_cap)
796 {
797 u8 shpc_cap;
798
799 if (pcie_cap) {
800 u16 pcie_flags = pci_config_readw(bus->bus_dev->bdf,
801 pcie_cap + PCI_EXP_FLAGS);
802 u8 port_type = ((pcie_flags & PCI_EXP_FLAGS_TYPE) >>
803 (__builtin_ffs(PCI_EXP_FLAGS_TYPE) - 1));
804 u8 downstream_port = (port_type == PCI_EXP_TYPE_DOWNSTREAM) ||
805 (port_type == PCI_EXP_TYPE_ROOT_PORT);
806 /*
807 * PCI Express SPEC, 7.8.2:
808 * Slot Implemented – When Set, this bit indicates that the Link
809 * HwInit associated with this Port is connected to a slot (as
810 * compared to being connected to a system-integrated device or
811 * being disabled).
812 * This bit is valid for Downstream Ports. This bit is undefined
813 * for Upstream Ports.
814 */
815 u16 slot_implemented = pcie_flags & PCI_EXP_FLAGS_SLOT;
816
817 return downstream_port && slot_implemented;
818 }
819
820 shpc_cap = pci_find_capability(bus->bus_dev->bdf, PCI_CAP_ID_SHPC, 0);
821 return !!shpc_cap;
822 }
823
824 /* Test whether bridge support forwarding of transactions
825 * of a specific type.
826 * Note: disables bridge's window registers as a side effect.
827 */
pci_bridge_has_region(struct pci_device * pci,enum pci_region_type region_type)828 static int pci_bridge_has_region(struct pci_device *pci,
829 enum pci_region_type region_type)
830 {
831 u8 base;
832
833 switch (region_type) {
834 case PCI_REGION_TYPE_IO:
835 base = PCI_IO_BASE;
836 break;
837 case PCI_REGION_TYPE_PREFMEM:
838 base = PCI_PREF_MEMORY_BASE;
839 break;
840 default:
841 /* Regular memory support is mandatory */
842 return 1;
843 }
844
845 pci_config_writeb(pci->bdf, base, 0xFF);
846
847 return pci_config_readb(pci->bdf, base) != 0;
848 }
849
pci_bios_check_devices(struct pci_bus * busses)850 static int pci_bios_check_devices(struct pci_bus *busses)
851 {
852 dprintf(1, "PCI: check devices\n");
853
854 // Calculate resources needed for regular (non-bus) devices.
855 struct pci_device *pci;
856 foreachpci(pci) {
857 if (pci->class == PCI_CLASS_BRIDGE_PCI)
858 busses[pci->secondary_bus].bus_dev = pci;
859
860 struct pci_bus *bus = &busses[pci_bdf_to_bus(pci->bdf)];
861 if (!bus->bus_dev)
862 /*
863 * Resources for all root busses go in busses[0]
864 */
865 bus = &busses[0];
866 int i;
867 for (i = 0; i < PCI_NUM_REGIONS; i++) {
868 if ((pci->class == PCI_CLASS_BRIDGE_PCI) &&
869 (i >= PCI_BRIDGE_NUM_REGIONS && i < PCI_ROM_SLOT))
870 continue;
871 int type, is64;
872 u64 size;
873 pci_bios_get_bar(pci, i, &type, &size, &is64);
874 if (size == 0)
875 continue;
876
877 if (type != PCI_REGION_TYPE_IO && size < PCI_DEVICE_MEM_MIN)
878 size = PCI_DEVICE_MEM_MIN;
879 struct pci_region_entry *entry = pci_region_create_entry(
880 bus, pci, i, size, size, type, is64);
881 if (!entry)
882 return -1;
883
884 if (is64)
885 i++;
886 }
887 }
888
889 // Propagate required bus resources to parent busses.
890 int secondary_bus;
891 for (secondary_bus=MaxPCIBus; secondary_bus>0; secondary_bus--) {
892 struct pci_bus *s = &busses[secondary_bus];
893 if (!s->bus_dev)
894 continue;
895 struct pci_bus *parent = &busses[pci_bdf_to_bus(s->bus_dev->bdf)];
896 if (!parent->bus_dev)
897 /*
898 * Resources for all root busses go in busses[0]
899 */
900 parent = &busses[0];
901 int type;
902 u16 bdf = s->bus_dev->bdf;
903 u8 pcie_cap = pci_find_capability(bdf, PCI_CAP_ID_EXP, 0);
904 u8 qemu_cap = pci_find_resource_reserve_capability(bdf);
905
906 int hotplug_support = pci_bus_hotplug_support(s, pcie_cap);
907 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
908 u64 align = (type == PCI_REGION_TYPE_IO) ?
909 PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN;
910 if (!pci_bridge_has_region(s->bus_dev, type))
911 continue;
912 u64 size = 0;
913 if (qemu_cap) {
914 u32 tmp_size;
915 u64 tmp_size_64;
916 switch(type) {
917 case PCI_REGION_TYPE_IO:
918 tmp_size_64 = (pci_config_readl(bdf, qemu_cap + RES_RESERVE_IO) |
919 (u64)pci_config_readl(bdf, qemu_cap + RES_RESERVE_IO + 4) << 32);
920 if (tmp_size_64 != (u64)-1) {
921 size = tmp_size_64;
922 }
923 break;
924 case PCI_REGION_TYPE_MEM:
925 tmp_size = pci_config_readl(bdf, qemu_cap + RES_RESERVE_MEM);
926 if (tmp_size != (u32)-1) {
927 size = tmp_size;
928 }
929 break;
930 case PCI_REGION_TYPE_PREFMEM:
931 tmp_size = pci_config_readl(bdf, qemu_cap + RES_RESERVE_PREF_MEM_32);
932 tmp_size_64 = (pci_config_readl(bdf, qemu_cap + RES_RESERVE_PREF_MEM_64) |
933 (u64)pci_config_readl(bdf, qemu_cap + RES_RESERVE_PREF_MEM_64 + 4) << 32);
934 if (tmp_size != (u32)-1 && tmp_size_64 == (u64)-1) {
935 size = tmp_size;
936 } else if (tmp_size == (u32)-1 && tmp_size_64 != (u64)-1) {
937 size = tmp_size_64;
938 } else if (tmp_size != (u32)-1 && tmp_size_64 != (u64)-1) {
939 dprintf(1, "PCI: resource reserve cap PREF32 and PREF64"
940 " conflict\n");
941 }
942 break;
943 default:
944 break;
945 }
946 }
947 if (pci_region_align(&s->r[type]) > align)
948 align = pci_region_align(&s->r[type]);
949 u64 sum = pci_region_sum(&s->r[type]);
950 int resource_optional = pcie_cap && (type == PCI_REGION_TYPE_IO);
951 if (!sum && hotplug_support && !resource_optional)
952 sum = align; /* reserve min size for hot-plug */
953 if (size > sum) {
954 dprintf(1, "PCI: QEMU resource reserve cap: "
955 "size %08llx type %s\n",
956 size, region_type_name[type]);
957 if (type != PCI_REGION_TYPE_IO) {
958 size = ALIGN(size, align);
959 }
960 } else {
961 size = ALIGN(sum, align);
962 }
963 int is64 = pci_bios_bridge_region_is64(&s->r[type],
964 s->bus_dev, type);
965 // entry->bar is -1 if the entry represents a bridge region
966 struct pci_region_entry *entry = pci_region_create_entry(
967 parent, s->bus_dev, -1, size, align, type, is64);
968 if (!entry)
969 return -1;
970 dprintf(1, "PCI: secondary bus %d size %08llx type %s\n",
971 entry->dev->secondary_bus, size,
972 region_type_name[entry->type]);
973 }
974 }
975 return 0;
976 }
977
978
979 /****************************************************************
980 * BAR assignment
981 ****************************************************************/
982
983 // Setup region bases (given the regions' size and alignment)
pci_bios_init_root_regions_io(struct pci_bus * bus)984 static int pci_bios_init_root_regions_io(struct pci_bus *bus)
985 {
986 /*
987 * QEMU I/O address space usage:
988 * 0000 - 0fff legacy isa, pci config, pci root bus, ...
989 * 1000 - 9fff free
990 * a000 - afff hotplug (cpu, pci via acpi, i440fx/piix only)
991 * b000 - bfff power management (PORT_ACPI_PM_BASE)
992 * [ qemu 1.4+ implements pci config registers
993 * properly so guests can place the registers
994 * where they want, on older versions its fixed ]
995 * c000 - ffff free, traditionally used for pci io
996 */
997 struct pci_region *r_io = &bus->r[PCI_REGION_TYPE_IO];
998 u64 sum = pci_region_sum(r_io);
999 if (sum < 0x4000) {
1000 /* traditional region is big enougth, use it */
1001 r_io->base = 0xc000;
1002 } else if (sum < pci_io_low_end - 0x1000) {
1003 /* use the larger region at 0x1000 */
1004 r_io->base = 0x1000;
1005 } else {
1006 /* not enouth io address space -> error out */
1007 return -1;
1008 }
1009 dprintf(1, "PCI: IO: %4llx - %4llx\n", r_io->base, r_io->base + sum - 1);
1010 return 0;
1011 }
1012
pci_bios_init_root_regions_mem(struct pci_bus * bus)1013 static int pci_bios_init_root_regions_mem(struct pci_bus *bus)
1014 {
1015 struct pci_region *r_end = &bus->r[PCI_REGION_TYPE_PREFMEM];
1016 struct pci_region *r_start = &bus->r[PCI_REGION_TYPE_MEM];
1017
1018 if (pci_region_align(r_start) < pci_region_align(r_end)) {
1019 // Swap regions to improve alignment.
1020 r_end = r_start;
1021 r_start = &bus->r[PCI_REGION_TYPE_PREFMEM];
1022 }
1023 u64 sum = pci_region_sum(r_end);
1024 u64 align = pci_region_align(r_end);
1025 r_end->base = ALIGN_DOWN((pcimem_end - sum), align);
1026 sum = pci_region_sum(r_start);
1027 align = pci_region_align(r_start);
1028 r_start->base = ALIGN_DOWN((r_end->base - sum), align);
1029
1030 if ((r_start->base < pcimem_start) ||
1031 (r_start->base > pcimem_end))
1032 // Memory range requested is larger than available.
1033 return -1;
1034 return 0;
1035 }
1036
1037 #define PCI_IO_SHIFT 8
1038 #define PCI_MEMORY_SHIFT 16
1039 #define PCI_PREF_MEMORY_SHIFT 16
1040
1041 static void
pci_region_map_one_entry(struct pci_region_entry * entry,u64 addr)1042 pci_region_map_one_entry(struct pci_region_entry *entry, u64 addr)
1043 {
1044 if (entry->bar >= 0) {
1045 dprintf(1, "PCI: map device bdf=%pP"
1046 " bar %d, addr %08llx, size %08llx [%s]\n",
1047 entry->dev,
1048 entry->bar, addr, entry->size, region_type_name[entry->type]);
1049
1050 pci_set_io_region_addr(entry->dev, entry->bar, addr, entry->is64);
1051 return;
1052 }
1053
1054 u16 bdf = entry->dev->bdf;
1055 u64 limit = addr + entry->size - 1;
1056 if (entry->type == PCI_REGION_TYPE_IO) {
1057 pci_config_writeb(bdf, PCI_IO_BASE, addr >> PCI_IO_SHIFT);
1058 pci_config_writew(bdf, PCI_IO_BASE_UPPER16, 0);
1059 pci_config_writeb(bdf, PCI_IO_LIMIT, limit >> PCI_IO_SHIFT);
1060 pci_config_writew(bdf, PCI_IO_LIMIT_UPPER16, 0);
1061 }
1062 if (entry->type == PCI_REGION_TYPE_MEM) {
1063 pci_config_writew(bdf, PCI_MEMORY_BASE, addr >> PCI_MEMORY_SHIFT);
1064 pci_config_writew(bdf, PCI_MEMORY_LIMIT, limit >> PCI_MEMORY_SHIFT);
1065 }
1066 if (entry->type == PCI_REGION_TYPE_PREFMEM) {
1067 pci_config_writew(bdf, PCI_PREF_MEMORY_BASE, addr >> PCI_PREF_MEMORY_SHIFT);
1068 pci_config_writew(bdf, PCI_PREF_MEMORY_LIMIT, limit >> PCI_PREF_MEMORY_SHIFT);
1069 pci_config_writel(bdf, PCI_PREF_BASE_UPPER32, addr >> 32);
1070 pci_config_writel(bdf, PCI_PREF_LIMIT_UPPER32, limit >> 32);
1071 }
1072 }
1073
pci_region_map_entries(struct pci_bus * busses,struct pci_region * r)1074 static void pci_region_map_entries(struct pci_bus *busses, struct pci_region *r)
1075 {
1076 struct hlist_node *n;
1077 struct pci_region_entry *entry;
1078 hlist_for_each_entry_safe(entry, n, &r->list, node) {
1079 u64 addr = r->base;
1080 r->base += entry->size;
1081 if (entry->bar == -1)
1082 // Update bus base address if entry is a bridge region
1083 busses[entry->dev->secondary_bus].r[entry->type].base = addr;
1084 pci_region_map_one_entry(entry, addr);
1085 hlist_del(&entry->node);
1086 free(entry);
1087 }
1088 }
1089
pci_bios_map_devices(struct pci_bus * busses)1090 static void pci_bios_map_devices(struct pci_bus *busses)
1091 {
1092 if (pci_bios_init_root_regions_io(busses))
1093 panic("PCI: out of I/O address space\n");
1094
1095 dprintf(1, "PCI: 32: %016llx - %016llx\n", pcimem_start, pcimem_end);
1096 if (pci_bios_init_root_regions_mem(busses)) {
1097 struct pci_region r64_mem, r64_pref;
1098 r64_mem.list.first = NULL;
1099 r64_pref.list.first = NULL;
1100 pci_region_migrate_64bit_entries(&busses[0].r[PCI_REGION_TYPE_MEM],
1101 &r64_mem);
1102 pci_region_migrate_64bit_entries(&busses[0].r[PCI_REGION_TYPE_PREFMEM],
1103 &r64_pref);
1104
1105 if (pci_bios_init_root_regions_mem(busses))
1106 panic("PCI: out of 32bit address space\n");
1107
1108 u64 sum_mem = pci_region_sum(&r64_mem);
1109 u64 sum_pref = pci_region_sum(&r64_pref);
1110 u64 align_mem = pci_region_align(&r64_mem);
1111 u64 align_pref = pci_region_align(&r64_pref);
1112
1113 r64_mem.base = le64_to_cpu(romfile_loadint("etc/reserved-memory-end", 0));
1114 if (r64_mem.base < 0x100000000LL + RamSizeOver4G)
1115 r64_mem.base = 0x100000000LL + RamSizeOver4G;
1116 r64_mem.base = ALIGN(r64_mem.base, align_mem);
1117 r64_mem.base = ALIGN(r64_mem.base, (1LL<<30)); // 1G hugepage
1118 r64_pref.base = r64_mem.base + sum_mem;
1119 r64_pref.base = ALIGN(r64_pref.base, align_pref);
1120 r64_pref.base = ALIGN(r64_pref.base, (1LL<<30)); // 1G hugepage
1121 pcimem64_start = r64_mem.base;
1122 pcimem64_end = r64_pref.base + sum_pref;
1123 pcimem64_end = ALIGN(pcimem64_end, (1LL<<30)); // 1G hugepage
1124 dprintf(1, "PCI: 64: %016llx - %016llx\n", pcimem64_start, pcimem64_end);
1125
1126 pci_region_map_entries(busses, &r64_mem);
1127 pci_region_map_entries(busses, &r64_pref);
1128 } else {
1129 // no bars mapped high -> drop 64bit window (see dsdt)
1130 pcimem64_start = 0;
1131 }
1132 // Map regions on each device.
1133 int bus;
1134 for (bus = 0; bus<=MaxPCIBus; bus++) {
1135 int type;
1136 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++)
1137 pci_region_map_entries(busses, &busses[bus].r[type]);
1138 }
1139 }
1140
1141
1142 /****************************************************************
1143 * Main setup code
1144 ****************************************************************/
1145
1146 void
pci_setup(void)1147 pci_setup(void)
1148 {
1149 if (!CONFIG_QEMU)
1150 return;
1151
1152 dprintf(3, "pci setup\n");
1153
1154 dprintf(1, "=== PCI bus & bridge init ===\n");
1155 if (pci_probe_host() != 0) {
1156 return;
1157 }
1158 pci_bios_init_bus();
1159
1160 dprintf(1, "=== PCI device probing ===\n");
1161 pci_probe_devices();
1162
1163 pcimem_start = RamSize;
1164 pci_bios_init_platform();
1165
1166 dprintf(1, "=== PCI new allocation pass #1 ===\n");
1167 struct pci_bus *busses = malloc_tmp(sizeof(*busses) * (MaxPCIBus + 1));
1168 if (!busses) {
1169 warn_noalloc();
1170 return;
1171 }
1172 memset(busses, 0, sizeof(*busses) * (MaxPCIBus + 1));
1173 if (pci_bios_check_devices(busses))
1174 return;
1175
1176 dprintf(1, "=== PCI new allocation pass #2 ===\n");
1177 pci_bios_map_devices(busses);
1178
1179 pci_bios_init_devices();
1180
1181 free(busses);
1182
1183 pci_enable_default_vga();
1184 }
1185