1 // Code for handling XHCI "Super speed" USB controllers.
2 //
3 // Copyright (C) 2013 Gerd Hoffmann <kraxel@redhat.com>
4 // Copyright (C) 2014 Kevin O'Connor <kevin@koconnor.net>
5 //
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
7
8 #include "config.h" // CONFIG_*
9 #include "malloc.h" // memalign_low
10 #include "memmap.h" // PAGE_SIZE
11 #include "output.h" // dprintf
12 #include "pcidevice.h" // foreachpci
13 #include "pci_ids.h" // PCI_CLASS_SERIAL_USB_XHCI
14 #include "pci_regs.h" // PCI_BASE_ADDRESS_0
15 #include "string.h" // memcpy
16 #include "usb.h" // struct usb_s
17 #include "usb-xhci.h" // struct ehci_qh
18 #include "util.h" // timer_calc
19 #include "x86.h" // readl
20
21 // --------------------------------------------------------------
22 // configuration
23
24 #define XHCI_RING_ITEMS 16
25 #define XHCI_RING_SIZE (XHCI_RING_ITEMS*sizeof(struct xhci_trb))
26
27 /*
28 * xhci_ring structs are allocated with XHCI_RING_SIZE alignment,
29 * then we can get it from a trb pointer (provided by evt ring).
30 */
31 #define XHCI_RING(_trb) \
32 ((struct xhci_ring*)((u32)(_trb) & ~(XHCI_RING_SIZE-1)))
33
34 // --------------------------------------------------------------
35 // bit definitions
36
37 #define XHCI_CMD_RS (1<<0)
38 #define XHCI_CMD_HCRST (1<<1)
39 #define XHCI_CMD_INTE (1<<2)
40 #define XHCI_CMD_HSEE (1<<3)
41 #define XHCI_CMD_LHCRST (1<<7)
42 #define XHCI_CMD_CSS (1<<8)
43 #define XHCI_CMD_CRS (1<<9)
44 #define XHCI_CMD_EWE (1<<10)
45 #define XHCI_CMD_EU3S (1<<11)
46
47 #define XHCI_STS_HCH (1<<0)
48 #define XHCI_STS_HSE (1<<2)
49 #define XHCI_STS_EINT (1<<3)
50 #define XHCI_STS_PCD (1<<4)
51 #define XHCI_STS_SSS (1<<8)
52 #define XHCI_STS_RSS (1<<9)
53 #define XHCI_STS_SRE (1<<10)
54 #define XHCI_STS_CNR (1<<11)
55 #define XHCI_STS_HCE (1<<12)
56
57 #define XHCI_PORTSC_CCS (1<<0)
58 #define XHCI_PORTSC_PED (1<<1)
59 #define XHCI_PORTSC_OCA (1<<3)
60 #define XHCI_PORTSC_PR (1<<4)
61 #define XHCI_PORTSC_PLS_SHIFT 5
62 #define XHCI_PORTSC_PLS_MASK 0xf
63 #define XHCI_PORTSC_PP (1<<9)
64 #define XHCI_PORTSC_SPEED_SHIFT 10
65 #define XHCI_PORTSC_SPEED_MASK 0xf
66 #define XHCI_PORTSC_SPEED_FULL (1<<10)
67 #define XHCI_PORTSC_SPEED_LOW (2<<10)
68 #define XHCI_PORTSC_SPEED_HIGH (3<<10)
69 #define XHCI_PORTSC_SPEED_SUPER (4<<10)
70 #define XHCI_PORTSC_PIC_SHIFT 14
71 #define XHCI_PORTSC_PIC_MASK 0x3
72 #define XHCI_PORTSC_LWS (1<<16)
73 #define XHCI_PORTSC_CSC (1<<17)
74 #define XHCI_PORTSC_PEC (1<<18)
75 #define XHCI_PORTSC_WRC (1<<19)
76 #define XHCI_PORTSC_OCC (1<<20)
77 #define XHCI_PORTSC_PRC (1<<21)
78 #define XHCI_PORTSC_PLC (1<<22)
79 #define XHCI_PORTSC_CEC (1<<23)
80 #define XHCI_PORTSC_CAS (1<<24)
81 #define XHCI_PORTSC_WCE (1<<25)
82 #define XHCI_PORTSC_WDE (1<<26)
83 #define XHCI_PORTSC_WOE (1<<27)
84 #define XHCI_PORTSC_DR (1<<30)
85 #define XHCI_PORTSC_WPR (1<<31)
86
87 #define TRB_C (1<<0)
88 #define TRB_TYPE_SHIFT 10
89 #define TRB_TYPE_MASK 0x3f
90 #define TRB_TYPE(t) (((t) >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
91
92 #define TRB_EV_ED (1<<2)
93
94 #define TRB_TR_ENT (1<<1)
95 #define TRB_TR_ISP (1<<2)
96 #define TRB_TR_NS (1<<3)
97 #define TRB_TR_CH (1<<4)
98 #define TRB_TR_IOC (1<<5)
99 #define TRB_TR_IDT (1<<6)
100 #define TRB_TR_TBC_SHIFT 7
101 #define TRB_TR_TBC_MASK 0x3
102 #define TRB_TR_BEI (1<<9)
103 #define TRB_TR_TLBPC_SHIFT 16
104 #define TRB_TR_TLBPC_MASK 0xf
105 #define TRB_TR_FRAMEID_SHIFT 20
106 #define TRB_TR_FRAMEID_MASK 0x7ff
107 #define TRB_TR_SIA (1<<31)
108
109 #define TRB_TR_DIR (1<<16)
110
111 #define TRB_CR_SLOTID_SHIFT 24
112 #define TRB_CR_SLOTID_MASK 0xff
113 #define TRB_CR_EPID_SHIFT 16
114 #define TRB_CR_EPID_MASK 0x1f
115
116 #define TRB_CR_BSR (1<<9)
117 #define TRB_CR_DC (1<<9)
118
119 #define TRB_LK_TC (1<<1)
120
121 #define TRB_INTR_SHIFT 22
122 #define TRB_INTR_MASK 0x3ff
123 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK)
124
125 typedef enum TRBType {
126 TRB_RESERVED = 0,
127 TR_NORMAL,
128 TR_SETUP,
129 TR_DATA,
130 TR_STATUS,
131 TR_ISOCH,
132 TR_LINK,
133 TR_EVDATA,
134 TR_NOOP,
135 CR_ENABLE_SLOT,
136 CR_DISABLE_SLOT,
137 CR_ADDRESS_DEVICE,
138 CR_CONFIGURE_ENDPOINT,
139 CR_EVALUATE_CONTEXT,
140 CR_RESET_ENDPOINT,
141 CR_STOP_ENDPOINT,
142 CR_SET_TR_DEQUEUE,
143 CR_RESET_DEVICE,
144 CR_FORCE_EVENT,
145 CR_NEGOTIATE_BW,
146 CR_SET_LATENCY_TOLERANCE,
147 CR_GET_PORT_BANDWIDTH,
148 CR_FORCE_HEADER,
149 CR_NOOP,
150 ER_TRANSFER = 32,
151 ER_COMMAND_COMPLETE,
152 ER_PORT_STATUS_CHANGE,
153 ER_BANDWIDTH_REQUEST,
154 ER_DOORBELL,
155 ER_HOST_CONTROLLER,
156 ER_DEVICE_NOTIFICATION,
157 ER_MFINDEX_WRAP,
158 } TRBType;
159
160 typedef enum TRBCCode {
161 CC_INVALID = 0,
162 CC_SUCCESS,
163 CC_DATA_BUFFER_ERROR,
164 CC_BABBLE_DETECTED,
165 CC_USB_TRANSACTION_ERROR,
166 CC_TRB_ERROR,
167 CC_STALL_ERROR,
168 CC_RESOURCE_ERROR,
169 CC_BANDWIDTH_ERROR,
170 CC_NO_SLOTS_ERROR,
171 CC_INVALID_STREAM_TYPE_ERROR,
172 CC_SLOT_NOT_ENABLED_ERROR,
173 CC_EP_NOT_ENABLED_ERROR,
174 CC_SHORT_PACKET,
175 CC_RING_UNDERRUN,
176 CC_RING_OVERRUN,
177 CC_VF_ER_FULL,
178 CC_PARAMETER_ERROR,
179 CC_BANDWIDTH_OVERRUN,
180 CC_CONTEXT_STATE_ERROR,
181 CC_NO_PING_RESPONSE_ERROR,
182 CC_EVENT_RING_FULL_ERROR,
183 CC_INCOMPATIBLE_DEVICE_ERROR,
184 CC_MISSED_SERVICE_ERROR,
185 CC_COMMAND_RING_STOPPED,
186 CC_COMMAND_ABORTED,
187 CC_STOPPED,
188 CC_STOPPED_LENGTH_INVALID,
189 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29,
190 CC_ISOCH_BUFFER_OVERRUN = 31,
191 CC_EVENT_LOST_ERROR,
192 CC_UNDEFINED_ERROR,
193 CC_INVALID_STREAM_ID_ERROR,
194 CC_SECONDARY_BANDWIDTH_ERROR,
195 CC_SPLIT_TRANSACTION_ERROR
196 } TRBCCode;
197
198 enum {
199 PLS_U0 = 0,
200 PLS_U1 = 1,
201 PLS_U2 = 2,
202 PLS_U3 = 3,
203 PLS_DISABLED = 4,
204 PLS_RX_DETECT = 5,
205 PLS_INACTIVE = 6,
206 PLS_POLLING = 7,
207 PLS_RECOVERY = 8,
208 PLS_HOT_RESET = 9,
209 PLS_COMPILANCE_MODE = 10,
210 PLS_TEST_MODE = 11,
211 PLS_RESUME = 15,
212 };
213
214 #define xhci_get_field(data, field) \
215 (((data) >> field##_SHIFT) & field##_MASK)
216
217 // --------------------------------------------------------------
218 // state structs
219
220 struct xhci_ring {
221 struct xhci_trb ring[XHCI_RING_ITEMS];
222 struct xhci_trb evt;
223 u32 eidx;
224 u32 nidx;
225 u32 cs;
226 struct mutex_s lock;
227 };
228
229 struct xhci_portmap {
230 u8 start;
231 u8 count;
232 };
233
234 struct usb_xhci_s {
235 struct usb_s usb;
236
237 /* devinfo */
238 u32 xcap;
239 u32 ports;
240 u32 slots;
241 u8 context64;
242 struct xhci_portmap usb2;
243 struct xhci_portmap usb3;
244
245 /* xhci registers */
246 struct xhci_caps *caps;
247 struct xhci_op *op;
248 struct xhci_pr *pr;
249 struct xhci_ir *ir;
250 struct xhci_db *db;
251
252 /* xhci data structures */
253 struct xhci_devlist *devs;
254 struct xhci_ring *cmds;
255 struct xhci_ring *evts;
256 struct xhci_er_seg *eseg;
257 };
258
259 struct xhci_pipe {
260 struct xhci_ring reqs;
261
262 struct usb_pipe pipe;
263 u32 slotid;
264 u32 epid;
265 void *buf;
266 int bufused;
267 };
268
269 // --------------------------------------------------------------
270 // tables
271
272 static const char *speed_name[16] = {
273 [ 0 ] = " - ",
274 [ 1 ] = "Full",
275 [ 2 ] = "Low",
276 [ 3 ] = "High",
277 [ 4 ] = "Super",
278 };
279
280 static const int speed_from_xhci[16] = {
281 [ 0 ] = -1,
282 [ 1 ] = USB_FULLSPEED,
283 [ 2 ] = USB_LOWSPEED,
284 [ 3 ] = USB_HIGHSPEED,
285 [ 4 ] = USB_SUPERSPEED,
286 [ 5 ... 15 ] = -1,
287 };
288
289 static const int speed_to_xhci[] = {
290 [ USB_FULLSPEED ] = 1,
291 [ USB_LOWSPEED ] = 2,
292 [ USB_HIGHSPEED ] = 3,
293 [ USB_SUPERSPEED ] = 4,
294 };
295
wait_bit(u32 * reg,u32 mask,int value,u32 timeout)296 static int wait_bit(u32 *reg, u32 mask, int value, u32 timeout)
297 {
298 u32 end = timer_calc(timeout);
299
300 while ((readl(reg) & mask) != value) {
301 if (timer_check(end)) {
302 warn_timeout();
303 return -1;
304 }
305 yield();
306 }
307 return 0;
308 }
309
310
311 /****************************************************************
312 * Root hub
313 ****************************************************************/
314
315 #define XHCI_TIME_POSTPOWER 20
316
317 // Check if device attached to port
318 static void
xhci_print_port_state(int loglevel,const char * prefix,u32 port,u32 portsc)319 xhci_print_port_state(int loglevel, const char *prefix, u32 port, u32 portsc)
320 {
321 u32 pls = xhci_get_field(portsc, XHCI_PORTSC_PLS);
322 u32 speed = xhci_get_field(portsc, XHCI_PORTSC_SPEED);
323
324 dprintf(loglevel, "%s port #%d: 0x%08x,%s%s pls %d, speed %d [%s]\n",
325 prefix, port + 1, portsc,
326 (portsc & XHCI_PORTSC_PP) ? " powered," : "",
327 (portsc & XHCI_PORTSC_PED) ? " enabled," : "",
328 pls, speed, speed_name[speed]);
329 }
330
331 static int
xhci_hub_detect(struct usbhub_s * hub,u32 port)332 xhci_hub_detect(struct usbhub_s *hub, u32 port)
333 {
334 struct usb_xhci_s *xhci = container_of(hub->cntl, struct usb_xhci_s, usb);
335 u32 portsc = readl(&xhci->pr[port].portsc);
336 return (portsc & XHCI_PORTSC_CCS) ? 1 : 0;
337 }
338
339 // Reset device on port
340 static int
xhci_hub_reset(struct usbhub_s * hub,u32 port)341 xhci_hub_reset(struct usbhub_s *hub, u32 port)
342 {
343 struct usb_xhci_s *xhci = container_of(hub->cntl, struct usb_xhci_s, usb);
344 u32 portsc = readl(&xhci->pr[port].portsc);
345 if (!(portsc & XHCI_PORTSC_CCS))
346 // Device no longer connected?!
347 return -1;
348
349 switch (xhci_get_field(portsc, XHCI_PORTSC_PLS)) {
350 case PLS_U0:
351 // A USB3 port - controller automatically performs reset
352 break;
353 case PLS_POLLING:
354 // A USB2 port - perform device reset
355 xhci_print_port_state(3, __func__, port, portsc);
356 writel(&xhci->pr[port].portsc, portsc | XHCI_PORTSC_PR);
357 break;
358 default:
359 return -1;
360 }
361
362 // Wait for device to complete reset and be enabled
363 u32 end = timer_calc(100);
364 for (;;) {
365 portsc = readl(&xhci->pr[port].portsc);
366 if (!(portsc & XHCI_PORTSC_CCS))
367 // Device disconnected during reset
368 return -1;
369 if (portsc & XHCI_PORTSC_PED)
370 // Reset complete
371 break;
372 if (timer_check(end)) {
373 warn_timeout();
374 return -1;
375 }
376 yield();
377 }
378
379 int rc = speed_from_xhci[xhci_get_field(portsc, XHCI_PORTSC_SPEED)];
380 xhci_print_port_state(1, "XHCI", port, portsc);
381 return rc;
382 }
383
384 static int
xhci_hub_portmap(struct usbhub_s * hub,u32 vport)385 xhci_hub_portmap(struct usbhub_s *hub, u32 vport)
386 {
387 struct usb_xhci_s *xhci = container_of(hub->cntl, struct usb_xhci_s, usb);
388 u32 pport = vport + 1;
389
390 if (vport + 1 >= xhci->usb3.start &&
391 vport + 1 < xhci->usb3.start + xhci->usb3.count)
392 pport = vport + 2 - xhci->usb3.start;
393
394 if (vport + 1 >= xhci->usb2.start &&
395 vport + 1 < xhci->usb2.start + xhci->usb2.count)
396 pport = vport + 2 - xhci->usb2.start;
397
398 return pport;
399 }
400
401 static void
xhci_hub_disconnect(struct usbhub_s * hub,u32 port)402 xhci_hub_disconnect(struct usbhub_s *hub, u32 port)
403 {
404 // XXX - should turn the port power off.
405 }
406
407 static struct usbhub_op_s xhci_hub_ops = {
408 .detect = xhci_hub_detect,
409 .reset = xhci_hub_reset,
410 .portmap = xhci_hub_portmap,
411 .disconnect = xhci_hub_disconnect,
412 };
413
414 // Find any devices connected to the root hub.
415 static int
xhci_check_ports(struct usb_xhci_s * xhci)416 xhci_check_ports(struct usb_xhci_s *xhci)
417 {
418 // Wait for port power to stabilize.
419 msleep(XHCI_TIME_POSTPOWER);
420
421 struct usbhub_s hub;
422 memset(&hub, 0, sizeof(hub));
423 hub.cntl = &xhci->usb;
424 hub.portcount = xhci->ports;
425 hub.op = &xhci_hub_ops;
426 usb_enumerate(&hub);
427 return hub.devcount;
428 }
429
430
431 /****************************************************************
432 * Setup
433 ****************************************************************/
434
435 static void
xhci_free_pipes(struct usb_xhci_s * xhci)436 xhci_free_pipes(struct usb_xhci_s *xhci)
437 {
438 // XXX - should walk list of pipes and free unused pipes.
439 }
440
441 static void
configure_xhci(void * data)442 configure_xhci(void *data)
443 {
444 struct usb_xhci_s *xhci = data;
445 u32 reg;
446
447 xhci->devs = memalign_high(64, sizeof(*xhci->devs) * (xhci->slots + 1));
448 xhci->eseg = memalign_high(64, sizeof(*xhci->eseg));
449 xhci->cmds = memalign_high(XHCI_RING_SIZE, sizeof(*xhci->cmds));
450 xhci->evts = memalign_high(XHCI_RING_SIZE, sizeof(*xhci->evts));
451 if (!xhci->devs || !xhci->cmds || !xhci->evts || !xhci->eseg) {
452 warn_noalloc();
453 goto fail;
454 }
455 memset(xhci->devs, 0, sizeof(*xhci->devs) * (xhci->slots + 1));
456 memset(xhci->cmds, 0, sizeof(*xhci->cmds));
457 memset(xhci->evts, 0, sizeof(*xhci->evts));
458 memset(xhci->eseg, 0, sizeof(*xhci->eseg));
459
460 reg = readl(&xhci->op->usbcmd);
461 if (reg & XHCI_CMD_RS) {
462 reg &= ~XHCI_CMD_RS;
463 writel(&xhci->op->usbcmd, reg);
464 if (wait_bit(&xhci->op->usbsts, XHCI_STS_HCH, XHCI_STS_HCH, 32) != 0)
465 goto fail;
466 }
467
468 dprintf(3, "%s: resetting\n", __func__);
469 writel(&xhci->op->usbcmd, XHCI_CMD_HCRST);
470 if (wait_bit(&xhci->op->usbcmd, XHCI_CMD_HCRST, 0, 100) != 0)
471 goto fail;
472 if (wait_bit(&xhci->op->usbsts, XHCI_STS_CNR, 0, 100) != 0)
473 goto fail;
474
475 writel(&xhci->op->config, xhci->slots);
476 writel(&xhci->op->dcbaap_low, (u32)xhci->devs);
477 writel(&xhci->op->dcbaap_high, 0);
478 writel(&xhci->op->crcr_low, (u32)xhci->cmds | 1);
479 writel(&xhci->op->crcr_high, 0);
480 xhci->cmds->cs = 1;
481
482 xhci->eseg->ptr_low = (u32)xhci->evts;
483 xhci->eseg->ptr_high = 0;
484 xhci->eseg->size = XHCI_RING_ITEMS;
485 writel(&xhci->ir->erstsz, 1);
486 writel(&xhci->ir->erdp_low, (u32)xhci->evts);
487 writel(&xhci->ir->erdp_high, 0);
488 writel(&xhci->ir->erstba_low, (u32)xhci->eseg);
489 writel(&xhci->ir->erstba_high, 0);
490 xhci->evts->cs = 1;
491
492 reg = readl(&xhci->caps->hcsparams2);
493 u32 spb = (reg >> 21 & 0x1f) << 5 | reg >> 27;
494 if (spb) {
495 dprintf(3, "%s: setup %d scratch pad buffers\n", __func__, spb);
496 u64 *spba = memalign_high(64, sizeof(*spba) * spb);
497 void *pad = memalign_high(PAGE_SIZE, PAGE_SIZE * spb);
498 if (!spba || !pad) {
499 warn_noalloc();
500 free(spba);
501 free(pad);
502 goto fail;
503 }
504 int i;
505 for (i = 0; i < spb; i++)
506 spba[i] = (u32)pad + (i * PAGE_SIZE);
507 xhci->devs[0].ptr_low = (u32)spba;
508 xhci->devs[0].ptr_high = 0;
509 }
510
511 reg = readl(&xhci->op->usbcmd);
512 reg |= XHCI_CMD_RS;
513 writel(&xhci->op->usbcmd, reg);
514
515 // Find devices
516 int count = xhci_check_ports(xhci);
517 xhci_free_pipes(xhci);
518 if (count)
519 // Success
520 return;
521
522 // No devices found - shutdown and free controller.
523 dprintf(1, "XHCI no devices found\n");
524 reg = readl(&xhci->op->usbcmd);
525 reg &= ~XHCI_CMD_RS;
526 writel(&xhci->op->usbcmd, reg);
527 wait_bit(&xhci->op->usbsts, XHCI_STS_HCH, XHCI_STS_HCH, 32);
528
529 fail:
530 free(xhci->eseg);
531 free(xhci->evts);
532 free(xhci->cmds);
533 free(xhci->devs);
534 free(xhci);
535 }
536
537 static void
xhci_controller_setup(struct pci_device * pci)538 xhci_controller_setup(struct pci_device *pci)
539 {
540 void *baseaddr = pci_enable_membar(pci, PCI_BASE_ADDRESS_0);
541 if (!baseaddr)
542 return;
543
544 struct usb_xhci_s *xhci = malloc_high(sizeof(*xhci));
545 if (!xhci) {
546 warn_noalloc();
547 return;
548 }
549 memset(xhci, 0, sizeof(*xhci));
550 xhci->caps = baseaddr;
551 xhci->op = baseaddr + readb(&xhci->caps->caplength);
552 xhci->pr = baseaddr + readb(&xhci->caps->caplength) + 0x400;
553 xhci->db = baseaddr + readl(&xhci->caps->dboff);
554 xhci->ir = baseaddr + readl(&xhci->caps->rtsoff) + 0x20;
555
556 u32 hcs1 = readl(&xhci->caps->hcsparams1);
557 u32 hcc = readl(&xhci->caps->hccparams);
558 xhci->ports = (hcs1 >> 24) & 0xff;
559 xhci->slots = hcs1 & 0xff;
560 xhci->xcap = ((hcc >> 16) & 0xffff) << 2;
561 xhci->context64 = (hcc & 0x04) ? 1 : 0;
562
563 xhci->usb.pci = pci;
564 xhci->usb.type = USB_TYPE_XHCI;
565
566 dprintf(1, "XHCI init on dev %pP: regs @ %p, %d ports, %d slots"
567 ", %d byte contexts\n"
568 , pci, xhci->caps, xhci->ports, xhci->slots
569 , xhci->context64 ? 64 : 32);
570
571 if (xhci->xcap) {
572 u32 off;
573 void *addr = baseaddr + xhci->xcap;
574 do {
575 struct xhci_xcap *xcap = addr;
576 u32 ports, name, cap = readl(&xcap->cap);
577 switch (cap & 0xff) {
578 case 0x02:
579 name = readl(&xcap->data[0]);
580 ports = readl(&xcap->data[1]);
581 u8 major = (cap >> 24) & 0xff;
582 u8 minor = (cap >> 16) & 0xff;
583 u8 count = (ports >> 8) & 0xff;
584 u8 start = (ports >> 0) & 0xff;
585 dprintf(1, "XHCI protocol %c%c%c%c %x.%02x"
586 ", %d ports (offset %d), def %x\n"
587 , (name >> 0) & 0xff
588 , (name >> 8) & 0xff
589 , (name >> 16) & 0xff
590 , (name >> 24) & 0xff
591 , major, minor
592 , count, start
593 , ports >> 16);
594 if (name == 0x20425355 /* "USB " */) {
595 if (major == 2) {
596 xhci->usb2.start = start;
597 xhci->usb2.count = count;
598 }
599 if (major == 3) {
600 xhci->usb3.start = start;
601 xhci->usb3.count = count;
602 }
603 }
604 break;
605 default:
606 dprintf(1, "XHCI extcap 0x%x @ %p\n", cap & 0xff, addr);
607 break;
608 }
609 off = (cap >> 8) & 0xff;
610 addr += off << 2;
611 } while (off > 0);
612 }
613
614 u32 pagesize = readl(&xhci->op->pagesize);
615 if (PAGE_SIZE != (pagesize<<12)) {
616 dprintf(1, "XHCI driver does not support page size code %d\n"
617 , pagesize<<12);
618 free(xhci);
619 return;
620 }
621
622 pci_enable_busmaster(pci);
623
624 run_thread(configure_xhci, xhci);
625 }
626
627 void
xhci_setup(void)628 xhci_setup(void)
629 {
630 if (! CONFIG_USB_XHCI)
631 return;
632 struct pci_device *pci;
633 foreachpci(pci) {
634 if (pci_classprog(pci) == PCI_CLASS_SERIAL_USB_XHCI)
635 xhci_controller_setup(pci);
636 }
637 }
638
639
640 /****************************************************************
641 * End point communication
642 ****************************************************************/
643
644 // Signal the hardware to process events on a TRB ring
xhci_doorbell(struct usb_xhci_s * xhci,u32 slotid,u32 value)645 static void xhci_doorbell(struct usb_xhci_s *xhci, u32 slotid, u32 value)
646 {
647 dprintf(5, "%s: slotid %d, epid %d\n", __func__, slotid, value);
648 struct xhci_db *db = xhci->db;
649 void *addr = &db[slotid].doorbell;
650 writel(addr, value);
651 }
652
653 // Dequeue events on the XHCI command ring generated by the hardware
xhci_process_events(struct usb_xhci_s * xhci)654 static void xhci_process_events(struct usb_xhci_s *xhci)
655 {
656 struct xhci_ring *evts = xhci->evts;
657
658 for (;;) {
659 /* check for event */
660 u32 nidx = evts->nidx;
661 u32 cs = evts->cs;
662 struct xhci_trb *etrb = evts->ring + nidx;
663 u32 control = etrb->control;
664 if ((control & TRB_C) != (cs ? 1 : 0))
665 return;
666
667 /* process event */
668 u32 evt_type = TRB_TYPE(control);
669 u32 evt_cc = (etrb->status >> 24) & 0xff;
670 switch (evt_type) {
671 case ER_TRANSFER:
672 case ER_COMMAND_COMPLETE:
673 {
674 struct xhci_trb *rtrb = (void*)etrb->ptr_low;
675 struct xhci_ring *ring = XHCI_RING(rtrb);
676 struct xhci_trb *evt = &ring->evt;
677 u32 eidx = rtrb - ring->ring + 1;
678 dprintf(5, "%s: ring %p [trb %p, evt %p, type %d, eidx %d, cc %d]\n",
679 __func__, ring, rtrb, evt, evt_type, eidx, evt_cc);
680 memcpy(evt, etrb, sizeof(*etrb));
681 ring->eidx = eidx;
682 break;
683 }
684 case ER_PORT_STATUS_CHANGE:
685 {
686 u32 port = ((etrb->ptr_low >> 24) & 0xff) - 1;
687 // Read status, and clear port status change bits
688 u32 portsc = readl(&xhci->pr[port].portsc);
689 u32 pclear = (((portsc & ~(XHCI_PORTSC_PED|XHCI_PORTSC_PR))
690 & ~(XHCI_PORTSC_PLS_MASK<<XHCI_PORTSC_PLS_SHIFT))
691 | (1<<XHCI_PORTSC_PLS_SHIFT));
692 writel(&xhci->pr[port].portsc, pclear);
693
694 xhci_print_port_state(3, __func__, port, portsc);
695 break;
696 }
697 default:
698 dprintf(1, "%s: unknown event, type %d, cc %d\n",
699 __func__, evt_type, evt_cc);
700 break;
701 }
702
703 /* move ring index, notify xhci */
704 nidx++;
705 if (nidx == XHCI_RING_ITEMS) {
706 nidx = 0;
707 cs = cs ? 0 : 1;
708 evts->cs = cs;
709 }
710 evts->nidx = nidx;
711 struct xhci_ir *ir = xhci->ir;
712 u32 erdp = (u32)(evts->ring + nidx);
713 writel(&ir->erdp_low, erdp);
714 writel(&ir->erdp_high, 0);
715 }
716 }
717
718 // Check if a ring has any pending TRBs
xhci_ring_busy(struct xhci_ring * ring)719 static int xhci_ring_busy(struct xhci_ring *ring)
720 {
721 u32 eidx = ring->eidx;
722 u32 nidx = ring->nidx;
723 return (eidx != nidx);
724 }
725
726 // Wait for a ring to empty (all TRBs processed by hardware)
xhci_event_wait(struct usb_xhci_s * xhci,struct xhci_ring * ring,u32 timeout)727 static int xhci_event_wait(struct usb_xhci_s *xhci,
728 struct xhci_ring *ring,
729 u32 timeout)
730 {
731 u32 end = timer_calc(timeout);
732
733 for (;;) {
734 xhci_process_events(xhci);
735 if (!xhci_ring_busy(ring)) {
736 u32 status = ring->evt.status;
737 return (status >> 24) & 0xff;
738 }
739 if (timer_check(end)) {
740 warn_timeout();
741 return -1;
742 }
743 yield();
744 }
745 }
746
747 // Add a TRB to the given ring
xhci_trb_fill(struct xhci_ring * ring,void * data,u32 xferlen,u32 flags)748 static void xhci_trb_fill(struct xhci_ring *ring
749 , void *data, u32 xferlen, u32 flags)
750 {
751 struct xhci_trb *dst = &ring->ring[ring->nidx];
752 if (flags & TRB_TR_IDT) {
753 memcpy(&dst->ptr_low, data, xferlen);
754 } else {
755 dst->ptr_low = (u32)data;
756 dst->ptr_high = 0;
757 }
758 dst->status = xferlen;
759 dst->control = flags | (ring->cs ? TRB_C : 0);
760 }
761
762 // Queue a TRB onto a ring, wrapping ring as needed
xhci_trb_queue(struct xhci_ring * ring,void * data,u32 xferlen,u32 flags)763 static void xhci_trb_queue(struct xhci_ring *ring,
764 void *data, u32 xferlen, u32 flags)
765 {
766 if (ring->nidx >= ARRAY_SIZE(ring->ring) - 1) {
767 xhci_trb_fill(ring, ring->ring, 0, (TR_LINK << 10) | TRB_LK_TC);
768 ring->nidx = 0;
769 ring->cs ^= 1;
770 dprintf(5, "%s: ring %p [linked]\n", __func__, ring);
771 }
772
773 xhci_trb_fill(ring, data, xferlen, flags);
774 ring->nidx++;
775 dprintf(5, "%s: ring %p [nidx %d, len %d]\n",
776 __func__, ring, ring->nidx, xferlen);
777 }
778
779 // Submit a command to the xhci controller ring
xhci_cmd_submit(struct usb_xhci_s * xhci,struct xhci_inctx * inctx,u32 flags)780 static int xhci_cmd_submit(struct usb_xhci_s *xhci, struct xhci_inctx *inctx
781 , u32 flags)
782 {
783 if (inctx) {
784 struct xhci_slotctx *slot = (void*)&inctx[1 << xhci->context64];
785 u32 port = ((slot->ctx[1] >> 16) & 0xff) - 1;
786 u32 portsc = readl(&xhci->pr[port].portsc);
787 if (!(portsc & XHCI_PORTSC_CCS)) {
788 // Device no longer connected?!
789 xhci_print_port_state(1, __func__, port, portsc);
790 return -1;
791 }
792 }
793
794 mutex_lock(&xhci->cmds->lock);
795 xhci_trb_queue(xhci->cmds, inctx, 0, flags);
796 xhci_doorbell(xhci, 0, 0);
797 int rc = xhci_event_wait(xhci, xhci->cmds, 1000);
798 mutex_unlock(&xhci->cmds->lock);
799 return rc;
800 }
801
xhci_cmd_enable_slot(struct usb_xhci_s * xhci)802 static int xhci_cmd_enable_slot(struct usb_xhci_s *xhci)
803 {
804 dprintf(3, "%s:\n", __func__);
805 int cc = xhci_cmd_submit(xhci, NULL, CR_ENABLE_SLOT << 10);
806 if (cc != CC_SUCCESS)
807 return -1;
808 return (xhci->cmds->evt.control >> 24) & 0xff;
809 }
810
xhci_cmd_disable_slot(struct usb_xhci_s * xhci,u32 slotid)811 static int xhci_cmd_disable_slot(struct usb_xhci_s *xhci, u32 slotid)
812 {
813 dprintf(3, "%s: slotid %d\n", __func__, slotid);
814 return xhci_cmd_submit(xhci, NULL, (CR_DISABLE_SLOT << 10) | (slotid << 24));
815 }
816
xhci_cmd_address_device(struct usb_xhci_s * xhci,u32 slotid,struct xhci_inctx * inctx)817 static int xhci_cmd_address_device(struct usb_xhci_s *xhci, u32 slotid
818 , struct xhci_inctx *inctx)
819 {
820 dprintf(3, "%s: slotid %d\n", __func__, slotid);
821 return xhci_cmd_submit(xhci, inctx
822 , (CR_ADDRESS_DEVICE << 10) | (slotid << 24));
823 }
824
xhci_cmd_configure_endpoint(struct usb_xhci_s * xhci,u32 slotid,struct xhci_inctx * inctx)825 static int xhci_cmd_configure_endpoint(struct usb_xhci_s *xhci, u32 slotid
826 , struct xhci_inctx *inctx)
827 {
828 dprintf(3, "%s: slotid %d, add 0x%x, del 0x%x\n", __func__,
829 slotid, inctx->add, inctx->del);
830 return xhci_cmd_submit(xhci, inctx
831 , (CR_CONFIGURE_ENDPOINT << 10) | (slotid << 24));
832 }
833
xhci_cmd_evaluate_context(struct usb_xhci_s * xhci,u32 slotid,struct xhci_inctx * inctx)834 static int xhci_cmd_evaluate_context(struct usb_xhci_s *xhci, u32 slotid
835 , struct xhci_inctx *inctx)
836 {
837 dprintf(3, "%s: slotid %d, add 0x%x, del 0x%x\n", __func__,
838 slotid, inctx->add, inctx->del);
839 return xhci_cmd_submit(xhci, inctx
840 , (CR_EVALUATE_CONTEXT << 10) | (slotid << 24));
841 }
842
843 static struct xhci_inctx *
xhci_alloc_inctx(struct usbdevice_s * usbdev,int maxepid)844 xhci_alloc_inctx(struct usbdevice_s *usbdev, int maxepid)
845 {
846 struct usb_xhci_s *xhci = container_of(
847 usbdev->hub->cntl, struct usb_xhci_s, usb);
848 int size = (sizeof(struct xhci_inctx) * 33) << xhci->context64;
849 struct xhci_inctx *in = memalign_tmphigh(2048 << xhci->context64, size);
850 if (!in) {
851 warn_noalloc();
852 return NULL;
853 }
854 memset(in, 0, size);
855
856 struct xhci_slotctx *slot = (void*)&in[1 << xhci->context64];
857 slot->ctx[0] |= maxepid << 27; // context entries
858 slot->ctx[0] |= speed_to_xhci[usbdev->speed] << 20;
859
860 // Set high-speed hub flags.
861 struct usbdevice_s *hubdev = usbdev->hub->usbdev;
862 if (hubdev) {
863 if (usbdev->speed == USB_LOWSPEED || usbdev->speed == USB_FULLSPEED) {
864 struct xhci_pipe *hpipe = container_of(
865 hubdev->defpipe, struct xhci_pipe, pipe);
866 if (hubdev->speed == USB_HIGHSPEED) {
867 slot->ctx[2] |= hpipe->slotid;
868 slot->ctx[2] |= (usbdev->port+1) << 8;
869 } else {
870 struct xhci_slotctx *hslot = (void*)xhci->devs[hpipe->slotid].ptr_low;
871 slot->ctx[2] = hslot->ctx[2];
872 }
873 }
874 u32 route = 0;
875 while (usbdev->hub->usbdev) {
876 route <<= 4;
877 route |= (usbdev->port+1) & 0xf;
878 usbdev = usbdev->hub->usbdev;
879 }
880 slot->ctx[0] |= route;
881 }
882
883 slot->ctx[1] |= (usbdev->port+1) << 16;
884
885 return in;
886 }
887
xhci_config_hub(struct usbhub_s * hub)888 static int xhci_config_hub(struct usbhub_s *hub)
889 {
890 struct usb_xhci_s *xhci = container_of(
891 hub->cntl, struct usb_xhci_s, usb);
892 struct xhci_pipe *pipe = container_of(
893 hub->usbdev->defpipe, struct xhci_pipe, pipe);
894 struct xhci_slotctx *hdslot = (void*)xhci->devs[pipe->slotid].ptr_low;
895 if ((hdslot->ctx[3] >> 27) == 3)
896 // Already configured
897 return 0;
898 struct xhci_inctx *in = xhci_alloc_inctx(hub->usbdev, 1);
899 if (!in)
900 return -1;
901 in->add = 0x01;
902 struct xhci_slotctx *slot = (void*)&in[1 << xhci->context64];
903 slot->ctx[0] |= 1 << 26;
904 slot->ctx[1] |= hub->portcount << 24;
905
906 int cc = xhci_cmd_configure_endpoint(xhci, pipe->slotid, in);
907 free(in);
908 if (cc != CC_SUCCESS) {
909 dprintf(1, "%s: configure hub: failed (cc %d)\n", __func__, cc);
910 return -1;
911 }
912 return 0;
913 }
914
915 static struct usb_pipe *
xhci_alloc_pipe(struct usbdevice_s * usbdev,struct usb_endpoint_descriptor * epdesc)916 xhci_alloc_pipe(struct usbdevice_s *usbdev
917 , struct usb_endpoint_descriptor *epdesc)
918 {
919 u8 eptype = epdesc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
920 struct usb_xhci_s *xhci = container_of(
921 usbdev->hub->cntl, struct usb_xhci_s, usb);
922 struct xhci_pipe *pipe;
923 u32 epid;
924
925 if (epdesc->bEndpointAddress == 0) {
926 epid = 1;
927 } else {
928 epid = (epdesc->bEndpointAddress & 0x0f) * 2;
929 epid += (epdesc->bEndpointAddress & USB_DIR_IN) ? 1 : 0;
930 }
931
932 if (eptype == USB_ENDPOINT_XFER_CONTROL)
933 pipe = memalign_high(XHCI_RING_SIZE, sizeof(*pipe));
934 else
935 pipe = memalign_low(XHCI_RING_SIZE, sizeof(*pipe));
936 if (!pipe) {
937 warn_noalloc();
938 return NULL;
939 }
940 memset(pipe, 0, sizeof(*pipe));
941
942 usb_desc2pipe(&pipe->pipe, usbdev, epdesc);
943 pipe->epid = epid;
944 pipe->reqs.cs = 1;
945 if (eptype == USB_ENDPOINT_XFER_INT) {
946 pipe->buf = malloc_high(pipe->pipe.maxpacket);
947 if (!pipe->buf) {
948 warn_noalloc();
949 free(pipe);
950 return NULL;
951 }
952 }
953
954 // Allocate input context and initialize endpoint info.
955 struct xhci_inctx *in = xhci_alloc_inctx(usbdev, epid);
956 if (!in)
957 goto fail;
958 in->add = 0x01 | (1 << epid);
959 struct xhci_epctx *ep = (void*)&in[(pipe->epid+1) << xhci->context64];
960 if (eptype == USB_ENDPOINT_XFER_INT)
961 ep->ctx[0] = (usb_get_period(usbdev, epdesc) + 3) << 16;
962 ep->ctx[1] |= eptype << 3;
963 if (epdesc->bEndpointAddress & USB_DIR_IN
964 || eptype == USB_ENDPOINT_XFER_CONTROL)
965 ep->ctx[1] |= 1 << 5;
966 ep->ctx[1] |= pipe->pipe.maxpacket << 16;
967 ep->deq_low = (u32)&pipe->reqs.ring[0];
968 ep->deq_low |= 1; // dcs
969 ep->length = pipe->pipe.maxpacket;
970
971 dprintf(3, "%s: usbdev %p, ring %p, slotid %d, epid %d\n", __func__,
972 usbdev, &pipe->reqs, pipe->slotid, pipe->epid);
973 if (pipe->epid == 1) {
974 if (usbdev->hub->usbdev) {
975 // Make sure parent hub is configured.
976 int ret = xhci_config_hub(usbdev->hub);
977 if (ret)
978 goto fail;
979 }
980 // Enable slot.
981 u32 size = (sizeof(struct xhci_slotctx) * 32) << xhci->context64;
982 struct xhci_slotctx *dev = memalign_high(1024 << xhci->context64, size);
983 if (!dev) {
984 warn_noalloc();
985 goto fail;
986 }
987 int slotid = xhci_cmd_enable_slot(xhci);
988 if (slotid < 0) {
989 dprintf(1, "%s: enable slot: failed\n", __func__);
990 free(dev);
991 goto fail;
992 }
993 dprintf(3, "%s: enable slot: got slotid %d\n", __func__, slotid);
994 memset(dev, 0, size);
995 xhci->devs[slotid].ptr_low = (u32)dev;
996 xhci->devs[slotid].ptr_high = 0;
997
998 // Send set_address command.
999 int cc = xhci_cmd_address_device(xhci, slotid, in);
1000 if (cc != CC_SUCCESS) {
1001 dprintf(1, "%s: address device: failed (cc %d)\n", __func__, cc);
1002 cc = xhci_cmd_disable_slot(xhci, slotid);
1003 if (cc != CC_SUCCESS) {
1004 dprintf(1, "%s: disable failed (cc %d)\n", __func__, cc);
1005 goto fail;
1006 }
1007 xhci->devs[slotid].ptr_low = 0;
1008 free(dev);
1009 goto fail;
1010 }
1011 pipe->slotid = slotid;
1012 } else {
1013 struct xhci_pipe *defpipe = container_of(
1014 usbdev->defpipe, struct xhci_pipe, pipe);
1015 pipe->slotid = defpipe->slotid;
1016 // Send configure command.
1017 int cc = xhci_cmd_configure_endpoint(xhci, pipe->slotid, in);
1018 if (cc != CC_SUCCESS) {
1019 dprintf(1, "%s: configure endpoint: failed (cc %d)\n", __func__, cc);
1020 goto fail;
1021 }
1022 }
1023 free(in);
1024 return &pipe->pipe;
1025
1026 fail:
1027 free(pipe->buf);
1028 free(pipe);
1029 free(in);
1030 return NULL;
1031 }
1032
1033 struct usb_pipe *
xhci_realloc_pipe(struct usbdevice_s * usbdev,struct usb_pipe * upipe,struct usb_endpoint_descriptor * epdesc)1034 xhci_realloc_pipe(struct usbdevice_s *usbdev, struct usb_pipe *upipe
1035 , struct usb_endpoint_descriptor *epdesc)
1036 {
1037 if (!CONFIG_USB_XHCI)
1038 return NULL;
1039 if (!epdesc) {
1040 usb_add_freelist(upipe);
1041 return NULL;
1042 }
1043 if (!upipe)
1044 return xhci_alloc_pipe(usbdev, epdesc);
1045 u8 eptype = epdesc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
1046 int oldmaxpacket = upipe->maxpacket;
1047 usb_desc2pipe(upipe, usbdev, epdesc);
1048 struct xhci_pipe *pipe = container_of(upipe, struct xhci_pipe, pipe);
1049 struct usb_xhci_s *xhci = container_of(
1050 pipe->pipe.cntl, struct usb_xhci_s, usb);
1051 dprintf(3, "%s: usbdev %p, ring %p, slotid %d, epid %d\n", __func__,
1052 usbdev, &pipe->reqs, pipe->slotid, pipe->epid);
1053 if (eptype != USB_ENDPOINT_XFER_CONTROL || upipe->maxpacket == oldmaxpacket)
1054 return upipe;
1055
1056 // maxpacket has changed on control endpoint - update controller.
1057 dprintf(1, "%s: reconf ctl endpoint pkt size: %d -> %d\n",
1058 __func__, oldmaxpacket, pipe->pipe.maxpacket);
1059 struct xhci_inctx *in = xhci_alloc_inctx(usbdev, 1);
1060 if (!in)
1061 return upipe;
1062 in->add = (1 << 1);
1063 struct xhci_epctx *ep = (void*)&in[2 << xhci->context64];
1064 ep->ctx[1] |= (pipe->pipe.maxpacket << 16);
1065 int cc = xhci_cmd_evaluate_context(xhci, pipe->slotid, in);
1066 if (cc != CC_SUCCESS) {
1067 dprintf(1, "%s: reconf ctl endpoint: failed (cc %d)\n",
1068 __func__, cc);
1069 }
1070 free(in);
1071
1072 return upipe;
1073 }
1074
1075 // Submit a USB "setup" message request to the pipe's ring
xhci_xfer_setup(struct xhci_pipe * pipe,int dir,void * cmd,void * data,int datalen)1076 static void xhci_xfer_setup(struct xhci_pipe *pipe, int dir, void *cmd
1077 , void *data, int datalen)
1078 {
1079 struct usb_xhci_s *xhci = container_of(
1080 pipe->pipe.cntl, struct usb_xhci_s, usb);
1081 xhci_trb_queue(&pipe->reqs, cmd, USB_CONTROL_SETUP_SIZE
1082 , (TR_SETUP << 10) | TRB_TR_IDT
1083 | ((datalen ? (dir ? 3 : 2) : 0) << 16));
1084 if (datalen)
1085 xhci_trb_queue(&pipe->reqs, data, datalen, (TR_DATA << 10)
1086 | ((dir ? 1 : 0) << 16));
1087 xhci_trb_queue(&pipe->reqs, NULL, 0, (TR_STATUS << 10) | TRB_TR_IOC
1088 | ((dir ? 0 : 1) << 16));
1089 xhci_doorbell(xhci, pipe->slotid, pipe->epid);
1090 }
1091
1092 // Submit a USB transfer request to the pipe's ring
xhci_xfer_normal(struct xhci_pipe * pipe,void * data,int datalen)1093 static void xhci_xfer_normal(struct xhci_pipe *pipe,
1094 void *data, int datalen)
1095 {
1096 struct usb_xhci_s *xhci = container_of(
1097 pipe->pipe.cntl, struct usb_xhci_s, usb);
1098 xhci_trb_queue(&pipe->reqs, data, datalen, (TR_NORMAL << 10) | TRB_TR_IOC);
1099 xhci_doorbell(xhci, pipe->slotid, pipe->epid);
1100 }
1101
1102 int
xhci_send_pipe(struct usb_pipe * p,int dir,const void * cmd,void * data,int datalen)1103 xhci_send_pipe(struct usb_pipe *p, int dir, const void *cmd
1104 , void *data, int datalen)
1105 {
1106 if (!CONFIG_USB_XHCI)
1107 return -1;
1108 struct xhci_pipe *pipe = container_of(p, struct xhci_pipe, pipe);
1109 struct usb_xhci_s *xhci = container_of(
1110 pipe->pipe.cntl, struct usb_xhci_s, usb);
1111
1112 if (cmd) {
1113 const struct usb_ctrlrequest *req = cmd;
1114 if (req->bRequest == USB_REQ_SET_ADDRESS)
1115 // Set address command sent during xhci_alloc_pipe.
1116 return 0;
1117 xhci_xfer_setup(pipe, dir, (void*)req, data, datalen);
1118 } else {
1119 xhci_xfer_normal(pipe, data, datalen);
1120 }
1121
1122 int cc = xhci_event_wait(xhci, &pipe->reqs, usb_xfer_time(p, datalen));
1123 if (cc != CC_SUCCESS) {
1124 dprintf(1, "%s: xfer failed (cc %d)\n", __func__, cc);
1125 return -1;
1126 }
1127
1128 return 0;
1129 }
1130
1131 int VISIBLE32FLAT
xhci_poll_intr(struct usb_pipe * p,void * data)1132 xhci_poll_intr(struct usb_pipe *p, void *data)
1133 {
1134 if (!CONFIG_USB_XHCI)
1135 return -1;
1136
1137 struct xhci_pipe *pipe = container_of(p, struct xhci_pipe, pipe);
1138 struct usb_xhci_s *xhci = container_of(
1139 pipe->pipe.cntl, struct usb_xhci_s, usb);
1140 u32 len = pipe->pipe.maxpacket;
1141 void *buf = pipe->buf;
1142 int bufused = pipe->bufused;
1143
1144 if (!bufused) {
1145 xhci_xfer_normal(pipe, buf, len);
1146 bufused = 1;
1147 pipe->bufused = bufused;
1148 return -1;
1149 }
1150
1151 xhci_process_events(xhci);
1152 if (xhci_ring_busy(&pipe->reqs))
1153 return -1;
1154 dprintf(5, "%s: st %x ct %x [ %p <= %p / %d ]\n", __func__,
1155 pipe->reqs.evt.status,
1156 pipe->reqs.evt.control,
1157 data, buf, len);
1158 memcpy(data, buf, len);
1159 xhci_xfer_normal(pipe, buf, len);
1160 return 0;
1161 }
1162