1 /* Copyright 2013-2015 IBM Corp.
2 *
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
12 * implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #define pr_fmt(fmt) "FIRENZE-PCI: " fmt
18 #include <skiboot.h>
19 #include <device.h>
20 #include <fsp.h>
21 #include <lock.h>
22 #include <timer.h>
23 #include <xscom.h>
24 #include <pci-cfg.h>
25 #include <pci.h>
26 #include <pci-slot.h>
27 #include <phb3.h>
28 #include <chip.h>
29 #include <i2c.h>
30
31 #include "ibm-fsp.h"
32 #include "lxvpd.h"
33
34 /* Dump PCI slots before sending to FSP */
35 #define FIRENZE_PCI_INVENTORY_DUMP
36
37 /*
38 * Firenze PCI slot states to override the default set.
39 * Refer to pci-slot.h for the default PCI state set
40 * when you're going to change below values.
41 */
42 #define FIRENZE_PCI_SLOT_NORMAL PCI_SLOT_STATE_NORMAL
43 #define FIRENZE_PCI_SLOT_LINK PCI_SLOT_STATE_LINK
44 #define FIRENZE_PCI_SLOT_LINK_START (FIRENZE_PCI_SLOT_LINK + 1)
45 #define FIRENZE_PCI_SLOT_HRESET PCI_SLOT_STATE_HRESET
46 #define FIRENZE_PCI_SLOT_HRESET_START (FIRENZE_PCI_SLOT_HRESET + 1)
47 #define FIRENZE_PCI_SLOT_FRESET PCI_SLOT_STATE_FRESET
48 #define FIRENZE_PCI_SLOT_FRESET_START (FIRENZE_PCI_SLOT_FRESET + 1)
49 #define FIRENZE_PCI_SLOT_FRESET_WAIT_RSP (FIRENZE_PCI_SLOT_FRESET + 2)
50 #define FIRENZE_PCI_SLOT_FRESET_DELAY (FIRENZE_PCI_SLOT_FRESET + 3)
51 #define FIRENZE_PCI_SLOT_FRESET_POWER_STATE (FIRENZE_PCI_SLOT_FRESET + 4)
52 #define FIRENZE_PCI_SLOT_FRESET_POWER_OFF (FIRENZE_PCI_SLOT_FRESET + 5)
53 #define FIRENZE_PCI_SLOT_FRESET_POWER_ON (FIRENZE_PCI_SLOT_FRESET + 6)
54 #define FIRENZE_PCI_SLOT_PERST_DEASSERT (FIRENZE_PCI_SLOT_FRESET + 7)
55 #define FIRENZE_PCI_SLOT_PERST_DELAY (FIRENZE_PCI_SLOT_FRESET + 8)
56 #define FIRENZE_PCI_SLOT_GPOWER PCI_SLOT_STATE_GPOWER
57 #define FIRENZE_PCI_SLOT_GPOWER_START (FIRENZE_PCI_SLOT_GPOWER + 1)
58 #define FIRENZE_PCI_SLOT_SPOWER PCI_SLOT_STATE_SPOWER
59 #define FIRENZE_PCI_SLOT_SPOWER_START (FIRENZE_PCI_SLOT_SPOWER + 1)
60 #define FIRENZE_PCI_SLOT_SPOWER_DONE (FIRENZE_PCI_SLOT_SPOWER + 2)
61
62 /* Timeout for power status */
63 #define FIRENZE_PCI_SLOT_RETRIES 500
64 #define FIRENZE_PCI_SLOT_DELAY 10 /* ms */
65 #define FIRENZE_PCI_I2C_TIMEOUT 500 /* ms */
66
67 /*
68 * Need figure out more stuff later: LED and presence
69 * detection sensors are accessed from PSI/FSP.
70 */
71 struct firenze_pci_slot {
72 struct lxvpd_pci_slot lxvpd_slot; /* LXVPD slot data */
73
74 /* Next slot state */
75 uint32_t next_state;
76
77 /* Power management */
78 struct i2c_bus *i2c_bus; /* Where MAX5961 seats */
79 struct i2c_request *req; /* I2C request message */
80 uint8_t i2c_rw_buf[8]; /* I2C read/write buffer */
81 uint8_t power_mask; /* Bits for power status */
82 uint8_t power_on; /* Bits for power on */
83 uint8_t power_off; /* Bits for power off */
84 uint8_t *power_status; /* Last power status */
85 uint16_t perst_reg; /* PERST config register */
86 uint16_t perst_bit; /* PERST bit */
87 };
88
89 struct firenze_pci_slot_info {
90 uint8_t index;
91 const char *label;
92 uint8_t external_power_mgt;
93 uint8_t inband_perst;
94 uint8_t chip_id;
95 uint8_t master_id;
96 uint8_t port_id;
97 uint8_t slave_addr;
98 uint8_t channel;
99 uint8_t power_status;
100 uint8_t buddy;
101 };
102
103 struct firenze_pci_slot_fixup_info {
104 const char *label;
105 uint8_t reg;
106 uint8_t val;
107 };
108
109 struct firenze_pci_inv {
110 uint32_t hw_proc_id;
111 uint16_t slot_idx;
112 uint16_t reserved;
113 uint16_t vendor_id;
114 uint16_t device_id;
115 uint16_t subsys_vendor_id;
116 uint16_t subsys_device_id;
117 };
118
119 struct firenze_pci_inv_data {
120 uint32_t version; /* currently 1 */
121 uint32_t num_entries;
122 uint32_t entry_size;
123 uint32_t entry_offset;
124 struct firenze_pci_inv entries[];
125 };
126
127 /*
128 * Note: According to Tuleta system workbook, I didn't figure
129 * out the I2C mapping info for slot C14/C15.
130 */
131 static struct firenze_pci_inv_data *firenze_inv_data;
132 static uint32_t firenze_inv_cnt;
133 static struct firenze_pci_slot_info firenze_pci_slots[] = {
134 { 0x0B, "C7", 1, 1, 0, 1, 0, 0x35, 1, 0xAA, 0 },
135 { 0x11, "C14", 0, 1, 0, 0, 0, 0x00, 0, 0xAA, 1 },
136 { 0x0F, "C11", 1, 1, 0, 1, 0, 0x32, 1, 0xAA, 2 },
137 { 0x10, "C12", 1, 1, 0, 1, 0, 0x39, 0, 0xAA, 3 },
138 { 0x0A, "C6", 1, 1, 0, 1, 0, 0x35, 0, 0xAA, 0 },
139 { 0x12, "C15", 0, 1, 0, 0, 0, 0x00, 0, 0xAA, 5 },
140 { 0x01, "USB", 0, 0, 0, 0, 0, 0x00, 0, 0xAA, 6 },
141 { 0x0C, "C8", 1, 1, 0, 1, 0, 0x36, 0, 0xAA, 7 },
142 { 0x0D, "C9", 1, 1, 0, 1, 0, 0x36, 1, 0xAA, 7 },
143 { 0x0E, "C10", 1, 1, 0, 1, 0, 0x32, 0, 0xAA, 2 },
144 { 0x09, "C5", 1, 1, 0x10, 1, 0, 0x39, 1, 0xAA, 10 },
145 { 0x08, "C4", 1, 1, 0x10, 1, 0, 0x39, 0, 0xAA, 10 },
146 { 0x07, "C3", 1, 1, 0x10, 1, 0, 0x3A, 1, 0xAA, 12 },
147 { 0x06, "C2", 1, 1, 0x10, 1, 0, 0x3A, 0, 0xAA, 12 }
148 };
149
150 /*
151 * I2C power controller register fix up table. Not sure what they do, but
152 * they seem to relate to the fast-trip setpoint.
153 */
154 static struct firenze_pci_slot_fixup_info firenze_pci_slot_fixup_tbl[] = {
155 { "C3", 0x5e, 0xfb },
156 { "C3", 0x5b, 0xff },
157 { "C5", 0x5e, 0xfb },
158 { "C5", 0x5b, 0xff },
159 { "C6", 0x5e, 0xfa },
160 { "C6", 0x5a, 0xff },
161 { "C6", 0x5b, 0xff },
162 { "C7", 0x5e, 0xfa },
163 { "C7", 0x5a, 0xff },
164 { "C7", 0x5b, 0xff }
165 };
166
firenze_pci_add_inventory(struct phb * phb,struct pci_device * pd)167 static void firenze_pci_add_inventory(struct phb *phb,
168 struct pci_device *pd)
169 {
170 struct lxvpd_pci_slot *lxvpd_slot;
171 struct firenze_pci_inv *entry;
172 struct proc_chip *chip;
173 size_t size;
174 bool need_init = false;
175
176 /*
177 * Do we need to add that to the FSP inventory for power
178 * management?
179 *
180 * For now, we only add devices that:
181 *
182 * - Are function 0
183 * - Are not an RC or a downstream bridge
184 * - Have a direct parent that has a slot entry
185 * - Slot entry says pluggable
186 * - Aren't an upstream switch that has slot info
187 */
188 if (!pd || !pd->parent)
189 return;
190 if (pd->bdfn & 7)
191 return;
192 if (pd->dev_type == PCIE_TYPE_ROOT_PORT ||
193 pd->dev_type == PCIE_TYPE_SWITCH_DNPORT)
194 return;
195 if (pd->dev_type == PCIE_TYPE_SWITCH_UPPORT &&
196 pd->slot && pd->slot->data)
197 return;
198 if (!pd->parent->slot ||
199 !pd->parent->slot->data)
200 return;
201 lxvpd_slot = pd->parent->slot->data;
202 if (!lxvpd_slot->pluggable)
203 return;
204
205 /* Check if we need to do some (Re)allocation */
206 if (!firenze_inv_data ||
207 firenze_inv_data->num_entries == firenze_inv_cnt) {
208 need_init = !firenze_inv_data;
209
210 /* (Re)allocate the block to the new size */
211 firenze_inv_cnt += 4;
212 size = sizeof(struct firenze_pci_inv_data) +
213 sizeof(struct firenze_pci_inv) * firenze_inv_cnt;
214 firenze_inv_data = realloc(firenze_inv_data, size);
215 }
216
217 /* Initialize the header for a new inventory */
218 if (need_init) {
219 firenze_inv_data->version = 1;
220 firenze_inv_data->num_entries = 0;
221 firenze_inv_data->entry_size =
222 sizeof(struct firenze_pci_inv);
223 firenze_inv_data->entry_offset =
224 offsetof(struct firenze_pci_inv_data, entries);
225 }
226
227 /* Append slot entry */
228 entry = &firenze_inv_data->entries[firenze_inv_data->num_entries++];
229 chip = get_chip(dt_get_chip_id(phb->dt_node));
230 if (!chip) {
231 /**
232 * @fwts-label FirenzePCIInventory
233 * @fwts-advice Device tree didn't contain enough information
234 * to correctly report back PCI inventory. Service processor
235 * is likely to be missing information about what hardware
236 * is physically present in the machine.
237 */
238 prlog(PR_ERR, "No chip device node for PHB%04x\n",
239 phb->opal_id);
240 return;
241 }
242
243 entry->hw_proc_id = chip->pcid;
244 entry->reserved = 0;
245 if (pd->parent &&
246 pd->parent->slot &&
247 pd->parent->slot->data) {
248 lxvpd_slot = pd->parent->slot->data;
249 entry->slot_idx = lxvpd_slot->slot_index;
250 }
251
252 pci_cfg_read16(phb, pd->bdfn, PCI_CFG_VENDOR_ID, &entry->vendor_id);
253 pci_cfg_read16(phb, pd->bdfn, PCI_CFG_DEVICE_ID, &entry->device_id);
254 if (pd->is_bridge) {
255 int64_t ssvc = pci_find_cap(phb, pd->bdfn,
256 PCI_CFG_CAP_ID_SUBSYS_VID);
257 if (ssvc <= 0) {
258 entry->subsys_vendor_id = 0xffff;
259 entry->subsys_device_id = 0xffff;
260 } else {
261 pci_cfg_read16(phb, pd->bdfn,
262 ssvc + PCICAP_SUBSYS_VID_VENDOR,
263 &entry->subsys_vendor_id);
264 pci_cfg_read16(phb, pd->bdfn,
265 ssvc + PCICAP_SUBSYS_VID_DEVICE,
266 &entry->subsys_device_id);
267 }
268 } else {
269 pci_cfg_read16(phb, pd->bdfn, PCI_CFG_SUBSYS_VENDOR_ID,
270 &entry->subsys_vendor_id);
271 pci_cfg_read16(phb, pd->bdfn, PCI_CFG_SUBSYS_ID,
272 &entry->subsys_device_id);
273 }
274 }
275
firenze_dump_pci_inventory(void)276 static void firenze_dump_pci_inventory(void)
277 {
278 #ifdef FIRENZE_PCI_INVENTORY_DUMP
279 struct firenze_pci_inv *e;
280 uint32_t i;
281
282 if (!firenze_inv_data)
283 return;
284
285 prlog(PR_INFO, "Dumping Firenze PCI inventory\n");
286 prlog(PR_INFO, "HWP SLT VDID DVID SVID SDID\n");
287 prlog(PR_INFO, "---------------------------\n");
288 for (i = 0; i < firenze_inv_data->num_entries; i++) {
289 e = &firenze_inv_data->entries[i];
290
291 prlog(PR_INFO, "%03d %03d %04x %04x %04x %04x\n",
292 e->hw_proc_id, e->slot_idx,
293 e->vendor_id, e->device_id,
294 e->subsys_vendor_id, e->subsys_device_id);
295 }
296 #endif /* FIRENZE_PCI_INVENTORY_DUMP */
297 }
298
firenze_pci_send_inventory(void)299 void firenze_pci_send_inventory(void)
300 {
301 uint64_t base, abase, end, aend, offset;
302 int64_t rc;
303
304 if (!firenze_inv_data)
305 return;
306
307 /* Dump the inventory */
308 prlog(PR_INFO, "Sending %d inventory to FSP\n",
309 firenze_inv_data->num_entries);
310 firenze_dump_pci_inventory();
311
312 /* Memory location for inventory */
313 base = (uint64_t)firenze_inv_data;
314 end = base +
315 sizeof(struct firenze_pci_inv_data) +
316 firenze_inv_data->num_entries * firenze_inv_data->entry_size;
317 abase = base & ~0xffful;
318 aend = (end + 0xffful) & ~0xffful;
319 offset = PSI_DMA_PCIE_INVENTORY + (base & 0xfff);
320
321 /* We can only accomodate so many entries in the PSI map */
322 if ((aend - abase) > PSI_DMA_PCIE_INVENTORY_SIZE) {
323 /**
324 * @fwts-label FirenzePCIInventoryTooLarge
325 * @fwts-advice More PCI inventory than we can send to service
326 * processor. The service processor will have an incomplete
327 * view of the world.
328 */
329 prlog(PR_ERR, "Inventory (%lld bytes) too large\n",
330 aend - abase);
331 goto bail;
332 }
333
334 /* Map this in the TCEs */
335 fsp_tce_map(PSI_DMA_PCIE_INVENTORY, (void *)abase, aend - abase);
336
337 /* Send FSP message */
338 rc = fsp_sync_msg(fsp_mkmsg(FSP_CMD_PCI_POWER_CONF, 3,
339 hi32(offset), lo32(offset),
340 end - base), true);
341 if (rc)
342 {
343 /**
344 * @fwts-label FirenzePCIInventoryError
345 * @fwts-advice Error communicating with service processor
346 * when sending PCI Inventory.
347 */
348 prlog(PR_ERR, "Error %lld sending inventory\n", rc);
349 }
350
351 /* Unmap */
352 fsp_tce_unmap(PSI_DMA_PCIE_INVENTORY, aend - abase);
353 bail:
354 /*
355 * We free the inventory. We'll have to redo that on hotplug
356 * when we support it but that isn't the case yet
357 */
358 free(firenze_inv_data);
359 firenze_inv_data = NULL;
360 firenze_inv_cnt = 0;
361 }
362
363 /* The function is called when the I2C request is completed
364 * successfully, or with errors.
365 */
firenze_i2c_req_done(int rc,struct i2c_request * req)366 static void firenze_i2c_req_done(int rc, struct i2c_request *req)
367 {
368 struct pci_slot *slot = req->user_data;
369 uint32_t state;
370
371 /* Check if there are errors for the completion */
372 if (rc) {
373 /**
374 * @fwts-label FirenzePCII2CError
375 * @fwts-advice On Firenze platforms, I2C is used to control
376 * power to PCI slots. Errors here mean we may be in trouble
377 * in regards to PCI slot power on/off.
378 */
379 prlog(PR_ERR, "Error %d from I2C request on slot %016llx\n",
380 rc, slot->id);
381 return;
382 }
383
384 /* Check the request type */
385 if (req->op != SMBUS_READ && req->op != SMBUS_WRITE) {
386 /**
387 * @fwts-label FirenzePCII2CInvalid
388 * @fwts-advice Likely a coding error: invalid I2C request.
389 */
390 prlog(PR_ERR, "Invalid I2C request %d on slot %016llx\n",
391 req->op, slot->id);
392 return;
393 }
394
395 /* After writting power status to I2C slave, we need at least
396 * 5ms delay for the slave to settle down. We also have the
397 * delay after reading the power status as well.
398 */
399 switch (slot->state) {
400 case FIRENZE_PCI_SLOT_FRESET_WAIT_RSP:
401 prlog(PR_DEBUG, "%016llx FRESET: I2C request completed\n",
402 slot->id);
403 state = FIRENZE_PCI_SLOT_FRESET_DELAY;
404 break;
405 case FIRENZE_PCI_SLOT_SPOWER_START:
406 prlog(PR_DEBUG, "%016llx SPOWER: I2C request completed\n",
407 slot->id);
408 state = FIRENZE_PCI_SLOT_SPOWER_DONE;
409 break;
410 default:
411 /**
412 * @fwts-label FirenzePCISlotI2CStateError
413 * @fwts-advice The Firenze platform uses I2C to control
414 * power to PCI slots. Something went wrong in the state
415 * machine controlling that. Slots may/may not have power.
416 */
417 prlog(PR_ERR, "Wrong state %08x on slot %016llx\n",
418 slot->state, slot->id);
419 return;
420 }
421
422 /* Switch to net state */
423 pci_slot_set_state(slot, state);
424 }
425
426 /* This function is called to setup normal PCI device or PHB slot.
427 * For the later case, the slot doesn't have the associated PCI
428 * device. Besides, the I2C response timeout is set to 5s. We might
429 * improve I2C in future to support priorized requests so that the
430 * timeout can be shortened.
431 */
firenze_pci_slot_freset(struct pci_slot * slot)432 static int64_t firenze_pci_slot_freset(struct pci_slot *slot)
433 {
434 struct firenze_pci_slot *plat_slot = slot->data;
435 uint8_t *pval, presence = 1;
436 uint32_t timeout;
437
438 switch (slot->state) {
439 case FIRENZE_PCI_SLOT_NORMAL:
440 case FIRENZE_PCI_SLOT_FRESET_START:
441 prlog(PR_DEBUG, "%016llx FRESET: Starts\n",
442 slot->id);
443
444 /* Bail if nothing is connected */
445 if (slot->ops.get_presence_state)
446 slot->ops.get_presence_state(slot, &presence);
447 if (!presence) {
448 prlog(PR_DEBUG, "%016llx FRESET: No device\n",
449 slot->id);
450 return OPAL_SUCCESS;
451 }
452
453 /* Prepare link down */
454 if (slot->ops.prepare_link_change) {
455 prlog(PR_DEBUG, "%016llx FRESET: Prepares link down\n",
456 slot->id);
457 slot->ops.prepare_link_change(slot, false);
458 }
459
460 /* Send I2C request */
461 prlog(PR_DEBUG, "%016llx FRESET: Check power state\n",
462 slot->id);
463 plat_slot->next_state =
464 FIRENZE_PCI_SLOT_FRESET_POWER_STATE;
465 plat_slot->req->op = SMBUS_READ;
466 slot->retries = FIRENZE_PCI_SLOT_RETRIES;
467 pci_slot_set_state(slot,
468 FIRENZE_PCI_SLOT_FRESET_WAIT_RSP);
469 if (pci_slot_has_flags(slot, PCI_SLOT_FLAG_BOOTUP))
470 plat_slot->req->timeout = FIRENZE_PCI_I2C_TIMEOUT;
471 else
472 plat_slot->req->timeout = 0ul;
473 i2c_queue_req(plat_slot->req);
474 return pci_slot_set_sm_timeout(slot,
475 msecs_to_tb(FIRENZE_PCI_SLOT_DELAY));
476 case FIRENZE_PCI_SLOT_FRESET_WAIT_RSP:
477 if (slot->retries-- == 0) {
478 prlog(PR_DEBUG, "%016llx FRESET: Timeout waiting for %08x\n",
479 slot->id, plat_slot->next_state);
480 goto out;
481 }
482
483 check_timers(false);
484 return pci_slot_set_sm_timeout(slot,
485 msecs_to_tb(FIRENZE_PCI_SLOT_DELAY));
486 case FIRENZE_PCI_SLOT_FRESET_DELAY:
487 prlog(PR_DEBUG, "%016llx FRESET: Delay %dms on I2C completion\n",
488 slot->id, FIRENZE_PCI_SLOT_DELAY);
489 pci_slot_set_state(slot, plat_slot->next_state);
490 return pci_slot_set_sm_timeout(slot,
491 msecs_to_tb(FIRENZE_PCI_SLOT_DELAY));
492 case FIRENZE_PCI_SLOT_FRESET_POWER_STATE:
493 /* Update last power status */
494 pval = (uint8_t *)(plat_slot->req->rw_buf);
495 *plat_slot->power_status = *pval;
496
497 /* Power is on, turn it off */
498 if (((*pval) & plat_slot->power_mask) == plat_slot->power_on) {
499 prlog(PR_DEBUG, "%016llx FRESET: Power (%02x) on, turn off\n",
500 slot->id, *pval);
501 (*pval) &= ~plat_slot->power_mask;
502 (*pval) |= plat_slot->power_off;
503 plat_slot->req->op = SMBUS_WRITE;
504 slot->retries = FIRENZE_PCI_SLOT_RETRIES;
505 plat_slot->next_state =
506 FIRENZE_PCI_SLOT_FRESET_POWER_OFF;
507 pci_slot_set_state(slot,
508 FIRENZE_PCI_SLOT_FRESET_WAIT_RSP);
509
510 if (pci_slot_has_flags(slot, PCI_SLOT_FLAG_BOOTUP))
511 timeout = FIRENZE_PCI_I2C_TIMEOUT;
512 else
513 timeout = 0ul;
514 plat_slot->req->timeout = timeout;
515
516 i2c_queue_req(plat_slot->req);
517 return pci_slot_set_sm_timeout(slot,
518 msecs_to_tb(FIRENZE_PCI_SLOT_DELAY));
519 }
520
521 /* Power is off, turn it on */
522 /* Fallthrough */
523 case FIRENZE_PCI_SLOT_FRESET_POWER_OFF:
524 /* Update last power status */
525 pval = (uint8_t *)(plat_slot->req->rw_buf);
526 *plat_slot->power_status = *pval;
527
528 prlog(PR_DEBUG, "%016llx FRESET: Power (%02x) off, turn on\n",
529 slot->id, *pval);
530 (*pval) &= ~plat_slot->power_mask;
531 (*pval) |= plat_slot->power_on;
532 plat_slot->req->op = SMBUS_WRITE;
533 plat_slot->next_state =
534 FIRENZE_PCI_SLOT_FRESET_POWER_ON;
535 slot->retries = FIRENZE_PCI_SLOT_RETRIES;
536 pci_slot_set_state(slot,
537 FIRENZE_PCI_SLOT_FRESET_WAIT_RSP);
538
539 if (pci_slot_has_flags(slot, PCI_SLOT_FLAG_BOOTUP))
540 plat_slot->req->timeout = FIRENZE_PCI_I2C_TIMEOUT;
541 else
542 plat_slot->req->timeout = 0ul;
543 i2c_queue_req(plat_slot->req);
544 return pci_slot_set_sm_timeout(slot,
545 msecs_to_tb(FIRENZE_PCI_SLOT_DELAY));
546 case FIRENZE_PCI_SLOT_FRESET_POWER_ON:
547 /* Update last power status */
548 pval = (uint8_t *)(plat_slot->req->rw_buf);
549 *plat_slot->power_status = *pval;
550
551 pci_slot_set_state(slot, FIRENZE_PCI_SLOT_LINK_START);
552 return slot->ops.poll_link(slot);
553 default:
554 prlog(PR_DEBUG, "%016llx FRESET: Unexpected state %08x\n",
555 slot->id, slot->state);
556 }
557
558 out:
559 pci_slot_set_state(slot, FIRENZE_PCI_SLOT_NORMAL);
560 return OPAL_HARDWARE;
561 }
562
firenze_pci_slot_perst(struct pci_slot * slot)563 static int64_t firenze_pci_slot_perst(struct pci_slot *slot)
564 {
565 struct firenze_pci_slot *plat_slot = slot->data;
566 uint8_t presence = 1;
567 uint16_t ctrl;
568
569 switch (slot->state) {
570 case FIRENZE_PCI_SLOT_NORMAL:
571 case FIRENZE_PCI_SLOT_FRESET_START:
572 prlog(PR_DEBUG, "%016llx PERST: Starts\n",
573 slot->id);
574
575 /* Bail if nothing is connected */
576 if (slot->ops.get_presence_state)
577 slot->ops.get_presence_state(slot, &presence);
578 if (!presence) {
579 prlog(PR_DEBUG, "%016llx PERST: No device\n",
580 slot->id);
581 return OPAL_SUCCESS;
582 }
583
584 /* Prepare link down */
585 if (slot->ops.prepare_link_change) {
586 prlog(PR_DEBUG, "%016llx PERST: Prepare link down\n",
587 slot->id);
588 slot->ops.prepare_link_change(slot, false);
589 }
590
591 /* Assert PERST */
592 prlog(PR_DEBUG, "%016llx PERST: Assert\n",
593 slot->id);
594 pci_cfg_read16(slot->phb, slot->pd->bdfn,
595 plat_slot->perst_reg, &ctrl);
596 ctrl |= plat_slot->perst_bit;
597 pci_cfg_write16(slot->phb, slot->pd->bdfn,
598 plat_slot->perst_reg, ctrl);
599 pci_slot_set_state(slot,
600 FIRENZE_PCI_SLOT_PERST_DEASSERT);
601 return pci_slot_set_sm_timeout(slot, msecs_to_tb(250));
602 case FIRENZE_PCI_SLOT_PERST_DEASSERT:
603 /* Deassert PERST */
604 pci_cfg_read16(slot->phb, slot->pd->bdfn,
605 plat_slot->perst_reg, &ctrl);
606 ctrl &= ~plat_slot->perst_bit;
607 pci_cfg_write16(slot->phb, slot->pd->bdfn,
608 plat_slot->perst_reg, ctrl);
609 pci_slot_set_state(slot,
610 FIRENZE_PCI_SLOT_PERST_DELAY);
611 return pci_slot_set_sm_timeout(slot, msecs_to_tb(1500));
612 case FIRENZE_PCI_SLOT_PERST_DELAY:
613 pci_slot_set_state(slot, FIRENZE_PCI_SLOT_LINK_START);
614 return slot->ops.poll_link(slot);
615 default:
616 prlog(PR_DEBUG, "%016llx PERST: Unexpected state %08x\n",
617 slot->id, slot->state);
618 }
619
620 pci_slot_set_state(slot, FIRENZE_PCI_SLOT_NORMAL);
621 return OPAL_HARDWARE;
622 }
623
firenze_pci_slot_get_power_state(struct pci_slot * slot,uint8_t * val)624 static int64_t firenze_pci_slot_get_power_state(struct pci_slot *slot,
625 uint8_t *val)
626 {
627 if (slot->state != FIRENZE_PCI_SLOT_NORMAL)
628 {
629 /**
630 * @fwts-label FirenzePCISlotGPowerState
631 * @fwts-advice Unexpected state in the FIRENZE PCI Slot
632 * state machine. This could mean PCI is not functioning
633 * correctly.
634 */
635 prlog(PR_ERR, "%016llx GPOWER: Unexpected state %08x\n",
636 slot->id, slot->state);
637 }
638
639 *val = slot->power_state;
640 return OPAL_SUCCESS;
641 }
642
firenze_pci_slot_set_power_state(struct pci_slot * slot,uint8_t val)643 static int64_t firenze_pci_slot_set_power_state(struct pci_slot *slot,
644 uint8_t val)
645 {
646 struct firenze_pci_slot *plat_slot = slot->data;
647 uint8_t *pval;
648
649 if (slot->state != FIRENZE_PCI_SLOT_NORMAL)
650 {
651 /**
652 * @fwts-label FirenzePCISlotSPowerState
653 * @fwts-advice Unexpected state in the FIRENZE PCI Slot
654 * state machine. This could mean PCI is not functioning
655 * correctly.
656 */
657 prlog(PR_ERR, "%016llx SPOWER: Unexpected state %08x\n",
658 slot->id, slot->state);
659 }
660
661 if (val != PCI_SLOT_POWER_OFF && val != PCI_SLOT_POWER_ON)
662 return OPAL_PARAMETER;
663
664 if (!pci_slot_has_flags(slot, PCI_SLOT_FLAG_ENFORCE) &&
665 slot->power_state == val)
666 return OPAL_SUCCESS;
667
668 /* Update with the requested power state and bail immediately when
669 * surprise hotplug is supported on the slot. It keeps the power
670 * supply to the slot on and it guarentees the link state change
671 * events will be raised properly during surprise hot add/remove.
672 */
673 if (!pci_slot_has_flags(slot, PCI_SLOT_FLAG_ENFORCE) &&
674 slot->surprise_pluggable) {
675 slot->power_state = val;
676 return OPAL_SUCCESS;
677 }
678
679 slot->power_state = val;
680 pci_slot_set_state(slot, FIRENZE_PCI_SLOT_SPOWER_START);
681
682 plat_slot->req->op = SMBUS_WRITE;
683 pval = (uint8_t *)plat_slot->req->rw_buf;
684 if (val == PCI_SLOT_POWER_ON) {
685 *pval = *plat_slot->power_status;
686 (*pval) &= ~plat_slot->power_mask;
687 (*pval) |= plat_slot->power_on;
688 } else {
689 *pval = *plat_slot->power_status;
690 (*pval) &= ~plat_slot->power_mask;
691 (*pval) |= plat_slot->power_off;
692 }
693
694 if (pci_slot_has_flags(slot, PCI_SLOT_FLAG_BOOTUP))
695 plat_slot->req->timeout = FIRENZE_PCI_I2C_TIMEOUT;
696 else
697 plat_slot->req->timeout = 0ul;
698 i2c_queue_req(plat_slot->req);
699
700 return OPAL_ASYNC_COMPLETION;
701 }
702
firenze_pci_find_i2c_bus(uint8_t chip,uint8_t eng,uint8_t port)703 static struct i2c_bus *firenze_pci_find_i2c_bus(uint8_t chip,
704 uint8_t eng,
705 uint8_t port)
706 {
707 struct dt_node *np, *child;
708 uint32_t reg;
709
710 /* Iterate I2C masters */
711 dt_for_each_compatible(dt_root, np, "ibm,power8-i2cm") {
712 if (!np->parent ||
713 !dt_node_is_compatible(np->parent, "ibm,power8-xscom"))
714 continue;
715
716 /* Check chip index */
717 reg = dt_prop_get_u32(np->parent, "ibm,chip-id");
718 if (reg != chip)
719 continue;
720
721 /* Check I2C master index */
722 reg = dt_prop_get_u32(np, "chip-engine#");
723 if (reg != eng)
724 continue;
725
726 /* Iterate I2C buses */
727 dt_for_each_child(np, child) {
728 if (!dt_node_is_compatible(child, "ibm,power8-i2c-port"))
729 continue;
730
731 /* Check I2C port index */
732 reg = dt_prop_get_u32(child, "reg");
733 if (reg != port)
734 continue;
735
736 reg = dt_prop_get_u32(child, "ibm,opal-id");
737 return i2c_find_bus_by_id(reg);
738 }
739 }
740
741 return NULL;
742 }
743
firenze_pci_slot_fixup_one_reg(struct pci_slot * slot,struct firenze_pci_slot_fixup_info * fixup)744 static int64_t firenze_pci_slot_fixup_one_reg(struct pci_slot *slot,
745 struct firenze_pci_slot_fixup_info *fixup)
746 {
747 struct firenze_pci_slot *plat_slot = slot->data;
748 struct i2c_request req;
749 uint8_t buf;
750 int64_t rc;
751
752 /*
753 * Fill out our own request structure since we don't want to invoke the
754 * normal completion handler.
755 */
756 memset(&req, 0, sizeof(req));
757 req.dev_addr = plat_slot->req->dev_addr;
758 req.bus = plat_slot->req->bus;
759 req.offset = fixup->reg;
760 req.offset_bytes = 1;
761 req.rw_buf = &buf;
762 req.rw_len = 1;
763 req.timeout = FIRENZE_PCI_I2C_TIMEOUT;
764
765 req.op = SMBUS_WRITE;
766 buf = fixup->val;
767 rc = i2c_request_sync(&req);
768 if (rc < 0)
769 return rc;
770
771 /*
772 * Check the register fixup has been applied. It's not the end of the
773 * world we don't, but eh...
774 */
775 req.op = SMBUS_READ;
776 rc = i2c_request_sync(&req);
777 if (rc == OPAL_SUCCESS && buf != fixup->val) {
778 prlog(PR_ERR, "Error verifying fixup [%s] - (%02x, %02x, %02x)\n",
779 fixup->label, fixup->reg, fixup->val, buf);
780 }
781
782 return rc;
783 }
784
firenze_pci_slot_fixup(struct pci_slot * slot,struct firenze_pci_slot_info * info)785 static void firenze_pci_slot_fixup(struct pci_slot *slot,
786 struct firenze_pci_slot_info *info)
787 {
788 int64_t rc, i, applied = 0;
789 const uint32_t *p;
790 uint64_t id;
791
792 p = dt_prop_get_def(dt_root, "ibm,vpd-lx-info", NULL);
793 id = p ? (((uint64_t)p[1] << 32) | p[2]) : 0ul;
794 if (id != LX_VPD_2S4U_BACKPLANE &&
795 id != LX_VPD_1S4U_BACKPLANE)
796 return;
797
798 for (i = 0; i < ARRAY_SIZE(firenze_pci_slot_fixup_tbl); i++) {
799 struct firenze_pci_slot_fixup_info *fixup =
800 &firenze_pci_slot_fixup_tbl[i];
801
802 if (strcmp(info->label, fixup->label))
803 continue;
804
805 rc = firenze_pci_slot_fixup_one_reg(slot, fixup);
806 if (rc) {
807 prlog(PR_ERR, "I2C error (%lld) applying fixup [%s] - (%02x, %02x)\n",
808 rc, fixup->label, fixup->reg, fixup->val);
809 return;
810 }
811
812 applied++;
813 }
814
815 if (applied)
816 prlog(PR_INFO, "Applied %lld fixups for [%s]\n",
817 applied, info->label);
818 }
819
firenze_pci_setup_power_mgt(struct pci_slot * slot,struct firenze_pci_slot * plat_slot,struct firenze_pci_slot_info * info)820 static void firenze_pci_setup_power_mgt(struct pci_slot *slot,
821 struct firenze_pci_slot *plat_slot,
822 struct firenze_pci_slot_info *info)
823 {
824 plat_slot->i2c_bus = firenze_pci_find_i2c_bus(info->chip_id,
825 info->master_id,
826 info->port_id);
827 if (!plat_slot->i2c_bus)
828 return;
829
830 plat_slot->req = zalloc(sizeof(*plat_slot->req));
831 if (!plat_slot->req)
832 return;
833
834 plat_slot->req->dev_addr = info->slave_addr;
835 plat_slot->req->offset_bytes = 1;
836 plat_slot->req->rw_buf = plat_slot->i2c_rw_buf;
837 plat_slot->req->rw_len = 1;
838 plat_slot->req->completion = firenze_i2c_req_done;
839 plat_slot->req->user_data = slot;
840 plat_slot->req->bus = plat_slot->i2c_bus;
841
842 firenze_pci_slot_fixup(slot, info);
843
844 /*
845 * For all slots, the register used to change the power state is
846 * always 0x69. It could have been set to something else in the
847 * above fixup. Lets fix it to 0x69 here.
848 *
849 * The power states of two slots are controlled by one register.
850 * This means two slots have to share data buffer for power states,
851 * which are tracked by struct firenze_pci_slot_info::power_status.
852 * With it, we can avoid affecting slot#B's power state when trying
853 * to adjust that on slot#A. Also, the initial power states for all
854 * slots are assumed to be PCI_SLOT_POWER_ON.
855 */
856 plat_slot->req->offset = 0x69;
857 plat_slot->power_status = &firenze_pci_slots[info->buddy].power_status;
858 switch (info->channel) {
859 case 0:
860 plat_slot->power_mask = 0x33;
861 plat_slot->power_on = 0x22;
862 plat_slot->power_off = 0;
863 break;
864 case 1:
865 plat_slot->power_status = &firenze_pci_slots[info->buddy].power_status;
866 plat_slot->power_mask = 0xcc;
867 plat_slot->power_on = 0x88;
868 plat_slot->power_off = 0;
869 break;
870 default:
871 prlog(PR_ERR, "%016llx: Invalid channel %d\n",
872 slot->id, info->channel);
873 }
874 }
875
firenze_pci_slot_init(struct pci_slot * slot)876 static void firenze_pci_slot_init(struct pci_slot *slot)
877 {
878 struct lxvpd_pci_slot *s = slot->data;
879 struct firenze_pci_slot *plat_slot = slot->data;
880 struct firenze_pci_slot_info *info = NULL;
881 uint32_t vdid;
882 int i;
883
884 /* Init the slot info from the LXVPD */
885 slot->ops.add_properties = lxvpd_add_slot_properties;
886
887 /* Search for power control information in the per-system table */
888 for (i = 0; i < ARRAY_SIZE(firenze_pci_slots); i++) {
889 if (firenze_pci_slots[i].index == s->slot_index &&
890 !strcmp(firenze_pci_slots[i].label, s->label)) {
891 info = &firenze_pci_slots[i];
892 break;
893 }
894 }
895 if (!info)
896 return;
897
898 /* Search I2C bus for external power mgt */
899 if (slot->power_ctl)
900 firenze_pci_setup_power_mgt(slot, plat_slot, info);
901
902 /*
903 * If the slot has external power logic, to override the
904 * default power management methods. Because of the bad
905 * I2C design, the API supplied by I2C is really hard to
906 * be utilized. To figure out power status retrival or
907 * configuration after we have a blocking API for that.
908 */
909 if (plat_slot->req) {
910 slot->ops.freset = firenze_pci_slot_freset;
911 slot->ops.get_power_state = firenze_pci_slot_get_power_state;
912 slot->ops.set_power_state = firenze_pci_slot_set_power_state;
913 prlog(PR_DEBUG, "%016llx: External power mgt initialized\n",
914 slot->id);
915 } else if (info->inband_perst) {
916 /*
917 * For PLX downstream ports, PCI config register can be
918 * leveraged to do PERST. If the slot doesn't have external
919 * power management stuff, lets try to stick to the PERST
920 * logic if applicable
921 */
922 if (slot->pd->dev_type == PCIE_TYPE_SWITCH_DNPORT) {
923 pci_cfg_read32(slot->phb, slot->pd->bdfn,
924 PCI_CFG_VENDOR_ID, &vdid);
925 switch (vdid) {
926 case 0x873210b5: /* PLX8732 */
927 case 0x874810b5: /* PLX8748 */
928 plat_slot->perst_reg = 0x80;
929 plat_slot->perst_bit = 0x0400;
930 slot->ops.freset = firenze_pci_slot_perst;
931 break;
932 }
933 }
934 }
935 }
936
firenze_pci_setup_phb(struct phb * phb,unsigned int index)937 void firenze_pci_setup_phb(struct phb *phb, unsigned int index)
938 {
939 uint32_t hub_id;
940
941 /* Grab Hub ID used to parse VPDs */
942 hub_id = dt_prop_get_u32_def(phb->dt_node, "ibm,hub-id", 0);
943
944 /* Process the pcie slot entries from the lx vpd lid */
945 lxvpd_process_slot_entries(phb, dt_root, hub_id,
946 index, sizeof(struct firenze_pci_slot));
947 }
948
firenze_pci_get_slot_info(struct phb * phb,struct pci_device * pd)949 void firenze_pci_get_slot_info(struct phb *phb, struct pci_device *pd)
950 {
951 struct pci_slot *slot;
952 struct lxvpd_pci_slot *s;
953
954 /* Prepare the PCI inventory */
955 firenze_pci_add_inventory(phb, pd);
956
957 if (pd->dev_type != PCIE_TYPE_ROOT_PORT &&
958 pd->dev_type != PCIE_TYPE_SWITCH_UPPORT &&
959 pd->dev_type != PCIE_TYPE_SWITCH_DNPORT &&
960 pd->dev_type != PCIE_TYPE_PCIE_TO_PCIX)
961 return;
962
963 /* Create PCIe slot */
964 slot = pcie_slot_create(phb, pd);
965 if (!slot)
966 return;
967
968 /* Root complex inherits methods from PHB slot */
969 if (!pd->parent && phb->slot)
970 memcpy(&slot->ops, &phb->slot->ops, sizeof(struct pci_slot_ops));
971
972 /* Patch PCIe slot */
973 s = lxvpd_get_slot(slot);
974 if (s) {
975 lxvpd_extract_info(slot, s);
976 firenze_pci_slot_init(slot);
977 }
978 }
979