1Freescale MPC7448hpc2 (Taiga) board 2=================================== 3 4Created 08/11/2006 Roy Zang 5-------------------------- 6MPC7448hpc2 (Taiga) board is a high-performance PowerPC server reference 7design, which is optimized for high speed throughput between the processor and 8the memory, disk drive and Ethernet port subsystems. 9 10MPC7448hpc2(Taiga) is designed to the micro-ATX chassis, allowing it to be 11used in 1U or 2U rack-mount chassis��, as well as in standard ATX/Micro-ATX 12chassis. 13 14Building U-Boot 15------------------ 16The mpc7448hpc2 code base is known to compile using: 17 Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3 18 19 $ make mpc7448hpc2_config 20 Configuring for mpc7448hpc2 board... 21 22 $ make 23 24Memory Map 25---------- 26 27The memory map is setup for Linux to operate properly. 28 29The mapping is: 30 31 Range Start Range End Definition Size 32 33 0x0000_0000 0x7fff_ffff DDR 2G 34 0xe000_0000 0xe7ff_ffff PCI Memory 128M 35 0xfa00_0000 0xfaff_ffff PCI IO 16M 36 0xfb00_0000 0xfbff_ffff PCI Config 16M 37 0xfc00_0000 0xfc0f_ffff NVRAM/CADMUS 1M 38 0xfe00_0000 0xfeff_ffff PromJet 16M 39 0xff00_0000 0xff80_0000 FLASH (boot flash) 8M 40 0xff80_0000 0xffff_ffff FLASH (second half flash) 8M 41 42Using Flash 43----------- 44 45The MPC7448hpc2 board has two "banks" of flash, each 8MB in size 46(2^23 = 0x00800000). 47 48Note: the "bank" here refers to half of the flash. In fact, there is only one 49bank of flash, which is divided into low and high half. Each is controlled by 50the most significant bit of the address bus. The so called "bank" is only for 51convenience. 52 53There is a switch which allows the "bank" to be selected. The switch 54settings for updating flash are given below. 55 56The u-boot commands for copying the boot-bank into the secondary bank are 57as follows: 58 59 erase ff800000 ff880000 60 cp.b ff000000 ff800000 80000 61 62U-boot commands for downloading an image via tftp and flashing 63it into the secondary bank: 64 65 tftp 10000 <u-boot.bin.image> 66 erase ff000000 ff080000 67 cp.b 10000 ff000000 80000 68 69After copying the image into the second bank of flash, be sure to toggle 70SW3[4] on board before resetting the board in order to set the 71secondary bank as the boot-bank. 72 73Board Switches 74---------------------- 75 76Most switches on the board should not be changed. The most frequent 77user-settable switches on the board are used to configure 78the flash banks and determining the PCI frequency. 79 80SW1[1-5]: Processor core voltage 81 82 12345 Core Voltage 83 ----- 84 SW1=01111 1.000V. 85 SW1=01101 1.100V. 86 SW1=01011 1.200V. 87 SW1=01001 1.300V only for MPC7447A. 88 89 90SW2[1-6]: CPU core frequency 91 92 CPU Core Frequency (MHz) 93 Bus Frequency 94 123456 100 133 167 200 Ratio 95 96 ------ 97 SW2=101100 500 667 833 1000 5x 98 SW2=100100 550 733 917 1100 5.5x 99 SW2=110100 600 800 1000 1200 6x 100 SW2=010100 650 866 1083 1300 6.5x 101 SW2=001000 700 930 1167 1400 7x 102 SW2=000100 750 1000 1250 1500 7.5x 103 SW2=110000 800 1066 1333 1600 8x 104 SW2=011000 850 1333 1417 1700 8.5x only for MPC7447A 105 SW2=011110 900 1200 1500 1800 9x 106 107This table shows only a subset of available frequency options; see the CPU 108hardware specifications for more information. 109 110SW2[7-8]: Bus Protocol and CPU Reset Option 111 112 7 113 - 114 SW2=0 System bus uses MPX bus protocol 115 SW2=1 System bus uses 60x bus protocol 116 117 8 118 - 119 SW2=0 TSI108 can cause CPU reset 120 SW2=1 TSI108 can not cause CPU reset 121 122SW3[1-8] system options 123 124 123 125 --- 126 SW3=xxx Connected to GPIO[0:2] on TSI108 127 128 4 129 - 130 SW3=0 CPU boots from low half of flash 131 SW3=1 CPU boots from high half of flash 132 133 5 134 - 135 SW3=0 SATA and slot2 connected to PCI bus 136 SW3=1 Only slot1 connected to PCI bus 137 138 6 139 - 140 SW3=0 USB connected to PCI bus 141 SW3=1 USB disconnected from PCI bus 142 143 7 144 - 145 SW3=0 Flash is write protected 146 SW3=1 Flash is NOT write protected 147 148 8 149 - 150 SW3=0 CPU will boot from flash 151 SW3=1 CPU will boot from PromJet 152 153SW4[1-3]: System bus frequency 154 155 Bus Frequency (MHz) 156 --- 157 SW4=010 183 158 SW4=011 100 159 SW4=100 133 160 SW4=101 166 only for MPC7447A 161 SW4=110 200 only for MPC7448 162 others reserved 163 164SW4[4-6]: DDR2 SDRAM frequency 165 166 Bus Frequency (MHz) 167 --- 168 SW4=000 external clock 169 SW4=011 system clock 170 SW4=100 133 171 SW4=101 166 172 SW4=110 200 173 others reserved 174 175SW4[7-8]: PCI/PCI-X frequency control 176 7 177 - 178 SW4=0 PCI/PCI-X bus operates normally 179 SW4=1 PCI bus forced to PCI-33 mode 180 181 8 182 - 183 SW4=0 PCI-X mode at 133 MHz allowed 184 SW4=1 PCI-X mode limited to 100 MHz 185