1 /*
2 * arch/powerpc/kernel/pci_auto.c
3 *
4 * PCI autoconfiguration library
5 *
6 * Author: Matt Porter <mporter@mvista.com>
7 *
8 * Copyright 2000 MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16 #include <common.h>
17
18 #include <pci.h>
19
20 #define DEBUG
21 #ifdef DEBUG
22 #define DEBUGF(x...) printf(x)
23 #else
24 #define DEBUGF(x...)
25 #endif /* DEBUG */
26
27 #define PCIAUTO_IDE_MODE_MASK 0x05
28
29 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
30 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
31 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
32 #endif
33
34 /*
35 *
36 */
37
pciauto_region_init(struct pci_region * res)38 void pciauto_region_init(struct pci_region* res)
39 {
40 /*
41 * Avoid allocating PCI resources from address 0 -- this is illegal
42 * according to PCI 2.1 and moreover, this is known to cause Linux IDE
43 * drivers to fail. Use a reasonable starting value of 0x1000 instead.
44 */
45 res->bus_lower = res->bus_start ? res->bus_start : 0x1000;
46 }
47
pciauto_region_align(struct pci_region * res,pci_size_t size)48 void pciauto_region_align(struct pci_region *res, pci_size_t size)
49 {
50 res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
51 }
52
pciauto_region_allocate(struct pci_region * res,pci_size_t size,pci_addr_t * bar)53 int pciauto_region_allocate(struct pci_region* res, pci_size_t size, pci_addr_t *bar)
54 {
55 pci_addr_t addr;
56
57 if (!res) {
58 DEBUGF("No resource");
59 goto error;
60 }
61
62 addr = ((res->bus_lower - 1) | (size - 1)) + 1;
63
64 if (addr - res->bus_start + size > res->size) {
65 DEBUGF("No room in resource");
66 goto error;
67 }
68
69 res->bus_lower = addr + size;
70
71 DEBUGF("address=0x%llx bus_lower=0x%llx", (u64)addr, (u64)res->bus_lower);
72
73 *bar = addr;
74 return 0;
75
76 error:
77 *bar = (pci_addr_t)-1;
78 return -1;
79 }
80
81 /*
82 *
83 */
84
85 #ifdef CONFIG_SAM460EX
pciauto_setup_device_io(struct pci_controller * hose,pci_dev_t dev,int bars_num,struct pci_region * mem,struct pci_region * prefetch,struct pci_region * io)86 void pciauto_setup_device_io(struct pci_controller *hose,
87 pci_dev_t dev, int bars_num,
88 struct pci_region *mem,
89 struct pci_region *prefetch,
90 struct pci_region *io)
91 {
92 unsigned int bar_response;
93 pci_addr_t bar_value;
94 pci_size_t bar_size;
95 unsigned int cmdstat = 0;
96 struct pci_region *bar_res;
97 int bar, bar_nr = 0;
98
99 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
100 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
101
102 for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) {
103 /* Tickle the BAR and get the response */
104 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
105 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
106
107 /* If BAR is not implemented go to the next BAR */
108 if (!bar_response)
109 continue;
110
111 /* Check the BAR type and set our address mask */
112 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
113 bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
114 & 0xffff) + 1;
115 bar_res = io;
116
117 DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", bar_nr, (u64)bar_size);
118
119 if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
120 /* Write it out and update our limit */
121 pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
122
123 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
124 PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
125 }
126 }
127 DEBUGF("\n");
128
129 bar_nr++;
130 }
131
132 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
133 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
134 CONFIG_SYS_PCI_CACHE_LINE_SIZE);
135 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
136 }
137
pciauto_setup_device_mem(struct pci_controller * hose,pci_dev_t dev,int bars_num,struct pci_region * mem,struct pci_region * prefetch,struct pci_region * io,pci_size_t bar_size_upper,pci_size_t bar_size_lower)138 void pciauto_setup_device_mem(struct pci_controller *hose,
139 pci_dev_t dev, int bars_num,
140 struct pci_region *mem,
141 struct pci_region *prefetch,
142 struct pci_region *io,
143 pci_size_t bar_size_upper,
144 pci_size_t bar_size_lower)
145 {
146 unsigned int bar_response;
147 pci_addr_t bar_value;
148 pci_size_t bar_size;
149 unsigned int cmdstat = 0;
150 struct pci_region *bar_res;
151 int bar, bar_nr = 0;
152 int found_mem64 = 0;
153
154 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
155 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
156
157 for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) {
158 /* Tickle the BAR and get the response */
159 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
160 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
161
162 /* If BAR is not implemented go to the next BAR */
163 if (!bar_response)
164 continue;
165
166 found_mem64 = 0;
167
168 /* Check the BAR type and set our address mask */
169 if ( ! (bar_response & PCI_BASE_ADDRESS_SPACE)) {
170 if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
171 PCI_BASE_ADDRESS_MEM_TYPE_64) {
172 u32 bar_response_upper;
173 u64 bar64;
174 pci_hose_write_config_dword(hose, dev, bar+4, 0xffffffff);
175 pci_hose_read_config_dword(hose, dev, bar+4, &bar_response_upper);
176
177 bar64 = ((u64)bar_response_upper << 32) | bar_response;
178
179 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
180 found_mem64 = 1;
181 } else {
182 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
183 }
184 if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
185 bar_res = prefetch;
186 else
187 bar_res = mem;
188
189 DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%llx, ", bar_nr, (u64)bar_size);
190 }
191
192 if ((bar_size >= bar_size_lower) && (bar_size <= bar_size_upper)) {
193 if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
194 /* Write it out and update our limit */
195 pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
196
197 if (found_mem64) {
198 bar += 4;
199 #ifdef CONFIG_SYS_PCI_64BIT
200 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
201 #else
202 /*
203 * If we are a 64-bit decoder then increment to the
204 * upper 32 bits of the bar and force it to locate
205 * in the lower 4GB of memory.
206 */
207 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
208 #endif
209 }
210
211 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
212 PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
213 }
214 }
215
216 DEBUGF("\n");
217
218 bar_nr++;
219 }
220
221 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
222 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
223 CONFIG_SYS_PCI_CACHE_LINE_SIZE);
224 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
225 }
226 #endif
227
pciauto_setup_device(struct pci_controller * hose,pci_dev_t dev,int bars_num,struct pci_region * mem,struct pci_region * prefetch,struct pci_region * io)228 void pciauto_setup_device(struct pci_controller *hose,
229 pci_dev_t dev, int bars_num,
230 struct pci_region *mem,
231 struct pci_region *prefetch,
232 struct pci_region *io)
233 {
234 unsigned int bar_response;
235 pci_addr_t bar_value;
236 pci_size_t bar_size;
237 unsigned int cmdstat = 0;
238 struct pci_region *bar_res;
239 int bar, bar_nr = 0;
240 int found_mem64 = 0;
241
242 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
243 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
244
245 for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) {
246 /* Tickle the BAR and get the response */
247 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
248 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
249
250 /* If BAR is not implemented go to the next BAR */
251 if (!bar_response)
252 continue;
253
254 found_mem64 = 0;
255
256 /* Check the BAR type and set our address mask */
257 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
258 bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
259 & 0xffff) + 1;
260 bar_res = io;
261
262 DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", bar_nr, (u64)bar_size);
263 } else {
264 if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
265 PCI_BASE_ADDRESS_MEM_TYPE_64) {
266 u32 bar_response_upper;
267 u64 bar64;
268 pci_hose_write_config_dword(hose, dev, bar+4, 0xffffffff);
269 pci_hose_read_config_dword(hose, dev, bar+4, &bar_response_upper);
270
271 bar64 = ((u64)bar_response_upper << 32) | bar_response;
272
273 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
274 found_mem64 = 1;
275 } else {
276 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
277 }
278 if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
279 bar_res = prefetch;
280 else
281 bar_res = mem;
282
283 DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%llx, ", bar_nr, (u64)bar_size);
284 }
285
286 if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
287 /* Write it out and update our limit */
288 pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
289
290 if (found_mem64) {
291 bar += 4;
292 #ifdef CONFIG_SYS_PCI_64BIT
293 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
294 #else
295 /*
296 * If we are a 64-bit decoder then increment to the
297 * upper 32 bits of the bar and force it to locate
298 * in the lower 4GB of memory.
299 */
300 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
301 #endif
302 }
303
304 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
305 PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
306 }
307
308 DEBUGF("\n");
309
310 bar_nr++;
311 }
312
313 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
314 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
315 CONFIG_SYS_PCI_CACHE_LINE_SIZE);
316 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
317 }
318
pciauto_prescan_setup_bridge(struct pci_controller * hose,pci_dev_t dev,int sub_bus)319 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
320 pci_dev_t dev, int sub_bus)
321 {
322 struct pci_region *pci_mem = hose->pci_mem;
323 struct pci_region *pci_prefetch = hose->pci_prefetch;
324 struct pci_region *pci_io = hose->pci_io;
325 unsigned int cmdstat;
326
327 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
328
329 /* Configure bus number registers */
330 pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
331 PCI_BUS(dev) - hose->first_busno);
332 pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
333 sub_bus - hose->first_busno);
334 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
335
336 if (pci_mem) {
337 /* Round memory allocator to 1MB boundary */
338 pciauto_region_align(pci_mem, 0x100000);
339
340 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
341 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
342 (pci_mem->bus_lower & 0xfff00000) >> 16);
343
344 cmdstat |= PCI_COMMAND_MEMORY;
345 }
346
347 if (pci_prefetch) {
348 /* Round memory allocator to 1MB boundary */
349 pciauto_region_align(pci_prefetch, 0x100000);
350
351 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
352 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
353 (pci_prefetch->bus_lower & 0xfff00000) >> 16);
354
355 cmdstat |= PCI_COMMAND_MEMORY;
356 } else {
357 /* We don't support prefetchable memory for now, so disable */
358 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
359 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
360 }
361
362 if (pci_io) {
363 /* Round I/O allocator to 4KB boundary */
364 pciauto_region_align(pci_io, 0x1000);
365
366 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
367 (pci_io->bus_lower & 0x0000f000) >> 8);
368 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
369 (pci_io->bus_lower & 0xffff0000) >> 16);
370
371 cmdstat |= PCI_COMMAND_IO;
372 }
373
374 /* Enable memory and I/O accesses, enable bus master */
375 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
376 }
377
pciauto_postscan_setup_bridge(struct pci_controller * hose,pci_dev_t dev,int sub_bus)378 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
379 pci_dev_t dev, int sub_bus)
380 {
381 struct pci_region *pci_mem = hose->pci_mem;
382 struct pci_region *pci_prefetch = hose->pci_prefetch;
383 struct pci_region *pci_io = hose->pci_io;
384
385 /* Configure bus number registers */
386 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
387 sub_bus - hose->first_busno);
388
389 if (pci_mem) {
390 /* Round memory allocator to 1MB boundary */
391 pciauto_region_align(pci_mem, 0x100000);
392
393 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
394 (pci_mem->bus_lower-1) >> 16);
395 }
396
397 if (pci_prefetch) {
398 /* Round memory allocator to 1MB boundary */
399 pciauto_region_align(pci_prefetch, 0x100000);
400
401 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
402 (pci_prefetch->bus_lower-1) >> 16);
403 }
404
405 if (pci_io) {
406 /* Round I/O allocator to 4KB boundary */
407 pciauto_region_align(pci_io, 0x1000);
408
409 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
410 ((pci_io->bus_lower-1) & 0x0000f000) >> 8);
411 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
412 ((pci_io->bus_lower-1) & 0xffff0000) >> 16);
413 }
414 }
415
416 /*
417 *
418 */
419
pciauto_config_init(struct pci_controller * hose)420 void pciauto_config_init(struct pci_controller *hose)
421 {
422 int i;
423
424 hose->pci_io = hose->pci_mem = NULL;
425
426 for (i=0; i<hose->region_count; i++) {
427 switch(hose->regions[i].flags) {
428 case PCI_REGION_IO:
429 if (!hose->pci_io ||
430 hose->pci_io->size < hose->regions[i].size)
431 hose->pci_io = hose->regions + i;
432 break;
433 case PCI_REGION_MEM:
434 if (!hose->pci_mem ||
435 hose->pci_mem->size < hose->regions[i].size)
436 hose->pci_mem = hose->regions + i;
437 break;
438 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
439 if (!hose->pci_prefetch ||
440 hose->pci_prefetch->size < hose->regions[i].size)
441 hose->pci_prefetch = hose->regions + i;
442 break;
443 }
444 }
445
446
447 if (hose->pci_mem) {
448 pciauto_region_init(hose->pci_mem);
449
450 DEBUGF("PCI Autoconfig: Bus Memory region: [0x%llx-0x%llx],\n"
451 "\t\tPhysical Memory [%llx-%llxx]\n",
452 (u64)hose->pci_mem->bus_start,
453 (u64)(hose->pci_mem->bus_start + hose->pci_mem->size - 1),
454 (u64)hose->pci_mem->phys_start,
455 (u64)(hose->pci_mem->phys_start + hose->pci_mem->size - 1));
456 }
457
458 if (hose->pci_prefetch) {
459 pciauto_region_init(hose->pci_prefetch);
460
461 DEBUGF("PCI Autoconfig: Bus Prefetchable Mem: [0x%llx-0x%llx],\n"
462 "\t\tPhysical Memory [%llx-%llx]\n",
463 (u64)hose->pci_prefetch->bus_start,
464 (u64)(hose->pci_prefetch->bus_start +
465 hose->pci_prefetch->size - 1),
466 (u64)hose->pci_prefetch->phys_start,
467 (u64)(hose->pci_prefetch->phys_start +
468 hose->pci_prefetch->size - 1));
469 }
470
471 if (hose->pci_io) {
472 pciauto_region_init(hose->pci_io);
473
474 DEBUGF("PCI Autoconfig: Bus I/O region: [0x%llx-0x%llx],\n"
475 "\t\tPhysical Memory: [%llx-%llx]\n",
476 (u64)hose->pci_io->bus_start,
477 (u64)(hose->pci_io->bus_start + hose->pci_io->size - 1),
478 (u64)hose->pci_io->phys_start,
479 (u64)(hose->pci_io->phys_start + hose->pci_io->size - 1));
480
481 }
482 }
483
484 /* HJF: Changed this to return int. I think this is required
485 * to get the correct result when scanning bridges
486 */
pciauto_config_device(struct pci_controller * hose,pci_dev_t dev)487 int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
488 {
489 unsigned int sub_bus = PCI_BUS(dev);
490 unsigned short class;
491 unsigned char prg_iface;
492 int n;
493
494 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
495
496 switch(class) {
497 case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
498 DEBUGF("PCI AutoConfig: Found PowerPC device\n");
499 pciauto_setup_device(hose, dev, 6, hose->pci_mem,
500 hose->pci_prefetch, hose->pci_io);
501 break;
502
503 case PCI_CLASS_BRIDGE_PCI:
504 hose->current_busno++;
505 pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
506
507 DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
508
509 /* Passing in current_busno allows for sibling P2P bridges */
510 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
511 /*
512 * need to figure out if this is a subordinate bridge on the bus
513 * to be able to properly set the pri/sec/sub bridge registers.
514 */
515 n = pci_hose_scan_bus(hose, hose->current_busno);
516
517 /* figure out the deepest we've gone for this leg */
518 sub_bus = max(n, sub_bus);
519 pciauto_postscan_setup_bridge(hose, dev, sub_bus);
520
521 sub_bus = hose->current_busno;
522 break;
523
524 case PCI_CLASS_STORAGE_IDE:
525 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface);
526 if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
527 DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n");
528 return sub_bus;
529 }
530
531 pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
532 break;
533
534 case PCI_CLASS_BRIDGE_CARDBUS:
535 /* just do a minimal setup of the bridge, let the OS take care of the rest */
536 pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
537
538 DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", PCI_DEV(dev));
539
540 hose->current_busno++;
541 break;
542
543 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
544 case PCI_CLASS_BRIDGE_OTHER:
545 DEBUGF("PCI Autoconfig: Skipping bridge device %d\n",
546 PCI_DEV(dev));
547 break;
548 #endif
549 #if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
550 case PCI_CLASS_BRIDGE_OTHER:
551 /*
552 * The host/PCI bridge 1 seems broken in 8349 - it presents
553 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
554 * device claiming resources io/mem/irq.. we only allow for
555 * the PIMMR window to be allocated (BAR0 - 1MB size)
556 */
557 DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n");
558 pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
559 break;
560 #endif
561 default:
562 DEBUGF("pciauto_setup_device_io\n");
563 pciauto_setup_device_io(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
564 DEBUGF("pciauto_setup_device_mem_high\n");
565 pciauto_setup_device_mem(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io, 0xFFFFFFFF, 0x00200000);
566 DEBUGF("pciauto_setup_device_mem_low\n");
567 pciauto_setup_device_mem(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io, 0x001FFFFF, 0x0);
568 break;
569 }
570
571 return sub_bus;
572 }
573