1 /* 2 * (C) Copyright 2001-2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * board/config.h - configuration options, board specific 26 */ 27 28 #ifndef __CONFIG_H 29 #define __CONFIG_H 30 31 /* External logbuffer support */ 32 #define CONFIG_LOGBUFFER 33 34 /* 35 * High Level Configuration Options 36 * (easy to change) 37 */ 38 39 #define CONFIG_MPC823 1 /* This is a MPC823E CPU */ 40 #define CONFIG_LWMON 1 /* ...on a LWMON board */ 41 42 /* Default Ethernet MAC address */ 43 #define CONFIG_ETHADDR 00:11:B0:00:00:00 44 45 /* The default Ethernet MAC address can be overwritten just once */ 46 #ifdef CONFIG_ETHADDR 47 #define CONFIG_OVERWRITE_ETHADDR_ONCE 1 48 #endif 49 50 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */ 51 #define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init() */ 52 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ 53 54 #define CONFIG_LCD 1 /* use LCD controller ... */ 55 #define CONFIG_HLD1045 1 /* ... with a HLD1045 display */ 56 57 #define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */ 58 #define CONFIG_LCD_INFO 1 /* ... and some board info */ 59 #define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ 60 61 #define CONFIG_SERIAL_MULTI 1 62 #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ 63 #define CONFIG_8xx_CONS_SCC2 1 /* Console is on SCC2 */ 64 65 #define CONFIG_BAUDRATE 115200 /* with watchdog >= 38400 needed */ 66 67 #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ 68 69 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ 70 71 /* pre-boot commands */ 72 #define CONFIG_PREBOOT "setenv bootdelay 15" 73 74 #undef CONFIG_BOOTARGS 75 76 /* POST support */ 77 #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ 78 CONFIG_SYS_POST_WATCHDOG | \ 79 CONFIG_SYS_POST_RTC | \ 80 CONFIG_SYS_POST_MEMORY | \ 81 CONFIG_SYS_POST_CPU | \ 82 CONFIG_SYS_POST_UART | \ 83 CONFIG_SYS_POST_ETHER | \ 84 CONFIG_SYS_POST_I2C | \ 85 CONFIG_SYS_POST_SPI | \ 86 CONFIG_SYS_POST_USB | \ 87 CONFIG_SYS_POST_SPR | \ 88 CONFIG_SYS_POST_SYSMON) 89 90 /* 91 * Keyboard commands: 92 * # = 0x28 = ENTER : enable bootmessages on LCD 93 * 2 = 0x3A+0x3C = F1 + F3 : enable update mode 94 * 3 = 0x3C+0x3F = F3 + F6 : enable test mode 95 */ 96 97 #define CONFIG_BOOTCOMMAND "source 40040000;saveenv" 98 99 /* "gatewayip=10.8.211.250\0" \ */ 100 #define CONFIG_EXTRA_ENV_SETTINGS \ 101 "kernel_addr=40080000\0" \ 102 "ramdisk_addr=40280000\0" \ 103 "netmask=255.255.192.0\0" \ 104 "serverip=10.8.2.101\0" \ 105 "ipaddr=10.8.57.0\0" \ 106 "magic_keys=#23\0" \ 107 "key_magic#=28\0" \ 108 "key_cmd#=setenv addfb setenv 'bootargs $bootargs console=tty0'\0" \ 109 "key_magic2=3A+3C\0" \ 110 "key_cmd2=echo *** Entering Update Mode ***;" \ 111 "if fatload ide 0:3 10000 update.scr;" \ 112 "then source 10000;" \ 113 "else echo *** UPDATE FAILED ***;" \ 114 "fi\0" \ 115 "key_magic3=3C+3F\0" \ 116 "key_cmd3=echo *** Entering Test Mode ***;" \ 117 "setenv add_misc 'setenv bootargs $bootargs testmode'\0" \ 118 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \ 119 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 120 "addfb=setenv bootargs $bootargs console=ttyS1,$baudrate\0" \ 121 "addip=setenv bootargs $bootargs " \ 122 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \ 123 "panic=1\0" \ 124 "add_wdt=setenv bootargs $bootargs $wdt_args\0" \ 125 "add_misc=setenv bootargs $bootargs runmode\0" \ 126 "flash_nfs=run nfsargs addip add_wdt addfb add_misc;" \ 127 "bootm $kernel_addr\0" \ 128 "flash_self=run ramargs addip add_wdt addfb add_misc;" \ 129 "bootm $kernel_addr $ramdisk_addr\0" \ 130 "net_nfs=tftp 100000 /tftpboot/uImage.lwmon;" \ 131 "run nfsargs addip add_wdt addfb;bootm\0" \ 132 "rootpath=/opt/eldk/ppc_8xx\0" \ 133 "load=tftp 100000 /tftpboot/u-boot.bin\0" \ 134 "update=protect off 1:0;era 1:0;cp.b 100000 40000000 $filesize\0" \ 135 "wdt_args=wdt_8xx=off\0" \ 136 "verify=no" 137 138 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 139 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 140 141 #define CONFIG_WATCHDOG 1 /* watchdog enabled */ 142 #define CONFIG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 20) 143 144 #undef CONFIG_STATUS_LED /* Status LED disabled */ 145 146 /* enable I2C and select the hardware/software driver */ 147 #undef CONFIG_HARD_I2C /* I2C with hardware support */ 148 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ 149 150 #define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */ 151 #define CONFIG_SYS_I2C_SLAVE 0xFE 152 153 #ifdef CONFIG_SOFT_I2C 154 /* 155 * Software (bit-bang) I2C driver configuration 156 */ 157 #define PB_SCL 0x00000020 /* PB 26 */ 158 #define PB_SDA 0x00000010 /* PB 27 */ 159 160 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) 161 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) 162 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) 163 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) 164 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ 165 else immr->im_cpm.cp_pbdat &= ~PB_SDA 166 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ 167 else immr->im_cpm.cp_pbdat &= ~PB_SCL 168 #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ 169 #endif /* CONFIG_SOFT_I2C */ 170 171 172 #define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ 173 174 175 /* 176 * Command line configuration. 177 */ 178 #include <config_cmd_default.h> 179 180 #define CONFIG_CMD_ASKENV 181 #define CONFIG_CMD_BMP 182 #define CONFIG_CMD_BSP 183 #define CONFIG_CMD_DATE 184 #define CONFIG_CMD_DHCP 185 #define CONFIG_CMD_EEPROM 186 #define CONFIG_CMD_FAT 187 #define CONFIG_CMD_I2C 188 #define CONFIG_CMD_IDE 189 #define CONFIG_CMD_NFS 190 #define CONFIG_CMD_SNTP 191 192 #ifdef CONFIG_POST 193 #define CONFIG_CMD_DIAG 194 #endif 195 196 197 #define CONFIG_MAC_PARTITION 198 #define CONFIG_DOS_PARTITION 199 200 /* 201 * BOOTP options 202 */ 203 #define CONFIG_BOOTP_SUBNETMASK 204 #define CONFIG_BOOTP_GATEWAY 205 #define CONFIG_BOOTP_HOSTNAME 206 #define CONFIG_BOOTP_BOOTPATH 207 #define CONFIG_BOOTP_BOOTFILESIZE 208 209 210 /* 211 * Miscellaneous configurable options 212 */ 213 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 214 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 215 216 #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ 217 #ifdef CONFIG_SYS_HUSH_PARSER 218 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 219 #endif 220 221 #if defined(CONFIG_CMD_KGDB) 222 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 223 #else 224 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 225 #endif 226 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 227 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 228 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 229 230 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 231 #define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ 232 233 #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ 234 235 #define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ 236 237 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 238 239 /* 240 * When the watchdog is enabled, output must be fast enough in Linux. 241 */ 242 #ifdef CONFIG_WATCHDOG 243 #define CONFIG_SYS_BAUDRATE_TABLE { 38400, 57600, 115200 } 244 #else 245 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 246 #endif 247 248 /*----------------------------------------------------------------------*/ 249 #define CONFIG_MODEM_SUPPORT 1 /* enable modem initialization stuff */ 250 #undef CONFIG_MODEM_SUPPORT_DEBUG 251 252 #define CONFIG_MODEM_KEY_MAGIC "3C+3D" /* press F3 + F4 keys to enable modem */ 253 #define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */ 254 #if 0 255 #define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */ 256 #define CONFIG_AUTOBOOT_PROMPT \ 257 "\nEnter password - autoboot in %d sec...\n", bootdelay 258 #define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */ 259 #endif 260 /*----------------------------------------------------------------------*/ 261 262 /* 263 * Low Level Configuration Settings 264 * (address mappings, register initial values, etc.) 265 * You should know what you are doing if you make changes here. 266 */ 267 /*----------------------------------------------------------------------- 268 * Internal Memory Mapped Register 269 */ 270 #define CONFIG_SYS_IMMR 0xFFF00000 271 272 /*----------------------------------------------------------------------- 273 * Definitions for initial stack pointer and data area (in DPRAM) 274 */ 275 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 276 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 277 #define CONFIG_SYS_GBL_DATA_SIZE 68 /* size in bytes reserved for initial data */ 278 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 279 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 280 281 /*----------------------------------------------------------------------- 282 * Start addresses for the final memory configuration 283 * (Set up by the startup code) 284 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 285 */ 286 #define CONFIG_SYS_SDRAM_BASE 0x00000000 287 #define CONFIG_SYS_FLASH_BASE 0x40000000 288 #if defined(DEBUG) || defined(CONFIG_CMD_IDE) 289 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 290 #else 291 #define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ 292 #endif 293 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 294 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 295 296 /* 297 * For booting Linux, the board info and command line data 298 * have to be in the first 8 MB of memory, since this is 299 * the maximum mapped by the Linux kernel during initialization. 300 */ 301 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 302 /*----------------------------------------------------------------------- 303 * FLASH organization 304 */ 305 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 306 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ 307 308 #define CONFIG_SYS_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ 309 #define CONFIG_SYS_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ 310 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 311 #define CONFIG_SYS_FLASH_BUFFER_WRITE_TOUT 2048 /* Timeout for Flash Buffer Write (in ms) */ 312 /* Buffer size. 313 We have two flash devices connected in parallel. 314 Each device incorporates a Write Buffer of 32 bytes. 315 */ 316 #define CONFIG_SYS_FLASH_BUFFER_SIZE (2*32) 317 318 /* Put environment in flash which is much faster to boot than using the EEPROM */ 319 #define CONFIG_ENV_IS_IN_FLASH 1 320 #define CONFIG_ENV_ADDR 0x40040000 /* Address of Environment Sector */ 321 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment */ 322 #define CONFIG_ENV_SECT_SIZE 0x40000 /* we have BIG sectors only :-( */ 323 324 /*----------------------------------------------------------------------- 325 * I2C/EEPROM Configuration 326 */ 327 328 #define CONFIG_SYS_I2C_AUDIO_ADDR 0x28 /* Audio volume control */ 329 #define CONFIG_SYS_I2C_SYSMON_ADDR 0x2E /* LM87 System Monitor */ 330 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ 331 #define CONFIG_SYS_I2C_POWER_A_ADDR 0x52 /* PCMCIA/USB power switch, channel A */ 332 #define CONFIG_SYS_I2C_POWER_B_ADDR 0x53 /* PCMCIA/USB power switch, channel B */ 333 #define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */ 334 #define CONFIG_SYS_I2C_PICIO_ADDR 0x57 /* PIC IO Expander */ 335 336 #undef CONFIG_USE_FRAM /* Use FRAM instead of EEPROM */ 337 338 #ifdef CONFIG_USE_FRAM /* use FRAM */ 339 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x55 /* FRAM FM24CL64 */ 340 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 341 #else /* use EEPROM */ 342 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 /* EEPROM AT24C164 */ 343 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 344 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ 345 #endif /* CONFIG_USE_FRAM */ 346 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 347 348 /* List of I2C addresses to be verified by POST */ 349 #ifdef CONFIG_USE_FRAM 350 #define I2C_ADDR_LIST { /* CONFIG_SYS_I2C_AUDIO_ADDR, */ \ 351 CONFIG_SYS_I2C_SYSMON_ADDR, \ 352 CONFIG_SYS_I2C_RTC_ADDR, \ 353 CONFIG_SYS_I2C_POWER_A_ADDR, \ 354 CONFIG_SYS_I2C_POWER_B_ADDR, \ 355 CONFIG_SYS_I2C_KEYBD_ADDR, \ 356 CONFIG_SYS_I2C_PICIO_ADDR, \ 357 CONFIG_SYS_I2C_EEPROM_ADDR, \ 358 } 359 #else /* Use EEPROM - which show up on 8 consequtive addresses */ 360 #define I2C_ADDR_LIST { /* CONFIG_SYS_I2C_AUDIO_ADDR, */ \ 361 CONFIG_SYS_I2C_SYSMON_ADDR, \ 362 CONFIG_SYS_I2C_RTC_ADDR, \ 363 CONFIG_SYS_I2C_POWER_A_ADDR, \ 364 CONFIG_SYS_I2C_POWER_B_ADDR, \ 365 CONFIG_SYS_I2C_KEYBD_ADDR, \ 366 CONFIG_SYS_I2C_PICIO_ADDR, \ 367 CONFIG_SYS_I2C_EEPROM_ADDR+0, \ 368 CONFIG_SYS_I2C_EEPROM_ADDR+1, \ 369 CONFIG_SYS_I2C_EEPROM_ADDR+2, \ 370 CONFIG_SYS_I2C_EEPROM_ADDR+3, \ 371 CONFIG_SYS_I2C_EEPROM_ADDR+4, \ 372 CONFIG_SYS_I2C_EEPROM_ADDR+5, \ 373 CONFIG_SYS_I2C_EEPROM_ADDR+6, \ 374 CONFIG_SYS_I2C_EEPROM_ADDR+7, \ 375 } 376 #endif /* CONFIG_USE_FRAM */ 377 378 /*----------------------------------------------------------------------- 379 * Cache Configuration 380 */ 381 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 382 #if defined(CONFIG_CMD_KGDB) 383 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 384 #endif 385 386 /*----------------------------------------------------------------------- 387 * SYPCR - System Protection Control 11-9 388 * SYPCR can only be written once after reset! 389 *----------------------------------------------------------------------- 390 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 391 */ 392 #if 0 && defined(CONFIG_WATCHDOG) /* LWMON uses external MAX706TESA WD */ 393 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 394 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 395 #else 396 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 397 #endif 398 399 /*----------------------------------------------------------------------- 400 * SIUMCR - SIU Module Configuration 11-6 401 *----------------------------------------------------------------------- 402 * PCMCIA config., multi-function pin tri-state 403 */ 404 /* EARB, DBGC and DBPC are initialised by the HCW */ 405 /* => 0x000000C0 */ 406 #define CONFIG_SYS_SIUMCR (SIUMCR_GB5E) 407 /*#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) */ 408 409 /*----------------------------------------------------------------------- 410 * TBSCR - Time Base Status and Control 11-26 411 *----------------------------------------------------------------------- 412 * Clear Reference Interrupt Status, Timebase freezing enabled 413 */ 414 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 415 416 /*----------------------------------------------------------------------- 417 * PISCR - Periodic Interrupt Status and Control 11-31 418 *----------------------------------------------------------------------- 419 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 420 */ 421 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 422 423 /*----------------------------------------------------------------------- 424 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 425 *----------------------------------------------------------------------- 426 * Reset PLL lock status sticky bit, timer expired status bit and timer 427 * interrupt status bit, set PLL multiplication factor ! 428 */ 429 /* 0x00405000 */ 430 #define CONFIG_SYS_PLPRCR_MF 4 /* (4+1) * 13.2 = 66 MHz Clock */ 431 #define CONFIG_SYS_PLPRCR \ 432 ( (CONFIG_SYS_PLPRCR_MF << PLPRCR_MF_SHIFT) | \ 433 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \ 434 /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ 435 PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \ 436 ) 437 438 #define CONFIG_8xx_GCLK_FREQ ((CONFIG_SYS_PLPRCR_MF+1)*13200000) 439 440 /*----------------------------------------------------------------------- 441 * SCCR - System Clock and reset Control Register 15-27 442 *----------------------------------------------------------------------- 443 * Set clock output, timebase and RTC source and divider, 444 * power management and some other internal clocks 445 */ 446 #define SCCR_MASK SCCR_EBDF11 447 /* 0x01800000 */ 448 #define CONFIG_SYS_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \ 449 SCCR_RTDIV | SCCR_RTSEL | \ 450 /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ 451 SCCR_EBDF00 | SCCR_DFSYNC00 | \ 452 SCCR_DFBRG00 | SCCR_DFNL000 | \ 453 SCCR_DFNH000 | SCCR_DFLCD100 | \ 454 SCCR_DFALCD01) 455 456 /*----------------------------------------------------------------------- 457 * RTCSC - Real-Time Clock Status and Control Register 11-27 458 *----------------------------------------------------------------------- 459 */ 460 /* 0x00C3 => 0x0003 */ 461 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 462 463 464 /*----------------------------------------------------------------------- 465 * RCCR - RISC Controller Configuration Register 19-4 466 *----------------------------------------------------------------------- 467 */ 468 #define CONFIG_SYS_RCCR 0x0000 469 470 /*----------------------------------------------------------------------- 471 * RMDS - RISC Microcode Development Support Control Register 472 *----------------------------------------------------------------------- 473 */ 474 #define CONFIG_SYS_RMDS 0 475 476 /*----------------------------------------------------------------------- 477 * 478 * Interrupt Levels 479 *----------------------------------------------------------------------- 480 */ 481 #define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ 482 483 /*----------------------------------------------------------------------- 484 * PCMCIA stuff 485 *----------------------------------------------------------------------- 486 * 487 */ 488 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0x50000000) 489 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 490 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0x54000000) 491 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 492 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0x58000000) 493 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 494 #define CONFIG_SYS_PCMCIA_IO_ADDR (0x5C000000) 495 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 496 497 /*----------------------------------------------------------------------- 498 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 499 *----------------------------------------------------------------------- 500 */ 501 502 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 503 504 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 505 #undef CONFIG_IDE_LED /* LED for ide not supported */ 506 #undef CONFIG_IDE_RESET /* reset for ide not supported */ 507 508 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 509 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 510 511 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 512 513 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 514 515 /* Offset for data I/O */ 516 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 517 518 /* Offset for normal register accesses */ 519 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 520 521 /* Offset for alternate registers */ 522 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 523 524 #define CONFIG_SUPPORT_VFAT /* enable VFAT support */ 525 526 /*----------------------------------------------------------------------- 527 * 528 *----------------------------------------------------------------------- 529 * 530 */ 531 #define CONFIG_SYS_DER 0 532 533 /* 534 * Init Memory Controller: 535 * 536 * BR0/1 and OR0/1 (FLASH) - second Flash bank optional 537 */ 538 539 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 540 #define FLASH_BASE1_PRELIM 0x41000000 /* FLASH bank #1 */ 541 542 /* used to re-map FLASH: 543 * restrict access enough to keep SRAM working (if any) 544 * but not too much to meddle with FLASH accesses 545 */ 546 #define CONFIG_SYS_REMAP_OR_AM 0xFF000000 /* OR addr mask */ 547 #define CONFIG_SYS_PRELIM_OR_AM 0xFF000000 /* OR addr mask */ 548 549 /* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */ 550 #define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_8_CLK) 551 552 #define CONFIG_SYS_OR0_REMAP ( CONFIG_SYS_REMAP_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ 553 CONFIG_SYS_OR_TIMING_FLASH) 554 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \ 555 CONFIG_SYS_OR_TIMING_FLASH) 556 /* 16 bit, bank valid */ 557 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V ) 558 559 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 560 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 561 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V ) 562 563 /* 564 * BR3/OR3: SDRAM 565 * 566 * Multiplexed addresses, GPL5 output to GPL5_A (don't care) 567 */ 568 #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ 569 #define SDRAM_PRELIM_OR_AM 0xF0000000 /* map 256 MB (>SDRAM_MAX_SIZE!) */ 570 #define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */ 571 572 #define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB SDRAM */ 573 574 #define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING ) 575 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 576 577 /* 578 * BR5/OR5: Touch Panel 579 * 580 * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0 581 */ 582 #define TOUCHPNL_BASE 0x20000000 583 #define TOUCHPNL_OR_AM 0xFFFF8000 584 #define TOUCHPNL_TIMING OR_SCY_0_CLK 585 586 #define CONFIG_SYS_OR5_PRELIM (TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ 587 TOUCHPNL_TIMING ) 588 #define CONFIG_SYS_BR5_PRELIM ((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V ) 589 590 #define CONFIG_SYS_MEMORY_75 591 #undef CONFIG_SYS_MEMORY_7E 592 #undef CONFIG_SYS_MEMORY_8E 593 594 /* 595 * Memory Periodic Timer Prescaler 596 */ 597 598 /* periodic timer for refresh */ 599 #define CONFIG_SYS_MPTPR 0x200 600 601 /* 602 * MAMR settings for SDRAM 603 */ 604 605 #define CONFIG_SYS_MAMR_8COL 0x80802114 606 #define CONFIG_SYS_MAMR_9COL 0x80904114 607 608 /* 609 * MAR setting for SDRAM 610 */ 611 #define CONFIG_SYS_MAR 0x00000088 612 613 /* 614 * Internal Definitions 615 * 616 * Boot Flags 617 */ 618 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 619 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 620 621 #endif /* __CONFIG_H */ 622