1 /* 2 * (C) Copyright 2004-2005 3 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> 4 * 5 * (C) Copyright 2004 6 * Vincent Dubey, Xa SA, vincent.dubey@xa-ch.com 7 * 8 * (C) Copyright 2002 9 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.ne 10 * 11 * (C) Copyright 2002 12 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 13 * Marius Groeger <mgroeger@sysgo.de> 14 * 15 * Configuation settings for the xaeniax board. 16 * 17 * See file CREDITS for list of people who contributed to this 18 * project. 19 * 20 * This program is free software; you can redistribute it and/or 21 * modify it under the terms of the GNU General Public License as 22 * published by the Free Software Foundation; either version 2 of 23 * the License, or (at your option) any later version. 24 * 25 * This program is distributed in the hope that it will be useful, 26 * but WITHOUT ANY WARRANTY; without even the implied warranty of 27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 28 * GNU General Public License for more details. 29 * 30 * You should have received a copy of the GNU General Public License 31 * along with this program; if not, write to the Free Software 32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 33 * MA 02111-1307 USA 34 */ 35 36 #ifndef __CONFIG_H 37 #define __CONFIG_H 38 39 /* 40 * High Level Configuration Options 41 * (easy to change) 42 */ 43 #define CONFIG_PXA250 1 /* This is an PXA255 CPU */ 44 #define CONFIG_XAENIAX 1 /* on a xaeniax board */ 45 46 47 #define BOARD_LATE_INIT 1 48 49 50 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ 51 52 /* we will never enable dcache, because we have to setup MMU first */ 53 #define CONFIG_SYS_NO_DCACHE 54 55 /* 56 * select serial console configuration 57 */ 58 #define CONFIG_PXA_SERIAL 59 #define CONFIG_BTUART 1 /* we use BTUART on XAENIAX */ 60 61 62 /* allow to overwrite serial and ethaddr */ 63 #define CONFIG_ENV_OVERWRITE 64 65 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 66 67 #define CONFIG_BAUDRATE 115200 68 69 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */ 70 71 72 /* 73 * BOOTP options 74 */ 75 #define CONFIG_BOOTP_BOOTFILESIZE 76 #define CONFIG_BOOTP_BOOTPATH 77 #define CONFIG_BOOTP_GATEWAY 78 #define CONFIG_BOOTP_HOSTNAME 79 80 81 /* 82 * Command line configuration. 83 */ 84 #include <config_cmd_default.h> 85 86 #define CONFIG_CMD_DHCP 87 #define CONFIG_CMD_DIAG 88 #define CONFIG_CMD_NFS 89 #define CONFIG_CMD_SDRAM 90 #define CONFIG_CMD_SNTP 91 92 #undef CONFIG_CMD_DTT 93 94 95 #define CONFIG_ETHADDR 08:00:3e:26:0a:5b 96 #define CONFIG_NETMASK 255.255.255.0 97 #define CONFIG_IPADDR 192.168.68.201 98 #define CONFIG_SERVERIP 192.168.68.62 99 100 #define CONFIG_BOOTDELAY 3 101 #define CONFIG_BOOTCOMMAND "bootm 0x00100000" 102 #define CONFIG_BOOTARGS "console=ttyS1,115200" 103 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 104 #define CONFIG_SETUP_MEMORY_TAGS 1 105 #define CONFIG_INITRD_TAG 1 106 107 #if defined(CONFIG_CMD_KGDB) 108 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ 109 #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ 110 #endif 111 112 /* 113 * Size of malloc() pool; this lives below the uppermost 128 KiB which are 114 * used for the RAM copy of the uboot code 115 */ 116 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) 117 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 118 119 /* 120 * Miscellaneous configurable options 121 */ 122 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 123 #define CONFIG_SYS_HUSH_PARSER 1 124 125 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 126 127 #ifdef CONFIG_SYS_HUSH_PARSER 128 #define CONFIG_SYS_PROMPT "u-boot$ " /* Monitor Command Prompt */ 129 #else 130 #define CONFIG_SYS_PROMPT "u-boot=> " /* Monitor Command Prompt */ 131 #endif 132 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 133 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 134 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 135 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 136 #define CONFIG_SYS_DEVICE_NULLDEV 1 137 138 #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ 139 #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ 140 141 #define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */ 142 143 #define CONFIG_SYS_HZ 1000 144 #define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */ 145 146 /* 147 * Physical Memory Map 148 */ 149 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks (partition) of DRAM */ 150 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ 151 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ 152 #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ 153 #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ 154 #define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ 155 #define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ 156 #define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ 157 #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ 158 159 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ 160 #define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ 161 #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ 162 #define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ 163 #define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ 164 165 #define CONFIG_SYS_DRAM_BASE 0xa0000000 166 #define CONFIG_SYS_DRAM_SIZE 0x04000000 167 168 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 169 170 /* 171 * FLASH and environment organization 172 */ 173 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 174 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ 175 176 /* timeout values are in ticks */ 177 #define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ 178 #define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */ 179 180 /* FIXME */ 181 #define CONFIG_ENV_IS_IN_FLASH 1 182 #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)/* Addr of Environment Sector */ 183 #define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ 184 185 /* 186 * Stack sizes 187 * 188 * The stack sizes are set up in start.S using the settings below 189 */ 190 #define CONFIG_STACKSIZE (128*1024) /* regular stack */ 191 #ifdef CONFIG_USE_IRQ 192 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ 193 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ 194 #endif 195 196 /* 197 * SMSC91C111 Network Card 198 */ 199 #define CONFIG_NET_MULTI 200 #define CONFIG_SMC91111 1 201 #define CONFIG_SMC91111_BASE 0x10000300 /* chip select 3 */ 202 #define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */ 203 #undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */ 204 #undef CONFIG_SHOW_ACTIVITY 205 #define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ 206 207 /* 208 * GPIO settings 209 */ 210 211 /* 212 * GP05 == nUSBReset is 1 213 * GP10 == CFReset is 1 214 * GP13 == nCFDataEnable is 1 215 * GP14 == nCFAddrEnable is 1 216 * GP15 == nCS1 is 1 217 * GP21 == ComBrdReset is 1 218 * GP24 == SFRM is 1 219 * GP25 == TXD is 1 220 * GP31 == SYNC is 1 221 * GP33 == nCS5 is 1 222 * GP39 == FFTXD is 1 223 * GP41 == RTS is 1 224 * GP43 == BTTXD is 1 225 * GP45 == BTRTS is 1 226 * GP47 == TXD is 1 227 * GP48 == nPOE is 1 228 * GP49 == nPWE is 1 229 * GP50 == nPIOR is 1 230 * GP51 == nPIOW is 1 231 * GP52 == nPCE[1] is 1 232 * GP53 == nPCE[2] is 1 233 * GP54 == nPSKTSEL is 1 234 * GP55 == nPREG is 1 235 * GP78 == nCS2 is 1 236 * GP79 == nCS3 is 1 237 * GP80 == nCS4 is 1 238 * GP82 == NSSPSFRM is 1 239 * GP83 == NSSPTXD is 1 240 */ 241 #define CONFIG_SYS_GPSR0_VAL 0x8320E420 242 #define CONFIG_SYS_GPSR1_VAL 0x00FFAA82 243 #define CONFIG_SYS_GPSR2_VAL 0x000DC000 244 245 /* 246 * GP03 == LANReset is 0 247 * GP06 == USBWakeUp is 0 248 * GP11 == USBControl is 0 249 * GP12 == Buzzer is 0 250 * GP16 == PWM0 is 0 251 * GP17 == PWM1 is 0 252 * GP23 == SCLK is 0 253 * GP30 == SDATA_OUT is 0 254 * GP81 == NSSPCLK is 0 255 */ 256 #define CONFIG_SYS_GPCR0_VAL 0x40C31848 257 #define CONFIG_SYS_GPCR1_VAL 0x00000000 258 #define CONFIG_SYS_GPCR2_VAL 0x00020000 259 260 /* 261 * GP00 == CPUWakeUpUSB is input 262 * GP01 == GP reset is input 263 * GP02 == LANInterrupt is input 264 * GP03 == LANReset is output 265 * GP04 == USBInterrupt is input 266 * GP05 == nUSBReset is output 267 * GP06 == USBWakeUp is output 268 * GP07 == CFReady/nBusy is input 269 * GP08 == nCFCardDetect1 is input 270 * GP09 == nCFCardDetect2 is input 271 * GP10 == nCFReset is output 272 * GP11 == USBControl is output 273 * GP12 == Buzzer is output 274 * GP13 == CFDataEnable is output 275 * GP14 == CFAddressEnable is output 276 * GP15 == nCS1 is output 277 * GP16 == PWM0 is output 278 * GP17 == PWM1 is output 279 * GP18 == RDY is input 280 * GP19 == ReaderReady is input 281 * GP20 == ReaderReset is input 282 * GP21 == ComBrdReset is output 283 * GP23 == SCLK is output 284 * GP24 == SFRM is output 285 * GP25 == TXD is output 286 * GP26 == RXD is input 287 * GP27 == EXTCLK is input 288 * GP28 == BITCLK is output 289 * GP29 == SDATA_IN0 is input 290 * GP30 == SDATA_OUT is output 291 * GP31 == SYNC is output 292 * GP32 == SYSSCLK is output 293 * GP33 == nCS5 is output 294 * GP34 == FFRXD is input 295 * GP35 == CTS is input 296 * GP36 == DCD is input 297 * GP37 == DSR is input 298 * GP38 == RI is input 299 * GP39 == FFTXD is output 300 * GP40 == DTR is output 301 * GP41 == RTS is output 302 * GP42 == BTRXD is input 303 * GP43 == BTTXD is output 304 * GP44 == BTCTS is input 305 * GP45 == BTRTS is output 306 * GP46 == RXD is input 307 * GP47 == TXD is output 308 * GP48 == nPOE is output 309 * GP49 == nPWE is output 310 * GP50 == nPIOR is output 311 * GP51 == nPIOW is output 312 * GP52 == nPCE[1] is output 313 * GP53 == nPCE[2] is output 314 * GP54 == nPSKTSEL is output 315 * GP55 == nPREG is output 316 * GP56 == nPWAIT is input 317 * GP57 == nPIOS16 is input 318 * GP58 == LDD[0] is output 319 * GP59 == LDD[1] is output 320 * GP60 == LDD[2] is output 321 * GP61 == LDD[3] is output 322 * GP62 == LDD[4] is output 323 * GP63 == LDD[5] is output 324 * GP64 == LDD[6] is output 325 * GP65 == LDD[7] is output 326 * GP66 == LDD[8] is output 327 * GP67 == LDD[9] is output 328 * GP68 == LDD[10] is output 329 * GP69 == LDD[11] is output 330 * GP70 == LDD[12] is output 331 * GP71 == LDD[13] is output 332 * GP72 == LDD[14] is output 333 * GP73 == LDD[15] is output 334 * GP74 == LCD_FCLK is output 335 * GP75 == LCD_LCLK is output 336 * GP76 == LCD_PCLK is output 337 * GP77 == LCD_ACBIAS is output 338 * GP78 == nCS2 is output 339 * GP79 == nCS3 is output 340 * GP80 == nCS4 is output 341 * GP81 == NSSPCLK is output 342 * GP82 == NSSPSFRM is output 343 * GP83 == NSSPTXD is output 344 * GP84 == NSSPRXD is input 345 */ 346 #define CONFIG_SYS_GPDR0_VAL 0xD3E3FC68 347 #define CONFIG_SYS_GPDR1_VAL 0xFCFFAB83 348 #define CONFIG_SYS_GPDR2_VAL 0x000FFFFF 349 350 /* 351 * GP01 == GP reset is AF01 352 * GP15 == nCS1 is AF10 353 * GP16 == PWM0 is AF10 354 * GP17 == PWM1 is AF10 355 * GP18 == RDY is AF01 356 * GP23 == SCLK is AF10 357 * GP24 == SFRM is AF10 358 * GP25 == TXD is AF10 359 * GP26 == RXD is AF01 360 * GP27 == EXTCLK is AF01 361 * GP28 == BITCLK is AF01 362 * GP29 == SDATA_IN0 is AF10 363 * GP30 == SDATA_OUT is AF01 364 * GP31 == SYNC is AF01 365 * GP32 == SYSCLK is AF01 366 * GP33 == nCS5 is AF10 367 * GP34 == FFRXD is AF01 368 * GP35 == CTS is AF01 369 * GP36 == DCD is AF01 370 * GP37 == DSR is AF01 371 * GP38 == RI is AF01 372 * GP39 == FFTXD is AF10 373 * GP40 == DTR is AF10 374 * GP41 == RTS is AF10 375 * GP42 == BTRXD is AF01 376 * GP43 == BTTXD is AF10 377 * GP44 == BTCTS is AF01 378 * GP45 == BTRTS is AF10 379 * GP46 == RXD is AF10 380 * GP47 == TXD is AF01 381 * GP48 == nPOE is AF10 382 * GP49 == nPWE is AF10 383 * GP50 == nPIOR is AF10 384 * GP51 == nPIOW is AF10 385 * GP52 == nPCE[1] is AF10 386 * GP53 == nPCE[2] is AF10 387 * GP54 == nPSKTSEL is AF10 388 * GP55 == nPREG is AF10 389 * GP56 == nPWAIT is AF01 390 * GP57 == nPIOS16 is AF01 391 * GP58 == LDD[0] is AF10 392 * GP59 == LDD[1] is AF10 393 * GP60 == LDD[2] is AF10 394 * GP61 == LDD[3] is AF10 395 * GP62 == LDD[4] is AF10 396 * GP63 == LDD[5] is AF10 397 * GP64 == LDD[6] is AF10 398 * GP65 == LDD[7] is AF10 399 * GP66 == LDD[8] is AF10 400 * GP67 == LDD[9] is AF10 401 * GP68 == LDD[10] is AF10 402 * GP69 == LDD[11] is AF10 403 * GP70 == LDD[12] is AF10 404 * GP71 == LDD[13] is AF10 405 * GP72 == LDD[14] is AF10 406 * GP73 == LDD[15] is AF10 407 * GP74 == LCD_FCLK is AF10 408 * GP75 == LCD_LCLK is AF10 409 * GP76 == LCD_PCLK is AF10 410 * GP77 == LCD_ACBIAS is AF10 411 * GP78 == nCS2 is AF10 412 * GP79 == nCS3 is AF10 413 * GP80 == nCS4 is AF10 414 * GP81 == NSSPCLK is AF01 415 * GP82 == NSSPSFRM is AF01 416 * GP83 == NSSPTXD is AF01 417 * GP84 == NSSPRXD is AF10 418 */ 419 #define CONFIG_SYS_GAFR0_L_VAL 0x80000004 420 #define CONFIG_SYS_GAFR0_U_VAL 0x595A801A 421 #define CONFIG_SYS_GAFR1_L_VAL 0x699A9559 422 #define CONFIG_SYS_GAFR1_U_VAL 0xAAA5AAAA 423 #define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA 424 #define CONFIG_SYS_GAFR2_U_VAL 0x00000256 425 426 /* 427 * clock settings 428 */ 429 /* RDH = 1 430 * PH = 0 431 * VFS = 0 432 * BFS = 0 433 * SSS = 0 434 */ 435 #define CONFIG_SYS_PSSR_VAL 0x00000030 436 437 #define CONFIG_SYS_CKEN_VAL 0x00000080 /* */ 438 #define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */ 439 440 441 /* 442 * Memory settings 443 * 444 * This is the configuration for nCS0/1 -> flash banks 445 * configuration for nCS1 : 446 * [31] 0 - 447 * [30:28] 000 - 448 * [27:24] 0000 - 449 * [23:20] 0000 - 450 * [19] 0 - 451 * [18:16] 000 - 452 * configuration for nCS0: 453 * [15] 0 - Slower Device 454 * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns 455 * [11:08] 0011 - Address to data valid in bursts: (3+1)*MemClk = 40 ns 456 * [07:04] 1111 - " for first access: (23+2)*MemClk = 250 ns (fixme 12+2?) 457 * [03] 0 - 32 Bit bus width 458 * [02:00] 010 - burst OF 4 ROM or FLASH 459 */ 460 #define CONFIG_SYS_MSC0_VAL 0x000023D2 461 462 /* This is the configuration for nCS2/3 -> USB controller, LAN 463 * configuration for nCS3: LAN 464 * [31] 0 - Slower Device 465 * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns 466 * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns 467 * [23:20] 0010 - RDF3: Address for first access: (2+1)*MemClk = 30 ns 468 * [19] 0 - 32 Bit bus width 469 * [18:16] 100 - variable latency I/O 470 * configuration for nCS2: USB 471 * [15] 1 - Faster Device 472 * [14:12] 010 - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns 473 * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns 474 * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns 475 * [03] 1 - 16 Bit bus width 476 * [02:00] 100 - variable latency I/O 477 */ 478 #define CONFIG_SYS_MSC1_VAL 0x1224A26C 479 480 /* This is the configuration for nCS4/5 -> LAN 481 * configuration for nCS5: 482 * [31] 0 - 483 * [30:28] 000 - 484 * [27:24] 0000 - 485 * [23:20] 0000 - 486 * [19] 0 - 487 * [18:16] 000 - 488 * configuration for nCS4: LAN 489 * [15] 1 - Faster Device 490 * [14:12] 010 - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns 491 * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns 492 * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns 493 * [03] 0 - 32 Bit bus width 494 * [02:00] 100 - variable latency I/O 495 */ 496 #define CONFIG_SYS_MSC2_VAL 0x00001224 497 498 /* MDCNFG: SDRAM Configuration Register 499 * 500 * [31:29] 000 - reserved 501 * [28] 0 - no SA1111 compatiblity mode 502 * [27] 0 - latch return data with return clock 503 * [26] 0 - alternate addressing for pair 2/3 504 * [25:24] 00 - timings 505 * [23] 0 - internal banks in lower partition 2/3 (not used) 506 * [22:21] 00 - row address bits for partition 2/3 (not used) 507 * [20:19] 00 - column address bits for partition 2/3 (not used) 508 * [18] 0 - SDRAM partition 2/3 width is 32 bit 509 * [17] 0 - SDRAM partition 3 disabled 510 * [16] 0 - SDRAM partition 2 disabled 511 * [15:13] 000 - reserved 512 * [12] 0 - no SA1111 compatiblity mode 513 * [11] 1 - latch return data with return clock 514 * [10] 0 - no alternate addressing for pair 0/1 515 * [09:08] 10 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk 516 * [7] 1 - 4 internal banks in lower partition pair 517 * [06:05] 10 - 13 row address bits for partition 0/1 518 * [04:03] 01 - 9 column address bits for partition 0/1 519 * [02] 0 - SDRAM partition 0/1 width is 32 bit 520 * [01] 0 - disable SDRAM partition 1 521 * [00] 1 - enable SDRAM partition 0 522 */ 523 /* use the configuration above but disable partition 0 */ 524 #define CONFIG_SYS_MDCNFG_VAL 0x00000AC9 525 526 /* MDREFR: SDRAM Refresh Control Register 527 * 528 * [32:26] 0 - reserved 529 * [25] 0 - K2FREE: not free running 530 * [24] 0 - K1FREE: not free running 531 * [23] 0 - K0FREE: not free running 532 * [22] 0 - SLFRSH: self refresh disabled 533 * [21] 0 - reserved 534 * [20] 1 - APD: auto power down 535 * [19] 0 - K2DB2: SDCLK2 is MemClk 536 * [18] 0 - K2RUN: disable SDCLK2 537 * [17] 0 - K1DB2: SDCLK1 is MemClk 538 * [16] 1 - K1RUN: enable SDCLK1 539 * [15] 1 - E1PIN: SDRAM clock enable 540 * [14] 0 - K0DB2: SDCLK0 is MemClk 541 * [13] 0 - K0RUN: disable SDCLK0 542 * [12] 0 - E0PIN: disable SDCKE0 543 * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24 544 */ 545 #define CONFIG_SYS_MDREFR_VAL 0x00138018 /* mh: was 0x00118018 */ 546 547 /* MDMRS: Mode Register Set Configuration Register 548 * 549 * [31] 0 - reserved 550 * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used) 551 * [22:20] 011 - MDCL2: SDRAM2/3 Cas Latency. (not used) 552 * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used) 553 * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used) 554 * [15] 0 - reserved 555 * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value. 556 * [06:04] 011 - MDCL0: SDRAM0/1 Cas Latency. 557 * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential. 558 * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4. 559 */ 560 #define CONFIG_SYS_MDMRS_VAL 0x00320032 561 562 /* 563 * PCMCIA and CF Interfaces 564 */ 565 #define CONFIG_SYS_MECR_VAL 0x00000000 566 #define CONFIG_SYS_MCMEM0_VAL 0x00010504 567 #define CONFIG_SYS_MCMEM1_VAL 0x00010504 568 #define CONFIG_SYS_MCATT0_VAL 0x00010504 569 #define CONFIG_SYS_MCATT1_VAL 0x00010504 570 #define CONFIG_SYS_MCIO0_VAL 0x00004715 571 #define CONFIG_SYS_MCIO1_VAL 0x00004715 572 573 574 #endif /* __CONFIG_H */ 575