1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Low-level board setup code for TI DaVinci SoC based boards.
4 *
5 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 *
7 * Partially based on TI sources, original copyrights follow:
8 */
9
10/*
11 * Board specific setup info
12 *
13 * (C) Copyright 2003
14 * Texas Instruments, <www.ti.com>
15 * Kshitij Gupta <Kshitij@ti.com>
16 *
17 * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
18 *
19 * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
20 *
21 * Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005
22 *
23 * Modified for DV-EVM board by Swaminathan S, Nov 2005
24 */
25
26#include <config.h>
27
28#define MDSTAT_STATE	0x3f
29
30.globl	lowlevel_init
31lowlevel_init:
32#ifdef CONFIG_SOC_DM644X
33
34	/*-------------------------------------------------------*
35	 * Mask all IRQs by setting all bits in the EINT default *
36	 *-------------------------------------------------------*/
37	mov	r1, $0
38	ldr	r0, =EINT_ENABLE0
39	str	r1, [r0]
40	ldr	r0, =EINT_ENABLE1
41	str	r1, [r0]
42
43	/*------------------------------------------------------*
44	 * Put the GEM in reset					*
45	 *------------------------------------------------------*/
46
47	/* Put the GEM in reset */
48	ldr	r8, PSC_GEM_FLAG_CLEAR
49	ldr	r6, MDCTL_GEM
50	ldr	r7, [r6]
51	and	r7, r7, r8
52	str	r7, [r6]
53
54	/* Enable the Power Domain Transition Command */
55	ldr	r6, PTCMD
56	ldr	r7, [r6]
57	orr	r7, r7, $0x02
58	str	r7, [r6]
59
60	/* Check for Transition Complete(PTSTAT) */
61checkStatClkStopGem:
62	ldr	r6, PTSTAT
63	ldr	r7, [r6]
64	ands	r7, r7, $0x02
65	bne	checkStatClkStopGem
66
67	/* Check for GEM Reset Completion */
68checkGemStatClkStop:
69	ldr	r6, MDSTAT_GEM
70	ldr	r7, [r6]
71	ands	r7, r7, $0x100
72	bne	checkGemStatClkStop
73
74	/* Do this for enabling a WDT initiated reset this is a workaround
75	   for a chip bug.  Not required under normal situations */
76	ldr	r6, P1394
77	mov	r10, $0
78	str	r10, [r6]
79
80	/*------------------------------------------------------*
81	 * Enable L1 & L2 Memories in Fast mode                 *
82	 *------------------------------------------------------*/
83	ldr	r6, DFT_ENABLE
84	mov	r10, $0x01
85	str	r10, [r6]
86
87	ldr	r6, MMARG_BRF0
88	ldr	r10, MMARG_BRF0_VAL
89	str	r10, [r6]
90
91	ldr	r6, DFT_ENABLE
92	mov	r10, $0
93	str	r10, [r6]
94
95	/*------------------------------------------------------*
96	 * DDR2 PLL Initialization				*
97	 *------------------------------------------------------*/
98
99	/* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
100	mov	r10, $0
101	ldr	r6, PLL2_CTL
102	ldr	r7, PLL_CLKSRC_MASK
103	ldr	r8, [r6]
104	and	r8, r8, r7
105	mov	r9, r10, lsl $8
106	orr	r8, r8, r9
107	str	r8, [r6]
108
109	/* Select the PLLEN source */
110	ldr	r7, PLL_ENSRC_MASK
111	and	r8, r8, r7
112	str	r8, [r6]
113
114	/* Bypass the PLL */
115	ldr	r7, PLL_BYPASS_MASK
116	and	r8, r8, r7
117	str	r8, [r6]
118
119	/* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
120	mov	r10, $0x20
121WaitPPL2Loop:
122	subs	r10, r10, $1
123	bne	WaitPPL2Loop
124
125	/* Reset the PLL */
126	ldr	r7, PLL_RESET_MASK
127	and	r8, r8, r7
128	str	r8, [r6]
129
130	/* Power up the PLL */
131	ldr	r7, PLL_PWRUP_MASK
132	and	r8, r8, r7
133	str	r8, [r6]
134
135	/* Enable the PLL from Disable Mode */
136	ldr	r7, PLL_DISABLE_ENABLE_MASK
137	and	r8, r8, r7
138	str	r8, [r6]
139
140	/* Program the PLL Multiplier */
141	ldr	r6, PLL2_PLLM
142	mov	r2, $0x17	/* 162 MHz */
143	str	r2, [r6]
144
145	/* Program the PLL2 Divisor Value */
146	ldr	r6, PLL2_DIV2
147	mov	r3, $0x01
148	str	r3, [r6]
149
150	/* Program the PLL2 Divisor Value */
151	ldr	r6, PLL2_DIV1
152	mov	r4, $0x0b	/* 54 MHz */
153	str	r4, [r6]
154
155	/* PLL2 DIV2 MMR */
156	ldr	r8, PLL2_DIV_MASK
157	ldr	r6, PLL2_DIV2
158	ldr	r9, [r6]
159	and	r8, r8, r9
160	mov	r9, $0x01
161	mov	r9, r9, lsl $15
162	orr	r8, r8, r9
163	str	r8, [r6]
164
165	/* Program the GOSET bit to take new divider values */
166	ldr	r6, PLL2_PLLCMD
167	ldr	r7, [r6]
168	orr	r7, r7, $0x01
169	str	r7, [r6]
170
171	/* Wait for Done */
172	ldr	r6, PLL2_PLLSTAT
173doneLoop_0:
174	ldr	r7, [r6]
175	ands	r7, r7, $0x01
176	bne	doneLoop_0
177
178	/* PLL2 DIV1 MMR */
179	ldr	r8, PLL2_DIV_MASK
180	ldr	r6, PLL2_DIV1
181	ldr	r9, [r6]
182	and	r8, r8, r9
183	mov	r9, $0x01
184	mov	r9, r9, lsl $15
185	orr	r8, r8, r9
186	str	r8, [r6]
187
188	/* Program the GOSET bit to take new divider values */
189	ldr	r6, PLL2_PLLCMD
190	ldr	r7, [r6]
191	orr	r7, r7, $0x01
192	str	r7, [r6]
193
194	/* Wait for Done */
195	ldr	r6, PLL2_PLLSTAT
196doneLoop:
197	ldr	r7, [r6]
198	ands	r7, r7, $0x01
199	bne	doneLoop
200
201	/* Wait for PLL to Reset Properly */
202	mov	r10, $0x218
203ResetPPL2Loop:
204	subs	r10, r10, $1
205	bne	ResetPPL2Loop
206
207	/* Bring PLL out of Reset */
208	ldr	r6, PLL2_CTL
209	ldr	r8, [r6]
210	orr	r8, r8, $0x08
211	str	r8, [r6]
212
213	/* Wait for PLL to Lock */
214	ldr	r10, PLL_LOCK_COUNT
215PLL2Lock:
216	subs	r10, r10, $1
217	bne	PLL2Lock
218
219	/* Enable the PLL */
220	ldr	r6, PLL2_CTL
221	ldr	r8, [r6]
222	orr	r8, r8, $0x01
223	str	r8, [r6]
224
225	/*------------------------------------------------------*
226	 * Issue Soft Reset to DDR Module			*
227	 *------------------------------------------------------*/
228
229	/* Shut down the DDR2 LPSC Module */
230	ldr	r8, PSC_FLAG_CLEAR
231	ldr	r6, MDCTL_DDR2
232	ldr	r7, [r6]
233	and	r7, r7, r8
234	orr	r7, r7, $0x03
235	str	r7, [r6]
236
237	/* Enable the Power Domain Transition Command */
238	ldr	r6, PTCMD
239	ldr	r7, [r6]
240	orr	r7, r7, $0x01
241	str	r7, [r6]
242
243	/* Check for Transition Complete(PTSTAT) */
244checkStatClkStop:
245	ldr	r6, PTSTAT
246	ldr	r7, [r6]
247	ands	r7, r7, $0x01
248	bne	checkStatClkStop
249
250	/* Check for DDR2 Controller Enable Completion */
251checkDDRStatClkStop:
252	ldr	r6, MDSTAT_DDR2
253	ldr	r7, [r6]
254	and	r7, r7, $MDSTAT_STATE
255	cmp	r7, $0x03
256	bne	checkDDRStatClkStop
257
258	/*------------------------------------------------------*
259	 * Program DDR2 MMRs for 162MHz Setting			*
260	 *------------------------------------------------------*/
261
262	/* Program PHY Control Register */
263	ldr	r6, DDRCTL
264	ldr	r7, DDRCTL_VAL
265	str	r7, [r6]
266
267	/* Program SDRAM Bank Config Register */
268	ldr	r6, SDCFG
269	ldr	r7, SDCFG_VAL
270	str	r7, [r6]
271
272	/* Program SDRAM TIM-0 Config Register */
273	ldr	r6, SDTIM0
274	ldr	r7, SDTIM0_VAL_162MHz
275	str	r7, [r6]
276
277	/* Program SDRAM TIM-1 Config Register */
278	ldr	r6, SDTIM1
279	ldr	r7, SDTIM1_VAL_162MHz
280	str	r7, [r6]
281
282	/* Program the SDRAM Bank Config Control Register */
283	ldr	r10, MASK_VAL
284	ldr	r8, SDCFG
285	ldr	r9, SDCFG_VAL
286	and	r9, r9, r10
287	str	r9, [r8]
288
289	/* Program SDRAM SDREF Config Register */
290	ldr	r6, SDREF
291	ldr	r7, SDREF_VAL
292	str	r7, [r6]
293
294	/*------------------------------------------------------*
295	 * Issue Soft Reset to DDR Module			*
296	 *------------------------------------------------------*/
297
298	/* Issue a Dummy DDR2 read/write */
299	ldr	r8, DDR2_START_ADDR
300	ldr	r7, DUMMY_VAL
301	str	r7, [r8]
302	ldr	r7, [r8]
303
304	/* Shut down the DDR2 LPSC Module */
305	ldr	r8, PSC_FLAG_CLEAR
306	ldr	r6, MDCTL_DDR2
307	ldr	r7, [r6]
308	and	r7, r7, r8
309	orr	r7, r7, $0x01
310	str	r7, [r6]
311
312	/* Enable the Power Domain Transition Command */
313	ldr	r6, PTCMD
314	ldr	r7, [r6]
315	orr	r7, r7, $0x01
316	str	r7, [r6]
317
318	/* Check for Transition Complete(PTSTAT) */
319checkStatClkStop2:
320	ldr	r6, PTSTAT
321	ldr	r7, [r6]
322	ands	r7, r7, $0x01
323	bne	checkStatClkStop2
324
325	/* Check for DDR2 Controller Enable Completion */
326checkDDRStatClkStop2:
327	ldr	r6, MDSTAT_DDR2
328	ldr	r7, [r6]
329	and	r7, r7, $MDSTAT_STATE
330	cmp	r7, $0x01
331	bne	checkDDRStatClkStop2
332
333	/*------------------------------------------------------*
334	 * Turn DDR2 Controller Clocks On			*
335	 *------------------------------------------------------*/
336
337	/* Enable the DDR2 LPSC Module */
338	ldr	r6, MDCTL_DDR2
339	ldr	r7, [r6]
340	orr	r7, r7, $0x03
341	str	r7, [r6]
342
343	/* Enable the Power Domain Transition Command */
344	ldr	r6, PTCMD
345	ldr	r7, [r6]
346	orr	r7, r7, $0x01
347	str	r7, [r6]
348
349	/* Check for Transition Complete(PTSTAT) */
350checkStatClkEn2:
351	ldr	r6, PTSTAT
352	ldr	r7, [r6]
353	ands	r7, r7, $0x01
354	bne	checkStatClkEn2
355
356	/* Check for DDR2 Controller Enable Completion */
357checkDDRStatClkEn2:
358	ldr	r6, MDSTAT_DDR2
359	ldr	r7, [r6]
360	and	r7, r7, $MDSTAT_STATE
361	cmp	r7, $0x03
362	bne	checkDDRStatClkEn2
363
364	/*  DDR Writes and Reads */
365	ldr	r6, CFGTEST
366	mov	r3, $0x01
367	str	r3, [r6]
368
369	/*------------------------------------------------------*
370	 * System PLL Initialization				*
371	 *------------------------------------------------------*/
372
373	/* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
374	mov	r2, $0
375	ldr	r6, PLL1_CTL
376	ldr	r7, PLL_CLKSRC_MASK
377	ldr	r8, [r6]
378	and	r8, r8, r7
379	mov	r9, r2, lsl $8
380	orr	r8, r8, r9
381	str	r8, [r6]
382
383	/* Select the PLLEN source */
384	ldr	r7, PLL_ENSRC_MASK
385	and	r8, r8, r7
386	str	r8, [r6]
387
388	/* Bypass the PLL */
389	ldr	r7, PLL_BYPASS_MASK
390	and	r8, r8, r7
391	str	r8, [r6]
392
393	/* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
394	mov	r10, $0x20
395
396WaitLoop:
397	subs	r10, r10, $1
398	bne	WaitLoop
399
400	/* Reset the PLL */
401	ldr	r7, PLL_RESET_MASK
402	and	r8, r8, r7
403	str	r8, [r6]
404
405	/* Disable the PLL */
406	orr	r8, r8, $0x10
407	str	r8, [r6]
408
409	/* Power up the PLL */
410	ldr	r7, PLL_PWRUP_MASK
411	and	r8, r8, r7
412	str	r8, [r6]
413
414	/* Enable the PLL from Disable Mode */
415	ldr	r7, PLL_DISABLE_ENABLE_MASK
416	and	r8, r8, r7
417	str	r8, [r6]
418
419	/* Program the PLL Multiplier */
420	ldr	r6, PLL1_PLLM
421	mov	r3, $0x15	/* For 594MHz */
422	str	r3, [r6]
423
424	/* Wait for PLL to Reset Properly */
425	mov	r10, $0xff
426
427ResetLoop:
428	subs	r10, r10, $1
429	bne	ResetLoop
430
431	/* Bring PLL out of Reset */
432	ldr	r6, PLL1_CTL
433	orr	r8, r8, $0x08
434	str	r8, [r6]
435
436	/* Wait for PLL to Lock */
437	ldr	r10, PLL_LOCK_COUNT
438
439PLL1Lock:
440	subs	r10, r10, $1
441	bne	PLL1Lock
442
443	/* Enable the PLL */
444	orr	r8, r8, $0x01
445	str	r8, [r6]
446
447	nop
448	nop
449	nop
450	nop
451
452	/*------------------------------------------------------*
453	 * AEMIF configuration for NOR Flash (double check)     *
454	 *------------------------------------------------------*/
455	ldr	r0, _PINMUX0
456	ldr	r1, _DEV_SETTING
457	str	r1, [r0]
458
459	ldr	r0, WAITCFG
460	ldr	r1, WAITCFG_VAL
461	ldr	r2, [r0]
462	orr	r2, r2, r1
463	str	r2, [r0]
464
465	ldr	r0, ACFG3
466	ldr	r1, ACFG3_VAL
467	ldr	r2, [r0]
468	and	r1, r2, r1
469	str	r1, [r0]
470
471	ldr	r0, ACFG4
472	ldr	r1, ACFG4_VAL
473	ldr	r2, [r0]
474	and	r1, r2, r1
475	str	r1, [r0]
476
477	ldr	r0, ACFG5
478	ldr	r1, ACFG5_VAL
479	ldr	r2, [r0]
480	and	r1, r2, r1
481	str	r1, [r0]
482
483	/*--------------------------------------*
484	 * VTP manual Calibration               *
485	 *--------------------------------------*/
486	ldr	r0, VTPIOCR
487	ldr	r1, VTP_MMR0
488	str	r1, [r0]
489
490	ldr	r0, VTPIOCR
491	ldr	r1, VTP_MMR1
492	str	r1, [r0]
493
494	/* Wait for 33 VTP CLK cycles.  VRP operates at 27 MHz */
495	ldr	r10, VTP_LOCK_COUNT
496VTPLock:
497	subs	r10, r10, $1
498	bne	VTPLock
499
500	ldr	r6, DFT_ENABLE
501	mov	r10, $0x01
502	str	r10, [r6]
503
504	ldr	r6, DDRVTPR
505	ldr	r7, [r6]
506	mov	r8, r7, LSL #32-10
507	mov	r8, r8, LSR #32-10        /* grab low 10 bits  */
508	ldr	r7, VTP_RECAL
509	orr	r8, r7, r8
510	ldr	r7, VTP_EN
511	orr	r8, r7, r8
512	str	r8, [r0]
513
514
515	/* Wait for 33 VTP CLK cycles.  VRP operates at 27 MHz */
516	ldr	r10, VTP_LOCK_COUNT
517VTP1Lock:
518	subs	r10, r10, $1
519	bne	VTP1Lock
520
521	ldr	r1, [r0]
522	ldr	r2, VTP_MASK
523	and	r2, r1, r2
524	str	r2, [r0]
525
526	ldr	r6, DFT_ENABLE
527	mov	r10, $0
528	str	r10, [r6]
529
530	/*
531	 * Call board-specific lowlevel init.
532	 * That MUST be present and THAT returns
533	 * back to arch calling code with "mov pc, lr."
534	 */
535	b	dv_board_init
536
537.ltorg
538
539_PINMUX0:
540	.word	0x01c40000		/* Device Configuration Registers */
541_PINMUX1:
542	.word	0x01c40004		/* Device Configuration Registers */
543
544_DEV_SETTING:
545	.word	0x00000c1f
546
547WAITCFG:
548	.word	0x01e00004
549WAITCFG_VAL:
550	.word	0
551ACFG3:
552	.word	0x01e00014
553ACFG3_VAL:
554	.word	0x3ffffffd
555ACFG4:
556	.word	0x01e00018
557ACFG4_VAL:
558	.word	0x3ffffffd
559ACFG5:
560	.word	0x01e0001c
561ACFG5_VAL:
562	.word	0x3ffffffd
563
564MDCTL_DDR2:
565	.word	0x01c41a34
566MDSTAT_DDR2:
567	.word	0x01c41834
568
569PTCMD:
570	.word	0x01c41120
571PTSTAT:
572	.word	0x01c41128
573
574EINT_ENABLE0:
575	.word	0x01c48018
576EINT_ENABLE1:
577	.word	0x01c4801c
578
579PSC_FLAG_CLEAR:
580	.word	0xffffffe0
581PSC_GEM_FLAG_CLEAR:
582	.word	0xfffffeff
583
584/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */
585DDRCTL:
586	.word	0x200000e4
587DDRCTL_VAL:
588	.word	0x50006405
589SDREF:
590	.word	0x2000000c
591SDREF_VAL:
592	.word	0x000005c3
593SDCFG:
594	.word	0x20000008
595SDCFG_VAL:
596#ifdef	DDR_4BANKS
597	.word	0x00178622
598#elif defined DDR_8BANKS
599	.word	0x00178632
600#else
601#error "Unknown DDR configuration!!!"
602#endif
603SDTIM0:
604	.word	0x20000010
605SDTIM0_VAL_162MHz:
606	.word	0x28923211
607SDTIM1:
608	.word	0x20000014
609SDTIM1_VAL_162MHz:
610	.word	0x0016c722
611VTPIOCR:
612	.word	0x200000f0	/* VTP IO Control register */
613DDRVTPR:
614	.word	0x01c42030	/* DDR VPTR MMR */
615VTP_MMR0:
616	.word	0x201f
617VTP_MMR1:
618	.word	0xa01f
619DFT_ENABLE:
620	.word	0x01c4004c
621VTP_LOCK_COUNT:
622	.word	0x5b0
623VTP_MASK:
624	.word	0xffffdfff
625VTP_RECAL:
626	.word	0x08000
627VTP_EN:
628	.word	0x02000
629CFGTEST:
630	.word	0x80010000
631MASK_VAL:
632	.word	0x00000fff
633
634/* GEM Power Up & LPSC Control Register */
635MDCTL_GEM:
636	.word	0x01c41a9c
637MDSTAT_GEM:
638	.word	0x01c4189c
639
640/* For WDT reset chip bug */
641P1394:
642	.word	0x01c41a20
643
644PLL_CLKSRC_MASK:
645	.word	0xfffffeff	/* Mask the Clock Mode bit */
646PLL_ENSRC_MASK:
647	.word	0xffffffdf	/* Select the PLLEN source */
648PLL_BYPASS_MASK:
649	.word	0xfffffffe	/* Put the PLL in BYPASS */
650PLL_RESET_MASK:
651	.word	0xfffffff7	/* Put the PLL in Reset Mode */
652PLL_PWRUP_MASK:
653	.word	0xfffffffd	/* PLL Power up Mask Bit  */
654PLL_DISABLE_ENABLE_MASK:
655	.word	0xffffffef	/* Enable the PLL from Disable */
656PLL_LOCK_COUNT:
657	.word	0x2000
658
659/* PLL1-SYSTEM PLL MMRs */
660PLL1_CTL:
661	.word	0x01c40900
662PLL1_PLLM:
663	.word	0x01c40910
664
665/* PLL2-SYSTEM PLL MMRs */
666PLL2_CTL:
667	.word	0x01c40d00
668PLL2_PLLM:
669	.word	0x01c40d10
670PLL2_DIV1:
671	.word	0x01c40d18
672PLL2_DIV2:
673	.word	0x01c40d1c
674PLL2_PLLCMD:
675	.word	0x01c40d38
676PLL2_PLLSTAT:
677	.word	0x01c40d3c
678PLL2_DIV_MASK:
679	.word	0xffff7fff
680
681MMARG_BRF0:
682	.word	0x01c42010	/* BRF margin mode 0 (R/W)*/
683MMARG_BRF0_VAL:
684	.word	0x00444400
685
686DDR2_START_ADDR:
687	.word	0x80000000
688DUMMY_VAL:
689	.word	0xa55aa55a
690#else /* CONFIG_SOC_DM644X */
691	mov pc, lr
692#endif
693