1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
4 */
5
6 #include <common.h>
7 #include <asm/io.h>
8 #include <asm/arch/clock.h>
9 #include <asm/arch/gp_padctrl.h>
10 #include <asm/arch/pinmux.h>
11 #include <asm/arch/tegra.h>
12 #include <asm/arch-tegra/clk_rst.h>
13 #include <asm/arch-tegra/pmc.h>
14 #include <asm/arch-tegra/scu.h>
15 #include "cpu.h"
16
get_num_cpus(void)17 int get_num_cpus(void)
18 {
19 struct apb_misc_gp_ctlr *gp;
20 uint rev;
21 debug("%s entry\n", __func__);
22
23 gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
24 rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
25
26 switch (rev) {
27 case CHIPID_TEGRA20:
28 return 2;
29 break;
30 case CHIPID_TEGRA30:
31 case CHIPID_TEGRA114:
32 case CHIPID_TEGRA124:
33 case CHIPID_TEGRA210:
34 default:
35 return 4;
36 break;
37 }
38 }
39
40 /*
41 * Timing tables for each SOC for all four oscillator options.
42 */
43 struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
44 /*
45 * T20: 1 GHz
46 *
47 * Register Field Bits Width
48 * ------------------------------
49 * PLLX_BASE p 22:20 3
50 * PLLX_BASE n 17: 8 10
51 * PLLX_BASE m 4: 0 5
52 * PLLX_MISC cpcon 11: 8 4
53 */
54 {
55 { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
56 { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
57 { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
58 { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
59 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
60 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
61 },
62 /*
63 * T25: 1.2 GHz
64 *
65 * Register Field Bits Width
66 * ------------------------------
67 * PLLX_BASE p 22:20 3
68 * PLLX_BASE n 17: 8 10
69 * PLLX_BASE m 4: 0 5
70 * PLLX_MISC cpcon 11: 8 4
71 */
72 {
73 { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
74 { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
75 { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
76 { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
77 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
78 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
79 },
80 /*
81 * T30: 600 MHz
82 *
83 * Register Field Bits Width
84 * ------------------------------
85 * PLLX_BASE p 22:20 3
86 * PLLX_BASE n 17: 8 10
87 * PLLX_BASE m 4: 0 5
88 * PLLX_MISC cpcon 11: 8 4
89 */
90 {
91 { .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
92 { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
93 { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
94 { .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
95 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
96 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
97 },
98 /*
99 * T114: 700 MHz
100 *
101 * Register Field Bits Width
102 * ------------------------------
103 * PLLX_BASE p 23:20 4
104 * PLLX_BASE n 15: 8 8
105 * PLLX_BASE m 7: 0 8
106 */
107 {
108 { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
109 { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
110 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
111 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
112 { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */
113 { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */
114 },
115
116 /*
117 * T124: 700 MHz
118 *
119 * Register Field Bits Width
120 * ------------------------------
121 * PLLX_BASE p 23:20 4
122 * PLLX_BASE n 15: 8 8
123 * PLLX_BASE m 7: 0 8
124 */
125 {
126 { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
127 { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
128 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
129 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
130 { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */
131 { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */
132 },
133
134 /*
135 * T210: 700 MHz
136 *
137 * Register Field Bits Width
138 * ------------------------------
139 * PLLX_BASE p 24:20 5
140 * PLLX_BASE n 15: 8 8
141 * PLLX_BASE m 7: 0 8
142 */
143 {
144 { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702 MHz*/
145 { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/
146 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz*/
147 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz*/
148 { .n = 36, .m = 1, .p = 1 }, /* OSC: 38.4 MHz = 691.2 MHz */
149 { .n = 58, .m = 2, .p = 1 }, /* OSC: 48.0 MHz = 696 MHz */
150 },
151 };
152
pllx_set_iddq(void)153 static inline void pllx_set_iddq(void)
154 {
155 #if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
156 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
157 u32 reg;
158 debug("%s entry\n", __func__);
159
160 /* Disable IDDQ */
161 reg = readl(&clkrst->crc_pllx_misc3);
162 reg &= ~PLLX_IDDQ_MASK;
163 writel(reg, &clkrst->crc_pllx_misc3);
164 udelay(2);
165 debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__,
166 readl(&clkrst->crc_pllx_misc3));
167 #endif
168 }
169
pllx_set_rate(struct clk_pll_simple * pll,u32 divn,u32 divm,u32 divp,u32 cpcon)170 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
171 u32 divp, u32 cpcon)
172 {
173 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU];
174 int chip = tegra_get_chip();
175 u32 reg;
176 debug("%s entry\n", __func__);
177
178 /* If PLLX is already enabled, just return */
179 if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
180 debug("%s: PLLX already enabled, returning\n", __func__);
181 return 0;
182 }
183
184 pllx_set_iddq();
185
186 /* Set BYPASS, m, n and p to PLLX_BASE */
187 reg = PLL_BYPASS_MASK | (divm << pllinfo->m_shift);
188 reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift);
189 writel(reg, &pll->pll_base);
190
191 /* Set cpcon to PLLX_MISC */
192 if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
193 reg = (cpcon << pllinfo->kcp_shift);
194 else
195 reg = 0;
196
197 /*
198 * TODO(twarren@nvidia.com) Check which SoCs use DCCON
199 * and add to pllinfo table if needed!
200 */
201 /* Set dccon to PLLX_MISC if freq > 600MHz */
202 if (divn > 600)
203 reg |= (1 << PLL_DCCON_SHIFT);
204 writel(reg, &pll->pll_misc);
205
206 /* Disable BYPASS */
207 reg = readl(&pll->pll_base);
208 reg &= ~PLL_BYPASS_MASK;
209 writel(reg, &pll->pll_base);
210 debug("%s: base = 0x%08X\n", __func__, reg);
211
212 /* Set lock_enable to PLLX_MISC if lock_ena is valid (i.e. 0-31) */
213 reg = readl(&pll->pll_misc);
214 if (pllinfo->lock_ena < 32)
215 reg |= (1 << pllinfo->lock_ena);
216 writel(reg, &pll->pll_misc);
217 debug("%s: misc = 0x%08X\n", __func__, reg);
218
219 /* Enable PLLX last, once it's all configured */
220 reg = readl(&pll->pll_base);
221 reg |= PLL_ENABLE_MASK;
222 writel(reg, &pll->pll_base);
223 debug("%s: base final = 0x%08X\n", __func__, reg);
224
225 return 0;
226 }
227
init_pllx(void)228 void init_pllx(void)
229 {
230 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
231 struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
232 int soc_type, sku_info, chip_sku;
233 enum clock_osc_freq osc;
234 struct clk_pll_table *sel;
235 debug("%s entry\n", __func__);
236
237 /* get SOC (chip) type */
238 soc_type = tegra_get_chip();
239 debug("%s: SoC = 0x%02X\n", __func__, soc_type);
240
241 /* get SKU info */
242 sku_info = tegra_get_sku_info();
243 debug("%s: SKU info byte = 0x%02X\n", __func__, sku_info);
244
245 /* get chip SKU, combo of the above info */
246 chip_sku = tegra_get_chip_sku();
247 debug("%s: Chip SKU = %d\n", __func__, chip_sku);
248
249 /* get osc freq */
250 osc = clock_get_osc_freq();
251 debug("%s: osc = %d\n", __func__, osc);
252
253 /* set pllx */
254 sel = &tegra_pll_x_table[chip_sku][osc];
255 pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
256 }
257
enable_cpu_clock(int enable)258 void enable_cpu_clock(int enable)
259 {
260 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
261 u32 clk;
262 debug("%s entry\n", __func__);
263
264 /*
265 * NOTE:
266 * Regardless of whether the request is to enable or disable the CPU
267 * clock, every processor in the CPU complex except the master (CPU 0)
268 * will have it's clock stopped because the AVP only talks to the
269 * master.
270 */
271
272 if (enable) {
273 /* Initialize PLLX */
274 init_pllx();
275
276 /* Wait until all clocks are stable */
277 udelay(PLL_STABILIZATION_DELAY);
278
279 writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
280 writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
281 }
282
283 /*
284 * Read the register containing the individual CPU clock enables and
285 * always stop the clocks to CPUs > 0.
286 */
287 clk = readl(&clkrst->crc_clk_cpu_cmplx);
288 clk |= 1 << CPU1_CLK_STP_SHIFT;
289 if (get_num_cpus() == 4)
290 clk |= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT);
291
292 /* Stop/Unstop the CPU clock */
293 clk &= ~CPU0_CLK_STP_MASK;
294 clk |= !enable << CPU0_CLK_STP_SHIFT;
295 writel(clk, &clkrst->crc_clk_cpu_cmplx);
296
297 clock_enable(PERIPH_ID_CPU);
298 }
299
is_cpu_powered(void)300 static int is_cpu_powered(void)
301 {
302 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
303
304 return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
305 }
306
remove_cpu_io_clamps(void)307 static void remove_cpu_io_clamps(void)
308 {
309 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
310 u32 reg;
311 debug("%s entry\n", __func__);
312
313 /* Remove the clamps on the CPU I/O signals */
314 reg = readl(&pmc->pmc_remove_clamping);
315 reg |= CPU_CLMP;
316 writel(reg, &pmc->pmc_remove_clamping);
317
318 /* Give I/O signals time to stabilize */
319 udelay(IO_STABILIZATION_DELAY);
320 }
321
powerup_cpu(void)322 void powerup_cpu(void)
323 {
324 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
325 u32 reg;
326 int timeout = IO_STABILIZATION_DELAY;
327 debug("%s entry\n", __func__);
328
329 if (!is_cpu_powered()) {
330 /* Toggle the CPU power state (OFF -> ON) */
331 reg = readl(&pmc->pmc_pwrgate_toggle);
332 reg &= PARTID_CP;
333 reg |= START_CP;
334 writel(reg, &pmc->pmc_pwrgate_toggle);
335
336 /* Wait for the power to come up */
337 while (!is_cpu_powered()) {
338 if (timeout-- == 0)
339 printf("CPU failed to power up!\n");
340 else
341 udelay(10);
342 }
343
344 /*
345 * Remove the I/O clamps from CPU power partition.
346 * Recommended only on a Warm boot, if the CPU partition gets
347 * power gated. Shouldn't cause any harm when called after a
348 * cold boot according to HW, probably just redundant.
349 */
350 remove_cpu_io_clamps();
351 }
352 }
353
reset_A9_cpu(int reset)354 void reset_A9_cpu(int reset)
355 {
356 /*
357 * NOTE: Regardless of whether the request is to hold the CPU in reset
358 * or take it out of reset, every processor in the CPU complex
359 * except the master (CPU 0) will be held in reset because the
360 * AVP only talks to the master. The AVP does not know that there
361 * are multiple processors in the CPU complex.
362 */
363 int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
364 int num_cpus = get_num_cpus();
365 int cpu;
366
367 debug("%s entry\n", __func__);
368 /* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
369 for (cpu = 1; cpu < num_cpus; cpu++)
370 reset_cmplx_set_enable(cpu, mask, 1);
371 reset_cmplx_set_enable(0, mask, reset);
372
373 /* Enable/Disable master CPU reset */
374 reset_set_enable(PERIPH_ID_CPU, reset);
375 }
376
clock_enable_coresight(int enable)377 void clock_enable_coresight(int enable)
378 {
379 u32 rst, src = 2;
380
381 debug("%s entry\n", __func__);
382 clock_set_enable(PERIPH_ID_CORESIGHT, enable);
383 reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
384
385 if (enable) {
386 /*
387 * Put CoreSight on PLLP_OUT0 and divide it down as per
388 * PLLP base frequency based on SoC type (T20/T30+).
389 * Clock divider request would setup CSITE clock as 144MHz
390 * for PLLP base 216MHz and 204MHz for PLLP base 408MHz
391 */
392 src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ);
393 clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
394
395 /* Unlock the CPU CoreSight interfaces */
396 rst = CORESIGHT_UNLOCK;
397 writel(rst, CSITE_CPU_DBG0_LAR);
398 writel(rst, CSITE_CPU_DBG1_LAR);
399 if (get_num_cpus() == 4) {
400 writel(rst, CSITE_CPU_DBG2_LAR);
401 writel(rst, CSITE_CPU_DBG3_LAR);
402 }
403 }
404 }
405
halt_avp(void)406 void halt_avp(void)
407 {
408 debug("%s entry\n", __func__);
409
410 for (;;) {
411 writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29),
412 FLOW_CTLR_HALT_COP_EVENTS);
413 }
414 }
415