1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. 4 */ 5 /* 6 * mpc8313epb board configuration file 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 16 #define CONFIG_MPC831x 1 17 #define CONFIG_MPC8313 1 18 #define CONFIG_MPC8313ERDB 1 19 20 #ifdef CONFIG_NAND 21 #define CONFIG_SPL_INIT_MINIMAL 22 #define CONFIG_SPL_FLUSH_IMAGE 23 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 24 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND 25 26 #ifdef CONFIG_SPL_BUILD 27 #define CONFIG_NS16550_MIN_FUNCTIONS 28 #endif 29 30 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 31 #define CONFIG_SPL_MAX_SIZE (4 * 1024) 32 #define CONFIG_SPL_PAD_TO 0x4000 33 34 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 35 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 36 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 37 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 38 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 39 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) 40 41 #ifdef CONFIG_SPL_BUILD 42 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 43 #endif 44 45 #endif /* CONFIG_NAND */ 46 47 #ifndef CONFIG_SYS_MONITOR_BASE 48 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 49 #endif 50 51 #define CONFIG_PCI_INDIRECT_BRIDGE 52 #define CONFIG_FSL_ELBC 1 53 54 /* 55 * On-board devices 56 * 57 * TSEC1 is VSC switch 58 * TSEC2 is SoC TSEC 59 */ 60 #define CONFIG_VSC7385_ENET 61 #define CONFIG_TSEC2 62 63 #ifdef CONFIG_SYS_66MHZ 64 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 65 #elif defined(CONFIG_SYS_33MHZ) 66 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 67 #else 68 #error Unknown oscillator frequency. 69 #endif 70 71 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 72 73 #define CONFIG_SYS_IMMR 0xE0000000 74 75 #if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD) 76 #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR 77 #endif 78 79 #define CONFIG_SYS_MEMTEST_START 0x00001000 80 #define CONFIG_SYS_MEMTEST_END 0x07f00000 81 82 /* Early revs of this board will lock up hard when attempting 83 * to access the PMC registers, unless a JTAG debugger is 84 * connected, or some resistor modifications are made. 85 */ 86 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 87 88 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 89 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 90 91 /* 92 * Device configurations 93 */ 94 95 /* Vitesse 7385 */ 96 97 #ifdef CONFIG_VSC7385_ENET 98 99 #define CONFIG_TSEC1 100 101 /* The flash address and size of the VSC7385 firmware image */ 102 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 103 #define CONFIG_VSC7385_IMAGE_SIZE 8192 104 105 #endif 106 107 /* 108 * DDR Setup 109 */ 110 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 111 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 112 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 113 114 /* 115 * Manually set up DDR parameters, as this board does not 116 * seem to have the SPD connected to I2C. 117 */ 118 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 119 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 120 | CSCONFIG_ODT_RD_NEVER \ 121 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 122 | CSCONFIG_ROW_BIT_13 \ 123 | CSCONFIG_COL_BIT_10) 124 /* 0x80010102 */ 125 126 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 127 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 128 | (0 << TIMING_CFG0_WRT_SHIFT) \ 129 | (0 << TIMING_CFG0_RRT_SHIFT) \ 130 | (0 << TIMING_CFG0_WWT_SHIFT) \ 131 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 132 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 133 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 134 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 135 /* 0x00220802 */ 136 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 137 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 138 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 139 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 140 | (10 << TIMING_CFG1_REFREC_SHIFT) \ 141 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 142 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 143 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 144 /* 0x3835a322 */ 145 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 146 | (5 << TIMING_CFG2_CPO_SHIFT) \ 147 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 148 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 149 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 150 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 151 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) 152 /* 0x129048c6 */ /* P9-45,may need tuning */ 153 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \ 154 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 155 /* 0x05100500 */ 156 #if defined(CONFIG_DDR_2T_TIMING) 157 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 158 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 159 | SDRAM_CFG_DBW_32 \ 160 | SDRAM_CFG_2T_EN) 161 /* 0x43088000 */ 162 #else 163 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 164 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 165 | SDRAM_CFG_DBW_32) 166 /* 0x43080000 */ 167 #endif 168 #define CONFIG_SYS_SDRAM_CFG2 0x00401000 169 /* set burst length to 8 for 32-bit data path */ 170 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ 171 | (0x0632 << SDRAM_MODE_SD_SHIFT)) 172 /* 0x44480632 */ 173 #define CONFIG_SYS_DDR_MODE_2 0x8000C000 174 175 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 176 /*0x02000000*/ 177 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 178 | DDRCDR_PZ_NOMZ \ 179 | DDRCDR_NZ_NOMZ \ 180 | DDRCDR_M_ODR) 181 182 /* 183 * FLASH on the Local Bus 184 */ 185 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 186 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 187 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 188 189 #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 190 | BR_PS_16 /* 16 bit port */ \ 191 | BR_MS_GPCM /* MSEL = GPCM */ \ 192 | BR_V) /* valid */ 193 #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 194 | OR_GPCM_XACS \ 195 | OR_GPCM_SCY_9 \ 196 | OR_GPCM_EHTR \ 197 | OR_GPCM_EAD) 198 /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 199 /* window base at flash base */ 200 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 201 /* 16 MB window size */ 202 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 203 204 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 205 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ 206 207 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 208 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 209 210 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \ 211 !defined(CONFIG_SPL_BUILD) 212 #define CONFIG_SYS_RAMBOOT 213 #endif 214 215 #define CONFIG_SYS_INIT_RAM_LOCK 1 216 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 217 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 218 219 #define CONFIG_SYS_GBL_DATA_OFFSET \ 220 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 221 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 222 223 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 224 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 225 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 226 227 /* 228 * Local Bus LCRR and LBCR regs 229 */ 230 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 231 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 232 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ 233 | (0xFF << LBCR_BMT_SHIFT) \ 234 | 0xF) /* 0x0004ff0f */ 235 236 /* LB refresh timer prescal, 266MHz/32 */ 237 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ 238 239 /* drivers/mtd/nand/raw/nand.c */ 240 #if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD) 241 #define CONFIG_SYS_NAND_BASE 0xFFF00000 242 #else 243 #define CONFIG_SYS_NAND_BASE 0xE2800000 244 #endif 245 246 #define CONFIG_MTD_PARTITION 247 248 #define CONFIG_SYS_MAX_NAND_DEVICE 1 249 #define CONFIG_NAND_FSL_ELBC 1 250 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 251 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) 252 253 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 254 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 255 | BR_PS_8 /* 8 bit port */ \ 256 | BR_MS_FCM /* MSEL = FCM */ \ 257 | BR_V) /* valid */ 258 #define CONFIG_SYS_NAND_OR_PRELIM \ 259 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 260 | OR_FCM_CSCT \ 261 | OR_FCM_CST \ 262 | OR_FCM_CHT \ 263 | OR_FCM_SCY_1 \ 264 | OR_FCM_TRLX \ 265 | OR_FCM_EHTR) 266 /* 0xFFFF8396 */ 267 268 #ifdef CONFIG_NAND 269 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM 270 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM 271 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM 272 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM 273 #else 274 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 275 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 276 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 277 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 278 #endif 279 280 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 281 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 282 283 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 284 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 285 286 /* local bus write LED / read status buffer (BCSR) mapping */ 287 #define CONFIG_SYS_BCSR_ADDR 0xFA000000 288 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ 289 /* map at 0xFA000000 on LCS3 */ 290 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \ 291 | BR_PS_8 /* 8 bit port */ \ 292 | BR_MS_GPCM /* MSEL = GPCM */ \ 293 | BR_V) /* valid */ 294 /* 0xFA000801 */ 295 #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \ 296 | OR_GPCM_CSNT \ 297 | OR_GPCM_ACS_DIV2 \ 298 | OR_GPCM_XACS \ 299 | OR_GPCM_SCY_15 \ 300 | OR_GPCM_TRLX_SET \ 301 | OR_GPCM_EHTR_SET \ 302 | OR_GPCM_EAD) 303 /* 0xFFFF8FF7 */ 304 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR 305 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 306 307 /* Vitesse 7385 */ 308 309 #ifdef CONFIG_VSC7385_ENET 310 311 /* VSC7385 Base address on LCS2 */ 312 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 313 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ 314 315 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 316 | BR_PS_8 /* 8 bit port */ \ 317 | BR_MS_GPCM /* MSEL = GPCM */ \ 318 | BR_V) /* valid */ 319 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ 320 | OR_GPCM_CSNT \ 321 | OR_GPCM_XACS \ 322 | OR_GPCM_SCY_15 \ 323 | OR_GPCM_SETA \ 324 | OR_GPCM_TRLX_SET \ 325 | OR_GPCM_EHTR_SET \ 326 | OR_GPCM_EAD) 327 /* 0xFFFE09FF */ 328 329 /* Access window base at VSC7385 base */ 330 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 331 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 332 333 #endif 334 335 #define CONFIG_MPC83XX_GPIO 1 336 337 /* 338 * Serial Port 339 */ 340 #define CONFIG_SYS_NS16550_SERIAL 341 #define CONFIG_SYS_NS16550_REG_SIZE 1 342 343 #define CONFIG_SYS_BAUDRATE_TABLE \ 344 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 345 346 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 347 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 348 349 /* I2C */ 350 #define CONFIG_SYS_I2C 351 #define CONFIG_SYS_I2C_FSL 352 #define CONFIG_SYS_FSL_I2C_SPEED 400000 353 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 354 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 355 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 356 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 357 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 358 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 359 360 /* 361 * General PCI 362 * Addresses are mapped 1-1. 363 */ 364 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 365 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 366 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 367 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 368 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 369 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 370 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 371 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 372 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 373 374 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 375 376 /* 377 * TSEC 378 */ 379 380 #define CONFIG_GMII /* MII PHY management */ 381 382 #ifdef CONFIG_TSEC1 383 #define CONFIG_HAS_ETH0 384 #define CONFIG_TSEC1_NAME "TSEC0" 385 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 386 #define TSEC1_PHY_ADDR 0x1c 387 #define TSEC1_FLAGS TSEC_GIGABIT 388 #define TSEC1_PHYIDX 0 389 #endif 390 391 #ifdef CONFIG_TSEC2 392 #define CONFIG_HAS_ETH1 393 #define CONFIG_TSEC2_NAME "TSEC1" 394 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 395 #define TSEC2_PHY_ADDR 4 396 #define TSEC2_FLAGS TSEC_GIGABIT 397 #define TSEC2_PHYIDX 0 398 #endif 399 400 /* Options are: TSEC[0-1] */ 401 #define CONFIG_ETHPRIME "TSEC1" 402 403 /* 404 * Configure on-board RTC 405 */ 406 #define CONFIG_RTC_DS1337 407 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 408 409 /* 410 * Environment 411 */ 412 #if defined(CONFIG_NAND) 413 #define CONFIG_ENV_OFFSET (512 * 1024) 414 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 415 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 416 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 417 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) 418 #define CONFIG_ENV_OFFSET_REDUND \ 419 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) 420 #elif !defined(CONFIG_SYS_RAMBOOT) 421 #define CONFIG_ENV_ADDR \ 422 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 423 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 424 #define CONFIG_ENV_SIZE 0x2000 425 426 /* Address and size of Redundant Environment Sector */ 427 #else 428 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 429 #define CONFIG_ENV_SIZE 0x2000 430 #endif 431 432 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 433 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 434 435 /* 436 * BOOTP options 437 */ 438 #define CONFIG_BOOTP_BOOTFILESIZE 439 440 /* 441 * Command line configuration. 442 */ 443 444 /* 445 * Miscellaneous configurable options 446 */ 447 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 448 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 449 450 /* Boot Argument Buffer Size */ 451 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 452 453 /* 454 * For booting Linux, the board info and command line data 455 * have to be in the first 256 MB of memory, since this is 456 * the maximum mapped by the Linux kernel during initialization. 457 */ 458 /* Initial Memory map for Linux*/ 459 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 460 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 461 462 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 463 464 #ifdef CONFIG_SYS_66MHZ 465 466 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 467 /* 0x62040000 */ 468 #define CONFIG_SYS_HRCW_LOW (\ 469 0x20000000 /* reserved, must be set */ |\ 470 HRCWL_DDRCM |\ 471 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 472 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 473 HRCWL_CSB_TO_CLKIN_2X1 |\ 474 HRCWL_CORE_TO_CSB_2X1) 475 476 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 477 478 #elif defined(CONFIG_SYS_33MHZ) 479 480 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 481 /* 0x65040000 */ 482 #define CONFIG_SYS_HRCW_LOW (\ 483 0x20000000 /* reserved, must be set */ |\ 484 HRCWL_DDRCM |\ 485 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 486 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 487 HRCWL_CSB_TO_CLKIN_5X1 |\ 488 HRCWL_CORE_TO_CSB_2X1) 489 490 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) 491 492 #endif 493 494 #define CONFIG_SYS_HRCW_HIGH_BASE (\ 495 HRCWH_PCI_HOST |\ 496 HRCWH_PCI1_ARBITER_ENABLE |\ 497 HRCWH_CORE_ENABLE |\ 498 HRCWH_BOOTSEQ_DISABLE |\ 499 HRCWH_SW_WATCHDOG_DISABLE |\ 500 HRCWH_TSEC1M_IN_RGMII |\ 501 HRCWH_TSEC2M_IN_RGMII |\ 502 HRCWH_BIG_ENDIAN) 503 504 #ifdef CONFIG_NAND 505 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 506 HRCWH_FROM_0XFFF00100 |\ 507 HRCWH_ROM_LOC_NAND_SP_8BIT |\ 508 HRCWH_RL_EXT_NAND) 509 #else 510 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 511 HRCWH_FROM_0X00000100 |\ 512 HRCWH_ROM_LOC_LOCAL_16BIT |\ 513 HRCWH_RL_EXT_LEGACY) 514 #endif 515 516 /* System IO Config */ 517 #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 518 /* Enable Internal USB Phy and GPIO on LCD Connector */ 519 #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC) 520 521 #define CONFIG_SYS_HID0_INIT 0x000000000 522 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 523 HID0_ENABLE_INSTRUCTION_CACHE | \ 524 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 525 526 #define CONFIG_SYS_HID2 HID2_HBE 527 528 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 529 530 /* DDR @ 0x00000000 */ 531 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) 532 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 533 | BATU_BL_256M \ 534 | BATU_VS \ 535 | BATU_VP) 536 537 /* PCI @ 0x80000000 */ 538 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) 539 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 540 | BATU_BL_256M \ 541 | BATU_VS \ 542 | BATU_VP) 543 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 544 | BATL_PP_RW \ 545 | BATL_CACHEINHIBIT \ 546 | BATL_GUARDEDSTORAGE) 547 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 548 | BATU_BL_256M \ 549 | BATU_VS \ 550 | BATU_VP) 551 552 /* PCI2 not supported on 8313 */ 553 #define CONFIG_SYS_IBAT3L (0) 554 #define CONFIG_SYS_IBAT3U (0) 555 #define CONFIG_SYS_IBAT4L (0) 556 #define CONFIG_SYS_IBAT4U (0) 557 558 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 559 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 560 | BATL_PP_RW \ 561 | BATL_CACHEINHIBIT \ 562 | BATL_GUARDEDSTORAGE) 563 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 564 | BATU_BL_256M \ 565 | BATU_VS \ 566 | BATU_VP) 567 568 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 569 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 570 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 571 572 #define CONFIG_SYS_IBAT7L (0) 573 #define CONFIG_SYS_IBAT7U (0) 574 575 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 576 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 577 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 578 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 579 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 580 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 581 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 582 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 583 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 584 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 585 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 586 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 587 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 588 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 589 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 590 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 591 592 /* 593 * Environment Configuration 594 */ 595 #define CONFIG_ENV_OVERWRITE 596 597 #define CONFIG_NETDEV "eth1" 598 599 #define CONFIG_HOSTNAME "mpc8313erdb" 600 #define CONFIG_ROOTPATH "/nfs/root/path" 601 #define CONFIG_BOOTFILE "uImage" 602 /* U-Boot image on TFTP server */ 603 #define CONFIG_UBOOTPATH "u-boot.bin" 604 #define CONFIG_FDTFILE "mpc8313erdb.dtb" 605 606 /* default location for tftp and bootm */ 607 #define CONFIG_LOADADDR 800000 608 609 #define CONFIG_EXTRA_ENV_SETTINGS \ 610 "netdev=" CONFIG_NETDEV "\0" \ 611 "ethprime=TSEC1\0" \ 612 "uboot=" CONFIG_UBOOTPATH "\0" \ 613 "tftpflash=tftpboot $loadaddr $uboot; " \ 614 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 615 " +$filesize; " \ 616 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 617 " +$filesize; " \ 618 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 619 " $filesize; " \ 620 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 621 " +$filesize; " \ 622 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 623 " $filesize\0" \ 624 "fdtaddr=780000\0" \ 625 "fdtfile=" CONFIG_FDTFILE "\0" \ 626 "console=ttyS0\0" \ 627 "setbootargs=setenv bootargs " \ 628 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 629 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 630 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ 631 "$netdev:off " \ 632 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 633 634 #define CONFIG_NFSBOOTCOMMAND \ 635 "setenv rootdev /dev/nfs;" \ 636 "run setbootargs;" \ 637 "run setipargs;" \ 638 "tftp $loadaddr $bootfile;" \ 639 "tftp $fdtaddr $fdtfile;" \ 640 "bootm $loadaddr - $fdtaddr" 641 642 #define CONFIG_RAMBOOTCOMMAND \ 643 "setenv rootdev /dev/ram;" \ 644 "run setbootargs;" \ 645 "tftp $ramdiskaddr $ramdiskfile;" \ 646 "tftp $loadaddr $bootfile;" \ 647 "tftp $fdtaddr $fdtfile;" \ 648 "bootm $loadaddr $ramdiskaddr $fdtaddr" 649 650 #endif /* __CONFIG_H */ 651