1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2002 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 */ 6 7 #include <common.h> 8 9 /* 10 * CPU test 11 * 12 * This test checks the arithmetic logic unit (ALU) of CPU. 13 * It tests independently various groups of instructions using 14 * run-time modification of the code to reduce the memory footprint. 15 * For more details refer to post/cpu/ *.c files. 16 */ 17 18 #include <watchdog.h> 19 #include <post.h> 20 #include <asm/mmu.h> 21 22 #if CONFIG_POST & CONFIG_SYS_POST_CPU 23 24 extern int cpu_post_test_cmp (void); 25 extern int cpu_post_test_cmpi (void); 26 extern int cpu_post_test_two (void); 27 extern int cpu_post_test_twox (void); 28 extern int cpu_post_test_three (void); 29 extern int cpu_post_test_threex (void); 30 extern int cpu_post_test_threei (void); 31 extern int cpu_post_test_andi (void); 32 extern int cpu_post_test_srawi (void); 33 extern int cpu_post_test_rlwnm (void); 34 extern int cpu_post_test_rlwinm (void); 35 extern int cpu_post_test_rlwimi (void); 36 extern int cpu_post_test_store (void); 37 extern int cpu_post_test_load (void); 38 extern int cpu_post_test_cr (void); 39 extern int cpu_post_test_b (void); 40 extern int cpu_post_test_multi (void); 41 extern int cpu_post_test_string (void); 42 extern int cpu_post_test_complex (void); 43 cpu_post_makecr(long v)44ulong cpu_post_makecr (long v) 45 { 46 ulong cr = 0; 47 48 if (v < 0) 49 cr |= 0x80000000; 50 if (v > 0) 51 cr |= 0x40000000; 52 if (v == 0) 53 cr |= 0x20000000; 54 55 return cr; 56 } 57 cpu_post_test(int flags)58int cpu_post_test (int flags) 59 { 60 int ic = icache_status (); 61 int ret = 0; 62 63 WATCHDOG_RESET(); 64 if (ic) 65 icache_disable (); 66 67 if (ret == 0) 68 ret = cpu_post_test_cmp (); 69 if (ret == 0) 70 ret = cpu_post_test_cmpi (); 71 if (ret == 0) 72 ret = cpu_post_test_two (); 73 if (ret == 0) 74 ret = cpu_post_test_twox (); 75 WATCHDOG_RESET(); 76 if (ret == 0) 77 ret = cpu_post_test_three (); 78 if (ret == 0) 79 ret = cpu_post_test_threex (); 80 if (ret == 0) 81 ret = cpu_post_test_threei (); 82 if (ret == 0) 83 ret = cpu_post_test_andi (); 84 WATCHDOG_RESET(); 85 if (ret == 0) 86 ret = cpu_post_test_srawi (); 87 if (ret == 0) 88 ret = cpu_post_test_rlwnm (); 89 if (ret == 0) 90 ret = cpu_post_test_rlwinm (); 91 if (ret == 0) 92 ret = cpu_post_test_rlwimi (); 93 WATCHDOG_RESET(); 94 if (ret == 0) 95 ret = cpu_post_test_store (); 96 if (ret == 0) 97 ret = cpu_post_test_load (); 98 if (ret == 0) 99 ret = cpu_post_test_cr (); 100 if (ret == 0) 101 ret = cpu_post_test_b (); 102 WATCHDOG_RESET(); 103 if (ret == 0) 104 ret = cpu_post_test_multi (); 105 WATCHDOG_RESET(); 106 if (ret == 0) 107 ret = cpu_post_test_string (); 108 if (ret == 0) 109 ret = cpu_post_test_complex (); 110 WATCHDOG_RESET(); 111 112 if (ic) 113 icache_enable (); 114 115 WATCHDOG_RESET(); 116 117 return ret; 118 } 119 120 #endif /* CONFIG_POST & CONFIG_SYS_POST_CPU */ 121