1 /*
2 * QEMU M48T59 and M48T08 NVRAM emulation (common header)
3 *
4 * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
5 * Copyright (c) 2013 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #ifndef HW_M48T59_INTERNAL_H
27 #define HW_M48T59_INTERNAL_H
28
29 /*
30 * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
31 * alarm and a watchdog timer and related control registers. In the
32 * PPC platform there is also a nvram lock function.
33 */
34
35 typedef struct M48txxInfo {
36 const char *bus_name;
37 uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
38 uint32_t size;
39 } M48txxInfo;
40
41 typedef struct M48t59State {
42 /* Hardware parameters */
43 qemu_irq IRQ;
44 MemoryRegion iomem;
45 uint32_t size;
46 int32_t base_year;
47 /* RTC management */
48 time_t time_offset;
49 time_t stop_time;
50 /* Alarm & watchdog */
51 struct tm alarm;
52 QEMUTimer *alrm_timer;
53 QEMUTimer *wd_timer;
54 /* NVRAM storage */
55 uint8_t *buffer;
56 /* Model parameters */
57 uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
58 /* NVRAM storage */
59 uint16_t addr;
60 uint8_t lock;
61 } M48t59State;
62
63 uint32_t m48t59_read(M48t59State *NVRAM, uint32_t addr);
64 void m48t59_write(M48t59State *NVRAM, uint32_t addr, uint32_t val);
65 void m48t59_reset_common(M48t59State *NVRAM);
66 void m48t59_realize_common(M48t59State *s, Error **errp);
67
m48t59_toggle_lock(M48t59State * NVRAM,int lock)68 static inline void m48t59_toggle_lock(M48t59State *NVRAM, int lock)
69 {
70 NVRAM->lock ^= 1 << lock;
71 }
72
73 extern const MemoryRegionOps m48t59_io_ops;
74
75 #endif /* HW_M48T59_INTERNAL_H */
76