1 /** @file 2 This file contains definitions for SPD DDR3. 3 4 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> 5 SPDX-License-Identifier: BSD-2-Clause-Patent 6 7 @par Revision Reference: 8 - Serial Presence Detect (SPD) for DDR3 SDRAM Modules Document Release 6 9 http://www.jedec.org/sites/default/files/docs/4_01_02_11R21A.pdf 10 **/ 11 12 #ifndef _SDRAM_SPD_DDR3_H_ 13 #define _SDRAM_SPD_DDR3_H_ 14 15 #pragma pack (push, 1) 16 17 typedef union { 18 struct { 19 UINT8 BytesUsed : 4; ///< Bits 3:0 20 UINT8 BytesTotal : 3; ///< Bits 6:4 21 UINT8 CrcCoverage : 1; ///< Bits 7:7 22 } Bits; 23 UINT8 Data; 24 } SPD3_DEVICE_DESCRIPTION_STRUCT; 25 26 typedef union { 27 struct { 28 UINT8 Minor : 4; ///< Bits 3:0 29 UINT8 Major : 4; ///< Bits 7:4 30 } Bits; 31 UINT8 Data; 32 } SPD3_REVISION_STRUCT; 33 34 typedef union { 35 struct { 36 UINT8 Type : 8; ///< Bits 7:0 37 } Bits; 38 UINT8 Data; 39 } SPD3_DRAM_DEVICE_TYPE_STRUCT; 40 41 typedef union { 42 struct { 43 UINT8 ModuleType : 4; ///< Bits 3:0 44 UINT8 Reserved : 4; ///< Bits 7:4 45 } Bits; 46 UINT8 Data; 47 } SPD3_MODULE_TYPE_STRUCT; 48 49 typedef union { 50 struct { 51 UINT8 Density : 4; ///< Bits 3:0 52 UINT8 BankAddress : 3; ///< Bits 6:4 53 UINT8 Reserved : 1; ///< Bits 7:7 54 } Bits; 55 UINT8 Data; 56 } SPD3_SDRAM_DENSITY_BANKS_STRUCT; 57 58 typedef union { 59 struct { 60 UINT8 ColumnAddress : 3; ///< Bits 2:0 61 UINT8 RowAddress : 3; ///< Bits 5:3 62 UINT8 Reserved : 2; ///< Bits 7:6 63 } Bits; 64 UINT8 Data; 65 } SPD3_SDRAM_ADDRESSING_STRUCT; 66 67 typedef union { 68 struct { 69 UINT8 OperationAt1_50 : 1; ///< Bits 0:0 70 UINT8 OperationAt1_35 : 1; ///< Bits 1:1 71 UINT8 OperationAt1_25 : 1; ///< Bits 2:2 72 UINT8 Reserved : 5; ///< Bits 7:3 73 } Bits; 74 UINT8 Data; 75 } SPD3_MODULE_NOMINAL_VOLTAGE_STRUCT; 76 77 typedef union { 78 struct { 79 UINT8 SdramDeviceWidth : 3; ///< Bits 2:0 80 UINT8 RankCount : 3; ///< Bits 5:3 81 UINT8 Reserved : 2; ///< Bits 7:6 82 } Bits; 83 UINT8 Data; 84 } SPD3_MODULE_ORGANIZATION_STRUCT; 85 86 typedef union { 87 struct { 88 UINT8 PrimaryBusWidth : 3; ///< Bits 2:0 89 UINT8 BusWidthExtension : 2; ///< Bits 4:3 90 UINT8 Reserved : 3; ///< Bits 7:5 91 } Bits; 92 UINT8 Data; 93 } SPD3_MODULE_MEMORY_BUS_WIDTH_STRUCT; 94 95 typedef union { 96 struct { 97 UINT8 Divisor : 4; ///< Bits 3:0 98 UINT8 Dividend : 4; ///< Bits 7:4 99 } Bits; 100 UINT8 Data; 101 } SPD3_FINE_TIMEBASE_STRUCT; 102 103 typedef union { 104 struct { 105 UINT8 Dividend : 8; ///< Bits 7:0 106 } Bits; 107 UINT8 Data; 108 } SPD3_MEDIUM_TIMEBASE_DIVIDEND_STRUCT; 109 110 typedef union { 111 struct { 112 UINT8 Divisor : 8; ///< Bits 7:0 113 } Bits; 114 UINT8 Data; 115 } SPD3_MEDIUM_TIMEBASE_DIVISOR_STRUCT; 116 117 typedef struct { 118 SPD3_MEDIUM_TIMEBASE_DIVIDEND_STRUCT Dividend; ///< Medium Timebase (MTB) Dividend 119 SPD3_MEDIUM_TIMEBASE_DIVISOR_STRUCT Divisor; ///< Medium Timebase (MTB) Divisor 120 } SPD3_MEDIUM_TIMEBASE; 121 122 typedef union { 123 struct { 124 UINT8 tCKmin : 8; ///< Bits 7:0 125 } Bits; 126 UINT8 Data; 127 } SPD3_TCK_MIN_MTB_STRUCT; 128 129 typedef union { 130 struct { 131 UINT16 Cl4 : 1; ///< Bits 0:0 132 UINT16 Cl5 : 1; ///< Bits 1:1 133 UINT16 Cl6 : 1; ///< Bits 2:2 134 UINT16 Cl7 : 1; ///< Bits 3:3 135 UINT16 Cl8 : 1; ///< Bits 4:4 136 UINT16 Cl9 : 1; ///< Bits 5:5 137 UINT16 Cl10 : 1; ///< Bits 6:6 138 UINT16 Cl11 : 1; ///< Bits 7:7 139 UINT16 Cl12 : 1; ///< Bits 8:8 140 UINT16 Cl13 : 1; ///< Bits 9:9 141 UINT16 Cl14 : 1; ///< Bits 10:10 142 UINT16 Cl15 : 1; ///< Bits 11:11 143 UINT16 Cl16 : 1; ///< Bits 12:12 144 UINT16 Cl17 : 1; ///< Bits 13:13 145 UINT16 Cl18 : 1; ///< Bits 14:14 146 UINT16 Reserved : 1; ///< Bits 15:15 147 } Bits; 148 UINT16 Data; 149 UINT8 Data8[2]; 150 } SPD3_CAS_LATENCIES_SUPPORTED_STRUCT; 151 152 typedef union { 153 struct { 154 UINT8 tAAmin : 8; ///< Bits 7:0 155 } Bits; 156 UINT8 Data; 157 } SPD3_TAA_MIN_MTB_STRUCT; 158 159 typedef union { 160 struct { 161 UINT8 tWRmin : 8; ///< Bits 7:0 162 } Bits; 163 UINT8 Data; 164 } SPD3_TWR_MIN_MTB_STRUCT; 165 166 typedef union { 167 struct { 168 UINT8 tRCDmin : 8; ///< Bits 7:0 169 } Bits; 170 UINT8 Data; 171 } SPD3_TRCD_MIN_MTB_STRUCT; 172 173 typedef union { 174 struct { 175 UINT8 tRRDmin : 8; ///< Bits 7:0 176 } Bits; 177 UINT8 Data; 178 } SPD3_TRRD_MIN_MTB_STRUCT; 179 180 typedef union { 181 struct { 182 UINT8 tRPmin : 8; ///< Bits 7:0 183 } Bits; 184 UINT8 Data; 185 } SPD3_TRP_MIN_MTB_STRUCT; 186 187 typedef union { 188 struct { 189 UINT8 tRASminUpper : 4; ///< Bits 3:0 190 UINT8 tRCminUpper : 4; ///< Bits 7:4 191 } Bits; 192 UINT8 Data; 193 } SPD3_TRAS_TRC_MIN_MTB_STRUCT; 194 195 typedef union { 196 struct { 197 UINT8 tRASmin : 8; ///< Bits 7:0 198 } Bits; 199 UINT8 Data; 200 } SPD3_TRAS_MIN_MTB_STRUCT; 201 202 typedef union { 203 struct { 204 UINT8 tRCmin : 8; ///< Bits 7:0 205 } Bits; 206 UINT8 Data; 207 } SPD3_TRC_MIN_MTB_STRUCT; 208 209 typedef union { 210 struct { 211 UINT16 tRFCmin : 16; ///< Bits 15:0 212 } Bits; 213 UINT16 Data; 214 UINT8 Data8[2]; 215 } SPD3_TRFC_MIN_MTB_STRUCT; 216 217 typedef union { 218 struct { 219 UINT8 tWTRmin : 8; ///< Bits 7:0 220 } Bits; 221 UINT8 Data; 222 } SPD3_TWTR_MIN_MTB_STRUCT; 223 224 typedef union { 225 struct { 226 UINT8 tRTPmin : 8; ///< Bits 7:0 227 } Bits; 228 UINT8 Data; 229 } SPD3_TRTP_MIN_MTB_STRUCT; 230 231 typedef union { 232 struct { 233 UINT8 tFAWminUpper : 4; ///< Bits 3:0 234 UINT8 Reserved : 4; ///< Bits 7:4 235 } Bits; 236 UINT8 Data; 237 } SPD3_TFAW_MIN_MTB_UPPER_STRUCT; 238 239 typedef union { 240 struct { 241 UINT8 tFAWmin : 8; ///< Bits 7:0 242 } Bits; 243 UINT8 Data; 244 } SPD3_TFAW_MIN_MTB_STRUCT; 245 246 typedef union { 247 struct { 248 UINT8 Rzq6 : 1; ///< Bits 0:0 249 UINT8 Rzq7 : 1; ///< Bits 1:1 250 UINT8 Reserved : 5; ///< Bits 6:2 251 UINT8 DllOff : 1; ///< Bits 7:7 252 } Bits; 253 UINT8 Data; 254 } SPD3_SDRAM_OPTIONAL_FEATURES_STRUCT; 255 256 typedef union { 257 struct { 258 UINT8 ExtendedTemperatureRange : 1; ///< Bits 0:0 259 UINT8 ExtendedTemperatureRefreshRate : 1; ///< Bits 1:1 260 UINT8 AutoSelfRefresh : 1; ///< Bits 2:2 261 UINT8 OnDieThermalSensor : 1; ///< Bits 3:3 262 UINT8 Reserved : 3; ///< Bits 6:4 263 UINT8 PartialArraySelfRefresh : 1; ///< Bits 7:7 264 } Bits; 265 UINT8 Data; 266 } SPD3_SDRAM_THERMAL_REFRESH_STRUCT; 267 268 typedef union { 269 struct { 270 UINT8 ThermalSensorAccuracy : 7; ///< Bits 6:0 271 UINT8 ThermalSensorPresence : 1; ///< Bits 7:7 272 } Bits; 273 UINT8 Data; 274 } SPD3_MODULE_THERMAL_SENSOR_STRUCT; 275 276 typedef union { 277 struct { 278 UINT8 SignalLoading : 2; ///< Bits 1:0 279 UINT8 Reserved : 2; ///< Bits 3:2 280 UINT8 DieCount : 3; ///< Bits 6:4 281 UINT8 SdramDeviceType : 1; ///< Bits 7:7 282 } Bits; 283 UINT8 Data; 284 } SPD3_SDRAM_DEVICE_TYPE_STRUCT; 285 286 typedef union { 287 struct { 288 INT8 tCKminFine : 8; ///< Bits 7:0 289 } Bits; 290 INT8 Data; 291 } SPD3_TCK_MIN_FTB_STRUCT; 292 293 typedef union { 294 struct { 295 INT8 tAAminFine : 8; ///< Bits 7:0 296 } Bits; 297 INT8 Data; 298 } SPD3_TAA_MIN_FTB_STRUCT; 299 300 typedef union { 301 struct { 302 INT8 tRCDminFine : 8; ///< Bits 7:0 303 } Bits; 304 INT8 Data; 305 } SPD3_TRCD_MIN_FTB_STRUCT; 306 307 typedef union { 308 struct { 309 INT8 tRPminFine : 8; ///< Bits 7:0 310 } Bits; 311 INT8 Data; 312 } SPD3_TRP_MIN_FTB_STRUCT; 313 314 typedef union { 315 struct { 316 INT8 tRCminFine : 8; ///< Bits 7:0 317 } Bits; 318 INT8 Data; 319 } SPD3_TRC_MIN_FTB_STRUCT; 320 321 typedef union { 322 struct { 323 UINT8 MaximumActivateCount : 4; ///< Bits 3:0 324 UINT8 MaximumActivateWindow : 2; ///< Bits 5:4 325 UINT8 VendorSpecific : 2; ///< Bits 7:6 326 } Bits; 327 UINT8 Data; 328 } SPD3_MAXIMUM_ACTIVE_COUNT_STRUCT; 329 330 typedef union { 331 struct { 332 UINT8 Height : 5; ///< Bits 4:0 333 UINT8 RawCardExtension : 3; ///< Bits 7:5 334 } Bits; 335 UINT8 Data; 336 } SPD3_UNBUF_MODULE_NOMINAL_HEIGHT; 337 338 typedef union { 339 struct { 340 UINT8 FrontThickness : 4; ///< Bits 3:0 341 UINT8 BackThickness : 4; ///< Bits 7:4 342 } Bits; 343 UINT8 Data; 344 } SPD3_UNBUF_MODULE_NOMINAL_THICKNESS; 345 346 typedef union { 347 struct { 348 UINT8 Card : 5; ///< Bits 4:0 349 UINT8 Revision : 2; ///< Bits 6:5 350 UINT8 Extension : 1; ///< Bits 7:7 351 } Bits; 352 UINT8 Data; 353 } SPD3_UNBUF_REFERENCE_RAW_CARD; 354 355 typedef union { 356 struct { 357 UINT8 MappingRank1 : 1; ///< Bits 0:0 358 UINT8 Reserved : 7; ///< Bits 7:1 359 } Bits; 360 UINT8 Data; 361 } SPD3_UNBUF_ADDRESS_MAPPING; 362 363 typedef union { 364 struct { 365 UINT8 Height : 5; ///< Bits 4:0 366 UINT8 Reserved : 3; ///< Bits 7:5 367 } Bits; 368 UINT8 Data; 369 } SPD3_RDIMM_MODULE_NOMINAL_HEIGHT; 370 371 typedef union { 372 struct { 373 UINT8 FrontThickness : 4; ///< Bits 3:0 374 UINT8 BackThickness : 4; ///< Bits 7:4 375 } Bits; 376 UINT8 Data; 377 } SPD3_RDIMM_MODULE_NOMINAL_THICKNESS; 378 379 typedef union { 380 struct { 381 UINT8 Card : 5; ///< Bits 4:0 382 UINT8 Revision : 2; ///< Bits 6:5 383 UINT8 Extension : 1; ///< Bits 7:7 384 } Bits; 385 UINT8 Data; 386 } SPD3_RDIMM_REFERENCE_RAW_CARD; 387 388 typedef union { 389 struct { 390 UINT8 RegisterCount : 2; ///< Bits 1:0 391 UINT8 DramRowCount : 2; ///< Bits 3:2 392 UINT8 RegisterType : 4; ///< Bits 7:4 393 } Bits; 394 UINT8 Data; 395 } SPD3_RDIMM_MODULE_ATTRIBUTES; 396 397 typedef union { 398 struct { 399 UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0 400 UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7 401 } Bits; 402 UINT8 Data; 403 } SPD3_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION; 404 405 typedef union { 406 struct { 407 UINT16 ContinuationCount : 7; ///< Bits 6:0 408 UINT16 ContinuationParity : 1; ///< Bits 7:7 409 UINT16 LastNonZeroByte : 8; ///< Bits 15:8 410 } Bits; 411 UINT16 Data; 412 UINT8 Data8[2]; 413 } SPD3_MANUFACTURER_ID_CODE; 414 415 typedef union { 416 struct { 417 UINT8 RegisterRevisionNumber; ///< Bits 7:0 418 } Bits; 419 UINT8 Data; 420 } SPD3_RDIMM_REGISTER_REVISION_NUMBER; 421 422 typedef union { 423 struct { 424 UINT8 Bit0 : 1; ///< Bits 0:0 425 UINT8 Bit1 : 1; ///< Bits 1:1 426 UINT8 Bit2 : 1; ///< Bits 2:2 427 UINT8 Reserved : 5; ///< Bits 7:3 428 } Bits; 429 UINT8 Data; 430 } SPD3_RDIMM_REGISTER_TYPE; 431 432 typedef union { 433 struct { 434 UINT8 Reserved : 4; ///< Bits 0:3 435 UINT8 CommandAddressAOutputs : 2; ///< Bits 5:4 436 UINT8 CommandAddressBOutputs : 2; ///< Bits 7:6 437 } Bits; 438 UINT8 Data; 439 } SPD3_RDIMM_REGISTER_CONTROL_COMMAND_ADDRESS; 440 441 typedef union { 442 struct { 443 UINT8 ControlSignalsAOutputs : 2; ///< Bits 0:1 444 UINT8 ControlSignalsBOutputs : 2; ///< Bits 3:2 445 UINT8 Y1Y3ClockOutputs : 2; ///< Bits 5:4 446 UINT8 Y0Y2ClockOutputs : 2; ///< Bits 7:6 447 } Bits; 448 UINT8 Data; 449 } SPD3_RDIMM_REGISTER_CONTROL_CONTROL_CLOCK; 450 451 typedef union { 452 struct { 453 UINT8 Reserved0 : 4; ///< Bits 0:3 454 UINT8 Reserved1 : 4; ///< Bits 7:4 455 } Bits; 456 UINT8 Data; 457 } SPD3_RDIMM_REGISTER_CONTROL_RESERVED; 458 459 typedef union { 460 struct { 461 UINT8 Height : 5; ///< Bits 4:0 462 UINT8 Reserved : 3; ///< Bits 7:5 463 } Bits; 464 UINT8 Data; 465 } SPD3_LRDIMM_MODULE_NOMINAL_HEIGHT; 466 467 typedef union { 468 struct { 469 UINT8 FrontThickness : 4; ///< Bits 3:0 470 UINT8 BackThickness : 4; ///< Bits 7:4 471 } Bits; 472 UINT8 Data; 473 } SPD3_LRDIMM_MODULE_NOMINAL_THICKNESS; 474 475 typedef union { 476 struct { 477 UINT8 Card : 5; ///< Bits 4:0 478 UINT8 Revision : 2; ///< Bits 6:5 479 UINT8 Extension : 1; ///< Bits 7:7 480 } Bits; 481 UINT8 Data; 482 } SPD3_LRDIMM_REFERENCE_RAW_CARD; 483 484 typedef union { 485 struct { 486 UINT8 RegisterCount : 2; ///< Bits 1:0 487 UINT8 DramRowCount : 2; ///< Bits 3:2 488 UINT8 RegisterType : 4; ///< Bits 7:4 489 } Bits; 490 UINT8 Data; 491 } SPD3_LRDIMM_MODULE_ATTRIBUTES; 492 493 typedef union { 494 struct { 495 UINT8 AddressCommandPrelaunch : 1; ///< Bits 0:0 496 UINT8 Rank1Rank5Swap : 1; ///< Bits 1:1 497 UINT8 Reserved0 : 1; ///< Bits 2:2 498 UINT8 Reserved1 : 1; ///< Bits 3:3 499 UINT8 AddressCommandOutputs : 2; ///< Bits 5:4 500 UINT8 QxCS_nOutputs : 2; ///< Bits 7:6 501 } Bits; 502 UINT8 Data; 503 } SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH; 504 505 typedef union { 506 struct { 507 UINT8 QxOdtOutputs : 2; ///< Bits 1:0 508 UINT8 QxCkeOutputs : 2; ///< Bits 3:2 509 UINT8 Y1Y3ClockOutputs : 2; ///< Bits 5:4 510 UINT8 Y0Y2ClockOutputs : 2; ///< Bits 7:6 511 } Bits; 512 UINT8 Data; 513 } SPD3_LRDIMM_TIMING_DRIVE_STRENGTH; 514 515 typedef union { 516 struct { 517 UINT8 YExtendedDelay : 2; ///< Bits 1:0 518 UINT8 QxCS_n : 2; ///< Bits 3:2 519 UINT8 QxOdt : 2; ///< Bits 5:4 520 UINT8 QxCke : 2; ///< Bits 7:6 521 } Bits; 522 UINT8 Data; 523 } SPD3_LRDIMM_EXTENDED_DELAY; 524 525 typedef union { 526 struct { 527 UINT8 DelayY : 3; ///< Bits 2:0 528 UINT8 Reserved : 1; ///< Bits 3:3 529 UINT8 QxCS_n : 4; ///< Bits 7:4 530 } Bits; 531 UINT8 Data; 532 } SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXCS_N_QXCA; 533 534 typedef union { 535 struct { 536 UINT8 QxCS_n : 4; ///< Bits 3:0 537 UINT8 QxOdt : 4; ///< Bits 7:4 538 } Bits; 539 UINT8 Data; 540 } SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXODT_QXCKE; 541 542 typedef union { 543 struct { 544 UINT8 RC8MdqOdtStrength : 3; ///< Bits 2:0 545 UINT8 RC8Reserved : 1; ///< Bits 3:3 546 UINT8 RC9MdqOdtStrength : 3; ///< Bits 6:4 547 UINT8 RC9Reserved : 1; ///< Bits 7:7 548 } Bits; 549 UINT8 Data; 550 } SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH; 551 552 typedef union { 553 struct { 554 UINT8 RC10DA3ValueR0 : 1; ///< Bits 0:0 555 UINT8 RC10DA4ValueR0 : 1; ///< Bits 1:1 556 UINT8 RC10DA3ValueR1 : 1; ///< Bits 2:2 557 UINT8 RC10DA4ValueR1 : 1; ///< Bits 3:3 558 UINT8 RC11DA3ValueR0 : 1; ///< Bits 4:4 559 UINT8 RC11DA4ValueR0 : 1; ///< Bits 5:5 560 UINT8 RC11DA3ValueR1 : 1; ///< Bits 6:6 561 UINT8 RC11DA4ValueR1 : 1; ///< Bits 7:7 562 } Bits; 563 UINT8 Data; 564 } SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL; 565 566 typedef union { 567 struct { 568 UINT8 Driver_Impedance : 2; ///< Bits 1:0 569 UINT8 Rtt_Nom : 3; ///< Bits 4:2 570 UINT8 Reserved : 1; ///< Bits 5:5 571 UINT8 Rtt_WR : 2; ///< Bits 7:6 572 } Bits; 573 UINT8 Data; 574 } SPD3_LRDIMM_MR_1_2; 575 576 typedef union { 577 struct { 578 UINT8 MinimumDelayTime : 7; ///< Bits 0:6 579 UINT8 Reserved : 1; ///< Bits 7:7 580 } Bits; 581 UINT8 Data; 582 } SPD3_LRDIMM_MODULE_DELAY_TIME; 583 584 typedef struct { 585 UINT8 Year; ///< Year represented in BCD (00h = 2000) 586 UINT8 Week; ///< Year represented in BCD (47h = week 47) 587 } SPD3_MANUFACTURING_DATE; 588 589 typedef union { 590 UINT32 Data; 591 UINT16 SerialNumber16[2]; 592 UINT8 SerialNumber8[4]; 593 } SPD3_MANUFACTURER_SERIAL_NUMBER; 594 595 typedef struct { 596 UINT8 Location; ///< Module Manufacturing Location 597 } SPD3_MANUFACTURING_LOCATION; 598 599 typedef struct { 600 SPD3_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code 601 SPD3_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location 602 SPD3_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255) 603 SPD3_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number 604 } SPD3_UNIQUE_MODULE_ID; 605 606 typedef union { 607 UINT16 Crc[1]; 608 UINT8 Data8[2]; 609 } SPD3_CYCLIC_REDUNDANCY_CODE; 610 611 typedef struct { 612 SPD3_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2 613 SPD3_REVISION_STRUCT Revision; ///< 1 SPD Revision 614 SPD3_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type 615 SPD3_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type 616 SPD3_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks 617 SPD3_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing 618 SPD3_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 6 Module Nominal Voltage, VDD 619 SPD3_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 7 Module Organization 620 SPD3_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 8 Module Memory Bus Width 621 SPD3_FINE_TIMEBASE_STRUCT FineTimebase; ///< 9 Fine Timebase (FTB) Dividend / Divisor 622 SPD3_MEDIUM_TIMEBASE MediumTimebase; ///< 10-11 Medium Timebase (MTB) Dividend 623 SPD3_TCK_MIN_MTB_STRUCT tCKmin; ///< 12 SDRAM Minimum Cycle Time (tCKmin) 624 UINT8 Reserved0; ///< 13 Reserved 625 SPD3_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 14-15 CAS Latencies Supported 626 SPD3_TAA_MIN_MTB_STRUCT tAAmin; ///< 16 Minimum CAS Latency Time (tAAmin) 627 SPD3_TWR_MIN_MTB_STRUCT tWRmin; ///< 17 Minimum Write Recovery Time (tWRmin) 628 SPD3_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 18 Minimum RAS# to CAS# Delay Time (tRCDmin) 629 SPD3_TRRD_MIN_MTB_STRUCT tRRDmin; ///< 19 Minimum Row Active to Row Active Delay Time (tRRDmin) 630 SPD3_TRP_MIN_MTB_STRUCT tRPmin; ///< 20 Minimum Row Precharge Delay Time (tRPmin) 631 SPD3_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 21 Upper Nibbles for tRAS and tRC 632 SPD3_TRAS_MIN_MTB_STRUCT tRASmin; ///< 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte 633 SPD3_TRC_MIN_MTB_STRUCT tRCmin; ///< 23 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte 634 SPD3_TRFC_MIN_MTB_STRUCT tRFCmin; ///< 24-25 Minimum Refresh Recovery Delay Time (tRFCmin) 635 SPD3_TWTR_MIN_MTB_STRUCT tWTRmin; ///< 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) 636 SPD3_TRTP_MIN_MTB_STRUCT tRTPmin; ///< 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) 637 SPD3_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 28 Upper Nibble for tFAW 638 SPD3_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 29 Minimum Four Activate Window Delay Time (tFAWmin) 639 SPD3_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 30 SDRAM Optional Features 640 SPD3_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 31 SDRAM Thermal And Refresh Options 641 SPD3_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 32 Module Thermal Sensor 642 SPD3_SDRAM_DEVICE_TYPE_STRUCT SdramDeviceType; ///< 33 SDRAM Device Type 643 SPD3_TCK_MIN_FTB_STRUCT tCKminFine; ///< 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) 644 SPD3_TAA_MIN_FTB_STRUCT tAAminFine; ///< 35 Fine Offset for Minimum CAS Latency Time (tAAmin) 645 SPD3_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) 646 SPD3_TRP_MIN_FTB_STRUCT tRPminFine; ///< 37 Minimum Row Precharge Delay Time (tRPmin) 647 SPD3_TRC_MIN_FTB_STRUCT tRCminFine; ///< 38 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin) 648 UINT8 Reserved1[40 - 39 + 1]; ///< 39 - 40 Reserved 649 SPD3_MAXIMUM_ACTIVE_COUNT_STRUCT MacValue; ///< 41 SDRAM Maximum Active Count (MAC) Value 650 UINT8 Reserved2[59 - 42 + 1]; ///< 42 - 59 Reserved 651 } SPD3_BASE_SECTION; 652 653 typedef struct { 654 SPD3_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height 655 SPD3_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness 656 SPD3_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used 657 SPD3_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn; ///< 63 Address Mapping from Edge Connector to DRAM 658 UINT8 Reserved[116 - 64 + 1]; ///< 64-116 Reserved 659 } SPD3_MODULE_UNBUFFERED; 660 661 typedef struct { 662 SPD3_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height 663 SPD3_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness 664 SPD3_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used 665 SPD3_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 63 DIMM Module Attributes 666 SPD3_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION ThermalHeatSpreaderSolution; ///< 64 RDIMM Thermal Heat Spreader Solution 667 SPD3_MANUFACTURER_ID_CODE RegisterManufacturerIdCode; ///< 65-66 Register Manufacturer ID Code 668 SPD3_RDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 67 Register Revision Number 669 SPD3_RDIMM_REGISTER_TYPE RegisterType; ///< 68 Register Type 670 SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc1Rc0; ///< 69 RC1 (MS Nibble) / RC0 (LS Nibble) - Reserved 671 SPD3_RDIMM_REGISTER_CONTROL_COMMAND_ADDRESS Rc3Rc2; ///< 70 RC3 (MS Nibble) / RC2 (LS Nibble) - Drive Strength, Command/Address 672 SPD3_RDIMM_REGISTER_CONTROL_CONTROL_CLOCK Rc5Rc4; ///< 71 RC5 (MS Nibble) / RC4 (LS Nibble) - Drive Strength, Control and Clock 673 SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc7Rc6; ///< 72 RC7 (MS Nibble) / RC6 (LS Nibble) - Reserved for Register Vendor 674 SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc9Rc8; ///< 73 RC9 (MS Nibble) / RC8 (LS Nibble) - Reserved 675 SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc11Rc10; ///< 74 RC11 (MS Nibble) / RC10 (LS Nibble) - Reserved 676 SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc13Rc12; ///< 75 RC12 (MS Nibble) / RC12 (LS Nibble) - Reserved 677 SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc15Rc14; ///< 76 RC15 (MS Nibble) / RC14 (LS Nibble) - Reserved 678 UINT8 Reserved[116 - 77 + 1]; ///< 77-116 Reserved 679 } SPD3_MODULE_REGISTERED; 680 681 typedef struct { 682 SPD3_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height 683 SPD3_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness 684 SPD3_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used 685 UINT8 Reserved[116 - 63 + 1]; ///< 63-116 Reserved 686 } SPD3_MODULE_CLOCKED; 687 688 typedef struct { 689 SPD3_LRDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height 690 SPD3_LRDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness 691 SPD3_LRDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used 692 SPD3_LRDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 63 Module Attributes 693 UINT8 MemoryBufferRevisionNumber; ///< 64 Memory Buffer Revision Number 694 SPD3_MANUFACTURER_ID_CODE ManufacturerIdCode; ///< 65-66 Memory Buffer Manufacturer ID Code 695 SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH TimingControlDriveStrengthCaCs; ///< 67 F0RC3 / F0RC2 - Timing Control & Drive Strength, CA & CS 696 SPD3_LRDIMM_TIMING_DRIVE_STRENGTH DriveStrength; ///< 68 F0RC5 / F0RC4 - Drive Strength, ODT & CKE and Y 697 SPD3_LRDIMM_EXTENDED_DELAY ExtendedDelay; ///< 69 F1RC11 / F1RC8 - Extended Delay for Y, CS and ODT & CKE 698 SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXCS_N_QXCA AdditiveDelayForCsCa; ///< 70 F1RC13 / F1RC12 - Additive Delay for CS and CA 699 SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXODT_QXCKE AdditiveDelayForOdtCke; ///< 71 F1RC15 / F1RC14 - Additive Delay for ODT & CKE 700 SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MdqTerminationDriveStrengthFor800_1066; ///< 72 F1RC15 / F1RC14 - Additive Delay for ODT & CKE 701 SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor800_1066; ///< 73 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066 702 SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor800_1066; ///< 74 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066 703 SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor800_1066; ///< 75 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066 704 SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor800_1066; ///< 76 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066 705 SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor800_1066; ///< 77 MR1,2 Registers for 800 & 1066 706 SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MdqTerminationDriveStrengthFor1333_1600; ///< 78 F1RC15 / F1RC14 - Additive Delay for ODT & CKE 707 SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor1333_1600; ///< 79 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066 708 SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor1333_1600; ///< 80 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066 709 SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor1333_1600; ///< 81 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066 710 SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor1333_1600; ///< 82 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066 711 SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor1333_1600; ///< 83 MR1,2 Registers for 800 & 1066 712 SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MdqTerminationDriveStrengthFor1866_2133; ///< 84 F1RC15 / F1RC14 - Additive Delay for ODT & CKE 713 SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor1866_2133; ///< 85 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066 714 SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor1866_2133; ///< 86 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066 715 SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor1866_2133; ///< 87 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066 716 SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor1866_2133; ///< 88 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066 717 SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor1866_2133; ///< 89 MR1,2 Registers for 800 & 1066 718 SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_5V; ///< 90 Minimum Module Delay Time for 1.5 V 719 SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_5V; ///< 91 Maximum Module Delay Time for 1.5 V 720 SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_35V; ///< 92 Minimum Module Delay Time for 1.35 V 721 SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_35V; ///< 93 Maximum Module Delay Time for 1.35 V 722 SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_25V; ///< 94 Minimum Module Delay Time for 1.25 V 723 SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_25V; ///< 95 Maximum Module Delay Time for 1.25 V 724 UINT8 Reserved[101 - 96 + 1]; ///< 96-101 Reserved 725 UINT8 PersonalityByte[116 - 102 + 1]; ///< 102-116 Memory Buffer Personality Bytes 726 } SPD3_MODULE_LOADREDUCED; 727 728 typedef union { 729 SPD3_MODULE_UNBUFFERED Unbuffered; ///< 128-255 Unbuffered Memory Module Types 730 SPD3_MODULE_REGISTERED Registered; ///< 128-255 Registered Memory Module Types 731 SPD3_MODULE_CLOCKED Clocked; ///< 128-255 Registered Memory Module Types 732 SPD3_MODULE_LOADREDUCED LoadReduced; ///< 128-255 Load Reduced Memory Module Types 733 } SPD3_MODULE_SPECIFIC; 734 735 typedef struct { 736 UINT8 ModulePartNumber[145 - 128 + 1]; ///< 128-145 Module Part Number 737 } SPD3_MODULE_PART_NUMBER; 738 739 typedef struct { 740 UINT8 ModuleRevisionCode[147 - 146 + 1]; ///< 146-147 Module Revision Code 741 } SPD3_MODULE_REVISION_CODE; 742 743 typedef struct { 744 UINT8 ManufacturerSpecificData[175 - 150 + 1];///< 150-175 Manufacturer's Specific Data 745 } SPD3_MANUFACTURER_SPECIFIC; 746 747 /// 748 /// DDR3 Serial Presence Detect structure 749 /// 750 typedef struct { 751 SPD3_BASE_SECTION General; ///< 0-59 General Section 752 SPD3_MODULE_SPECIFIC Module; ///< 60-116 Module-Specific Section 753 SPD3_UNIQUE_MODULE_ID ModuleId; ///< 117-125 Unique Module ID 754 SPD3_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC) 755 SPD3_MODULE_PART_NUMBER ModulePartNumber; ///< 128-145 Module Part Number 756 SPD3_MODULE_REVISION_CODE ModuleRevisionCode; ///< 146-147 Module Revision Code 757 SPD3_MANUFACTURER_ID_CODE DramIdCode; ///< 148-149 Dram Manufacturer ID Code 758 SPD3_MANUFACTURER_SPECIFIC ManufacturerSpecificData; ///< 150-175 Manufacturer's Specific Data 759 UINT8 Reserved[255 - 176 + 1]; ///< 176-255 Open for Customer Use 760 } SPD_DDR3; 761 762 #pragma pack (pop) 763 #endif 764