1 /** @file
2   MSR Definitions for Intel Atom processors based on the Goldmont microarchitecture.
3 
4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5   are provided for MSRs that contain one or more bit fields.  If the MSR value
6   returned is a single 32-bit or 64-bit value, then a data structure is not
7   provided for that MSR.
8 
9   Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
10   SPDX-License-Identifier: BSD-2-Clause-Patent
11 
12   @par Specification Reference:
13   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
14   May 2018, Volume 4: Model-Specific-Registers (MSR)
15 
16 **/
17 
18 #ifndef __GOLDMONT_MSR_H__
19 #define __GOLDMONT_MSR_H__
20 
21 #include <Register/Intel/ArchitecturalMsr.h>
22 
23 /**
24   Is Intel Atom processors based on the Goldmont microarchitecture?
25 
26   @param   DisplayFamily  Display Family ID
27   @param   DisplayModel   Display Model ID
28 
29   @retval  TRUE   Yes, it is.
30   @retval  FALSE  No, it isn't.
31 **/
32 #define IS_GOLDMONT_PROCESSOR(DisplayFamily, DisplayModel) \
33   (DisplayFamily == 0x06 && \
34    (                        \
35     DisplayModel == 0x5C    \
36     )                       \
37    )
38 
39 /**
40   Core. Control Features in Intel 64Processor (R/W).
41 
42   @param  ECX  MSR_GOLDMONT_FEATURE_CONTROL (0x0000003A)
43   @param  EAX  Lower 32-bits of MSR value.
44                Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER.
45   @param  EDX  Upper 32-bits of MSR value.
46                Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER.
47 
48   <b>Example usage</b>
49   @code
50   MSR_GOLDMONT_FEATURE_CONTROL_REGISTER  Msr;
51 
52   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_FEATURE_CONTROL);
53   AsmWriteMsr64 (MSR_GOLDMONT_FEATURE_CONTROL, Msr.Uint64);
54   @endcode
55   @note MSR_GOLDMONT_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.
56 **/
57 #define MSR_GOLDMONT_FEATURE_CONTROL             0x0000003A
58 
59 /**
60   MSR information returned for MSR index #MSR_GOLDMONT_FEATURE_CONTROL
61 **/
62 typedef union {
63   ///
64   /// Individual bit fields
65   ///
66   struct {
67     ///
68     /// [Bit 0] Lock bit (R/WL)
69     ///
70     UINT32  Lock:1;
71     ///
72     /// [Bit 1] Enable VMX inside SMX operation (R/WL)
73     ///
74     UINT32  EnableVmxInsideSmx:1;
75     ///
76     /// [Bit 2] Enable VMX outside SMX operation (R/WL)
77     ///
78     UINT32  EnableVmxOutsideSmx:1;
79     UINT32  Reserved1:5;
80     ///
81     /// [Bits 14:8] SENTER local function enables (R/WL)
82     ///
83     UINT32  SenterLocalFunctionEnables:7;
84     ///
85     /// [Bit 15] SENTER global functions enable (R/WL)
86     ///
87     UINT32  SenterGlobalEnable:1;
88     UINT32  Reserved2:2;
89     ///
90     /// [Bit 18] SGX global functions enable (R/WL)
91     ///
92     UINT32  SgxEnable:1;
93     UINT32  Reserved3:13;
94     UINT32  Reserved4:32;
95   } Bits;
96   ///
97   /// All bit fields as a 32-bit value
98   ///
99   UINT32  Uint32;
100   ///
101   /// All bit fields as a 64-bit value
102   ///
103   UINT64  Uint64;
104 } MSR_GOLDMONT_FEATURE_CONTROL_REGISTER;
105 
106 
107 /**
108   Package. See http://biosbits.org.
109 
110   @param  ECX  MSR_GOLDMONT_PLATFORM_INFO (0x000000CE)
111   @param  EAX  Lower 32-bits of MSR value.
112                Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER.
113   @param  EDX  Upper 32-bits of MSR value.
114                Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER.
115 
116   <b>Example usage</b>
117   @code
118   MSR_GOLDMONT_PLATFORM_INFO_REGISTER  Msr;
119 
120   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PLATFORM_INFO);
121   AsmWriteMsr64 (MSR_GOLDMONT_PLATFORM_INFO, Msr.Uint64);
122   @endcode
123   @note MSR_GOLDMONT_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
124 **/
125 #define MSR_GOLDMONT_PLATFORM_INFO               0x000000CE
126 
127 /**
128   MSR information returned for MSR index #MSR_GOLDMONT_PLATFORM_INFO
129 **/
130 typedef union {
131   ///
132   /// Individual bit fields
133   ///
134   struct {
135     UINT32  Reserved1:8;
136     ///
137     /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O)  The is the ratio
138     /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
139     /// MHz.
140     ///
141     UINT32  MaximumNonTurboRatio:8;
142     UINT32  Reserved2:12;
143     ///
144     /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O)  When
145     /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
146     /// enabled, and when set to 0, indicates Programmable Ratio Limits for
147     /// Turbo mode is disabled.
148     ///
149     UINT32  RatioLimit:1;
150     ///
151     /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O)  When
152     /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
153     /// and when set to 0, indicates TDP Limit for Turbo mode is not
154     /// programmable.
155     ///
156     UINT32  TDPLimit:1;
157     ///
158     /// [Bit 30] Package. Programmable TJ OFFSET (R/O)  When set to 1,
159     /// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to
160     /// specify an temperature offset.
161     ///
162     UINT32  TJOFFSET:1;
163     UINT32  Reserved3:1;
164     UINT32  Reserved4:8;
165     ///
166     /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O)  The is the
167     /// minimum ratio (maximum efficiency) that the processor can operates, in
168     /// units of 100MHz.
169     ///
170     UINT32  MaximumEfficiencyRatio:8;
171     UINT32  Reserved5:16;
172   } Bits;
173   ///
174   /// All bit fields as a 64-bit value
175   ///
176   UINT64  Uint64;
177 } MSR_GOLDMONT_PLATFORM_INFO_REGISTER;
178 
179 
180 /**
181   Core. C-State Configuration Control (R/W)  Note: C-state values are
182   processor specific C-state code names, unrelated to MWAIT extension C-state
183   parameters or ACPI CStates. See http://biosbits.org.
184 
185   @param  ECX  MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL (0x000000E2)
186   @param  EAX  Lower 32-bits of MSR value.
187                Described by the type
188                MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER.
189   @param  EDX  Upper 32-bits of MSR value.
190                Described by the type
191                MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER.
192 
193   <b>Example usage</b>
194   @code
195   MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
196 
197   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL);
198   AsmWriteMsr64 (MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
199   @endcode
200   @note MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
201 **/
202 #define MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL      0x000000E2
203 
204 /**
205   MSR information returned for MSR index #MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL
206 **/
207 typedef union {
208   ///
209   /// Individual bit fields
210   ///
211   struct {
212     ///
213     /// [Bits 3:0] Package C-State Limit (R/W)  Specifies the lowest
214     /// processor-specific C-state code name (consuming the least power). for
215     /// the package. The default is set as factory-configured package C-state
216     /// limit. The following C-state code name encodings are supported: 0000b:
217     /// No limit 0001b: C1 0010b: C3 0011b: C6 0100b: C7 0101b: C7S 0110b: C8
218     /// 0111b: C9 1000b: C10.
219     ///
220     UINT32  Limit:4;
221     UINT32  Reserved1:6;
222     ///
223     /// [Bit 10] I/O MWAIT Redirection Enable (R/W)  When set, will map
224     /// IO_read instructions sent to IO register specified by
225     /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
226     ///
227     UINT32  IO_MWAIT:1;
228     UINT32  Reserved2:4;
229     ///
230     /// [Bit 15] CFG Lock (R/WO)  When set, lock bits 15:0 of this register
231     /// until next reset.
232     ///
233     UINT32  CFGLock:1;
234     UINT32  Reserved3:16;
235     UINT32  Reserved4:32;
236   } Bits;
237   ///
238   /// All bit fields as a 32-bit value
239   ///
240   UINT32  Uint32;
241   ///
242   /// All bit fields as a 64-bit value
243   ///
244   UINT64  Uint64;
245 } MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER;
246 
247 
248 /**
249   Core. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement.
250   Accessible only while in SMM.
251 
252   @param  ECX  MSR_GOLDMONT_SMM_MCA_CAP (0x0000017D)
253   @param  EAX  Lower 32-bits of MSR value.
254                Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER.
255   @param  EDX  Upper 32-bits of MSR value.
256                Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER.
257 
258   <b>Example usage</b>
259   @code
260   MSR_GOLDMONT_SMM_MCA_CAP_REGISTER  Msr;
261 
262   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_MCA_CAP);
263   AsmWriteMsr64 (MSR_GOLDMONT_SMM_MCA_CAP, Msr.Uint64);
264   @endcode
265   @note MSR_GOLDMONT_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
266 **/
267 #define MSR_GOLDMONT_SMM_MCA_CAP                 0x0000017D
268 
269 /**
270   MSR information returned for MSR index #MSR_GOLDMONT_SMM_MCA_CAP
271 **/
272 typedef union {
273   ///
274   /// Individual bit fields
275   ///
276   struct {
277     UINT32  Reserved1:32;
278     UINT32  Reserved2:26;
279     ///
280     /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
281     /// SMM code access restriction is supported and the
282     /// MSR_SMM_FEATURE_CONTROL is supported.
283     ///
284     UINT32  SMM_Code_Access_Chk:1;
285     ///
286     /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
287     /// SMM long flow indicator is supported and the MSR_SMM_DELAYED is
288     /// supported.
289     ///
290     UINT32  Long_Flow_Indication:1;
291     UINT32  Reserved3:4;
292   } Bits;
293   ///
294   /// All bit fields as a 64-bit value
295   ///
296   UINT64  Uint64;
297 } MSR_GOLDMONT_SMM_MCA_CAP_REGISTER;
298 
299 
300 /**
301   Enable Misc. Processor Features (R/W)  Allows a variety of processor
302   functions to be enabled and disabled.
303 
304   @param  ECX  MSR_GOLDMONT_IA32_MISC_ENABLE (0x000001A0)
305   @param  EAX  Lower 32-bits of MSR value.
306                Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER.
307   @param  EDX  Upper 32-bits of MSR value.
308                Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER.
309 
310   <b>Example usage</b>
311   @code
312   MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER  Msr;
313 
314   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_MISC_ENABLE);
315   AsmWriteMsr64 (MSR_GOLDMONT_IA32_MISC_ENABLE, Msr.Uint64);
316   @endcode
317   @note MSR_GOLDMONT_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
318 **/
319 #define MSR_GOLDMONT_IA32_MISC_ENABLE            0x000001A0
320 
321 /**
322   MSR information returned for MSR index #MSR_GOLDMONT_IA32_MISC_ENABLE
323 **/
324 typedef union {
325   ///
326   /// Individual bit fields
327   ///
328   struct {
329     ///
330     /// [Bit 0] Core. Fast-Strings Enable See Table 2-2.
331     ///
332     UINT32  FastStrings:1;
333     UINT32  Reserved1:2;
334     ///
335     /// [Bit 3] Package. Automatic Thermal Control Circuit Enable (R/W) See
336     /// Table 2-2. Default value is 1.
337     ///
338     UINT32  AutomaticThermalControlCircuit:1;
339     UINT32  Reserved2:3;
340     ///
341     /// [Bit 7] Core. Performance Monitoring Available (R) See Table 2-2.
342     ///
343     UINT32  PerformanceMonitoring:1;
344     UINT32  Reserved3:3;
345     ///
346     /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 2-2.
347     ///
348     UINT32  BTS:1;
349     ///
350     /// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See
351     /// Table 2-2.
352     ///
353     UINT32  PEBS:1;
354     UINT32  Reserved4:3;
355     ///
356     /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See
357     /// Table 2-2.
358     ///
359     UINT32  EIST:1;
360     UINT32  Reserved5:1;
361     ///
362     /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 2-2.
363     ///
364     UINT32  MONITOR:1;
365     UINT32  Reserved6:3;
366     ///
367     /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 2-2.
368     ///
369     UINT32  LimitCpuidMaxval:1;
370     ///
371     /// [Bit 23] Package. xTPR Message Disable (R/W) See Table 2-2.
372     ///
373     UINT32  xTPR_Message_Disable:1;
374     UINT32  Reserved7:8;
375     UINT32  Reserved8:2;
376     ///
377     /// [Bit 34] Core. XD Bit Disable (R/W) See Table 2-2.
378     ///
379     UINT32  XD:1;
380     UINT32  Reserved9:3;
381     ///
382     /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors
383     /// that support Intel Turbo Boost Technology, the turbo mode feature is
384     /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:
385     /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:
386     /// EAX[1] reports the processor's support of turbo mode is enabled. Note:
387     /// the power-on default value is used by BIOS to detect hardware support
388     /// of turbo mode. If power-on default value is 1, turbo mode is available
389     /// in the processor. If power-on default value is 0, turbo mode is not
390     /// available.
391     ///
392     UINT32  TurboModeDisable:1;
393     UINT32  Reserved10:25;
394   } Bits;
395   ///
396   /// All bit fields as a 64-bit value
397   ///
398   UINT64  Uint64;
399 } MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER;
400 
401 
402 /**
403   Miscellaneous Feature Control (R/W).
404 
405   @param  ECX  MSR_GOLDMONT_MISC_FEATURE_CONTROL (0x000001A4)
406   @param  EAX  Lower 32-bits of MSR value.
407                Described by the type MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER.
408   @param  EDX  Upper 32-bits of MSR value.
409                Described by the type MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER.
410 
411   <b>Example usage</b>
412   @code
413   MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER  Msr;
414 
415   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_MISC_FEATURE_CONTROL);
416   AsmWriteMsr64 (MSR_GOLDMONT_MISC_FEATURE_CONTROL, Msr.Uint64);
417   @endcode
418   @note MSR_GOLDMONT_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
419 **/
420 #define MSR_GOLDMONT_MISC_FEATURE_CONTROL        0x000001A4
421 
422 /**
423   MSR information returned for MSR index #MSR_GOLDMONT_MISC_FEATURE_CONTROL
424 **/
425 typedef union {
426   ///
427   /// Individual bit fields
428   ///
429   struct {
430     ///
431     /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W)  If 1, disables the
432     /// L2 hardware prefetcher, which fetches additional lines of code or data
433     /// into the L2 cache.
434     ///
435     UINT32  L2HardwarePrefetcherDisable:1;
436     UINT32  Reserved1:1;
437     ///
438     /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W)  If 1, disables
439     /// the L1 data cache prefetcher, which fetches the next cache line into
440     /// L1 data cache.
441     ///
442     UINT32  DCUHardwarePrefetcherDisable:1;
443     UINT32  Reserved2:29;
444     UINT32  Reserved3:32;
445   } Bits;
446   ///
447   /// All bit fields as a 32-bit value
448   ///
449   UINT32  Uint32;
450   ///
451   /// All bit fields as a 64-bit value
452   ///
453   UINT64  Uint64;
454 } MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER;
455 
456 
457 /**
458   Package. See http://biosbits.org.
459 
460   @param  ECX  MSR_GOLDMONT_MISC_PWR_MGMT (0x000001AA)
461   @param  EAX  Lower 32-bits of MSR value.
462                Described by the type MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER.
463   @param  EDX  Upper 32-bits of MSR value.
464                Described by the type MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER.
465 
466   <b>Example usage</b>
467   @code
468   MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER  Msr;
469 
470   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_MISC_PWR_MGMT);
471   AsmWriteMsr64 (MSR_GOLDMONT_MISC_PWR_MGMT, Msr.Uint64);
472   @endcode
473   @note MSR_GOLDMONT_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.
474 **/
475 #define MSR_GOLDMONT_MISC_PWR_MGMT               0x000001AA
476 
477 /**
478   MSR information returned for MSR index #MSR_GOLDMONT_MISC_PWR_MGMT
479 **/
480 typedef union {
481   ///
482   /// Individual bit fields
483   ///
484   struct {
485     ///
486     /// [Bit 0] EIST Hardware Coordination Disable (R/W) When 0, enables
487     /// hardware coordination of Enhanced Intel Speedstep Technology request
488     /// from processor cores; When 1, disables hardware coordination of
489     /// Enhanced Intel Speedstep Technology requests.
490     ///
491     UINT32  EISTHardwareCoordinationDisable:1;
492     UINT32  Reserved1:21;
493     ///
494     /// [Bit 22] Thermal Interrupt Coordination Enable (R/W)  If set, then
495     /// thermal interrupt on one core is routed to all cores.
496     ///
497     UINT32  ThermalInterruptCoordinationEnable:1;
498     UINT32  Reserved2:9;
499     UINT32  Reserved3:32;
500   } Bits;
501   ///
502   /// All bit fields as a 32-bit value
503   ///
504   UINT32  Uint32;
505   ///
506   /// All bit fields as a 64-bit value
507   ///
508   UINT64  Uint64;
509 } MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER;
510 
511 
512 /**
513   Package. Maximum Ratio Limit of Turbo Mode by Core Groups (RW) Specifies
514   Maximum Ratio Limit for each Core Group. Max ratio for groups with more
515   cores must decrease monotonically. For groups with less than 4 cores, the
516   max ratio must be 32 or less. For groups with 4-5 cores, the max ratio must
517   be 22 or less. For groups with more than 5 cores, the max ratio must be 16
518   or less..
519 
520   @param  ECX  MSR_GOLDMONT_TURBO_RATIO_LIMIT (0x000001AD)
521   @param  EAX  Lower 32-bits of MSR value.
522                Described by the type MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER.
523   @param  EDX  Upper 32-bits of MSR value.
524                Described by the type MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER.
525 
526   <b>Example usage</b>
527   @code
528   MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER  Msr;
529 
530   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_RATIO_LIMIT);
531   AsmWriteMsr64 (MSR_GOLDMONT_TURBO_RATIO_LIMIT, Msr.Uint64);
532   @endcode
533   @note MSR_GOLDMONT_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
534 **/
535 #define MSR_GOLDMONT_TURBO_RATIO_LIMIT           0x000001AD
536 
537 /**
538   MSR information returned for MSR index #MSR_GOLDMONT_TURBO_RATIO_LIMIT
539 **/
540 typedef union {
541   ///
542   /// Individual bit fields
543   ///
544   struct {
545     ///
546     /// [Bits 7:0] Package. Maximum Ratio Limit for Active cores in Group 0
547     /// Maximum turbo ratio limit when number of active cores is less or equal
548     /// to Group 0 threshold.
549     ///
550     UINT32  MaxRatioLimitGroup0:8;
551     ///
552     /// [Bits 15:8] Package. Maximum Ratio Limit for Active cores in Group 1
553     /// Maximum turbo ratio limit when number of active cores is less or equal
554     /// to Group 1 threshold and greater than Group 0 threshold.
555     ///
556     UINT32  MaxRatioLimitGroup1:8;
557     ///
558     /// [Bits 23:16] Package. Maximum Ratio Limit for Active cores in Group 2
559     /// Maximum turbo ratio limit when number of active cores is less or equal
560     /// to Group 2 threshold and greater than Group 1 threshold.
561     ///
562     UINT32  MaxRatioLimitGroup2:8;
563     ///
564     /// [Bits 31:24] Package. Maximum Ratio Limit for Active cores in Group 3
565     /// Maximum turbo ratio limit when number of active cores is less or equal
566     /// to Group 3 threshold and greater than Group 2 threshold.
567     ///
568     UINT32  MaxRatioLimitGroup3:8;
569     ///
570     /// [Bits 39:32] Package. Maximum Ratio Limit for Active cores in Group 4
571     /// Maximum turbo ratio limit when number of active cores is less or equal
572     /// to Group 4 threshold and greater than Group 3 threshold.
573     ///
574     UINT32  MaxRatioLimitGroup4:8;
575     ///
576     /// [Bits 47:40] Package. Maximum Ratio Limit for Active cores in Group 5
577     /// Maximum turbo ratio limit when number of active cores is less or equal
578     /// to Group 5 threshold and greater than Group 4 threshold.
579     ///
580     UINT32  MaxRatioLimitGroup5:8;
581     ///
582     /// [Bits 55:48] Package. Maximum Ratio Limit for Active cores in Group 6
583     /// Maximum turbo ratio limit when number of active cores is less or equal
584     /// to Group 6 threshold and greater than Group 5 threshold.
585     ///
586     UINT32  MaxRatioLimitGroup6:8;
587     ///
588     /// [Bits 63:56] Package. Maximum Ratio Limit for Active cores in Group 7
589     /// Maximum turbo ratio limit when number of active cores is less or equal
590     /// to Group 7 threshold and greater than Group 6 threshold.
591     ///
592     UINT32  MaxRatioLimitGroup7:8;
593   } Bits;
594   ///
595   /// All bit fields as a 64-bit value
596   ///
597   UINT64  Uint64;
598 } MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER;
599 
600 
601 /**
602   Package. Group Size of Active Cores for Turbo Mode Operation (RW) Writes of
603   0 threshold is ignored.
604 
605   @param  ECX  MSR_GOLDMONT_TURBO_GROUP_CORECNT (0x000001AE)
606   @param  EAX  Lower 32-bits of MSR value.
607                Described by the type MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER.
608   @param  EDX  Upper 32-bits of MSR value.
609                Described by the type MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER.
610 
611   <b>Example usage</b>
612   @code
613   MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER  Msr;
614 
615   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_GROUP_CORECNT);
616   AsmWriteMsr64 (MSR_GOLDMONT_TURBO_GROUP_CORECNT, Msr.Uint64);
617   @endcode
618   @note MSR_GOLDMONT_TURBO_GROUP_CORECNT is defined as MSR_TURBO_GROUP_CORECNT in SDM.
619 **/
620 #define MSR_GOLDMONT_TURBO_GROUP_CORECNT         0x000001AE
621 
622 /**
623   MSR information returned for MSR index #MSR_GOLDMONT_TURBO_GROUP_CORECNT
624 **/
625 typedef union {
626   ///
627   /// Individual bit fields
628   ///
629   struct {
630     ///
631     /// [Bits 7:0] Package. Group 0 Core Count Threshold Maximum number of
632     /// active cores to operate under Group 0 Max Turbo Ratio limit.
633     ///
634     UINT32  CoreCountThresholdGroup0:8;
635     ///
636     /// [Bits 15:8] Package. Group 1 Core Count Threshold Maximum number of
637     /// active cores to operate under Group 1 Max Turbo Ratio limit. Must be
638     /// greater than Group 0 Core Count.
639     ///
640     UINT32  CoreCountThresholdGroup1:8;
641     ///
642     /// [Bits 23:16] Package. Group 2 Core Count Threshold Maximum number of
643     /// active cores to operate under Group 2 Max Turbo Ratio limit. Must be
644     /// greater than Group 1 Core Count.
645     ///
646     UINT32  CoreCountThresholdGroup2:8;
647     ///
648     /// [Bits 31:24] Package. Group 3 Core Count Threshold Maximum number of
649     /// active cores to operate under Group 3 Max Turbo Ratio limit. Must be
650     /// greater than Group 2 Core Count.
651     ///
652     UINT32  CoreCountThresholdGroup3:8;
653     ///
654     /// [Bits 39:32] Package. Group 4 Core Count Threshold Maximum number of
655     /// active cores to operate under Group 4 Max Turbo Ratio limit. Must be
656     /// greater than Group 3 Core Count.
657     ///
658     UINT32  CoreCountThresholdGroup4:8;
659     ///
660     /// [Bits 47:40] Package. Group 5 Core Count Threshold Maximum number of
661     /// active cores to operate under Group 5 Max Turbo Ratio limit. Must be
662     /// greater than Group 4 Core Count.
663     ///
664     UINT32  CoreCountThresholdGroup5:8;
665     ///
666     /// [Bits 55:48] Package. Group 6 Core Count Threshold Maximum number of
667     /// active cores to operate under Group 6 Max Turbo Ratio limit. Must be
668     /// greater than Group 5 Core Count.
669     ///
670     UINT32  CoreCountThresholdGroup6:8;
671     ///
672     /// [Bits 63:56] Package. Group 7 Core Count Threshold Maximum number of
673     /// active cores to operate under Group 7 Max Turbo Ratio limit. Must be
674     /// greater than Group 6 Core Count and not less than the total number of
675     /// processor cores in the package. E.g. specify 255.
676     ///
677     UINT32  CoreCountThresholdGroup7:8;
678   } Bits;
679   ///
680   /// All bit fields as a 64-bit value
681   ///
682   UINT64  Uint64;
683 } MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER;
684 
685 
686 /**
687   Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,
688   "Filtering of Last Branch Records.".
689 
690   @param  ECX  MSR_GOLDMONT_LBR_SELECT (0x000001C8)
691   @param  EAX  Lower 32-bits of MSR value.
692                Described by the type MSR_GOLDMONT_LBR_SELECT_REGISTER.
693   @param  EDX  Upper 32-bits of MSR value.
694                Described by the type MSR_GOLDMONT_LBR_SELECT_REGISTER.
695 
696   <b>Example usage</b>
697   @code
698   MSR_GOLDMONT_LBR_SELECT_REGISTER  Msr;
699 
700   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LBR_SELECT);
701   AsmWriteMsr64 (MSR_GOLDMONT_LBR_SELECT, Msr.Uint64);
702   @endcode
703   @note MSR_GOLDMONT_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
704 **/
705 #define MSR_GOLDMONT_LBR_SELECT                  0x000001C8
706 
707 /**
708   MSR information returned for MSR index #MSR_GOLDMONT_LBR_SELECT
709 **/
710 typedef union {
711   ///
712   /// Individual bit fields
713   ///
714   struct {
715     ///
716     /// [Bit 0] CPL_EQ_0.
717     ///
718     UINT32  CPL_EQ_0:1;
719     ///
720     /// [Bit 1] CPL_NEQ_0.
721     ///
722     UINT32  CPL_NEQ_0:1;
723     ///
724     /// [Bit 2] JCC.
725     ///
726     UINT32  JCC:1;
727     ///
728     /// [Bit 3] NEAR_REL_CALL.
729     ///
730     UINT32  NEAR_REL_CALL:1;
731     ///
732     /// [Bit 4] NEAR_IND_CALL.
733     ///
734     UINT32  NEAR_IND_CALL:1;
735     ///
736     /// [Bit 5] NEAR_RET.
737     ///
738     UINT32  NEAR_RET:1;
739     ///
740     /// [Bit 6] NEAR_IND_JMP.
741     ///
742     UINT32  NEAR_IND_JMP:1;
743     ///
744     /// [Bit 7] NEAR_REL_JMP.
745     ///
746     UINT32  NEAR_REL_JMP:1;
747     ///
748     /// [Bit 8] FAR_BRANCH.
749     ///
750     UINT32  FAR_BRANCH:1;
751     ///
752     /// [Bit 9] EN_CALL_STACK.
753     ///
754     UINT32  EN_CALL_STACK:1;
755     UINT32  Reserved1:22;
756     UINT32  Reserved2:32;
757   } Bits;
758   ///
759   /// All bit fields as a 32-bit value
760   ///
761   UINT32  Uint32;
762   ///
763   /// All bit fields as a 64-bit value
764   ///
765   UINT64  Uint64;
766 } MSR_GOLDMONT_LBR_SELECT_REGISTER;
767 
768 
769 /**
770   Core. Last Branch Record Stack TOS (R/W)  Contains an index (bits 0-4) that
771   points to the MSR containing the most recent branch record. See
772   MSR_LASTBRANCH_0_FROM_IP.
773 
774   @param  ECX  MSR_GOLDMONT_LASTBRANCH_TOS (0x000001C9)
775   @param  EAX  Lower 32-bits of MSR value.
776   @param  EDX  Upper 32-bits of MSR value.
777 
778   <b>Example usage</b>
779   @code
780   UINT64  Msr;
781 
782   Msr = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_TOS);
783   AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_TOS, Msr);
784   @endcode
785   @note MSR_GOLDMONT_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
786 **/
787 #define MSR_GOLDMONT_LASTBRANCH_TOS              0x000001C9
788 
789 
790 /**
791   Core. Power Control Register. See http://biosbits.org.
792 
793   @param  ECX  MSR_GOLDMONT_POWER_CTL (0x000001FC)
794   @param  EAX  Lower 32-bits of MSR value.
795                Described by the type MSR_GOLDMONT_POWER_CTL_REGISTER.
796   @param  EDX  Upper 32-bits of MSR value.
797                Described by the type MSR_GOLDMONT_POWER_CTL_REGISTER.
798 
799   <b>Example usage</b>
800   @code
801   MSR_GOLDMONT_POWER_CTL_REGISTER  Msr;
802 
803   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_POWER_CTL);
804   AsmWriteMsr64 (MSR_GOLDMONT_POWER_CTL, Msr.Uint64);
805   @endcode
806   @note MSR_GOLDMONT_POWER_CTL is defined as MSR_POWER_CTL in SDM.
807 **/
808 #define MSR_GOLDMONT_POWER_CTL                   0x000001FC
809 
810 /**
811   MSR information returned for MSR index #MSR_GOLDMONT_POWER_CTL
812 **/
813 typedef union {
814   ///
815   /// Individual bit fields
816   ///
817   struct {
818     UINT32  Reserved1:1;
819     ///
820     /// [Bit 1] Package. C1E Enable (R/W)  When set to '1', will enable the
821     /// CPU to switch to the Minimum Enhanced Intel SpeedStep Technology
822     /// operating point when all execution cores enter MWAIT (C1).
823     ///
824     UINT32  C1EEnable:1;
825     UINT32  Reserved2:30;
826     UINT32  Reserved3:32;
827   } Bits;
828   ///
829   /// All bit fields as a 32-bit value
830   ///
831   UINT32  Uint32;
832   ///
833   /// All bit fields as a 64-bit value
834   ///
835   UINT64  Uint64;
836 } MSR_GOLDMONT_POWER_CTL_REGISTER;
837 
838 
839 /**
840   Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update
841   CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in
842   the package. Lower 64 bits of an 128-bit external entropy value for key
843   derivation of an enclave.
844 
845   @param  ECX  MSR_GOLDMONT_SGXOWNEREPOCH0 (0x00000300)
846   @param  EAX  Lower 32-bits of MSR value.
847   @param  EDX  Upper 32-bits of MSR value.
848 
849   <b>Example usage</b>
850   @code
851   UINT64  Msr;
852 
853   Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNEREPOCH0);
854   @endcode
855   @note MSR_GOLDMONT_SGXOWNEREPOCH0 is defined as MSR_SGXOWNEREPOCH0 in SDM.
856 **/
857 #define MSR_GOLDMONT_SGXOWNEREPOCH0                   0x00000300
858 
859 
860 //
861 // Define MSR_GOLDMONT_SGXOWNER0 for compatibility due to name change in the SDM.
862 //
863 #define MSR_GOLDMONT_SGXOWNER0                        MSR_GOLDMONT_SGXOWNEREPOCH0
864 
865 
866 /**
867   Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of
868   an 128-bit external entropy value for key derivation of an enclave.
869 
870   @param  ECX  MSR_GOLDMONT_SGXOWNEREPOCH1 (0x00000301)
871   @param  EAX  Lower 32-bits of MSR value.
872   @param  EDX  Upper 32-bits of MSR value.
873 
874   <b>Example usage</b>
875   @code
876   UINT64  Msr;
877 
878   Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNEREPOCH1);
879   @endcode
880   @note MSR_GOLDMONT_SGXOWNEREPOCH1 is defined as MSR_SGXOWNEREPOCH1 in SDM.
881 **/
882 #define MSR_GOLDMONT_SGXOWNEREPOCH1                   0x00000301
883 
884 
885 //
886 // Define MSR_GOLDMONT_SGXOWNER1 for compatibility due to name change in the SDM.
887 //
888 #define MSR_GOLDMONT_SGXOWNER1                        MSR_GOLDMONT_SGXOWNEREPOCH1
889 
890 
891 /**
892   Core. See Table 2-2. See Section 18.2.4, "Architectural Performance
893   Monitoring Version 4.".
894 
895   @param  ECX  MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)
896   @param  EAX  Lower 32-bits of MSR value.
897                Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
898   @param  EDX  Upper 32-bits of MSR value.
899                Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
900 
901   <b>Example usage</b>
902   @code
903   MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER  Msr;
904 
905   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET);
906   AsmWriteMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);
907   @endcode
908   @note MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.
909 **/
910 #define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
911 
912 /**
913   MSR information returned for MSR index
914   #MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET
915 **/
916 typedef union {
917   ///
918   /// Individual bit fields
919   ///
920   struct {
921     ///
922     /// [Bit 0] Set 1 to clear Ovf_PMC0.
923     ///
924     UINT32  Ovf_PMC0:1;
925     ///
926     /// [Bit 1] Set 1 to clear Ovf_PMC1.
927     ///
928     UINT32  Ovf_PMC1:1;
929     ///
930     /// [Bit 2] Set 1 to clear Ovf_PMC2.
931     ///
932     UINT32  Ovf_PMC2:1;
933     ///
934     /// [Bit 3] Set 1 to clear Ovf_PMC3.
935     ///
936     UINT32  Ovf_PMC3:1;
937     UINT32  Reserved1:28;
938     ///
939     /// [Bit 32] Set 1 to clear Ovf_FixedCtr0.
940     ///
941     UINT32  Ovf_FixedCtr0:1;
942     ///
943     /// [Bit 33] Set 1 to clear Ovf_FixedCtr1.
944     ///
945     UINT32  Ovf_FixedCtr1:1;
946     ///
947     /// [Bit 34] Set 1 to clear Ovf_FixedCtr2.
948     ///
949     UINT32  Ovf_FixedCtr2:1;
950     UINT32  Reserved2:20;
951     ///
952     /// [Bit 55] Set 1 to clear Trace_ToPA_PMI.
953     ///
954     UINT32  Trace_ToPA_PMI:1;
955     UINT32  Reserved3:2;
956     ///
957     /// [Bit 58] Set 1 to clear LBR_Frz.
958     ///
959     UINT32  LBR_Frz:1;
960     ///
961     /// [Bit 59] Set 1 to clear CTR_Frz.
962     ///
963     UINT32  CTR_Frz:1;
964     ///
965     /// [Bit 60] Set 1 to clear ASCI.
966     ///
967     UINT32  ASCI:1;
968     ///
969     /// [Bit 61] Set 1 to clear Ovf_Uncore.
970     ///
971     UINT32  Ovf_Uncore:1;
972     ///
973     /// [Bit 62] Set 1 to clear Ovf_BufDSSAVE.
974     ///
975     UINT32  Ovf_BufDSSAVE:1;
976     ///
977     /// [Bit 63] Set 1 to clear CondChgd.
978     ///
979     UINT32  CondChgd:1;
980   } Bits;
981   ///
982   /// All bit fields as a 64-bit value
983   ///
984   UINT64  Uint64;
985 } MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;
986 
987 
988 /**
989   Core. See Table 2-2. See Section 18.2.4, "Architectural Performance
990   Monitoring Version 4.".
991 
992   @param  ECX  MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)
993   @param  EAX  Lower 32-bits of MSR value.
994                Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
995   @param  EDX  Upper 32-bits of MSR value.
996                Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
997 
998   <b>Example usage</b>
999   @code
1000   MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER  Msr;
1001 
1002   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET);
1003   AsmWriteMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);
1004   @endcode
1005   @note MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.
1006 **/
1007 #define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET 0x00000391
1008 
1009 /**
1010   MSR information returned for MSR index
1011   #MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET
1012 **/
1013 typedef union {
1014   ///
1015   /// Individual bit fields
1016   ///
1017   struct {
1018     ///
1019     /// [Bit 0] Set 1 to cause Ovf_PMC0 = 1.
1020     ///
1021     UINT32  Ovf_PMC0:1;
1022     ///
1023     /// [Bit 1] Set 1 to cause Ovf_PMC1 = 1.
1024     ///
1025     UINT32  Ovf_PMC1:1;
1026     ///
1027     /// [Bit 2] Set 1 to cause Ovf_PMC2 = 1.
1028     ///
1029     UINT32  Ovf_PMC2:1;
1030     ///
1031     /// [Bit 3] Set 1 to cause Ovf_PMC3 = 1.
1032     ///
1033     UINT32  Ovf_PMC3:1;
1034     UINT32  Reserved1:28;
1035     ///
1036     /// [Bit 32] Set 1 to cause Ovf_FixedCtr0 = 1.
1037     ///
1038     UINT32  Ovf_FixedCtr0:1;
1039     ///
1040     /// [Bit 33] Set 1 to cause Ovf_FixedCtr1 = 1.
1041     ///
1042     UINT32  Ovf_FixedCtr1:1;
1043     ///
1044     /// [Bit 34] Set 1 to cause Ovf_FixedCtr2 = 1.
1045     ///
1046     UINT32  Ovf_FixedCtr2:1;
1047     UINT32  Reserved2:20;
1048     ///
1049     /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1.
1050     ///
1051     UINT32  Trace_ToPA_PMI:1;
1052     UINT32  Reserved3:2;
1053     ///
1054     /// [Bit 58] Set 1 to cause LBR_Frz = 1.
1055     ///
1056     UINT32  LBR_Frz:1;
1057     ///
1058     /// [Bit 59] Set 1 to cause CTR_Frz = 1.
1059     ///
1060     UINT32  CTR_Frz:1;
1061     ///
1062     /// [Bit 60] Set 1 to cause ASCI = 1.
1063     ///
1064     UINT32  ASCI:1;
1065     ///
1066     /// [Bit 61] Set 1 to cause Ovf_Uncore.
1067     ///
1068     UINT32  Ovf_Uncore:1;
1069     ///
1070     /// [Bit 62] Set 1 to cause Ovf_BufDSSAVE.
1071     ///
1072     UINT32  Ovf_BufDSSAVE:1;
1073     UINT32  Reserved4:1;
1074   } Bits;
1075   ///
1076   /// All bit fields as a 64-bit value
1077   ///
1078   UINT64  Uint64;
1079 } MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;
1080 
1081 
1082 /**
1083   Core. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling
1084   (PEBS).".
1085 
1086   @param  ECX  MSR_GOLDMONT_PEBS_ENABLE (0x000003F1)
1087   @param  EAX  Lower 32-bits of MSR value.
1088                Described by the type MSR_GOLDMONT_PEBS_ENABLE_REGISTER.
1089   @param  EDX  Upper 32-bits of MSR value.
1090                Described by the type MSR_GOLDMONT_PEBS_ENABLE_REGISTER.
1091 
1092   <b>Example usage</b>
1093   @code
1094   MSR_GOLDMONT_PEBS_ENABLE_REGISTER  Msr;
1095 
1096   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PEBS_ENABLE);
1097   AsmWriteMsr64 (MSR_GOLDMONT_PEBS_ENABLE, Msr.Uint64);
1098   @endcode
1099   @note MSR_GOLDMONT_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
1100 **/
1101 #define MSR_GOLDMONT_PEBS_ENABLE                 0x000003F1
1102 
1103 /**
1104   MSR information returned for MSR index #MSR_GOLDMONT_PEBS_ENABLE
1105 **/
1106 typedef union {
1107   ///
1108   /// Individual bit fields
1109   ///
1110   struct {
1111     ///
1112     /// [Bit 0] Enable PEBS trigger and recording for the programmed event
1113     /// (precise or otherwise) on IA32_PMC0. (R/W).
1114     ///
1115     UINT32  Enable:1;
1116     UINT32  Reserved1:31;
1117     UINT32  Reserved2:32;
1118   } Bits;
1119   ///
1120   /// All bit fields as a 32-bit value
1121   ///
1122   UINT32  Uint32;
1123   ///
1124   /// All bit fields as a 64-bit value
1125   ///
1126   UINT64  Uint64;
1127 } MSR_GOLDMONT_PEBS_ENABLE_REGISTER;
1128 
1129 
1130 /**
1131   Package. Note: C-state values are processor specific C-state code names,
1132   unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3
1133   Residency Counter. (R/O) Value since last reset that this package is in
1134   processor-specific C3 states. Count at the same frequency as the TSC.
1135 
1136   @param  ECX  MSR_GOLDMONT_PKG_C3_RESIDENCY (0x000003F8)
1137   @param  EAX  Lower 32-bits of MSR value.
1138   @param  EDX  Upper 32-bits of MSR value.
1139 
1140   <b>Example usage</b>
1141   @code
1142   UINT64  Msr;
1143 
1144   Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C3_RESIDENCY);
1145   AsmWriteMsr64 (MSR_GOLDMONT_PKG_C3_RESIDENCY, Msr);
1146   @endcode
1147   @note MSR_GOLDMONT_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.
1148 **/
1149 #define MSR_GOLDMONT_PKG_C3_RESIDENCY            0x000003F8
1150 
1151 
1152 /**
1153   Package. Note: C-state values are processor specific C-state code names,
1154   unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6
1155   Residency Counter. (R/O) Value since last reset that this package is in
1156   processor-specific C6 states. Count at the same frequency as the TSC.
1157 
1158   @param  ECX  MSR_GOLDMONT_PKG_C6_RESIDENCY (0x000003F9)
1159   @param  EAX  Lower 32-bits of MSR value.
1160   @param  EDX  Upper 32-bits of MSR value.
1161 
1162   <b>Example usage</b>
1163   @code
1164   UINT64  Msr;
1165 
1166   Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C6_RESIDENCY);
1167   AsmWriteMsr64 (MSR_GOLDMONT_PKG_C6_RESIDENCY, Msr);
1168   @endcode
1169   @note MSR_GOLDMONT_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
1170 **/
1171 #define MSR_GOLDMONT_PKG_C6_RESIDENCY            0x000003F9
1172 
1173 
1174 /**
1175   Core. Note: C-state values are processor specific C-state code names,
1176   unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3
1177   Residency Counter. (R/O) Value since last reset that this core is in
1178   processor-specific C3 states. Count at the same frequency as the TSC.
1179 
1180   @param  ECX  MSR_GOLDMONT_CORE_C3_RESIDENCY (0x000003FC)
1181   @param  EAX  Lower 32-bits of MSR value.
1182   @param  EDX  Upper 32-bits of MSR value.
1183 
1184   <b>Example usage</b>
1185   @code
1186   UINT64  Msr;
1187 
1188   Msr = AsmReadMsr64 (MSR_GOLDMONT_CORE_C3_RESIDENCY);
1189   AsmWriteMsr64 (MSR_GOLDMONT_CORE_C3_RESIDENCY, Msr);
1190   @endcode
1191   @note MSR_GOLDMONT_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.
1192 **/
1193 #define MSR_GOLDMONT_CORE_C3_RESIDENCY           0x000003FC
1194 
1195 
1196 /**
1197   Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability
1198   Enhancement. Accessible only while in SMM.
1199 
1200   @param  ECX  MSR_GOLDMONT_SMM_FEATURE_CONTROL (0x000004E0)
1201   @param  EAX  Lower 32-bits of MSR value.
1202                Described by the type MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER.
1203   @param  EDX  Upper 32-bits of MSR value.
1204                Described by the type MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER.
1205 
1206   <b>Example usage</b>
1207   @code
1208   MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER  Msr;
1209 
1210   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_FEATURE_CONTROL);
1211   AsmWriteMsr64 (MSR_GOLDMONT_SMM_FEATURE_CONTROL, Msr.Uint64);
1212   @endcode
1213   @note MSR_GOLDMONT_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM.
1214 **/
1215 #define MSR_GOLDMONT_SMM_FEATURE_CONTROL         0x000004E0
1216 
1217 /**
1218   MSR information returned for MSR index #MSR_GOLDMONT_SMM_FEATURE_CONTROL
1219 **/
1220 typedef union {
1221   ///
1222   /// Individual bit fields
1223   ///
1224   struct {
1225     ///
1226     /// [Bit 0] Lock (SMM-RWO) When set to '1' locks this register from
1227     /// further changes.
1228     ///
1229     UINT32  Lock:1;
1230     UINT32  Reserved1:1;
1231     ///
1232     /// [Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if
1233     /// MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the
1234     /// logical processors are prevented from executing SMM code outside the
1235     /// ranges defined by the SMRR. When set to '1' any logical processor in
1236     /// the package that attempts to execute SMM code not within the ranges
1237     /// defined by the SMRR will assert an unrecoverable MCE.
1238     ///
1239     UINT32  SMM_Code_Chk_En:1;
1240     UINT32  Reserved2:29;
1241     UINT32  Reserved3:32;
1242   } Bits;
1243   ///
1244   /// All bit fields as a 32-bit value
1245   ///
1246   UINT32  Uint32;
1247   ///
1248   /// All bit fields as a 64-bit value
1249   ///
1250   UINT64  Uint64;
1251 } MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER;
1252 
1253 
1254 /**
1255   Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical
1256   processors in the package. Available only while in SMM and
1257   MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.
1258 
1259   @param  ECX  MSR_GOLDMONT_SMM_DELAYED (0x000004E2)
1260   @param  EAX  Lower 32-bits of MSR value.
1261                Described by the type MSR_GOLDMONT_SMM_DELAYED_REGISTER.
1262   @param  EDX  Upper 32-bits of MSR value.
1263                Described by the type MSR_GOLDMONT_SMM_DELAYED_REGISTER.
1264 
1265   <b>Example usage</b>
1266   @code
1267   MSR_GOLDMONT_SMM_DELAYED_REGISTER  Msr;
1268 
1269   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_DELAYED);
1270   AsmWriteMsr64 (MSR_GOLDMONT_SMM_DELAYED, Msr.Uint64);
1271   @endcode
1272   @note MSR_GOLDMONT_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM.
1273 **/
1274 #define MSR_GOLDMONT_SMM_DELAYED                 0x000004E2
1275 
1276 
1277 /**
1278   Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical
1279   processors in the package. Available only while in SMM.
1280 
1281   @param  ECX  MSR_GOLDMONT_SMM_BLOCKED (0x000004E3)
1282   @param  EAX  Lower 32-bits of MSR value.
1283                Described by the type MSR_GOLDMONT_SMM_BLOCKED_REGISTER.
1284   @param  EDX  Upper 32-bits of MSR value.
1285                Described by the type MSR_GOLDMONT_SMM_BLOCKED_REGISTER.
1286 
1287   <b>Example usage</b>
1288   @code
1289   MSR_GOLDMONT_SMM_BLOCKED_REGISTER  Msr;
1290 
1291   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_BLOCKED);
1292   AsmWriteMsr64 (MSR_GOLDMONT_SMM_BLOCKED, Msr.Uint64);
1293   @endcode
1294   @note MSR_GOLDMONT_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM.
1295 **/
1296 #define MSR_GOLDMONT_SMM_BLOCKED                 0x000004E3
1297 
1298 
1299 /**
1300   Core. Trace Control Register (R/W).
1301 
1302   @param  ECX  MSR_GOLDMONT_IA32_RTIT_CTL (0x00000570)
1303   @param  EAX  Lower 32-bits of MSR value.
1304                Described by the type MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER.
1305   @param  EDX  Upper 32-bits of MSR value.
1306                Described by the type MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER.
1307 
1308   <b>Example usage</b>
1309   @code
1310   MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER  Msr;
1311 
1312   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_RTIT_CTL);
1313   AsmWriteMsr64 (MSR_GOLDMONT_IA32_RTIT_CTL, Msr.Uint64);
1314   @endcode
1315   @note MSR_GOLDMONT_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.
1316 **/
1317 #define MSR_IA32_RTIT_CTL                        0x00000570
1318 
1319 /**
1320   MSR information returned for MSR index #MSR_IA32_RTIT_CTL
1321 **/
1322 typedef union {
1323   ///
1324   /// Individual bit fields
1325   ///
1326   struct {
1327     ///
1328     /// [Bit 0] TraceEn.
1329     ///
1330     UINT32  TraceEn:1;
1331     ///
1332     /// [Bit 1] CYCEn.
1333     ///
1334     UINT32  CYCEn:1;
1335     ///
1336     /// [Bit 2] OS.
1337     ///
1338     UINT32  OS:1;
1339     ///
1340     /// [Bit 3] User.
1341     ///
1342     UINT32  User:1;
1343     UINT32  Reserved1:3;
1344     ///
1345     /// [Bit 7] CR3 filter.
1346     ///
1347     UINT32  CR3:1;
1348     ///
1349     /// [Bit 8] ToPA. Writing 0 will #GP if also setting TraceEn.
1350     ///
1351     UINT32  ToPA:1;
1352     ///
1353     /// [Bit 9] MTCEn.
1354     ///
1355     UINT32  MTCEn:1;
1356     ///
1357     /// [Bit 10] TSCEn.
1358     ///
1359     UINT32  TSCEn:1;
1360     ///
1361     /// [Bit 11] DisRETC.
1362     ///
1363     UINT32  DisRETC:1;
1364     UINT32  Reserved2:1;
1365     ///
1366     /// [Bit 13] BranchEn.
1367     ///
1368     UINT32  BranchEn:1;
1369     ///
1370     /// [Bits 17:14] MTCFreq.
1371     ///
1372     UINT32  MTCFreq:4;
1373     UINT32  Reserved3:1;
1374     ///
1375     /// [Bits 22:19] CYCThresh.
1376     ///
1377     UINT32  CYCThresh:4;
1378     UINT32  Reserved4:1;
1379     ///
1380     /// [Bits 27:24] PSBFreq.
1381     ///
1382     UINT32  PSBFreq:4;
1383     UINT32  Reserved5:4;
1384     ///
1385     /// [Bits 35:32] ADDR0_CFG.
1386     ///
1387     UINT32  ADDR0_CFG:4;
1388     ///
1389     /// [Bits 39:36] ADDR1_CFG.
1390     ///
1391     UINT32  ADDR1_CFG:4;
1392     UINT32  Reserved6:24;
1393   } Bits;
1394   ///
1395   /// All bit fields as a 64-bit value
1396   ///
1397   UINT64  Uint64;
1398 } MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER;
1399 
1400 
1401 /**
1402   Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,
1403   "RAPL Interfaces.".
1404 
1405   @param  ECX  MSR_GOLDMONT_RAPL_POWER_UNIT (0x00000606)
1406   @param  EAX  Lower 32-bits of MSR value.
1407                Described by the type MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER.
1408   @param  EDX  Upper 32-bits of MSR value.
1409                Described by the type MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER.
1410 
1411   <b>Example usage</b>
1412   @code
1413   MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER  Msr;
1414 
1415   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_RAPL_POWER_UNIT);
1416   @endcode
1417   @note MSR_GOLDMONT_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
1418 **/
1419 #define MSR_GOLDMONT_RAPL_POWER_UNIT             0x00000606
1420 
1421 /**
1422   MSR information returned for MSR index #MSR_GOLDMONT_RAPL_POWER_UNIT
1423 **/
1424 typedef union {
1425   ///
1426   /// Individual bit fields
1427   ///
1428   struct {
1429     ///
1430     /// [Bits 3:0] Power Units. Power related information (in Watts) is in
1431     /// unit of, 1W/2^PU; where PU is an unsigned integer represented by bits
1432     /// 3:0. Default value is 1000b, indicating power unit is in 3.9
1433     /// milliWatts increment.
1434     ///
1435     UINT32  PowerUnits:4;
1436     UINT32  Reserved1:4;
1437     ///
1438     /// [Bits 12:8] Energy Status Units. Energy related information (in
1439     /// Joules) is in unit of, 1Joule/ (2^ESU); where ESU is an unsigned
1440     /// integer represented by bits 12:8. Default value is 01110b, indicating
1441     /// energy unit is in 61 microJoules.
1442     ///
1443     UINT32  EnergyStatusUnits:5;
1444     UINT32  Reserved2:3;
1445     ///
1446     /// [Bits 19:16] Time Unit. Time related information (in seconds) is in
1447     /// unit of, 1S/2^TU; where TU is an unsigned integer represented by bits
1448     /// 19:16. Default value is 1010b, indicating power unit is in 0.977
1449     /// millisecond.
1450     ///
1451     UINT32  TimeUnit:4;
1452     UINT32  Reserved3:12;
1453     UINT32  Reserved4:32;
1454   } Bits;
1455   ///
1456   /// All bit fields as a 32-bit value
1457   ///
1458   UINT32  Uint32;
1459   ///
1460   /// All bit fields as a 64-bit value
1461   ///
1462   UINT64  Uint64;
1463 } MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER;
1464 
1465 
1466 /**
1467   Package. Package C3 Interrupt Response Limit (R/W)  Note: C-state values are
1468   processor specific C-state code names, unrelated to MWAIT extension C-state
1469   parameters or ACPI CStates.
1470 
1471   @param  ECX  MSR_GOLDMONT_PKGC3_IRTL (0x0000060A)
1472   @param  EAX  Lower 32-bits of MSR value.
1473                Described by the type MSR_GOLDMONT_PKGC3_IRTL_REGISTER.
1474   @param  EDX  Upper 32-bits of MSR value.
1475                Described by the type MSR_GOLDMONT_PKGC3_IRTL_REGISTER.
1476 
1477   <b>Example usage</b>
1478   @code
1479   MSR_GOLDMONT_PKGC3_IRTL_REGISTER  Msr;
1480 
1481   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC3_IRTL);
1482   AsmWriteMsr64 (MSR_GOLDMONT_PKGC3_IRTL, Msr.Uint64);
1483   @endcode
1484   @note MSR_GOLDMONT_PKGC3_IRTL is defined as MSR_PKGC3_IRTL in SDM.
1485 **/
1486 #define MSR_GOLDMONT_PKGC3_IRTL                  0x0000060A
1487 
1488 /**
1489   MSR information returned for MSR index #MSR_GOLDMONT_PKGC3_IRTL
1490 **/
1491 typedef union {
1492   ///
1493   /// Individual bit fields
1494   ///
1495   struct {
1496     ///
1497     /// [Bits 9:0] Interrupt response time limit (R/W)  Specifies the limit
1498     /// that should be used to decide if the package should be put into a
1499     /// package C3 state.
1500     ///
1501     UINT32  InterruptResponseTimeLimit:10;
1502     ///
1503     /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
1504     /// of the interrupt response time limit. See Table 2-19 for supported
1505     /// time unit encodings.
1506     ///
1507     UINT32  TimeUnit:3;
1508     UINT32  Reserved1:2;
1509     ///
1510     /// [Bit 15] Valid (R/W)  Indicates whether the values in bits 12:0 are
1511     /// valid and can be used by the processor for package C-sate management.
1512     ///
1513     UINT32  Valid:1;
1514     UINT32  Reserved2:16;
1515     UINT32  Reserved3:32;
1516   } Bits;
1517   ///
1518   /// All bit fields as a 32-bit value
1519   ///
1520   UINT32  Uint32;
1521   ///
1522   /// All bit fields as a 64-bit value
1523   ///
1524   UINT64  Uint64;
1525 } MSR_GOLDMONT_PKGC3_IRTL_REGISTER;
1526 
1527 
1528 /**
1529   Package. Package C6/C7S Interrupt Response Limit 1 (R/W)  This MSR defines
1530   the interrupt response time limit used by the processor to manage transition
1531   to package C6 or C7S state. Note: C-state values are processor specific
1532   C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
1533   CStates.
1534 
1535   @param  ECX  MSR_GOLDMONT_PKGC_IRTL1 (0x0000060B)
1536   @param  EAX  Lower 32-bits of MSR value.
1537                Described by the type MSR_GOLDMONT_PKGC_IRTL1_REGISTER.
1538   @param  EDX  Upper 32-bits of MSR value.
1539                Described by the type MSR_GOLDMONT_PKGC_IRTL1_REGISTER.
1540 
1541   <b>Example usage</b>
1542   @code
1543   MSR_GOLDMONT_PKGC_IRTL1_REGISTER  Msr;
1544 
1545   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC_IRTL1);
1546   AsmWriteMsr64 (MSR_GOLDMONT_PKGC_IRTL1, Msr.Uint64);
1547   @endcode
1548   @note MSR_GOLDMONT_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM.
1549 **/
1550 #define MSR_GOLDMONT_PKGC_IRTL1                  0x0000060B
1551 
1552 /**
1553   MSR information returned for MSR index #MSR_GOLDMONT_PKGC_IRTL1
1554 **/
1555 typedef union {
1556   ///
1557   /// Individual bit fields
1558   ///
1559   struct {
1560     ///
1561     /// [Bits 9:0] Interrupt response time limit (R/W)  Specifies the limit
1562     /// that should be used to decide if the package should be put into a
1563     /// package C6 or C7S state.
1564     ///
1565     UINT32  InterruptResponseTimeLimit:10;
1566     ///
1567     /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
1568     /// of the interrupt response time limit. See Table 2-19 for supported
1569     /// time unit encodings.
1570     ///
1571     UINT32  TimeUnit:3;
1572     UINT32  Reserved1:2;
1573     ///
1574     /// [Bit 15] Valid (R/W)  Indicates whether the values in bits 12:0 are
1575     /// valid and can be used by the processor for package C-sate management.
1576     ///
1577     UINT32  Valid:1;
1578     UINT32  Reserved2:16;
1579     UINT32  Reserved3:32;
1580   } Bits;
1581   ///
1582   /// All bit fields as a 32-bit value
1583   ///
1584   UINT32  Uint32;
1585   ///
1586   /// All bit fields as a 64-bit value
1587   ///
1588   UINT64  Uint64;
1589 } MSR_GOLDMONT_PKGC_IRTL1_REGISTER;
1590 
1591 
1592 /**
1593   Package. Package C7 Interrupt Response Limit 2 (R/W)  This MSR defines the
1594   interrupt response time limit used by the processor to manage transition to
1595   package C7 state. Note: C-state values are processor specific C-state code
1596   names, unrelated to MWAIT extension C-state parameters or ACPI CStates.
1597 
1598   @param  ECX  MSR_GOLDMONT_PKGC_IRTL2 (0x0000060C)
1599   @param  EAX  Lower 32-bits of MSR value.
1600                Described by the type MSR_GOLDMONT_PKGC_IRTL2_REGISTER.
1601   @param  EDX  Upper 32-bits of MSR value.
1602                Described by the type MSR_GOLDMONT_PKGC_IRTL2_REGISTER.
1603 
1604   <b>Example usage</b>
1605   @code
1606   MSR_GOLDMONT_PKGC_IRTL2_REGISTER  Msr;
1607 
1608   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC_IRTL2);
1609   AsmWriteMsr64 (MSR_GOLDMONT_PKGC_IRTL2, Msr.Uint64);
1610   @endcode
1611   @note MSR_GOLDMONT_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM.
1612 **/
1613 #define MSR_GOLDMONT_PKGC_IRTL2                  0x0000060C
1614 
1615 /**
1616   MSR information returned for MSR index #MSR_GOLDMONT_PKGC_IRTL2
1617 **/
1618 typedef union {
1619   ///
1620   /// Individual bit fields
1621   ///
1622   struct {
1623     ///
1624     /// [Bits 9:0] Interrupt response time limit (R/W)  Specifies the limit
1625     /// that should be used to decide if the package should be put into a
1626     /// package C7 state.
1627     ///
1628     UINT32  InterruptResponseTimeLimit:10;
1629     ///
1630     /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
1631     /// of the interrupt response time limit. See Table 2-19 for supported
1632     /// time unit encodings.
1633     ///
1634     UINT32  TimeUnit:3;
1635     UINT32  Reserved1:2;
1636     ///
1637     /// [Bit 15] Valid (R/W)  Indicates whether the values in bits 12:0 are
1638     /// valid and can be used by the processor for package C-sate management.
1639     ///
1640     UINT32  Valid:1;
1641     UINT32  Reserved2:16;
1642     UINT32  Reserved3:32;
1643   } Bits;
1644   ///
1645   /// All bit fields as a 32-bit value
1646   ///
1647   UINT32  Uint32;
1648   ///
1649   /// All bit fields as a 64-bit value
1650   ///
1651   UINT64  Uint64;
1652 } MSR_GOLDMONT_PKGC_IRTL2_REGISTER;
1653 
1654 
1655 /**
1656   Package. Note: C-state values are processor specific C-state code names,
1657   unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2
1658   Residency Counter. (R/O) Value since last reset that this package is in
1659   processor-specific C2 states. Count at the same frequency as the TSC.
1660 
1661   @param  ECX  MSR_GOLDMONT_PKG_C2_RESIDENCY (0x0000060D)
1662   @param  EAX  Lower 32-bits of MSR value.
1663   @param  EDX  Upper 32-bits of MSR value.
1664 
1665   <b>Example usage</b>
1666   @code
1667   UINT64  Msr;
1668 
1669   Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C2_RESIDENCY);
1670   AsmWriteMsr64 (MSR_GOLDMONT_PKG_C2_RESIDENCY, Msr);
1671   @endcode
1672   @note MSR_GOLDMONT_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
1673 **/
1674 #define MSR_GOLDMONT_PKG_C2_RESIDENCY            0x0000060D
1675 
1676 
1677 /**
1678   Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package
1679   RAPL Domain.".
1680 
1681   @param  ECX  MSR_GOLDMONT_PKG_POWER_LIMIT (0x00000610)
1682   @param  EAX  Lower 32-bits of MSR value.
1683   @param  EDX  Upper 32-bits of MSR value.
1684 
1685   <b>Example usage</b>
1686   @code
1687   UINT64  Msr;
1688 
1689   Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_POWER_LIMIT);
1690   AsmWriteMsr64 (MSR_GOLDMONT_PKG_POWER_LIMIT, Msr);
1691   @endcode
1692   @note MSR_GOLDMONT_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
1693 **/
1694 #define MSR_GOLDMONT_PKG_POWER_LIMIT             0x00000610
1695 
1696 
1697 /**
1698   Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
1699 
1700   @param  ECX  MSR_GOLDMONT_PKG_ENERGY_STATUS (0x00000611)
1701   @param  EAX  Lower 32-bits of MSR value.
1702   @param  EDX  Upper 32-bits of MSR value.
1703 
1704   <b>Example usage</b>
1705   @code
1706   UINT64  Msr;
1707 
1708   Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_ENERGY_STATUS);
1709   @endcode
1710   @note MSR_GOLDMONT_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.
1711 **/
1712 #define MSR_GOLDMONT_PKG_ENERGY_STATUS           0x00000611
1713 
1714 
1715 /**
1716   Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
1717 
1718   @param  ECX  MSR_GOLDMONT_PKG_PERF_STATUS (0x00000613)
1719   @param  EAX  Lower 32-bits of MSR value.
1720   @param  EDX  Upper 32-bits of MSR value.
1721 
1722   <b>Example usage</b>
1723   @code
1724   UINT64  Msr;
1725 
1726   Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_PERF_STATUS);
1727   @endcode
1728   @note MSR_GOLDMONT_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
1729 **/
1730 #define MSR_GOLDMONT_PKG_PERF_STATUS             0x00000613
1731 
1732 
1733 /**
1734   Package. PKG RAPL Parameters (R/W).
1735 
1736   @param  ECX  MSR_GOLDMONT_PKG_POWER_INFO (0x00000614)
1737   @param  EAX  Lower 32-bits of MSR value.
1738                Described by the type MSR_GOLDMONT_PKG_POWER_INFO_REGISTER.
1739   @param  EDX  Upper 32-bits of MSR value.
1740                Described by the type MSR_GOLDMONT_PKG_POWER_INFO_REGISTER.
1741 
1742   <b>Example usage</b>
1743   @code
1744   MSR_GOLDMONT_PKG_POWER_INFO_REGISTER  Msr;
1745 
1746   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKG_POWER_INFO);
1747   AsmWriteMsr64 (MSR_GOLDMONT_PKG_POWER_INFO, Msr.Uint64);
1748   @endcode
1749   @note MSR_GOLDMONT_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
1750 **/
1751 #define MSR_GOLDMONT_PKG_POWER_INFO              0x00000614
1752 
1753 /**
1754   MSR information returned for MSR index #MSR_GOLDMONT_PKG_POWER_INFO
1755 **/
1756 typedef union {
1757   ///
1758   /// Individual bit fields
1759   ///
1760   struct {
1761     ///
1762     /// [Bits 14:0] Thermal Spec Power (R/W)  See Section 14.9.3, "Package
1763     /// RAPL Domain.".
1764     ///
1765     UINT32  ThermalSpecPower:15;
1766     UINT32  Reserved1:1;
1767     ///
1768     /// [Bits 30:16] Minimum Power (R/W)  See Section 14.9.3, "Package RAPL
1769     /// Domain.".
1770     ///
1771     UINT32  MinimumPower:15;
1772     UINT32  Reserved2:1;
1773     ///
1774     /// [Bits 46:32] Maximum Power (R/W)  See Section 14.9.3, "Package RAPL
1775     /// Domain.".
1776     ///
1777     UINT32  MaximumPower:15;
1778     UINT32  Reserved3:1;
1779     ///
1780     /// [Bits 54:48] Maximum Time Window (R/W)  Specified by 2^Y * (1.0 +
1781     /// Z/4.0) * Time_Unit, where "Y" is the unsigned integer value
1782     /// represented. by bits 52:48, "Z" is an unsigned integer represented by
1783     /// bits 54:53. "Time_Unit" is specified by the "Time Units" field of
1784     /// MSR_RAPL_POWER_UNIT.
1785     ///
1786     UINT32  MaximumTimeWindow:7;
1787     UINT32  Reserved4:9;
1788   } Bits;
1789   ///
1790   /// All bit fields as a 64-bit value
1791   ///
1792   UINT64  Uint64;
1793 } MSR_GOLDMONT_PKG_POWER_INFO_REGISTER;
1794 
1795 
1796 /**
1797   Package. DRAM RAPL Power Limit Control (R/W)  See Section 14.9.5, "DRAM RAPL
1798   Domain.".
1799 
1800   @param  ECX  MSR_GOLDMONT_DRAM_POWER_LIMIT (0x00000618)
1801   @param  EAX  Lower 32-bits of MSR value.
1802   @param  EDX  Upper 32-bits of MSR value.
1803 
1804   <b>Example usage</b>
1805   @code
1806   UINT64  Msr;
1807 
1808   Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_POWER_LIMIT);
1809   AsmWriteMsr64 (MSR_GOLDMONT_DRAM_POWER_LIMIT, Msr);
1810   @endcode
1811   @note MSR_GOLDMONT_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
1812 **/
1813 #define MSR_GOLDMONT_DRAM_POWER_LIMIT            0x00000618
1814 
1815 
1816 /**
1817   Package. DRAM Energy Status (R/O)  See Section 14.9.5, "DRAM RAPL Domain.".
1818 
1819   @param  ECX  MSR_GOLDMONT_DRAM_ENERGY_STATUS (0x00000619)
1820   @param  EAX  Lower 32-bits of MSR value.
1821   @param  EDX  Upper 32-bits of MSR value.
1822 
1823   <b>Example usage</b>
1824   @code
1825   UINT64  Msr;
1826 
1827   Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_ENERGY_STATUS);
1828   @endcode
1829   @note MSR_GOLDMONT_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
1830 **/
1831 #define MSR_GOLDMONT_DRAM_ENERGY_STATUS          0x00000619
1832 
1833 
1834 /**
1835   Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
1836   RAPL Domain.".
1837 
1838   @param  ECX  MSR_GOLDMONT_DRAM_PERF_STATUS (0x0000061B)
1839   @param  EAX  Lower 32-bits of MSR value.
1840   @param  EDX  Upper 32-bits of MSR value.
1841 
1842   <b>Example usage</b>
1843   @code
1844   UINT64  Msr;
1845 
1846   Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_PERF_STATUS);
1847   @endcode
1848   @note MSR_GOLDMONT_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
1849 **/
1850 #define MSR_GOLDMONT_DRAM_PERF_STATUS            0x0000061B
1851 
1852 
1853 /**
1854   Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
1855 
1856   @param  ECX  MSR_GOLDMONT_DRAM_POWER_INFO (0x0000061C)
1857   @param  EAX  Lower 32-bits of MSR value.
1858   @param  EDX  Upper 32-bits of MSR value.
1859 
1860   <b>Example usage</b>
1861   @code
1862   UINT64  Msr;
1863 
1864   Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_POWER_INFO);
1865   AsmWriteMsr64 (MSR_GOLDMONT_DRAM_POWER_INFO, Msr);
1866   @endcode
1867   @note MSR_GOLDMONT_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
1868 **/
1869 #define MSR_GOLDMONT_DRAM_POWER_INFO             0x0000061C
1870 
1871 
1872 /**
1873   Package. Note: C-state values are processor specific C-state code names,.
1874   Package C10 Residency Counter. (R/O) Value since last reset that the entire
1875   SOC is in an S0i3 state. Count at the same frequency as the TSC.
1876 
1877   @param  ECX  MSR_GOLDMONT_PKG_C10_RESIDENCY (0x00000632)
1878   @param  EAX  Lower 32-bits of MSR value.
1879   @param  EDX  Upper 32-bits of MSR value.
1880 
1881   <b>Example usage</b>
1882   @code
1883   UINT64  Msr;
1884 
1885   Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C10_RESIDENCY);
1886   AsmWriteMsr64 (MSR_GOLDMONT_PKG_C10_RESIDENCY, Msr);
1887   @endcode
1888   @note MSR_GOLDMONT_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.
1889 **/
1890 #define MSR_GOLDMONT_PKG_C10_RESIDENCY           0x00000632
1891 
1892 
1893 /**
1894   Package. PP0 Energy Status (R/O)  See Section 14.9.4, "PP0/PP1 RAPL
1895   Domains.".
1896 
1897   @param  ECX  MSR_GOLDMONT_PP0_ENERGY_STATUS (0x00000639)
1898   @param  EAX  Lower 32-bits of MSR value.
1899   @param  EDX  Upper 32-bits of MSR value.
1900 
1901   <b>Example usage</b>
1902   @code
1903   UINT64  Msr;
1904 
1905   Msr = AsmReadMsr64 (MSR_GOLDMONT_PP0_ENERGY_STATUS);
1906   @endcode
1907   @note MSR_GOLDMONT_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
1908 **/
1909 #define MSR_GOLDMONT_PP0_ENERGY_STATUS           0x00000639
1910 
1911 
1912 /**
1913   Package. PP1 Energy Status (R/O)  See Section 14.9.4, "PP0/PP1 RAPL
1914   Domains.".
1915 
1916   @param  ECX  MSR_GOLDMONT_PP1_ENERGY_STATUS (0x00000641)
1917   @param  EAX  Lower 32-bits of MSR value.
1918   @param  EDX  Upper 32-bits of MSR value.
1919 
1920   <b>Example usage</b>
1921   @code
1922   UINT64  Msr;
1923 
1924   Msr = AsmReadMsr64 (MSR_GOLDMONT_PP1_ENERGY_STATUS);
1925   @endcode
1926   @note MSR_GOLDMONT_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.
1927 **/
1928 #define MSR_GOLDMONT_PP1_ENERGY_STATUS           0x00000641
1929 
1930 
1931 /**
1932   Package. ConfigTDP Control (R/W).
1933 
1934   @param  ECX  MSR_GOLDMONT_TURBO_ACTIVATION_RATIO (0x0000064C)
1935   @param  EAX  Lower 32-bits of MSR value.
1936                Described by the type MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER.
1937   @param  EDX  Upper 32-bits of MSR value.
1938                Described by the type MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER.
1939 
1940   <b>Example usage</b>
1941   @code
1942   MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER  Msr;
1943 
1944   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_ACTIVATION_RATIO);
1945   AsmWriteMsr64 (MSR_GOLDMONT_TURBO_ACTIVATION_RATIO, Msr.Uint64);
1946   @endcode
1947   @note MSR_GOLDMONT_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.
1948 **/
1949 #define MSR_GOLDMONT_TURBO_ACTIVATION_RATIO      0x0000064C
1950 
1951 /**
1952   MSR information returned for MSR index #MSR_GOLDMONT_TURBO_ACTIVATION_RATIO
1953 **/
1954 typedef union {
1955   ///
1956   /// Individual bit fields
1957   ///
1958   struct {
1959     ///
1960     /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this
1961     /// field.
1962     ///
1963     UINT32  MAX_NON_TURBO_RATIO:8;
1964     UINT32  Reserved1:23;
1965     ///
1966     /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the
1967     /// content of this register is locked until a reset.
1968     ///
1969     UINT32  TURBO_ACTIVATION_RATIO_Lock:1;
1970     UINT32  Reserved2:32;
1971   } Bits;
1972   ///
1973   /// All bit fields as a 32-bit value
1974   ///
1975   UINT32  Uint32;
1976   ///
1977   /// All bit fields as a 64-bit value
1978   ///
1979   UINT64  Uint64;
1980 } MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER;
1981 
1982 
1983 /**
1984   Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
1985   refers to processor core frequency).
1986 
1987   @param  ECX  MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS (0x0000064F)
1988   @param  EAX  Lower 32-bits of MSR value.
1989                Described by the type MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER.
1990   @param  EDX  Upper 32-bits of MSR value.
1991                Described by the type MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER.
1992 
1993   <b>Example usage</b>
1994   @code
1995   MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER  Msr;
1996 
1997   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS);
1998   AsmWriteMsr64 (MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
1999   @endcode
2000   @note MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
2001 **/
2002 #define MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS     0x0000064F
2003 
2004 /**
2005   MSR information returned for MSR index #MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS
2006 **/
2007 typedef union {
2008   ///
2009   /// Individual bit fields
2010   ///
2011   struct {
2012     ///
2013     /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is
2014     /// reduced below the operating system request due to assertion of
2015     /// external PROCHOT.
2016     ///
2017     UINT32  PROCHOTStatus:1;
2018     ///
2019     /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
2020     /// operating system request due to a thermal event.
2021     ///
2022     UINT32  ThermalStatus:1;
2023     ///
2024     /// [Bit 2] Package-Level Power Limiting PL1 Status (R0) When set,
2025     /// frequency is reduced below the operating system request due to
2026     /// package-level power limiting PL1.
2027     ///
2028     UINT32  PL1Status:1;
2029     ///
2030     /// [Bit 3] Package-Level PL2 Power Limiting Status (R0) When set,
2031     /// frequency is reduced below the operating system request due to
2032     /// package-level power limiting PL2.
2033     ///
2034     UINT32  PL2Status:1;
2035     UINT32  Reserved1:5;
2036     ///
2037     /// [Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced
2038     /// below the operating system request due to domain-level power limiting.
2039     ///
2040     UINT32  PowerLimitingStatus:1;
2041     ///
2042     /// [Bit 10] VR Therm Alert Status (R0) When set, frequency is reduced
2043     /// below the operating system request due to a thermal alert from the
2044     /// Voltage Regulator.
2045     ///
2046     UINT32  VRThermAlertStatus:1;
2047     ///
2048     /// [Bit 11] Max Turbo Limit Status (R0) When set, frequency is reduced
2049     /// below the operating system request due to multi-core turbo limits.
2050     ///
2051     UINT32  MaxTurboLimitStatus:1;
2052     ///
2053     /// [Bit 12] Electrical Design Point Status (R0) When set, frequency is
2054     /// reduced below the operating system request due to electrical design
2055     /// point constraints (e.g. maximum electrical current consumption).
2056     ///
2057     UINT32  ElectricalDesignPointStatus:1;
2058     ///
2059     /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency
2060     /// is reduced below the operating system request due to Turbo transition
2061     /// attenuation. This prevents performance degradation due to frequent
2062     /// operating ratio changes.
2063     ///
2064     UINT32  TurboTransitionAttenuationStatus:1;
2065     ///
2066     /// [Bit 14] Maximum Efficiency Frequency Status (R0) When set, frequency
2067     /// is reduced below the maximum efficiency frequency.
2068     ///
2069     UINT32  MaximumEfficiencyFrequencyStatus:1;
2070     UINT32  Reserved2:1;
2071     ///
2072     /// [Bit 16] PROCHOT Log  When set, indicates that the PROCHOT Status bit
2073     /// has asserted since the log bit was last cleared. This log bit will
2074     /// remain set until cleared by software writing 0.
2075     ///
2076     UINT32  PROCHOT:1;
2077     ///
2078     /// [Bit 17] Thermal Log  When set, indicates that the Thermal Status bit
2079     /// has asserted since the log bit was last cleared. This log bit will
2080     /// remain set until cleared by software writing 0.
2081     ///
2082     UINT32  ThermalLog:1;
2083     ///
2084     /// [Bit 18] Package-Level PL1 Power Limiting Log  When set, indicates
2085     /// that the Package Level PL1 Power Limiting Status bit has asserted
2086     /// since the log bit was last cleared. This log bit will remain set until
2087     /// cleared by software writing 0.
2088     ///
2089     UINT32  PL1Log:1;
2090     ///
2091     /// [Bit 19] Package-Level PL2 Power Limiting Log When set, indicates that
2092     /// the Package Level PL2 Power Limiting Status bit has asserted since the
2093     /// log bit was last cleared. This log bit will remain set until cleared
2094     /// by software writing 0.
2095     ///
2096     UINT32  PL2Log:1;
2097     UINT32  Reserved3:5;
2098     ///
2099     /// [Bit 25] Core Power Limiting Log  When set, indicates that the Core
2100     /// Power Limiting Status bit has asserted since the log bit was last
2101     /// cleared. This log bit will remain set until cleared by software
2102     /// writing 0.
2103     ///
2104     UINT32  CorePowerLimitingLog:1;
2105     ///
2106     /// [Bit 26] VR Therm Alert Log  When set, indicates that the VR Therm
2107     /// Alert Status bit has asserted since the log bit was last cleared. This
2108     /// log bit will remain set until cleared by software writing 0.
2109     ///
2110     UINT32  VRThermAlertLog:1;
2111     ///
2112     /// [Bit 27] Max Turbo Limit Log When set, indicates that the Max Turbo
2113     /// Limit Status bit has asserted since the log bit was last cleared. This
2114     /// log bit will remain set until cleared by software writing 0.
2115     ///
2116     UINT32  MaxTurboLimitLog:1;
2117     ///
2118     /// [Bit 28] Electrical Design Point Log  When set, indicates that the EDP
2119     /// Status bit has asserted since the log bit was last cleared. This log
2120     /// bit will remain set until cleared by software writing 0.
2121     ///
2122     UINT32  ElectricalDesignPointLog:1;
2123     ///
2124     /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
2125     /// Turbo Transition Attenuation Status bit has asserted since the log bit
2126     /// was last cleared. This log bit will remain set until cleared by
2127     /// software writing 0.
2128     ///
2129     UINT32  TurboTransitionAttenuationLog:1;
2130     ///
2131     /// [Bit 30] Maximum Efficiency Frequency Log  When set, indicates that
2132     /// the Maximum Efficiency Frequency Status bit has asserted since the log
2133     /// bit was last cleared. This log bit will remain set until cleared by
2134     /// software writing 0.
2135     ///
2136     UINT32  MaximumEfficiencyFrequencyLog:1;
2137     UINT32  Reserved4:1;
2138     UINT32  Reserved5:32;
2139   } Bits;
2140   ///
2141   /// All bit fields as a 32-bit value
2142   ///
2143   UINT32  Uint32;
2144   ///
2145   /// All bit fields as a 64-bit value
2146   ///
2147   UINT64  Uint64;
2148 } MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER;
2149 
2150 
2151 /**
2152   Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch
2153   record registers on the last branch record stack. The From_IP part of the
2154   stack contains pointers to the source instruction . See also: -  Last Branch
2155   Record Stack TOS at 1C9H -  Section 17.6 and record format in Section
2156   17.4.8.1.
2157 
2158   @param  ECX  MSR_GOLDMONT_LASTBRANCH_n_FROM_IP
2159   @param  EAX  Lower 32-bits of MSR value.
2160                Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER.
2161   @param  EDX  Upper 32-bits of MSR value.
2162                Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER.
2163 
2164   <b>Example usage</b>
2165   @code
2166   MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER  Msr;
2167 
2168   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_n_FROM_IP);
2169   AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_n_FROM_IP, Msr.Uint64);
2170   @endcode
2171   @note MSR_GOLDMONT_LASTBRANCH_0_FROM_IP  is defined as MSR_LASTBRANCH_0_FROM_IP  in SDM.
2172         MSR_GOLDMONT_LASTBRANCH_1_FROM_IP  is defined as MSR_LASTBRANCH_1_FROM_IP  in SDM.
2173         MSR_GOLDMONT_LASTBRANCH_2_FROM_IP  is defined as MSR_LASTBRANCH_2_FROM_IP  in SDM.
2174         MSR_GOLDMONT_LASTBRANCH_3_FROM_IP  is defined as MSR_LASTBRANCH_3_FROM_IP  in SDM.
2175         MSR_GOLDMONT_LASTBRANCH_4_FROM_IP  is defined as MSR_LASTBRANCH_4_FROM_IP  in SDM.
2176         MSR_GOLDMONT_LASTBRANCH_5_FROM_IP  is defined as MSR_LASTBRANCH_5_FROM_IP  in SDM.
2177         MSR_GOLDMONT_LASTBRANCH_6_FROM_IP  is defined as MSR_LASTBRANCH_6_FROM_IP  in SDM.
2178         MSR_GOLDMONT_LASTBRANCH_7_FROM_IP  is defined as MSR_LASTBRANCH_7_FROM_IP  in SDM.
2179         MSR_GOLDMONT_LASTBRANCH_8_FROM_IP  is defined as MSR_LASTBRANCH_8_FROM_IP  in SDM.
2180         MSR_GOLDMONT_LASTBRANCH_9_FROM_IP  is defined as MSR_LASTBRANCH_9_FROM_IP  in SDM.
2181         MSR_GOLDMONT_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.
2182         MSR_GOLDMONT_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.
2183         MSR_GOLDMONT_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.
2184         MSR_GOLDMONT_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.
2185         MSR_GOLDMONT_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.
2186         MSR_GOLDMONT_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.
2187         MSR_GOLDMONT_LASTBRANCH_16_FROM_IP is defined as MSR_LASTBRANCH_16_FROM_IP in SDM.
2188         MSR_GOLDMONT_LASTBRANCH_17_FROM_IP is defined as MSR_LASTBRANCH_17_FROM_IP in SDM.
2189         MSR_GOLDMONT_LASTBRANCH_18_FROM_IP is defined as MSR_LASTBRANCH_18_FROM_IP in SDM.
2190         MSR_GOLDMONT_LASTBRANCH_19_FROM_IP is defined as MSR_LASTBRANCH_19_FROM_IP in SDM.
2191         MSR_GOLDMONT_LASTBRANCH_20_FROM_IP is defined as MSR_LASTBRANCH_20_FROM_IP in SDM.
2192         MSR_GOLDMONT_LASTBRANCH_21_FROM_IP is defined as MSR_LASTBRANCH_21_FROM_IP in SDM.
2193         MSR_GOLDMONT_LASTBRANCH_22_FROM_IP is defined as MSR_LASTBRANCH_22_FROM_IP in SDM.
2194         MSR_GOLDMONT_LASTBRANCH_23_FROM_IP is defined as MSR_LASTBRANCH_23_FROM_IP in SDM.
2195         MSR_GOLDMONT_LASTBRANCH_24_FROM_IP is defined as MSR_LASTBRANCH_24_FROM_IP in SDM.
2196         MSR_GOLDMONT_LASTBRANCH_25_FROM_IP is defined as MSR_LASTBRANCH_25_FROM_IP in SDM.
2197         MSR_GOLDMONT_LASTBRANCH_26_FROM_IP is defined as MSR_LASTBRANCH_26_FROM_IP in SDM.
2198         MSR_GOLDMONT_LASTBRANCH_27_FROM_IP is defined as MSR_LASTBRANCH_27_FROM_IP in SDM.
2199         MSR_GOLDMONT_LASTBRANCH_28_FROM_IP is defined as MSR_LASTBRANCH_28_FROM_IP in SDM.
2200         MSR_GOLDMONT_LASTBRANCH_29_FROM_IP is defined as MSR_LASTBRANCH_29_FROM_IP in SDM.
2201         MSR_GOLDMONT_LASTBRANCH_30_FROM_IP is defined as MSR_LASTBRANCH_30_FROM_IP in SDM.
2202         MSR_GOLDMONT_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM.
2203   @{
2204 **/
2205 #define MSR_GOLDMONT_LASTBRANCH_0_FROM_IP        0x00000680
2206 #define MSR_GOLDMONT_LASTBRANCH_1_FROM_IP        0x00000681
2207 #define MSR_GOLDMONT_LASTBRANCH_2_FROM_IP        0x00000682
2208 #define MSR_GOLDMONT_LASTBRANCH_3_FROM_IP        0x00000683
2209 #define MSR_GOLDMONT_LASTBRANCH_4_FROM_IP        0x00000684
2210 #define MSR_GOLDMONT_LASTBRANCH_5_FROM_IP        0x00000685
2211 #define MSR_GOLDMONT_LASTBRANCH_6_FROM_IP        0x00000686
2212 #define MSR_GOLDMONT_LASTBRANCH_7_FROM_IP        0x00000687
2213 #define MSR_GOLDMONT_LASTBRANCH_8_FROM_IP        0x00000688
2214 #define MSR_GOLDMONT_LASTBRANCH_9_FROM_IP        0x00000689
2215 #define MSR_GOLDMONT_LASTBRANCH_10_FROM_IP       0x0000068A
2216 #define MSR_GOLDMONT_LASTBRANCH_11_FROM_IP       0x0000068B
2217 #define MSR_GOLDMONT_LASTBRANCH_12_FROM_IP       0x0000068C
2218 #define MSR_GOLDMONT_LASTBRANCH_13_FROM_IP       0x0000068D
2219 #define MSR_GOLDMONT_LASTBRANCH_14_FROM_IP       0x0000068E
2220 #define MSR_GOLDMONT_LASTBRANCH_15_FROM_IP       0x0000068F
2221 #define MSR_GOLDMONT_LASTBRANCH_16_FROM_IP       0x00000690
2222 #define MSR_GOLDMONT_LASTBRANCH_17_FROM_IP       0x00000691
2223 #define MSR_GOLDMONT_LASTBRANCH_18_FROM_IP       0x00000692
2224 #define MSR_GOLDMONT_LASTBRANCH_19_FROM_IP       0x00000693
2225 #define MSR_GOLDMONT_LASTBRANCH_20_FROM_IP       0x00000694
2226 #define MSR_GOLDMONT_LASTBRANCH_21_FROM_IP       0x00000695
2227 #define MSR_GOLDMONT_LASTBRANCH_22_FROM_IP       0x00000696
2228 #define MSR_GOLDMONT_LASTBRANCH_23_FROM_IP       0x00000697
2229 #define MSR_GOLDMONT_LASTBRANCH_24_FROM_IP       0x00000698
2230 #define MSR_GOLDMONT_LASTBRANCH_25_FROM_IP       0x00000699
2231 #define MSR_GOLDMONT_LASTBRANCH_26_FROM_IP       0x0000069A
2232 #define MSR_GOLDMONT_LASTBRANCH_27_FROM_IP       0x0000069B
2233 #define MSR_GOLDMONT_LASTBRANCH_28_FROM_IP       0x0000069C
2234 #define MSR_GOLDMONT_LASTBRANCH_29_FROM_IP       0x0000069D
2235 #define MSR_GOLDMONT_LASTBRANCH_30_FROM_IP       0x0000069E
2236 #define MSR_GOLDMONT_LASTBRANCH_31_FROM_IP       0x0000069F
2237 /// @}
2238 
2239 /**
2240   MSR information returned for MSR indexes #MSR_GOLDMONT_LASTBRANCH_0_FROM_IP
2241   to #MSR_GOLDMONT_LASTBRANCH_31_FROM_IP.
2242 **/
2243 typedef union {
2244   ///
2245   /// Individual bit fields
2246   ///
2247   struct {
2248     ///
2249     /// [Bit 31:0] From Linear Address (R/W).
2250     ///
2251     UINT32  FromLinearAddress:32;
2252     ///
2253     /// [Bit 47:32] From Linear Address (R/W).
2254     ///
2255     UINT32  FromLinearAddressHi:16;
2256     ///
2257     /// [Bits 62:48] Signed extension of bits 47:0.
2258     ///
2259     UINT32  SignedExtension:15;
2260     ///
2261     /// [Bit 63] Mispred.
2262     ///
2263     UINT32  Mispred:1;
2264   } Bits;
2265   ///
2266   /// All bit fields as a 32-bit value
2267   ///
2268   UINT32  Uint32;
2269   ///
2270   /// All bit fields as a 64-bit value
2271   ///
2272   UINT64  Uint64;
2273 } MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER;
2274 
2275 
2276 /**
2277   Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record
2278   registers on the last branch record stack. The To_IP part of the stack
2279   contains pointers to the Destination instruction and elapsed cycles from
2280   last LBR update. See also: - Section 17.6.
2281 
2282   @param  ECX  MSR_GOLDMONT_LASTBRANCH_n_TO_IP
2283   @param  EAX  Lower 32-bits of MSR value.
2284                Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER.
2285   @param  EDX  Upper 32-bits of MSR value.
2286                Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER.
2287 
2288   <b>Example usage</b>
2289   @code
2290   MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER  Msr;
2291 
2292   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_0_TO_IP);
2293   AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_0_TO_IP, Msr.Uint64);
2294   @endcode
2295   @note MSR_GOLDMONT_LASTBRANCH_0_TO_IP  is defined as MSR_LASTBRANCH_0_TO_IP  in SDM.
2296         MSR_GOLDMONT_LASTBRANCH_1_TO_IP  is defined as MSR_LASTBRANCH_1_TO_IP  in SDM.
2297         MSR_GOLDMONT_LASTBRANCH_2_TO_IP  is defined as MSR_LASTBRANCH_2_TO_IP  in SDM.
2298         MSR_GOLDMONT_LASTBRANCH_3_TO_IP  is defined as MSR_LASTBRANCH_3_TO_IP  in SDM.
2299         MSR_GOLDMONT_LASTBRANCH_4_TO_IP  is defined as MSR_LASTBRANCH_4_TO_IP  in SDM.
2300         MSR_GOLDMONT_LASTBRANCH_5_TO_IP  is defined as MSR_LASTBRANCH_5_TO_IP  in SDM.
2301         MSR_GOLDMONT_LASTBRANCH_6_TO_IP  is defined as MSR_LASTBRANCH_6_TO_IP  in SDM.
2302         MSR_GOLDMONT_LASTBRANCH_7_TO_IP  is defined as MSR_LASTBRANCH_7_TO_IP  in SDM.
2303         MSR_GOLDMONT_LASTBRANCH_8_TO_IP  is defined as MSR_LASTBRANCH_8_TO_IP  in SDM.
2304         MSR_GOLDMONT_LASTBRANCH_9_TO_IP  is defined as MSR_LASTBRANCH_9_TO_IP  in SDM.
2305         MSR_GOLDMONT_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.
2306         MSR_GOLDMONT_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.
2307         MSR_GOLDMONT_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.
2308         MSR_GOLDMONT_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.
2309         MSR_GOLDMONT_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.
2310         MSR_GOLDMONT_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.
2311         MSR_GOLDMONT_LASTBRANCH_16_TO_IP is defined as MSR_LASTBRANCH_16_TO_IP in SDM.
2312         MSR_GOLDMONT_LASTBRANCH_17_TO_IP is defined as MSR_LASTBRANCH_17_TO_IP in SDM.
2313         MSR_GOLDMONT_LASTBRANCH_18_TO_IP is defined as MSR_LASTBRANCH_18_TO_IP in SDM.
2314         MSR_GOLDMONT_LASTBRANCH_19_TO_IP is defined as MSR_LASTBRANCH_19_TO_IP in SDM.
2315         MSR_GOLDMONT_LASTBRANCH_20_TO_IP is defined as MSR_LASTBRANCH_20_TO_IP in SDM.
2316         MSR_GOLDMONT_LASTBRANCH_21_TO_IP is defined as MSR_LASTBRANCH_21_TO_IP in SDM.
2317         MSR_GOLDMONT_LASTBRANCH_22_TO_IP is defined as MSR_LASTBRANCH_22_TO_IP in SDM.
2318         MSR_GOLDMONT_LASTBRANCH_23_TO_IP is defined as MSR_LASTBRANCH_23_TO_IP in SDM.
2319         MSR_GOLDMONT_LASTBRANCH_24_TO_IP is defined as MSR_LASTBRANCH_24_TO_IP in SDM.
2320         MSR_GOLDMONT_LASTBRANCH_25_TO_IP is defined as MSR_LASTBRANCH_25_TO_IP in SDM.
2321         MSR_GOLDMONT_LASTBRANCH_26_TO_IP is defined as MSR_LASTBRANCH_26_TO_IP in SDM.
2322         MSR_GOLDMONT_LASTBRANCH_27_TO_IP is defined as MSR_LASTBRANCH_27_TO_IP in SDM.
2323         MSR_GOLDMONT_LASTBRANCH_28_TO_IP is defined as MSR_LASTBRANCH_28_TO_IP in SDM.
2324         MSR_GOLDMONT_LASTBRANCH_29_TO_IP is defined as MSR_LASTBRANCH_29_TO_IP in SDM.
2325         MSR_GOLDMONT_LASTBRANCH_30_TO_IP is defined as MSR_LASTBRANCH_30_TO_IP in SDM.
2326         MSR_GOLDMONT_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM.
2327   @{
2328 **/
2329 #define MSR_GOLDMONT_LASTBRANCH_0_TO_IP          0x000006C0
2330 #define MSR_GOLDMONT_LASTBRANCH_1_TO_IP          0x000006C1
2331 #define MSR_GOLDMONT_LASTBRANCH_2_TO_IP          0x000006C2
2332 #define MSR_GOLDMONT_LASTBRANCH_3_TO_IP          0x000006C3
2333 #define MSR_GOLDMONT_LASTBRANCH_4_TO_IP          0x000006C4
2334 #define MSR_GOLDMONT_LASTBRANCH_5_TO_IP          0x000006C5
2335 #define MSR_GOLDMONT_LASTBRANCH_6_TO_IP          0x000006C6
2336 #define MSR_GOLDMONT_LASTBRANCH_7_TO_IP          0x000006C7
2337 #define MSR_GOLDMONT_LASTBRANCH_8_TO_IP          0x000006C8
2338 #define MSR_GOLDMONT_LASTBRANCH_9_TO_IP          0x000006C9
2339 #define MSR_GOLDMONT_LASTBRANCH_10_TO_IP         0x000006CA
2340 #define MSR_GOLDMONT_LASTBRANCH_11_TO_IP         0x000006CB
2341 #define MSR_GOLDMONT_LASTBRANCH_12_TO_IP         0x000006CC
2342 #define MSR_GOLDMONT_LASTBRANCH_13_TO_IP         0x000006CD
2343 #define MSR_GOLDMONT_LASTBRANCH_14_TO_IP         0x000006CE
2344 #define MSR_GOLDMONT_LASTBRANCH_15_TO_IP         0x000006CF
2345 #define MSR_GOLDMONT_LASTBRANCH_16_TO_IP         0x000006D0
2346 #define MSR_GOLDMONT_LASTBRANCH_17_TO_IP         0x000006D1
2347 #define MSR_GOLDMONT_LASTBRANCH_18_TO_IP         0x000006D2
2348 #define MSR_GOLDMONT_LASTBRANCH_19_TO_IP         0x000006D3
2349 #define MSR_GOLDMONT_LASTBRANCH_20_TO_IP         0x000006D4
2350 #define MSR_GOLDMONT_LASTBRANCH_21_TO_IP         0x000006D5
2351 #define MSR_GOLDMONT_LASTBRANCH_22_TO_IP         0x000006D6
2352 #define MSR_GOLDMONT_LASTBRANCH_23_TO_IP         0x000006D7
2353 #define MSR_GOLDMONT_LASTBRANCH_24_TO_IP         0x000006D8
2354 #define MSR_GOLDMONT_LASTBRANCH_25_TO_IP         0x000006D9
2355 #define MSR_GOLDMONT_LASTBRANCH_26_TO_IP         0x000006DA
2356 #define MSR_GOLDMONT_LASTBRANCH_27_TO_IP         0x000006DB
2357 #define MSR_GOLDMONT_LASTBRANCH_28_TO_IP         0x000006DC
2358 #define MSR_GOLDMONT_LASTBRANCH_29_TO_IP         0x000006DD
2359 #define MSR_GOLDMONT_LASTBRANCH_30_TO_IP         0x000006DE
2360 #define MSR_GOLDMONT_LASTBRANCH_31_TO_IP         0x000006DF
2361 /// @}
2362 
2363 /**
2364   MSR information returned for MSR indexes #MSR_GOLDMONT_LASTBRANCH_0_TO_IP to
2365   #MSR_GOLDMONT_LASTBRANCH_31_TO_IP.
2366 **/
2367 typedef union {
2368   ///
2369   /// Individual bit fields
2370   ///
2371   struct {
2372     ///
2373     /// [Bit 31:0] Target Linear Address (R/W).
2374     ///
2375     UINT32  TargetLinearAddress:32;
2376     ///
2377     /// [Bit 47:32] Target Linear Address (R/W).
2378     ///
2379     UINT32  TargetLinearAddressHi:16;
2380     ///
2381     /// [Bits 63:48] Elapsed cycles from last update to the LBR.
2382     ///
2383     UINT32  ElapsedCycles:16;
2384   } Bits;
2385   ///
2386   /// All bit fields as a 32-bit value
2387   ///
2388   UINT32  Uint32;
2389   ///
2390   /// All bit fields as a 64-bit value
2391   ///
2392   UINT64  Uint64;
2393 } MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER;
2394 
2395 
2396 /**
2397   Core. Resource Association Register (R/W).
2398 
2399   @param  ECX  MSR_GOLDMONT_IA32_PQR_ASSOC (0x00000C8F)
2400   @param  EAX  Lower 32-bits of MSR value.
2401                Described by the type MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER.
2402   @param  EDX  Upper 32-bits of MSR value.
2403                Described by the type MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER.
2404 
2405   <b>Example usage</b>
2406   @code
2407   MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER  Msr;
2408 
2409   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PQR_ASSOC);
2410   AsmWriteMsr64 (MSR_GOLDMONT_IA32_PQR_ASSOC, Msr.Uint64);
2411   @endcode
2412   @note MSR_GOLDMONT_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
2413 **/
2414 #define MSR_GOLDMONT_IA32_PQR_ASSOC              0x00000C8F
2415 
2416 /**
2417   MSR information returned for MSR index #MSR_GOLDMONT_IA32_PQR_ASSOC
2418 **/
2419 typedef union {
2420   ///
2421   /// Individual bit fields
2422   ///
2423   struct {
2424     UINT32  Reserved1:32;
2425     ///
2426     /// [Bits 33:32] COS (R/W).
2427     ///
2428     UINT32  COS:2;
2429     UINT32  Reserved2:30;
2430   } Bits;
2431   ///
2432   /// All bit fields as a 64-bit value
2433   ///
2434   UINT64  Uint64;
2435 } MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER;
2436 
2437 
2438 /**
2439   Module. L2 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H,
2440   ECX=1):EDX.COS_MAX[15:0] >=n.
2441 
2442   @param  ECX  MSR_GOLDMONT_IA32_L2_QOS_MASK_n
2443   @param  EAX  Lower 32-bits of MSR value.
2444                Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER.
2445   @param  EDX  Upper 32-bits of MSR value.
2446                Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER.
2447 
2448   <b>Example usage</b>
2449   @code
2450   MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER  Msr;
2451 
2452   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_n);
2453   AsmWriteMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_n, Msr.Uint64);
2454   @endcode
2455   @note MSR_GOLDMONT_IA32_L2_QOS_MASK_0 is defined as IA32_L2_QOS_MASK_0 in SDM.
2456         MSR_GOLDMONT_IA32_L2_QOS_MASK_1 is defined as IA32_L2_QOS_MASK_1 in SDM.
2457         MSR_GOLDMONT_IA32_L2_QOS_MASK_2 is defined as IA32_L2_QOS_MASK_2 in SDM.
2458   @{
2459 **/
2460 #define MSR_GOLDMONT_IA32_L2_QOS_MASK_0          0x00000D10
2461 #define MSR_GOLDMONT_IA32_L2_QOS_MASK_1          0x00000D11
2462 #define MSR_GOLDMONT_IA32_L2_QOS_MASK_2          0x00000D12
2463 /// @}
2464 
2465 /**
2466   MSR information returned for MSR indexes #MSR_GOLDMONT_IA32_L2_QOS_MASK_0 to
2467   #MSR_GOLDMONT_IA32_L2_QOS_MASK_2.
2468 **/
2469 typedef union {
2470   ///
2471   /// Individual bit fields
2472   ///
2473   struct {
2474     ///
2475     /// [Bits 7:0] CBM: Bit vector of available L2 ways for COS 0 enforcement
2476     ///
2477     UINT32  CBM:8;
2478     UINT32  Reserved1:24;
2479     UINT32  Reserved2:32;
2480   } Bits;
2481   ///
2482   /// All bit fields as a 32-bit value
2483   ///
2484   UINT32  Uint32;
2485   ///
2486   /// All bit fields as a 64-bit value
2487   ///
2488   UINT64  Uint64;
2489 } MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER;
2490 
2491 
2492 /**
2493   Package. L2 Class Of Service Mask - COS 3 (R/W) if CPUID.(EAX=10H,
2494   ECX=1):EDX.COS_MAX[15:0] >=3.
2495 
2496   @param  ECX  MSR_GOLDMONT_IA32_L2_QOS_MASK_3
2497   @param  EAX  Lower 32-bits of MSR value.
2498                Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER.
2499   @param  EDX  Upper 32-bits of MSR value.
2500                Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER.
2501 
2502   <b>Example usage</b>
2503   @code
2504   MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER  Msr;
2505 
2506   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_3);
2507   AsmWriteMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_3, Msr.Uint64);
2508   @endcode
2509   @note MSR_GOLDMONT_IA32_L2_QOS_MASK_3 is defined as IA32_L2_QOS_MASK_3 in SDM.
2510 **/
2511 #define MSR_GOLDMONT_IA32_L2_QOS_MASK_3          0x00000D13
2512 
2513 /**
2514   MSR information returned for MSR index #MSR_GOLDMONT_IA32_L2_QOS_MASK_3.
2515 **/
2516 typedef union {
2517   ///
2518   /// Individual bit fields
2519   ///
2520   struct {
2521     ///
2522     /// [Bits 19:0] CBM: Bit vector of available L2 ways for COS 0 enforcement
2523     ///
2524     UINT32  CBM:20;
2525     UINT32  Reserved1:12;
2526     UINT32  Reserved2:32;
2527   } Bits;
2528   ///
2529   /// All bit fields as a 32-bit value
2530   ///
2531   UINT32  Uint32;
2532   ///
2533   /// All bit fields as a 64-bit value
2534   ///
2535   UINT64  Uint64;
2536 } MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER;
2537 
2538 
2539 #endif
2540