1 // Initialize PCI devices (on emulators)
2 //
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
5 //
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
7
8 #include "byteorder.h" // le64_to_cpu
9 #include "config.h" // CONFIG_*
10 #include "dev-q35.h" // Q35_HOST_BRIDGE_PCIEXBAR_ADDR
11 #include "dev-piix.h" // PIIX_*
12 #include "e820map.h" // e820_add
13 #include "hw/ata.h" // PORT_ATA1_CMD_BASE
14 #include "hw/pci.h" // pci_config_readl
15 #include "hw/pcidevice.h" // pci_probe_devices
16 #include "hw/pci_ids.h" // PCI_VENDOR_ID_INTEL
17 #include "hw/pci_regs.h" // PCI_COMMAND
18 #include "fw/dev-pci.h" // REDHAT_CAP_RESOURCE_RESERVE
19 #include "list.h" // struct hlist_node
20 #include "malloc.h" // free
21 #include "output.h" // dprintf
22 #include "paravirt.h" // RamSize
23 #include "romfile.h" // romfile_loadint
24 #include "string.h" // memset
25 #include "util.h" // pci_setup
26 #include "x86.h" // outb
27
28 #define PCI_DEVICE_MEM_MIN (1<<12) // 4k == page size
29 #define PCI_BRIDGE_MEM_MIN (1<<21) // 2M == hugepage size
30 #define PCI_BRIDGE_IO_MIN 0x1000 // mandated by pci bridge spec
31
32 #define PCI_ROM_SLOT 6
33 #define PCI_NUM_REGIONS 7
34 #define PCI_BRIDGE_NUM_REGIONS 2
35
36 enum pci_region_type {
37 PCI_REGION_TYPE_IO,
38 PCI_REGION_TYPE_MEM,
39 PCI_REGION_TYPE_PREFMEM,
40 PCI_REGION_TYPE_COUNT,
41 };
42
43 static const char *region_type_name[] = {
44 [ PCI_REGION_TYPE_IO ] = "io",
45 [ PCI_REGION_TYPE_MEM ] = "mem",
46 [ PCI_REGION_TYPE_PREFMEM ] = "prefmem",
47 };
48
49 u64 pcimem_start = BUILD_PCIMEM_START;
50 u64 pcimem_end = BUILD_PCIMEM_END;
51 u64 pcimem64_start = BUILD_PCIMEM64_START;
52 u64 pcimem64_end = BUILD_PCIMEM64_END;
53 u64 pci_io_low_end = 0xa000;
54
55 struct pci_region_entry {
56 struct pci_device *dev;
57 int bar;
58 u64 size;
59 u64 align;
60 int is64;
61 enum pci_region_type type;
62 struct hlist_node node;
63 };
64
65 struct pci_region {
66 /* pci region assignments */
67 u64 base;
68 struct hlist_head list;
69 };
70
71 struct pci_bus {
72 struct pci_region r[PCI_REGION_TYPE_COUNT];
73 struct pci_device *bus_dev;
74 };
75
pci_bar(struct pci_device * pci,int region_num)76 static u32 pci_bar(struct pci_device *pci, int region_num)
77 {
78 if (region_num != PCI_ROM_SLOT) {
79 return PCI_BASE_ADDRESS_0 + region_num * 4;
80 }
81
82 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
83 u8 type = pci->header_type & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
84 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
85 }
86
87 static void
pci_set_io_region_addr(struct pci_device * pci,int bar,u64 addr,int is64)88 pci_set_io_region_addr(struct pci_device *pci, int bar, u64 addr, int is64)
89 {
90 u32 ofs = pci_bar(pci, bar);
91 pci_config_writel(pci->bdf, ofs, addr);
92 if (is64)
93 pci_config_writel(pci->bdf, ofs + 4, addr >> 32);
94 }
95
96
97 /****************************************************************
98 * Misc. device init
99 ****************************************************************/
100
101 /* host irqs corresponding to PCI irqs A-D */
102 const u8 pci_irqs[4] = {
103 10, 10, 11, 11
104 };
105
dummy_pci_slot_get_irq(struct pci_device * pci,int pin)106 static int dummy_pci_slot_get_irq(struct pci_device *pci, int pin)
107 {
108 dprintf(1, "pci_slot_get_irq called with unknown routing\n");
109
110 return 0xff; /* PCI defined "unknown" or "no connection" for x86 */
111 }
112
113 static int (*pci_slot_get_irq)(struct pci_device *pci, int pin) =
114 dummy_pci_slot_get_irq;
115
116 // Return the global irq number corresponding to a host bus device irq pin.
piix_pci_slot_get_irq(struct pci_device * pci,int pin)117 static int piix_pci_slot_get_irq(struct pci_device *pci, int pin)
118 {
119 int slot_addend = 0;
120
121 while (pci->parent != NULL) {
122 slot_addend += pci_bdf_to_dev(pci->bdf);
123 pci = pci->parent;
124 }
125 slot_addend += pci_bdf_to_dev(pci->bdf) - 1;
126 return pci_irqs[(pin - 1 + slot_addend) & 3];
127 }
128
mch_pci_slot_get_irq(struct pci_device * pci,int pin)129 static int mch_pci_slot_get_irq(struct pci_device *pci, int pin)
130 {
131 int pin_addend = 0;
132 while (pci->parent != NULL) {
133 pin_addend += pci_bdf_to_dev(pci->bdf);
134 pci = pci->parent;
135 }
136 u8 slot = pci_bdf_to_dev(pci->bdf);
137 if (slot <= 24)
138 /* Slots 0-24 rotate slot:pin mapping similar to piix above, but
139 with a different starting index - see q35-acpi-dsdt.dsl */
140 return pci_irqs[(pin - 1 + pin_addend + slot) & 3];
141 /* Slots 25-31 all use LNKA mapping (or LNKE, but A:D = E:H) */
142 return pci_irqs[(pin - 1 + pin_addend) & 3];
143 }
144
145 /* PIIX3/PIIX4 PCI to ISA bridge */
piix_isa_bridge_setup(struct pci_device * pci,void * arg)146 static void piix_isa_bridge_setup(struct pci_device *pci, void *arg)
147 {
148 int i, irq;
149 u8 elcr[2];
150
151 elcr[0] = 0x00;
152 elcr[1] = 0x00;
153 for (i = 0; i < 4; i++) {
154 irq = pci_irqs[i];
155 /* set to trigger level */
156 elcr[irq >> 3] |= (1 << (irq & 7));
157 /* activate irq remapping in PIIX */
158 pci_config_writeb(pci->bdf, 0x60 + i, irq);
159 }
160 outb(elcr[0], PIIX_PORT_ELCR1);
161 outb(elcr[1], PIIX_PORT_ELCR2);
162 dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]);
163 }
164
mch_isa_lpc_setup(u16 bdf)165 static void mch_isa_lpc_setup(u16 bdf)
166 {
167 /* pm io base */
168 pci_config_writel(bdf, ICH9_LPC_PMBASE,
169 acpi_pm_base | ICH9_LPC_PMBASE_RTE);
170
171 /* acpi enable, SCI: IRQ9 000b = irq9*/
172 pci_config_writeb(bdf, ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_ACPI_EN);
173
174 /* set root complex register block BAR */
175 pci_config_writel(bdf, ICH9_LPC_RCBA,
176 ICH9_LPC_RCBA_ADDR | ICH9_LPC_RCBA_EN);
177 }
178
179 static int ICH9LpcBDF = -1;
180
181 /* ICH9 LPC PCI to ISA bridge */
182 /* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_LPC */
mch_isa_bridge_setup(struct pci_device * dev,void * arg)183 static void mch_isa_bridge_setup(struct pci_device *dev, void *arg)
184 {
185 u16 bdf = dev->bdf;
186 int i, irq;
187 u8 elcr[2];
188
189 elcr[0] = 0x00;
190 elcr[1] = 0x00;
191
192 for (i = 0; i < 4; i++) {
193 irq = pci_irqs[i];
194 /* set to trigger level */
195 elcr[irq >> 3] |= (1 << (irq & 7));
196
197 /* activate irq remapping in LPC */
198
199 /* PIRQ[A-D] routing */
200 pci_config_writeb(bdf, ICH9_LPC_PIRQA_ROUT + i, irq);
201 /* PIRQ[E-H] routing */
202 pci_config_writeb(bdf, ICH9_LPC_PIRQE_ROUT + i, irq);
203 }
204 outb(elcr[0], ICH9_LPC_PORT_ELCR1);
205 outb(elcr[1], ICH9_LPC_PORT_ELCR2);
206 dprintf(1, "Q35 LPC init: elcr=%02x %02x\n", elcr[0], elcr[1]);
207
208 ICH9LpcBDF = bdf;
209
210 mch_isa_lpc_setup(bdf);
211
212 e820_add(ICH9_LPC_RCBA_ADDR, 16*1024, E820_RESERVED);
213
214 acpi_pm1a_cnt = acpi_pm_base + 0x04;
215 pmtimer_setup(acpi_pm_base + 0x08);
216 }
217
storage_ide_setup(struct pci_device * pci,void * arg)218 static void storage_ide_setup(struct pci_device *pci, void *arg)
219 {
220 /* On parisc, keep PCI IDE IO ports in PCI mem space */
221 if (CONFIG_PARISC)
222 return;
223
224 /* IDE: we map it as in ISA mode */
225 pci_set_io_region_addr(pci, 0, PORT_ATA1_CMD_BASE, 0);
226 pci_set_io_region_addr(pci, 1, PORT_ATA1_CTRL_BASE, 0);
227 pci_set_io_region_addr(pci, 2, PORT_ATA2_CMD_BASE, 0);
228 pci_set_io_region_addr(pci, 3, PORT_ATA2_CTRL_BASE, 0);
229 }
230
231 /* PIIX3/PIIX4 IDE */
piix_ide_setup(struct pci_device * pci,void * arg)232 static void piix_ide_setup(struct pci_device *pci, void *arg)
233 {
234 u16 bdf = pci->bdf;
235 pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
236 pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
237 }
238
pic_ibm_setup(struct pci_device * pci,void * arg)239 static void pic_ibm_setup(struct pci_device *pci, void *arg)
240 {
241 /* PIC, IBM, MPIC & MPIC2 */
242 pci_set_io_region_addr(pci, 0, 0x80800000 + 0x00040000, 0);
243 }
244
apple_macio_setup(struct pci_device * pci,void * arg)245 static void apple_macio_setup(struct pci_device *pci, void *arg)
246 {
247 /* macio bridge */
248 pci_set_io_region_addr(pci, 0, 0x80800000, 0);
249 }
250
piix4_pm_config_setup(u16 bdf)251 static void piix4_pm_config_setup(u16 bdf)
252 {
253 // acpi sci is hardwired to 9
254 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
255
256 pci_config_writel(bdf, PIIX_PMBASE, acpi_pm_base | 1);
257 pci_config_writeb(bdf, PIIX_PMREGMISC, 0x01); /* enable PM io space */
258 pci_config_writel(bdf, PIIX_SMBHSTBASE, (acpi_pm_base + 0x100) | 1);
259 pci_config_writeb(bdf, PIIX_SMBHSTCFG, 0x09); /* enable SMBus io space */
260 }
261
262 static int PiixPmBDF = -1;
263
264 /* PIIX4 Power Management device (for ACPI) */
piix4_pm_setup(struct pci_device * pci,void * arg)265 static void piix4_pm_setup(struct pci_device *pci, void *arg)
266 {
267 PiixPmBDF = pci->bdf;
268 piix4_pm_config_setup(pci->bdf);
269
270 acpi_pm1a_cnt = acpi_pm_base + 0x04;
271 pmtimer_setup(acpi_pm_base + 0x08);
272 }
273
ich9_smbus_enable(u16 bdf)274 static void ich9_smbus_enable(u16 bdf)
275 {
276 /* map smbus into io space */
277 pci_config_writel(bdf, ICH9_SMB_SMB_BASE,
278 (acpi_pm_base + 0x100) | PCI_BASE_ADDRESS_SPACE_IO);
279
280 /* enable SMBus */
281 pci_config_writeb(bdf, ICH9_SMB_HOSTC, ICH9_SMB_HOSTC_HST_EN);
282 }
283
284 static int ICH9SmbusBDF = -1;
285
286 /* ICH9 SMBUS */
287 /* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_SMBUS */
ich9_smbus_setup(struct pci_device * dev,void * arg)288 static void ich9_smbus_setup(struct pci_device *dev, void *arg)
289 {
290 ICH9SmbusBDF = dev->bdf;
291
292 ich9_smbus_enable(dev->bdf);
293 }
294
intel_igd_setup(struct pci_device * dev,void * arg)295 static void intel_igd_setup(struct pci_device *dev, void *arg)
296 {
297 struct romfile_s *opregion = romfile_find("etc/igd-opregion");
298 u64 bdsm_size = le64_to_cpu(romfile_loadint("etc/igd-bdsm-size", 0));
299 void *addr;
300 u16 bdf = dev->bdf;
301
302 /* Apply OpRegion to any Intel VGA device, more than one is undefined */
303 if (opregion && opregion->size) {
304 addr = memalign_high(PAGE_SIZE, opregion->size);
305 if (!addr) {
306 warn_noalloc();
307 return;
308 }
309
310 if (opregion->copy(opregion, addr, opregion->size) < 0) {
311 free(addr);
312 return;
313 }
314
315 pci_config_writel(bdf, 0xFC, cpu_to_le32((u32)addr));
316
317 dprintf(1, "Intel IGD OpRegion enabled at 0x%08x, size %dKB, dev "
318 "%02x:%02x.%x\n", (u32)addr, opregion->size >> 10,
319 pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf));
320 }
321
322 /* Apply BDSM only to Intel VGA at 00:02.0 */
323 if (bdsm_size && (bdf == pci_to_bdf(0, 2, 0))) {
324 addr = memalign_tmphigh(1024 * 1024, bdsm_size);
325 if (!addr) {
326 warn_noalloc();
327 return;
328 }
329
330 e820_add((u32)addr, bdsm_size, E820_RESERVED);
331
332 pci_config_writel(bdf, 0x5C, cpu_to_le32((u32)addr));
333
334 dprintf(1, "Intel IGD BDSM enabled at 0x%08x, size %lldMB, dev "
335 "00:02.0\n", (u32)addr, bdsm_size >> 20);
336 }
337 }
338
339 static const struct pci_device_id pci_device_tbl[] = {
340 /* PIIX3/PIIX4 PCI to ISA bridge */
341 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0,
342 piix_isa_bridge_setup),
343 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
344 piix_isa_bridge_setup),
345 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_LPC,
346 mch_isa_bridge_setup),
347
348 /* STORAGE IDE */
349 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1,
350 PCI_CLASS_STORAGE_IDE, piix_ide_setup),
351 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
352 PCI_CLASS_STORAGE_IDE, piix_ide_setup),
353 PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
354 storage_ide_setup),
355
356 /* PIC, IBM, MPIC & MPIC2 */
357 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0x0046, PCI_CLASS_SYSTEM_PIC,
358 pic_ibm_setup),
359 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0xFFFF, PCI_CLASS_SYSTEM_PIC,
360 pic_ibm_setup),
361
362 /* PIIX4 Power Management device (for ACPI) */
363 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
364 piix4_pm_setup),
365 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_SMBUS,
366 ich9_smbus_setup),
367
368 /* 0xff00 */
369 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_setup),
370 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0022, 0xff00, apple_macio_setup),
371
372 /* Intel IGD OpRegion setup */
373 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
374 intel_igd_setup),
375
376 PCI_DEVICE_END,
377 };
378
379 static int MCHMmcfgBDF = -1;
380 static void mch_mmconfig_setup(u16 bdf);
381
pci_resume(void)382 void pci_resume(void)
383 {
384 if (!CONFIG_QEMU) {
385 return;
386 }
387
388 if (PiixPmBDF >= 0) {
389 piix4_pm_config_setup(PiixPmBDF);
390 }
391
392 if (ICH9LpcBDF >= 0) {
393 mch_isa_lpc_setup(ICH9LpcBDF);
394 }
395
396 if (ICH9SmbusBDF >= 0) {
397 ich9_smbus_enable(ICH9SmbusBDF);
398 }
399
400 if(MCHMmcfgBDF >= 0) {
401 mch_mmconfig_setup(MCHMmcfgBDF);
402 }
403 }
404
pci_bios_init_device(struct pci_device * pci)405 static void pci_bios_init_device(struct pci_device *pci)
406 {
407 dprintf(1, "PCI: init bdf=%pP id=%04x:%04x\n"
408 , pci, pci->vendor, pci->device);
409
410 /* map the interrupt */
411 u16 bdf = pci->bdf;
412 int pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
413 if (pin != 0)
414 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pci_slot_get_irq(pci, pin));
415
416 pci_init_device(pci_device_tbl, pci, NULL);
417
418 /* enable memory mappings */
419 pci_config_maskw(bdf, PCI_COMMAND, 0,
420 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_SERR);
421 /* enable SERR# for forwarding */
422 if (pci->header_type & PCI_HEADER_TYPE_BRIDGE)
423 pci_config_maskw(bdf, PCI_BRIDGE_CONTROL, 0,
424 PCI_BRIDGE_CTL_SERR);
425 }
426
pci_bios_init_devices(void)427 static void pci_bios_init_devices(void)
428 {
429 struct pci_device *pci;
430 foreachpci(pci) {
431 pci_bios_init_device(pci);
432 }
433 }
434
pci_enable_default_vga(void)435 static void pci_enable_default_vga(void)
436 {
437 struct pci_device *pci;
438
439 foreachpci(pci) {
440 if (is_pci_vga(pci)) {
441 dprintf(1, "PCI: Using %pP for primary VGA\n", pci);
442 return;
443 }
444 }
445
446 pci = pci_find_class(PCI_CLASS_DISPLAY_VGA);
447 if (!pci) {
448 dprintf(1, "PCI: No VGA devices found\n");
449 return;
450 }
451
452 dprintf(1, "PCI: Enabling %pP for primary VGA\n", pci);
453
454 pci_config_maskw(pci->bdf, PCI_COMMAND, 0,
455 PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
456
457 while (pci->parent) {
458 pci = pci->parent;
459
460 dprintf(1, "PCI: Setting VGA enable on bridge %pP\n", pci);
461
462 pci_config_maskw(pci->bdf, PCI_BRIDGE_CONTROL, 0, PCI_BRIDGE_CTL_VGA);
463 pci_config_maskw(pci->bdf, PCI_COMMAND, 0,
464 PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
465 }
466 }
467
468 /****************************************************************
469 * Platform device initialization
470 ****************************************************************/
471
i440fx_mem_addr_setup(struct pci_device * dev,void * arg)472 static void i440fx_mem_addr_setup(struct pci_device *dev, void *arg)
473 {
474 if (RamSize <= 0x80000000)
475 pcimem_start = 0x80000000;
476 else if (RamSize <= 0xc0000000)
477 pcimem_start = 0xc0000000;
478
479 pci_slot_get_irq = piix_pci_slot_get_irq;
480 }
481
mch_mmconfig_setup(u16 bdf)482 static void mch_mmconfig_setup(u16 bdf)
483 {
484 u64 addr = Q35_HOST_BRIDGE_PCIEXBAR_ADDR;
485 u32 upper = addr >> 32;
486 u32 lower = (addr & 0xffffffff) | Q35_HOST_BRIDGE_PCIEXBAREN;
487 pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, 0);
488 pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR + 4, upper);
489 pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, lower);
490 }
491
mch_mem_addr_setup(struct pci_device * dev,void * arg)492 static void mch_mem_addr_setup(struct pci_device *dev, void *arg)
493 {
494 u64 addr = Q35_HOST_BRIDGE_PCIEXBAR_ADDR;
495 u32 size = Q35_HOST_BRIDGE_PCIEXBAR_SIZE;
496
497 /* setup mmconfig */
498 MCHMmcfgBDF = dev->bdf;
499 mch_mmconfig_setup(dev->bdf);
500 e820_add(addr, size, E820_RESERVED);
501
502 /* setup pci i/o window (above mmconfig) */
503 pcimem_start = addr + size;
504
505 pci_slot_get_irq = mch_pci_slot_get_irq;
506
507 /* setup io address space */
508 if (acpi_pm_base < 0x1000)
509 pci_io_low_end = 0x10000;
510 else
511 pci_io_low_end = acpi_pm_base;
512 }
513
514 #if CONFIG_PARISC
dino_pci_slot_get_irq(struct pci_device * pci,int pin)515 static int dino_pci_slot_get_irq(struct pci_device *pci, int pin)
516 {
517 int slot = pci_bdf_to_dev(pci->bdf);
518 return slot & 0x03;
519 }
520
dino_mem_addr_setup(struct pci_device * dev,void * arg)521 static void dino_mem_addr_setup(struct pci_device *dev, void *arg)
522 {
523 pcimem_start = 0xf2000000ULL;
524 pcimem_end = 0xff800000ULL;
525
526 /* Setup DINO PCI I/O and mem window */
527
528 outl(DINO_HPA | 1, 0xfffc0020); /* Set Dino Flex (Address) */
529 outl(0x00000080, DINO_HPA + 0x038); /* IO_CONTROL - enable DINO PCI */
530 // outl(0x00000000, DINO_HPA + 0x804); /* Set PAMR */
531 // outl(0x00000000, DINO_HPA + 0x808); /* Set PAPR */
532 outl(0x7ffffffe, DINO_HPA + 0x060); /* Set DINO_IO_ADDR_EN */
533 // outl(0x00000001, DINO_HPA + 0x05c); /* Set IO_FBB_EN */
534 // outl(0x0000006f, DINO_HPA + 0x810); /* Set PCICMD */
535 #if 0
536 m01 ghost_em write1 0xfffc0020 0xff000001 /* Set Flex */
537 m02 ghost_em write1 0xff000038 0x00000080 /* Set IO_CONTROL */
538 m03 ghost_em write1 0xff000804 0x00000000 /* Set PAMR */
539 m04 ghost_em write1 0xff000808 0x00000000 /* Set PAPR */
540 m05 ghost_em write1 0xff00005c 0x00000001 /* Set IO_FBB_EN */
541 m06 ghost_em write1 0xff000060 0x0000fffe /* Set IO_ADDR_EN */
542 m07 ghost_em write1 0xff00080c 0x00000000 /* Set DAMODE */
543 m08 ghost_em write1 0xff000824 0x00000000 /* Set PCIROR read hint=1 */
544 m09 ghost_em write1 0xff000828 0x00000000 /* Set PCIWOR write hint=1 */
545 m10 ghost_em write1 0xff000810 0x0000006f /* Set PCICMD reset PCI */
546 #endif
547
548 pci_slot_get_irq = dino_pci_slot_get_irq;
549
550 /* setup io address space */
551 pci_io_low_end = 0xa000;
552 }
553 #endif /* CONFIG_PARISC */
554
555
556 static const struct pci_device_id pci_platform_tbl[] = {
557 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441,
558 i440fx_mem_addr_setup),
559 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q35_MCH,
560 mch_mem_addr_setup),
561 PCI_DEVICE_END
562 };
563
pci_bios_init_platform(void)564 static void pci_bios_init_platform(void)
565 {
566 struct pci_device *pci;
567
568 if (CONFIG_X86) {
569 foreachpci(pci) {
570 pci_init_device(pci_platform_tbl, pci, NULL);
571 }
572 }
573
574 #if CONFIG_PARISC
575 dino_mem_addr_setup(NULL, NULL);
576 #endif
577 }
578
pci_find_resource_reserve_capability(u16 bdf)579 static u8 pci_find_resource_reserve_capability(u16 bdf)
580 {
581 u16 device_id;
582
583 if (pci_config_readw(bdf, PCI_VENDOR_ID) != PCI_VENDOR_ID_REDHAT) {
584 dprintf(3, "PCI: This is non-QEMU bridge.\n");
585 return 0;
586 }
587
588 device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
589
590 if (device_id != PCI_DEVICE_ID_REDHAT_ROOT_PORT &&
591 device_id != PCI_DEVICE_ID_REDHAT_BRIDGE) {
592 dprintf(1, "PCI: QEMU resource reserve cap device ID doesn't match.\n");
593 return 0;
594 }
595 u8 cap = 0;
596
597 do {
598 cap = pci_find_capability(bdf, PCI_CAP_ID_VNDR, cap);
599 } while (cap &&
600 pci_config_readb(bdf, cap + PCI_CAP_REDHAT_TYPE_OFFSET) !=
601 REDHAT_CAP_RESOURCE_RESERVE);
602 if (cap) {
603 u8 cap_len = pci_config_readb(bdf, cap + PCI_CAP_FLAGS);
604 if (cap_len < RES_RESERVE_CAP_SIZE) {
605 dprintf(1, "PCI: QEMU resource reserve cap length %d is invalid\n",
606 cap_len);
607 return 0;
608 }
609 } else {
610 dprintf(1, "PCI: QEMU resource reserve cap not found\n");
611 }
612 return cap;
613 }
614
615 /****************************************************************
616 * Bus initialization
617 ****************************************************************/
618
619 static void
pci_bios_init_bus_rec(int bus,u8 * pci_bus)620 pci_bios_init_bus_rec(int bus, u8 *pci_bus)
621 {
622 int bdf;
623 u16 class;
624
625 dprintf(1, "PCI: %s bus = 0x%x\n", __func__, bus);
626
627 /* prevent accidental access to unintended devices */
628 foreachbdf(bdf, bus) {
629 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
630 if (class == PCI_CLASS_BRIDGE_PCI) {
631 pci_config_writeb(bdf, PCI_SECONDARY_BUS, 255);
632 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 0);
633 }
634 }
635
636 foreachbdf(bdf, bus) {
637 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
638 if (class != PCI_CLASS_BRIDGE_PCI) {
639 continue;
640 }
641 dprintf(1, "PCI: %s bdf = 0x%x\n", __func__, bdf);
642
643 u8 pribus = pci_config_readb(bdf, PCI_PRIMARY_BUS);
644 if (pribus != bus) {
645 dprintf(1, "PCI: primary bus = 0x%x -> 0x%x\n", pribus, bus);
646 pci_config_writeb(bdf, PCI_PRIMARY_BUS, bus);
647 } else {
648 dprintf(1, "PCI: primary bus = 0x%x\n", pribus);
649 }
650
651 u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
652 (*pci_bus)++;
653 if (*pci_bus != secbus) {
654 dprintf(1, "PCI: secondary bus = 0x%x -> 0x%x\n",
655 secbus, *pci_bus);
656 secbus = *pci_bus;
657 pci_config_writeb(bdf, PCI_SECONDARY_BUS, secbus);
658 } else {
659 dprintf(1, "PCI: secondary bus = 0x%x\n", secbus);
660 }
661
662 /* set to max for access to all subordinate buses.
663 later set it to accurate value */
664 u8 subbus = pci_config_readb(bdf, PCI_SUBORDINATE_BUS);
665 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 255);
666
667 pci_bios_init_bus_rec(secbus, pci_bus);
668
669 if (subbus != *pci_bus) {
670 u8 res_bus = *pci_bus;
671 u8 cap = pci_find_resource_reserve_capability(bdf);
672
673 if (cap) {
674 u32 tmp_res_bus = pci_config_readl(bdf,
675 cap + RES_RESERVE_BUS_RES);
676 if (tmp_res_bus != (u32)-1) {
677 res_bus = tmp_res_bus & 0xFF;
678 if ((u8)(res_bus + secbus) < secbus ||
679 (u8)(res_bus + secbus) < res_bus) {
680 dprintf(1, "PCI: bus_reserve value %d is invalid\n",
681 res_bus);
682 res_bus = 0;
683 }
684 if (secbus + res_bus > *pci_bus) {
685 dprintf(1, "PCI: QEMU resource reserve cap: bus = %u\n",
686 res_bus);
687 res_bus = secbus + res_bus;
688 }
689 }
690 }
691 dprintf(1, "PCI: subordinate bus = 0x%x -> 0x%x\n",
692 subbus, res_bus);
693 subbus = res_bus;
694 *pci_bus = res_bus;
695 } else {
696 dprintf(1, "PCI: subordinate bus = 0x%x\n", subbus);
697 }
698 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, subbus);
699 }
700 }
701
702 static void
pci_bios_init_bus(void)703 pci_bios_init_bus(void)
704 {
705 u8 extraroots = romfile_loadint("etc/extra-pci-roots", 0);
706 u8 pci_bus = 0;
707
708 pci_bios_init_bus_rec(0 /* host bus */, &pci_bus);
709
710 if (extraroots) {
711 while (pci_bus < 0xff) {
712 pci_bus++;
713 pci_bios_init_bus_rec(pci_bus, &pci_bus);
714 }
715 }
716 }
717
718
719 /****************************************************************
720 * Bus sizing
721 ****************************************************************/
722
723 static void
pci_bios_get_bar(struct pci_device * pci,int bar,int * ptype,u64 * psize,int * pis64)724 pci_bios_get_bar(struct pci_device *pci, int bar,
725 int *ptype, u64 *psize, int *pis64)
726 {
727 u32 ofs = pci_bar(pci, bar);
728 u16 bdf = pci->bdf;
729 u32 old = pci_config_readl(bdf, ofs);
730 int is64 = 0, type = PCI_REGION_TYPE_MEM;
731 u64 mask;
732
733 if (bar == PCI_ROM_SLOT) {
734 mask = PCI_ROM_ADDRESS_MASK;
735 pci_config_writel(bdf, ofs, mask);
736 } else {
737 if (old & PCI_BASE_ADDRESS_SPACE_IO) {
738 mask = PCI_BASE_ADDRESS_IO_MASK;
739 type = PCI_REGION_TYPE_IO;
740 } else {
741 mask = PCI_BASE_ADDRESS_MEM_MASK;
742 if (old & PCI_BASE_ADDRESS_MEM_PREFETCH)
743 type = PCI_REGION_TYPE_PREFMEM;
744 is64 = ((old & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
745 == PCI_BASE_ADDRESS_MEM_TYPE_64);
746 }
747 pci_config_writel(bdf, ofs, ~0);
748 }
749 u64 val = pci_config_readl(bdf, ofs);
750 pci_config_writel(bdf, ofs, old);
751 if (is64) {
752 u32 hold = pci_config_readl(bdf, ofs + 4);
753 pci_config_writel(bdf, ofs + 4, ~0);
754 u32 high = pci_config_readl(bdf, ofs + 4);
755 pci_config_writel(bdf, ofs + 4, hold);
756 val |= ((u64)high << 32);
757 mask |= ((u64)0xffffffff << 32);
758 *psize = (~(val & mask)) + 1;
759 } else {
760 *psize = ((~(val & mask)) + 1) & 0xffffffff;
761 }
762 *ptype = type;
763 *pis64 = is64;
764 }
765
pci_bios_bridge_region_is64(struct pci_region * r,struct pci_device * pci,int type)766 static int pci_bios_bridge_region_is64(struct pci_region *r,
767 struct pci_device *pci, int type)
768 {
769 if (type != PCI_REGION_TYPE_PREFMEM)
770 return 0;
771 u32 pmem = pci_config_readl(pci->bdf, PCI_PREF_MEMORY_BASE);
772 if (!pmem) {
773 pci_config_writel(pci->bdf, PCI_PREF_MEMORY_BASE, 0xfff0fff0);
774 pmem = pci_config_readl(pci->bdf, PCI_PREF_MEMORY_BASE);
775 pci_config_writel(pci->bdf, PCI_PREF_MEMORY_BASE, 0x0);
776 }
777 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) != PCI_PREF_RANGE_TYPE_64)
778 return 0;
779 struct pci_region_entry *entry;
780 hlist_for_each_entry(entry, &r->list, node) {
781 if (!entry->is64)
782 return 0;
783 }
784 return 1;
785 }
786
pci_region_align(struct pci_region * r)787 static u64 pci_region_align(struct pci_region *r)
788 {
789 struct pci_region_entry *entry;
790 hlist_for_each_entry(entry, &r->list, node) {
791 // The first entry in the sorted list has the largest alignment
792 return entry->align;
793 }
794 return 1;
795 }
796
pci_region_sum(struct pci_region * r)797 static u64 pci_region_sum(struct pci_region *r)
798 {
799 u64 sum = 0;
800 struct pci_region_entry *entry;
801 hlist_for_each_entry(entry, &r->list, node) {
802 sum += entry->size;
803 }
804 return sum;
805 }
806
pci_region_migrate_64bit_entries(struct pci_region * from,struct pci_region * to)807 static void pci_region_migrate_64bit_entries(struct pci_region *from,
808 struct pci_region *to)
809 {
810 struct hlist_node *n, **last = &to->list.first;
811 struct pci_region_entry *entry;
812 hlist_for_each_entry_safe(entry, n, &from->list, node) {
813 if (!entry->is64)
814 continue;
815 if (entry->dev->class == PCI_CLASS_SERIAL_USB)
816 continue;
817 // Move from source list to destination list.
818 hlist_del(&entry->node);
819 hlist_add(&entry->node, last);
820 last = &entry->node.next;
821 }
822 }
823
824 static struct pci_region_entry *
pci_region_create_entry(struct pci_bus * bus,struct pci_device * dev,int bar,u64 size,u64 align,int type,int is64)825 pci_region_create_entry(struct pci_bus *bus, struct pci_device *dev,
826 int bar, u64 size, u64 align, int type, int is64)
827 {
828 struct pci_region_entry *entry = malloc_tmp(sizeof(*entry));
829 if (!entry) {
830 warn_noalloc();
831 return NULL;
832 }
833 memset(entry, 0, sizeof(*entry));
834 entry->dev = dev;
835 entry->bar = bar;
836 entry->size = size;
837 entry->align = align;
838 entry->is64 = is64;
839 entry->type = type;
840 // Insert into list in sorted order.
841 struct hlist_node **pprev;
842 struct pci_region_entry *pos;
843 hlist_for_each_entry_pprev(pos, pprev, &bus->r[type].list, node) {
844 if (pos->align < align || (pos->align == align && pos->size < size))
845 break;
846 }
847 hlist_add(&entry->node, pprev);
848 return entry;
849 }
850
pci_bus_hotplug_support(struct pci_bus * bus,u8 pcie_cap)851 static int pci_bus_hotplug_support(struct pci_bus *bus, u8 pcie_cap)
852 {
853 u8 shpc_cap;
854
855 if (pcie_cap) {
856 u16 pcie_flags = pci_config_readw(bus->bus_dev->bdf,
857 pcie_cap + PCI_EXP_FLAGS);
858 u8 port_type = ((pcie_flags & PCI_EXP_FLAGS_TYPE) >>
859 (__builtin_ffs(PCI_EXP_FLAGS_TYPE) - 1));
860 u8 downstream_port = (port_type == PCI_EXP_TYPE_DOWNSTREAM) ||
861 (port_type == PCI_EXP_TYPE_ROOT_PORT);
862 /*
863 * PCI Express SPEC, 7.8.2:
864 * Slot Implemented – When Set, this bit indicates that the Link
865 * HwInit associated with this Port is connected to a slot (as
866 * compared to being connected to a system-integrated device or
867 * being disabled).
868 * This bit is valid for Downstream Ports. This bit is undefined
869 * for Upstream Ports.
870 */
871 u16 slot_implemented = pcie_flags & PCI_EXP_FLAGS_SLOT;
872
873 return downstream_port && slot_implemented;
874 }
875
876 shpc_cap = pci_find_capability(bus->bus_dev->bdf, PCI_CAP_ID_SHPC, 0);
877 return !!shpc_cap;
878 }
879
880 /* Test whether bridge support forwarding of transactions
881 * of a specific type.
882 * Note: disables bridge's window registers as a side effect.
883 */
pci_bridge_has_region(struct pci_device * pci,enum pci_region_type region_type)884 static int pci_bridge_has_region(struct pci_device *pci,
885 enum pci_region_type region_type)
886 {
887 u8 base;
888
889 switch (region_type) {
890 case PCI_REGION_TYPE_IO:
891 base = PCI_IO_BASE;
892 break;
893 case PCI_REGION_TYPE_PREFMEM:
894 base = PCI_PREF_MEMORY_BASE;
895 break;
896 default:
897 /* Regular memory support is mandatory */
898 return 1;
899 }
900
901 pci_config_writeb(pci->bdf, base, 0xFF);
902
903 return pci_config_readb(pci->bdf, base) != 0;
904 }
905
pci_bios_check_devices(struct pci_bus * busses)906 static int pci_bios_check_devices(struct pci_bus *busses)
907 {
908 dprintf(1, "PCI: check devices\n");
909
910 // Calculate resources needed for regular (non-bus) devices.
911 struct pci_device *pci;
912 foreachpci(pci) {
913 if (pci->class == PCI_CLASS_BRIDGE_PCI)
914 busses[pci->secondary_bus].bus_dev = pci;
915
916 struct pci_bus *bus = &busses[pci_bdf_to_bus(pci->bdf)];
917 if (!bus->bus_dev)
918 /*
919 * Resources for all root busses go in busses[0]
920 */
921 bus = &busses[0];
922 int i;
923 for (i = 0; i < PCI_NUM_REGIONS; i++) {
924 if ((pci->class == PCI_CLASS_BRIDGE_PCI) &&
925 (i >= PCI_BRIDGE_NUM_REGIONS && i < PCI_ROM_SLOT))
926 continue;
927 int type, is64;
928 u64 size;
929 pci_bios_get_bar(pci, i, &type, &size, &is64);
930 if (size == 0)
931 continue;
932
933 if (type != PCI_REGION_TYPE_IO && size < PCI_DEVICE_MEM_MIN)
934 size = PCI_DEVICE_MEM_MIN;
935 struct pci_region_entry *entry = pci_region_create_entry(
936 bus, pci, i, size, size, type, is64);
937 if (!entry)
938 return -1;
939
940 if (is64)
941 i++;
942 }
943 }
944
945 // Propagate required bus resources to parent busses.
946 int secondary_bus;
947 for (secondary_bus=MaxPCIBus; secondary_bus>0; secondary_bus--) {
948 struct pci_bus *s = &busses[secondary_bus];
949 if (!s->bus_dev)
950 continue;
951 struct pci_bus *parent = &busses[pci_bdf_to_bus(s->bus_dev->bdf)];
952 if (!parent->bus_dev)
953 /*
954 * Resources for all root busses go in busses[0]
955 */
956 parent = &busses[0];
957 int type;
958 u16 bdf = s->bus_dev->bdf;
959 u8 pcie_cap = pci_find_capability(bdf, PCI_CAP_ID_EXP, 0);
960 u8 qemu_cap = pci_find_resource_reserve_capability(bdf);
961
962 int hotplug_support = pci_bus_hotplug_support(s, pcie_cap);
963 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
964 u64 align = (type == PCI_REGION_TYPE_IO) ?
965 PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN;
966 if (!pci_bridge_has_region(s->bus_dev, type))
967 continue;
968 u64 size = 0;
969 if (qemu_cap) {
970 u32 tmp_size;
971 u64 tmp_size_64;
972 switch(type) {
973 case PCI_REGION_TYPE_IO:
974 tmp_size_64 = (pci_config_readl(bdf, qemu_cap + RES_RESERVE_IO) |
975 (u64)pci_config_readl(bdf, qemu_cap + RES_RESERVE_IO + 4) << 32);
976 if (tmp_size_64 != (u64)-1) {
977 size = tmp_size_64;
978 }
979 break;
980 case PCI_REGION_TYPE_MEM:
981 tmp_size = pci_config_readl(bdf, qemu_cap + RES_RESERVE_MEM);
982 if (tmp_size != (u32)-1) {
983 size = tmp_size;
984 }
985 break;
986 case PCI_REGION_TYPE_PREFMEM:
987 tmp_size = pci_config_readl(bdf, qemu_cap + RES_RESERVE_PREF_MEM_32);
988 tmp_size_64 = (pci_config_readl(bdf, qemu_cap + RES_RESERVE_PREF_MEM_64) |
989 (u64)pci_config_readl(bdf, qemu_cap + RES_RESERVE_PREF_MEM_64 + 4) << 32);
990 if (tmp_size != (u32)-1 && tmp_size_64 == (u64)-1) {
991 size = tmp_size;
992 } else if (tmp_size == (u32)-1 && tmp_size_64 != (u64)-1) {
993 size = tmp_size_64;
994 } else if (tmp_size != (u32)-1 && tmp_size_64 != (u64)-1) {
995 dprintf(1, "PCI: resource reserve cap PREF32 and PREF64"
996 " conflict\n");
997 }
998 break;
999 default:
1000 break;
1001 }
1002 }
1003 if (pci_region_align(&s->r[type]) > align)
1004 align = pci_region_align(&s->r[type]);
1005 u64 sum = pci_region_sum(&s->r[type]);
1006 int resource_optional = pcie_cap && (type == PCI_REGION_TYPE_IO);
1007 if (!sum && hotplug_support && !resource_optional)
1008 sum = align; /* reserve min size for hot-plug */
1009 if (size > sum) {
1010 dprintf(1, "PCI: QEMU resource reserve cap: "
1011 "size %08llx type %s\n",
1012 size, region_type_name[type]);
1013 if (type != PCI_REGION_TYPE_IO) {
1014 size = ALIGN(size, align);
1015 }
1016 } else {
1017 size = ALIGN(sum, align);
1018 }
1019 int is64 = pci_bios_bridge_region_is64(&s->r[type],
1020 s->bus_dev, type);
1021 // entry->bar is -1 if the entry represents a bridge region
1022 struct pci_region_entry *entry = pci_region_create_entry(
1023 parent, s->bus_dev, -1, size, align, type, is64);
1024 if (!entry)
1025 return -1;
1026 dprintf(1, "PCI: secondary bus %d size %08llx type %s\n",
1027 entry->dev->secondary_bus, size,
1028 region_type_name[entry->type]);
1029 }
1030 }
1031 return 0;
1032 }
1033
1034
1035 /****************************************************************
1036 * BAR assignment
1037 ****************************************************************/
1038
1039 // Setup region bases (given the regions' size and alignment)
pci_bios_init_root_regions_io(struct pci_bus * bus)1040 static int pci_bios_init_root_regions_io(struct pci_bus *bus)
1041 {
1042 /*
1043 * QEMU I/O address space usage:
1044 * 0000 - 0fff legacy isa, pci config, pci root bus, ...
1045 * 1000 - 9fff free
1046 * a000 - afff hotplug (cpu, pci via acpi, i440fx/piix only)
1047 * b000 - bfff power management (PORT_ACPI_PM_BASE)
1048 * [ qemu 1.4+ implements pci config registers
1049 * properly so guests can place the registers
1050 * where they want, on older versions its fixed ]
1051 * c000 - ffff free, traditionally used for pci io
1052 */
1053 struct pci_region *r_io = &bus->r[PCI_REGION_TYPE_IO];
1054 u64 sum = pci_region_sum(r_io);
1055 if (sum < 0x4000 && !CONFIG_PARISC) {
1056 /* traditional region is big enough, use it */
1057 r_io->base = 0xc000;
1058 } else if (sum < pci_io_low_end - 0x1000) {
1059 /* use the larger region at 0x1000 */
1060 r_io->base = 0x1000;
1061 } else {
1062 /* not enouth io address space -> error out */
1063 return -1;
1064 }
1065 dprintf(1, "PCI: IO: %4llx - %4llx\n", r_io->base, r_io->base + sum - 1);
1066 return 0;
1067 }
1068
pci_bios_init_root_regions_mem(struct pci_bus * bus)1069 static int pci_bios_init_root_regions_mem(struct pci_bus *bus)
1070 {
1071 struct pci_region *r_end = &bus->r[PCI_REGION_TYPE_PREFMEM];
1072 struct pci_region *r_start = &bus->r[PCI_REGION_TYPE_MEM];
1073
1074 if (pci_region_align(r_start) < pci_region_align(r_end)) {
1075 // Swap regions to improve alignment.
1076 r_end = r_start;
1077 r_start = &bus->r[PCI_REGION_TYPE_PREFMEM];
1078 }
1079 u64 sum = pci_region_sum(r_end);
1080 u64 align = pci_region_align(r_end);
1081 r_end->base = ALIGN_DOWN((pcimem_end - sum), align);
1082 sum = pci_region_sum(r_start);
1083 align = pci_region_align(r_start);
1084 r_start->base = ALIGN_DOWN((r_end->base - sum), align);
1085
1086 if ((r_start->base < pcimem_start) ||
1087 (r_start->base > pcimem_end))
1088 // Memory range requested is larger than available.
1089 return -1;
1090 return 0;
1091 }
1092
1093 #define PCI_IO_SHIFT 8
1094 #define PCI_MEMORY_SHIFT 16
1095 #define PCI_PREF_MEMORY_SHIFT 16
1096
1097 static void
pci_region_map_one_entry(struct pci_region_entry * entry,u64 addr)1098 pci_region_map_one_entry(struct pci_region_entry *entry, u64 addr)
1099 {
1100 if (entry->bar >= 0) {
1101 dprintf(1, "PCI: map device bdf=%pP"
1102 " bar %d, addr %08llx, size %08llx [%d: %s]\n",
1103 entry->dev,
1104 entry->bar, addr, entry->size, entry->type, region_type_name[entry->type]);
1105
1106 pci_set_io_region_addr(entry->dev, entry->bar, addr, entry->is64);
1107 return;
1108 }
1109
1110 u16 bdf = entry->dev->bdf;
1111 u64 limit = addr + entry->size - 1;
1112 if (entry->type == PCI_REGION_TYPE_IO) {
1113 pci_config_writeb(bdf, PCI_IO_BASE, addr >> PCI_IO_SHIFT);
1114 pci_config_writew(bdf, PCI_IO_BASE_UPPER16, 0);
1115 pci_config_writeb(bdf, PCI_IO_LIMIT, limit >> PCI_IO_SHIFT);
1116 pci_config_writew(bdf, PCI_IO_LIMIT_UPPER16, 0);
1117 }
1118 if (entry->type == PCI_REGION_TYPE_MEM) {
1119 pci_config_writew(bdf, PCI_MEMORY_BASE, addr >> PCI_MEMORY_SHIFT);
1120 pci_config_writew(bdf, PCI_MEMORY_LIMIT, limit >> PCI_MEMORY_SHIFT);
1121 }
1122 if (entry->type == PCI_REGION_TYPE_PREFMEM) {
1123 pci_config_writew(bdf, PCI_PREF_MEMORY_BASE, addr >> PCI_PREF_MEMORY_SHIFT);
1124 pci_config_writew(bdf, PCI_PREF_MEMORY_LIMIT, limit >> PCI_PREF_MEMORY_SHIFT);
1125 pci_config_writel(bdf, PCI_PREF_BASE_UPPER32, addr >> 32);
1126 pci_config_writel(bdf, PCI_PREF_LIMIT_UPPER32, limit >> 32);
1127 }
1128 }
1129
pci_region_map_entries(struct pci_bus * busses,struct pci_region * r)1130 static void pci_region_map_entries(struct pci_bus *busses, struct pci_region *r)
1131 {
1132 struct hlist_node *n;
1133 struct pci_region_entry *entry;
1134 hlist_for_each_entry_safe(entry, n, &r->list, node) {
1135 u64 addr = r->base;
1136 r->base += entry->size;
1137 if (entry->bar == -1)
1138 // Update bus base address if entry is a bridge region
1139 busses[entry->dev->secondary_bus].r[entry->type].base = addr;
1140 pci_region_map_one_entry(entry, addr);
1141 hlist_del(&entry->node);
1142 free(entry);
1143 }
1144 }
1145
pci_bios_map_devices(struct pci_bus * busses)1146 static void pci_bios_map_devices(struct pci_bus *busses)
1147 {
1148 if (pci_bios_init_root_regions_io(busses))
1149 panic("PCI: out of I/O address space\n");
1150
1151 dprintf(1, "PCI: 32: %016llx - %016llx\n", pcimem_start, pcimem_end);
1152 if (pci_bios_init_root_regions_mem(busses)) {
1153 struct pci_region r64_mem, r64_pref;
1154 r64_mem.list.first = NULL;
1155 r64_pref.list.first = NULL;
1156 pci_region_migrate_64bit_entries(&busses[0].r[PCI_REGION_TYPE_MEM],
1157 &r64_mem);
1158 pci_region_migrate_64bit_entries(&busses[0].r[PCI_REGION_TYPE_PREFMEM],
1159 &r64_pref);
1160
1161 if (pci_bios_init_root_regions_mem(busses))
1162 panic("PCI: out of 32bit address space\n");
1163
1164 u64 sum_mem = pci_region_sum(&r64_mem);
1165 u64 sum_pref = pci_region_sum(&r64_pref);
1166 u64 align_mem = pci_region_align(&r64_mem);
1167 u64 align_pref = pci_region_align(&r64_pref);
1168
1169 r64_mem.base = le64_to_cpu(romfile_loadint("etc/reserved-memory-end", 0));
1170 if (r64_mem.base < 0x100000000LL + RamSizeOver4G)
1171 r64_mem.base = 0x100000000LL + RamSizeOver4G;
1172 r64_mem.base = ALIGN(r64_mem.base, align_mem);
1173 r64_mem.base = ALIGN(r64_mem.base, (1LL<<30)); // 1G hugepage
1174 r64_pref.base = r64_mem.base + sum_mem;
1175 r64_pref.base = ALIGN(r64_pref.base, align_pref);
1176 r64_pref.base = ALIGN(r64_pref.base, (1LL<<30)); // 1G hugepage
1177 pcimem64_start = r64_mem.base;
1178 pcimem64_end = r64_pref.base + sum_pref;
1179 pcimem64_end = ALIGN(pcimem64_end, (1LL<<30)); // 1G hugepage
1180 dprintf(1, "PCI: 64: %016llx - %016llx\n", pcimem64_start, pcimem64_end);
1181
1182 pci_region_map_entries(busses, &r64_mem);
1183 pci_region_map_entries(busses, &r64_pref);
1184 } else {
1185 // no bars mapped high -> drop 64bit window (see dsdt)
1186 pcimem64_start = 0;
1187 }
1188 // Map regions on each device.
1189 int bus;
1190 for (bus = 0; bus<=MaxPCIBus; bus++) {
1191 int type;
1192 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++)
1193 pci_region_map_entries(busses, &busses[bus].r[type]);
1194 }
1195 }
1196
1197
1198 /****************************************************************
1199 * Main setup code
1200 ****************************************************************/
1201
1202 void
pci_setup(void)1203 pci_setup(void)
1204 {
1205 if (!CONFIG_QEMU)
1206 return;
1207
1208 dprintf(3, "pci setup\n");
1209
1210 dprintf(1, "=== PCI bus & bridge init ===\n");
1211 if (pci_probe_host() != 0) {
1212 return;
1213 }
1214 pci_bios_init_bus();
1215
1216 dprintf(1, "=== PCI device probing ===\n");
1217 pci_probe_devices();
1218
1219 pcimem_start = RamSize;
1220 pci_bios_init_platform();
1221
1222 dprintf(1, "=== PCI new allocation pass #1 ===\n");
1223 struct pci_bus *busses = malloc_tmp(sizeof(*busses) * (MaxPCIBus + 1));
1224 if (!busses) {
1225 warn_noalloc();
1226 return;
1227 }
1228 memset(busses, 0, sizeof(*busses) * (MaxPCIBus + 1));
1229 if (pci_bios_check_devices(busses))
1230 return;
1231
1232 dprintf(1, "=== PCI new allocation pass #2 ===\n");
1233 pci_bios_map_devices(busses);
1234
1235 pci_bios_init_devices();
1236
1237 free(busses);
1238
1239 pci_enable_default_vga();
1240 }
1241