1 /* Copyright 2013-2018 IBM Corp.
2 *
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
12 * implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #include <inttypes.h>
18 #include <device.h>
19 #include "spira.h"
20 #include <cpu.h>
21 #include <vpd.h>
22 #include <interrupts.h>
23 #include <ccan/str/str.h>
24 #include <chip.h>
25 #include <fsp-mdst-table.h>
26 #include <fsp-attn.h>
27 #include <fsp-leds.h>
28
29 #include "hdata.h"
30 #include "hostservices.h"
31
32 /* Processor Initialization structure, contains
33 * the initial NIA and MSR values for the entry
34 * point
35 *
36 * Note: It appears to be ignoring the entry point
37 * and always going to 0x180
38 */
39
40 static int cpu_type;
41
42 __section(".procin.data") struct proc_init_data proc_init_data = {
43 .hdr = HDIF_SIMPLE_HDR("PROCIN", 1, struct proc_init_data),
44 .regs_ptr = HDIF_IDATA_PTR(offsetof(struct proc_init_data, regs), 0x10),
45 .regs = {
46 .nia = CPU_TO_BE64(0x180),
47 .msr = CPU_TO_BE64(0x9000000000000000ULL), /* SF | HV */
48 },
49 };
50
51 __section(".cpuctrl.data") struct sp_addr_table cpu_ctl_spat_area;
52 __section(".cpuctrl.data") struct sp_attn_area cpu_ctl_sp_attn_area1;
53 __section(".cpuctrl.data") struct sp_attn_area cpu_ctl_sp_attn_area2;
54 __section(".cpuctrl.data") struct hsr_data_area cpu_ctl_hsr_area;
55
56 __section(".cpuctrl.data") struct cpu_ctl_init_data cpu_ctl_init_data = {
57 .hdr = HDIF_SIMPLE_HDR(CPU_CTL_HDIF_SIG, 2, struct cpu_ctl_init_data),
58 .cpu_ctl = HDIF_IDATA_PTR(offsetof(struct cpu_ctl_init_data, cpu_ctl_lt), sizeof(struct cpu_ctl_legacy_table)),
59 #if !defined(TEST)
60 .cpu_ctl_lt = {
61 .spat = {
62 .addr = CPU_TO_BE64((unsigned long)&(cpu_ctl_spat_area) + SKIBOOT_BASE),
63 .size = CPU_TO_BE64(sizeof(struct sp_addr_table)),
64 },
65 .sp_attn_area1 = {
66 .addr = CPU_TO_BE64((unsigned long)&(cpu_ctl_sp_attn_area1) + SKIBOOT_BASE),
67 .size = CPU_TO_BE64(sizeof(struct sp_attn_area)),
68 },
69 .sp_attn_area2 = {
70 .addr = CPU_TO_BE64((unsigned long)&(cpu_ctl_sp_attn_area2) + SKIBOOT_BASE),
71 .size = CPU_TO_BE64(sizeof(struct sp_attn_area)),
72 },
73 .hsr_area = {
74 .addr = CPU_TO_BE64((unsigned long)&(cpu_ctl_hsr_area) + SKIBOOT_BASE),
75 .size = CPU_TO_BE64(sizeof(struct hsr_data_area)),
76 },
77 },
78 #endif
79 };
80
81 /* Populate MDST table
82 *
83 * Note that we only pass sapphire console buffer here so that we can
84 * capture early failure logs. Later dump component (fsp_dump_mdst_init)
85 * creates new table with all the memory sections we are interested and
86 * sends updated table to FSP via MBOX.
87 *
88 * To help the FSP distinguishing between TCE tokens and actual physical
89 * addresses, we set the top bit to 1 on physical addresses
90 */
91
92 __section(".mdst.data") struct dump_mdst_table init_mdst_table[2] = {
93 {
94 .addr = CPU_TO_BE64(INMEM_CON_START | HRMOR_BIT),
95 .type = CPU_TO_BE32(DUMP_REGION_CONSOLE),
96 .size = CPU_TO_BE32(INMEM_CON_LEN),
97 },
98 {
99 .addr = CPU_TO_BE64(HBRT_CON_START | HRMOR_BIT),
100 .type = CPU_TO_BE32(DUMP_REGION_HBRT_LOG),
101 .size = CPU_TO_BE32(HBRT_CON_LEN),
102 },
103 };
104
105 /* SP Interface Root Array, aka SPIRA */
106 __section(".spira.data") struct spira spira = {
107 .hdr = HDIF_SIMPLE_HDR("SPIRA ", SPIRA_VERSION, struct spira),
108 .ntuples_ptr = HDIF_IDATA_PTR(offsetof(struct spira, ntuples),
109 sizeof(struct spira_ntuples)),
110 .ntuples = {
111 .array_hdr = {
112 .offset = CPU_TO_BE32(HDIF_ARRAY_OFFSET),
113 .ecnt = CPU_TO_BE32(SPIRA_NTUPLES_COUNT),
114 .esize
115 = CPU_TO_BE32(sizeof(struct spira_ntuple)),
116 .eactsz = CPU_TO_BE32(0x18),
117 },
118 /* We only populate some n-tuples */
119 .proc_init = {
120 .addr = CPU_TO_BE64(PROCIN_OFF),
121 .alloc_cnt = CPU_TO_BE16(1),
122 .act_cnt = CPU_TO_BE16(1),
123 .alloc_len
124 = CPU_TO_BE32(sizeof(struct proc_init_data)),
125 },
126 .heap = {
127 .addr = CPU_TO_BE64(SPIRA_HEAP_BASE),
128 .alloc_cnt = CPU_TO_BE16(1),
129 .alloc_len = CPU_TO_BE32(SPIRA_HEAP_SIZE),
130 },
131 .mdump_src = {
132 .addr = CPU_TO_BE64(MDST_TABLE_OFF),
133 .alloc_cnt = CPU_TO_BE16(ARRAY_SIZE(init_mdst_table)),
134 .act_cnt = CPU_TO_BE16(ARRAY_SIZE(init_mdst_table)),
135 .alloc_len =
136 CPU_TO_BE32(sizeof(init_mdst_table)),
137 },
138 #if !defined(TEST)
139 .cpu_ctrl = {
140 .addr = CPU_TO_BE64((unsigned long)&cpu_ctl_init_data),
141 .alloc_cnt = CPU_TO_BE16(1),
142 .act_cnt = CPU_TO_BE16(1),
143 .alloc_len =
144 CPU_TO_BE32(sizeof(cpu_ctl_init_data)),
145 },
146 #endif
147 },
148 };
149
150 /* The Hypervisor SPIRA-H Structure */
151 __section(".spirah.data") struct spirah spirah = {
152 .hdr = HDIF_SIMPLE_HDR(SPIRAH_HDIF_SIG, SPIRAH_VERSION, struct spirah),
153 .ntuples_ptr = HDIF_IDATA_PTR(offsetof(struct spirah, ntuples),
154 sizeof(struct spirah_ntuples)),
155 .ntuples = {
156 .array_hdr = {
157 .offset = CPU_TO_BE32(HDIF_ARRAY_OFFSET),
158 .ecnt = CPU_TO_BE32(SPIRAH_NTUPLES_COUNT),
159 .esize
160 = CPU_TO_BE32(sizeof(struct spira_ntuple)),
161 .eactsz = CPU_TO_BE32(0x18),
162 },
163 /* Host Data Areas */
164 .hs_data_area = {
165 .addr = CPU_TO_BE64(SPIRA_HEAP_BASE),
166 .alloc_cnt = CPU_TO_BE16(1),
167 .alloc_len = CPU_TO_BE32(SPIRA_HEAP_SIZE),
168 },
169 /* We only populate some n-tuples */
170 .proc_init = {
171 .addr = CPU_TO_BE64(PROCIN_OFF),
172 .alloc_cnt = CPU_TO_BE16(1),
173 .act_cnt = CPU_TO_BE16(1),
174 .alloc_len
175 = CPU_TO_BE32(sizeof(struct proc_init_data)),
176 },
177 #if !defined(TEST)
178 .cpu_ctrl = {
179 .addr = CPU_TO_BE64((unsigned long)&cpu_ctl_init_data),
180 .alloc_cnt = CPU_TO_BE16(1),
181 .act_cnt = CPU_TO_BE16(1),
182 .alloc_len =
183 CPU_TO_BE32(sizeof(cpu_ctl_init_data)),
184 },
185 #endif
186 .mdump_src = {
187 .addr = CPU_TO_BE64(MDST_TABLE_OFF),
188 .alloc_cnt = CPU_TO_BE16(ARRAY_SIZE(init_mdst_table)),
189 .act_cnt = CPU_TO_BE16(ARRAY_SIZE(init_mdst_table)),
190 .alloc_len =
191 CPU_TO_BE32(sizeof(init_mdst_table)),
192 },
193 },
194 };
195
196 /* The service processor SPIRA-S structure */
197 struct spiras *spiras;
198
199 /* Overridden for testing. */
200 #ifndef spira_check_ptr
spira_check_ptr(const void * ptr,const char * file,unsigned int line)201 bool spira_check_ptr(const void *ptr, const char *file, unsigned int line)
202 {
203 if (!ptr)
204 return false;
205 if (((unsigned long)ptr) >= SPIRA_HEAP_BASE &&
206 ((unsigned long)ptr) < (SPIRA_HEAP_BASE + SPIRA_HEAP_SIZE))
207 return true;
208
209 prerror("SPIRA: Bad pointer %p at %s line %d\n", ptr, file, line);
210 return false;
211 }
212 #endif
213
__get_hdif(struct spira_ntuple * n,const char id[],const char * file,int line)214 struct HDIF_common_hdr *__get_hdif(struct spira_ntuple *n, const char id[],
215 const char *file, int line)
216 {
217 struct HDIF_common_hdr *h = ntuple_addr(n);
218 u16 act_cnt, alloc_cnt;
219 u32 act_len, alloc_len;
220
221 if (!spira_check_ptr(h, file, line))
222 return NULL;
223
224 act_cnt = be16_to_cpu(n->act_cnt);
225 alloc_cnt = be16_to_cpu(n->alloc_cnt);
226
227 if (act_cnt > alloc_cnt) {
228 prerror("SPIRA: bad ntuple, act_cnt > alloc_cnt (%u > %u)\n",
229 act_cnt, alloc_cnt);
230 return NULL;
231 }
232
233 act_len = be32_to_cpu(n->act_len);
234 alloc_len = be32_to_cpu(n->alloc_len);
235
236 if (act_len > alloc_len) {
237 prerror("SPIRA: bad ntuple, act_len > alloc_len (%u > %u)\n",
238 act_len, alloc_len);
239 return NULL;
240 }
241
242 if (!HDIF_check(h, id)) {
243 prerror("SPIRA: bad tuple %p: expected %s at %s line %d\n",
244 h, id, file, line);
245 return NULL;
246 }
247 return h;
248 }
249
add_xscom_node(uint64_t base,uint32_t hw_id,uint32_t proc_chip_id)250 static struct dt_node *add_xscom_node(uint64_t base, uint32_t hw_id,
251 uint32_t proc_chip_id)
252 {
253 struct dt_node *node;
254 uint64_t addr, size;
255 uint64_t freq;
256
257 switch (proc_gen) {
258 case proc_gen_p8:
259 /* On P8 all the chip SCOMs share single region */
260 addr = base | ((uint64_t)hw_id << PPC_BITLSHIFT(28));
261 break;
262 case proc_gen_p9:
263 default:
264 /* On P9 we need to put the chip ID in the natural powerbus
265 * position.
266 */
267 addr = base | (((uint64_t)hw_id) << 42);
268 break;
269 };
270
271 size = (u64)1 << PPC_BITLSHIFT(28);
272
273 prlog(PR_INFO, "XSCOM: Found HW ID 0x%x (PCID 0x%x) @ 0x%llx\n",
274 hw_id, proc_chip_id, (long long)addr);
275
276 node = dt_new_addr(dt_root, "xscom", addr);
277 if (!node)
278 return NULL;
279
280 dt_add_property_cells(node, "ibm,chip-id", hw_id);
281 dt_add_property_cells(node, "ibm,proc-chip-id", proc_chip_id);
282 dt_add_property_cells(node, "#address-cells", 1);
283 dt_add_property_cells(node, "#size-cells", 1);
284 dt_add_property(node, "scom-controller", NULL, 0);
285
286 switch(proc_gen) {
287 case proc_gen_p8:
288 dt_add_property_strings(node, "compatible",
289 "ibm,xscom", "ibm,power8-xscom");
290 break;
291 case proc_gen_p9:
292 dt_add_property_strings(node, "compatible",
293 "ibm,xscom", "ibm,power9-xscom");
294 break;
295 default:
296 dt_add_property_strings(node, "compatible", "ibm,xscom");
297 }
298 dt_add_property_u64s(node, "reg", addr, size);
299
300 /*
301 * The bus-frequency of the xscom node is actually the PIB/PCB
302 * frequency. It is derived from the nest-clock via a 4:1 divider
303 */
304 freq = dt_prop_get_u64_def(dt_root, "nest-frequency", 0);
305 freq /= 4;
306 if (freq)
307 dt_add_property_u64(node, "bus-frequency", freq);
308
309 return node;
310 }
311
312 /*
313 * Given a xscom@ node this will return a pointer into the SPPCRD
314 * structure corresponding to that node
315 */
316 #define GET_HDIF_HDR -1
xscom_to_pcrd(struct dt_node * xscom,int idata_index)317 static const void *xscom_to_pcrd(struct dt_node *xscom, int idata_index)
318 {
319 struct spira_ntuple *t = &spira.ntuples.proc_chip;
320 const struct HDIF_common_hdr *hdif;
321 const void *idata;
322 unsigned int size;
323 uint32_t i;
324 void *base;
325
326 i = dt_prop_get_u32_def(xscom, DT_PRIVATE "sppcrd-index", 0xffffffff);
327 if (i == 0xffffffff)
328 return NULL;
329
330 base = get_hdif(t, "SPPCRD");
331 assert(base);
332 assert(i < be16_to_cpu(t->act_cnt));
333
334 hdif = base + i * be32_to_cpu(t->alloc_len);
335 assert(hdif);
336
337 if (idata_index == GET_HDIF_HDR)
338 return hdif;
339
340 idata = HDIF_get_idata(hdif, idata_index, &size);
341 if (!idata || !size)
342 return NULL;
343
344 return idata;
345 }
346
find_xscom_for_chip(uint32_t chip_id)347 struct dt_node *find_xscom_for_chip(uint32_t chip_id)
348 {
349 struct dt_node *node;
350 uint32_t id;
351
352 dt_for_each_compatible(dt_root, node, "ibm,xscom") {
353 id = dt_get_chip_id(node);
354 if (id == chip_id)
355 return node;
356 }
357
358 return NULL;
359 }
360
add_psihb_node(struct dt_node * np)361 static void add_psihb_node(struct dt_node *np)
362 {
363 u32 psi_scom, psi_slen;
364 const char *psi_comp;
365
366 /*
367 * We add a few things under XSCOM that aren't added
368 * by any other HDAT path
369 */
370
371 /* PSI host bridge */
372 switch(proc_gen) {
373 case proc_gen_p8:
374 psi_scom = 0x2010900;
375 psi_slen = 0x20;
376 psi_comp = "ibm,power8-psihb-x";
377 break;
378 case proc_gen_p9:
379 psi_scom = 0x5012900;
380 psi_slen = 0x100;
381 psi_comp = "ibm,power9-psihb-x";
382 break;
383 default:
384 psi_comp = NULL;
385 }
386 if (psi_comp) {
387 struct dt_node *psi_np;
388
389 psi_np = dt_new_addr(np, "psihb", psi_scom);
390 if (!psi_np)
391 return;
392
393 dt_add_property_cells(psi_np, "reg", psi_scom, psi_slen);
394 dt_add_property_strings(psi_np, "compatible", psi_comp,
395 "ibm,psihb-x");
396 }
397 }
398
add_xive_node(struct dt_node * np)399 static void add_xive_node(struct dt_node *np)
400 {
401 struct dt_node *xive = dt_new_addr(np, "xive", 0x5013000);
402
403 dt_add_property_cells(xive, "reg", 0x5013000, 0x300);
404 dt_add_property_string(xive, "compatible", "ibm,power9-xive-x");
405
406 /* HACK: required for simics */
407 dt_add_property(xive, "force-assign-bars", NULL, 0);
408 }
409
410 /*
411 * SCOM Base Address from P9 SCOM Assignment spreadsheet
412 */
413 #define VAS_SCOM_BASE_ADDR 0x03011800
414
add_vas_node(struct dt_node * np,int idx)415 static void add_vas_node(struct dt_node *np, int idx)
416 {
417 struct dt_node *vas = dt_new_addr(np, "vas", VAS_SCOM_BASE_ADDR);
418
419 dt_add_property_cells(vas, "reg", VAS_SCOM_BASE_ADDR, 0x300);
420 dt_add_property_string(vas, "compatible", "ibm,power9-vas-x");
421 dt_add_property_cells(vas, "ibm,vas-id", idx);
422 }
423
add_ecid_data(const struct HDIF_common_hdr * hdr,struct dt_node * xscom)424 static void add_ecid_data(const struct HDIF_common_hdr *hdr,
425 struct dt_node *xscom)
426 {
427 char wafer_id[11];
428 uint8_t tmp;
429 int i;
430 uint32_t size = 0;
431 struct sppcrd_ecid *ecid;
432 const struct HDIF_array_hdr *ec_hdr;
433
434 ec_hdr = HDIF_get_idata(hdr, SPPCRD_IDATA_EC_LEVEL, &size);
435 if (!ec_hdr || !size)
436 return;
437
438 ecid = (void *)ec_hdr + be32_to_cpu(ec_hdr->offset);
439 dt_add_property_u64s(xscom, "ecid", be64_to_cpu(ecid->low),
440 be64_to_cpu(ecid->high));
441
442 /*
443 * bits 4:63 of ECID data contains wafter ID data (ten 6 bit fields
444 * each containing a code).
445 */
446 for (i = 0; i < 10; i++) {
447 tmp = (u8)((be64_to_cpu(ecid->low) >> (i * 6)) & 0x3f);
448 if (tmp <= 9)
449 wafer_id[9 - i] = tmp + '0';
450 else if (tmp >= 0xA && tmp <= 0x23)
451 wafer_id[9 - i] = tmp + '0' + 7;
452 else if (tmp == 0x3D)
453 wafer_id[9 - i] = '-';
454 else if (tmp == 0x3E)
455 wafer_id[9 - i] = '.';
456 else if (tmp == 0x3F)
457 wafer_id[9 - i] = ' ';
458 else /* Unknown code */
459 wafer_id[9 - i] = tmp + '0';
460 }
461 wafer_id[10] = '\0';
462 dt_add_property_nstr(xscom, "wafer-id", wafer_id, 10);
463
464 dt_add_property_cells(xscom, "wafer-location",
465 (u32)((be64_to_cpu(ecid->high) >> 56) & 0xff),
466 (u32)((be64_to_cpu(ecid->high) >> 48) & 0xff));
467 }
468
add_xscom_add_pcia_assoc(struct dt_node * np,uint32_t pcid)469 static void add_xscom_add_pcia_assoc(struct dt_node *np, uint32_t pcid)
470 {
471 const struct HDIF_common_hdr *hdr;
472 u32 size;
473
474
475 /*
476 * The SPPCRD doesn't contain all the affinity data, we have
477 * to dig it out of a core. I assume this is so that node
478 * affinity can be different for groups of cores within the
479 * chip, but for now we are going to ignore that
480 */
481 hdr = get_hdif(&spira.ntuples.pcia, SPPCIA_HDIF_SIG);
482 if (!hdr)
483 return;
484
485 for_each_pcia(hdr) {
486 const struct sppcia_core_unique *id;
487
488 id = HDIF_get_idata(hdr, SPPCIA_IDATA_CORE_UNIQUE, &size);
489 if (!id || size < sizeof(*id))
490 continue;
491
492 if (be32_to_cpu(id->proc_chip_id) != pcid)
493 continue;
494
495 dt_add_property_cells(np, "ibm,ccm-node-id",
496 be32_to_cpu(id->ccm_node_id));
497 dt_add_property_cells(np, "ibm,hw-card-id",
498 be32_to_cpu(id->hw_card_id));
499 dt_add_property_cells(np, "ibm,hw-module-id",
500 be32_to_cpu(id->hw_module_id));
501 if (!dt_find_property(np, "ibm,dbob-id"))
502 dt_add_property_cells(np, "ibm,dbob-id",
503 be32_to_cpu(id->drawer_book_octant_blade_id));
504 if (proc_gen < proc_gen_p9) {
505 dt_add_property_cells(np, "ibm,mem-interleave-scope",
506 be32_to_cpu(id->memory_interleaving_scope));
507 }
508 return;
509 }
510 }
511
add_xscom_sppcrd(uint64_t xscom_base)512 static bool add_xscom_sppcrd(uint64_t xscom_base)
513 {
514 const struct HDIF_common_hdr *hdif;
515 unsigned int i, vpd_sz;
516 const void *vpd;
517 struct dt_node *np, *vpd_node;
518
519 for_each_ntuple_idx(&spira.ntuples.proc_chip, hdif, i,
520 SPPCRD_HDIF_SIG) {
521 const struct sppcrd_chip_info *cinfo;
522 const struct spira_fru_id *fru_id = NULL;
523 unsigned int csize;
524 u32 ve, version;
525
526 cinfo = HDIF_get_idata(hdif, SPPCRD_IDATA_CHIP_INFO, &csize);
527 if (!CHECK_SPPTR(cinfo)) {
528 prerror("XSCOM: Bad ChipID data %d\n", i);
529 continue;
530 }
531
532 ve = be32_to_cpu(cinfo->verif_exist_flags) & CHIP_VERIFY_MASK;
533 ve >>= CHIP_VERIFY_SHIFT;
534 if (ve == CHIP_VERIFY_NOT_INSTALLED ||
535 ve == CHIP_VERIFY_UNUSABLE)
536 continue;
537
538 /* Create the XSCOM node */
539 np = add_xscom_node(xscom_base,
540 be32_to_cpu(cinfo->xscom_id),
541 be32_to_cpu(cinfo->proc_chip_id));
542 if (!np)
543 continue;
544
545
546 dt_add_property_cells(np, DT_PRIVATE "sppcrd-index", i);
547
548 version = be16_to_cpu(hdif->version);
549
550 /* Version 0A has additional OCC related stuff */
551 if (version >= 0x000a) {
552 if (!dt_find_property(np, "ibm,dbob-id"))
553 dt_add_property_cells(np, "ibm,dbob-id",
554 be32_to_cpu(cinfo->dbob_id));
555 dt_add_property_cells(np, "ibm,occ-functional-state",
556 be32_to_cpu(cinfo->occ_state));
557 }
558
559 /* Add chip VPD */
560 vpd_node = dt_add_vpd_node(hdif, SPPCRD_IDATA_FRU_ID,
561 SPPCRD_IDATA_KW_VPD);
562 if (vpd_node)
563 dt_add_property_cells(vpd_node, "ibm,chip-id",
564 be32_to_cpu(cinfo->xscom_id));
565
566 fru_id = HDIF_get_idata(hdif, SPPCRD_IDATA_FRU_ID, NULL);
567 if (fru_id)
568 slca_vpd_add_loc_code(np, be16_to_cpu(fru_id->slca_index));
569
570 /* Add module VPD on version A and later */
571 if (version >= 0x000a) {
572 vpd = HDIF_get_idata(hdif, SPPCRD_IDATA_MODULE_VPD,
573 &vpd_sz);
574 if (CHECK_SPPTR(vpd)) {
575 dt_add_property(np, "ibm,module-vpd", vpd,
576 vpd_sz);
577 vpd_data_parse(np, vpd, vpd_sz);
578 if (vpd_node)
579 dt_add_proc_vendor(vpd_node, vpd, vpd_sz);
580 }
581 }
582
583 /*
584 * Extract additional associativity information from
585 * the core data. Pick one core on that chip
586 */
587 add_xscom_add_pcia_assoc(np, be32_to_cpu(cinfo->proc_chip_id));
588
589 /* Add PSI Host bridge */
590 add_psihb_node(np);
591
592 if (proc_gen >= proc_gen_p9) {
593 add_xive_node(np);
594 parse_i2c_devs(hdif, SPPCRD_IDATA_HOST_I2C, np);
595 add_vas_node(np, i);
596 add_ecid_data(hdif, np);
597
598 if (be32_to_cpu(cinfo->verif_exist_flags) & CHIP_VERIFY_MASTER_PROC)
599 dt_add_property(np, "primary", NULL, 0);
600 }
601
602 /*
603 * Add sw checkstop scom address (ibm,sw-checkstop-fir)
604 *
605 * The latest HDAT versions have sw checkstop scom address
606 * info. But not sure from which version onwards (at least
607 * HDAT spec do not mention that explicitly). Hence use the
608 * sppcrd struct size returned by HDIF_get_idata to figure out
609 * whether it contains sw checkstop scom address info. Also
610 * check if sw_xstop_fir_scom address is non-zero.
611 */
612 if ((csize >= (offsetof(struct sppcrd_chip_info,
613 sw_xstop_fir_bitpos) + 1)) &&
614 cinfo->sw_xstop_fir_scom) {
615 __be32 fir_bit = cinfo->sw_xstop_fir_bitpos;
616
617 if (!dt_find_property(dt_root, "ibm,sw-checkstop-fir"))
618 dt_add_property_cells(dt_root,
619 "ibm,sw-checkstop-fir",
620 be32_to_cpu(cinfo->sw_xstop_fir_scom),
621 be32_to_cpu(fir_bit));
622 }
623 }
624
625 return i > 0;
626 }
627
add_xscom(void)628 static void add_xscom(void)
629 {
630 const void *ms_vpd;
631 const struct msvpd_pmover_bsr_synchro *pmbs;
632 unsigned int size;
633 uint64_t xscom_base;
634
635 ms_vpd = get_hdif(&spira.ntuples.ms_vpd, MSVPD_HDIF_SIG);
636 if (!ms_vpd) {
637 prerror("XSCOM: Can't find MS VPD\n");
638 return;
639 }
640
641 pmbs = HDIF_get_idata(ms_vpd, MSVPD_IDATA_PMOVER_SYNCHRO, &size);
642 if (!CHECK_SPPTR(pmbs) || size < sizeof(*pmbs)) {
643 prerror("XSCOM: absent or bad PMBS size %u @ %p\n", size, pmbs);
644 return;
645 }
646
647 if (!(be32_to_cpu(pmbs->flags) & MSVPD_PMS_FLAG_XSCOMBASE_VALID)) {
648 prerror("XSCOM: No XSCOM base in PMBS, using default\n");
649 return;
650 }
651
652 xscom_base = be64_to_cpu(pmbs->xscom_addr);
653
654 /* Get rid of the top bits */
655 xscom_base = cleanup_addr(xscom_base);
656
657 /* First, try the new proc_chip ntuples for chip data */
658 if (add_xscom_sppcrd(xscom_base))
659 return;
660 }
661
add_chiptod_node(unsigned int chip_id,int flags)662 static void add_chiptod_node(unsigned int chip_id, int flags)
663 {
664 struct dt_node *node, *xscom_node;
665 const char *compat_str;
666 uint32_t addr, len;
667
668 if ((flags & CHIPTOD_ID_FLAGS_STATUS_MASK) !=
669 CHIPTOD_ID_FLAGS_STATUS_OK)
670 return;
671
672 xscom_node = find_xscom_for_chip(chip_id);
673 if (!xscom_node) {
674 prerror("CHIPTOD: No xscom for chiptod %d?\n", chip_id);
675 return;
676 }
677
678 addr = 0x40000;
679 len = 0x34;
680
681 switch(proc_gen) {
682 case proc_gen_p8:
683 compat_str = "ibm,power8-chiptod";
684 break;
685 case proc_gen_p9:
686 compat_str = "ibm,power9-chiptod";
687 break;
688 default:
689 return;
690 }
691
692 prlog(PR_DEBUG, "CHIPTOD: Found on chip 0x%x %s\n", chip_id,
693 (flags & CHIPTOD_ID_FLAGS_PRIMARY) ? "[primary]" :
694 ((flags & CHIPTOD_ID_FLAGS_SECONDARY) ? "[secondary]" : ""));
695
696 node = dt_new_addr(xscom_node, "chiptod", addr);
697 if (!node)
698 return;
699
700 dt_add_property_cells(node, "reg", addr, len);
701 dt_add_property_strings(node, "compatible", "ibm,power-chiptod",
702 compat_str);
703
704 if (flags & CHIPTOD_ID_FLAGS_PRIMARY)
705 dt_add_property(node, "primary", NULL, 0);
706 if (flags & CHIPTOD_ID_FLAGS_SECONDARY)
707 dt_add_property(node, "secondary", NULL, 0);
708 }
709
add_chiptod_old(void)710 static bool add_chiptod_old(void)
711 {
712 const void *hdif;
713 unsigned int i;
714 bool found = false;
715
716 /*
717 * Locate chiptod ID structures in SPIRA
718 */
719 if (!get_hdif(&spira.ntuples.chip_tod, "TOD "))
720 return found;
721
722 for_each_ntuple_idx(&spira.ntuples.chip_tod, hdif, i, "TOD ") {
723 const struct chiptod_chipid *id;
724
725 id = HDIF_get_idata(hdif, CHIPTOD_IDATA_CHIPID, NULL);
726 if (!CHECK_SPPTR(id)) {
727 prerror("CHIPTOD: Bad ChipID data %d\n", i);
728 continue;
729 }
730
731 add_chiptod_node(pcid_to_chip_id(be32_to_cpu(id->chip_id)),
732 be32_to_cpu(id->flags));
733 found = true;
734 }
735 return found;
736 }
737
add_chiptod_new(void)738 static bool add_chiptod_new(void)
739 {
740 const void *hdif;
741 unsigned int i;
742 bool found = false;
743
744 /*
745 * Locate Proc Chip ID structures in SPIRA
746 */
747 if (!get_hdif(&spira.ntuples.proc_chip, SPPCRD_HDIF_SIG))
748 return found;
749
750 for_each_ntuple_idx(&spira.ntuples.proc_chip, hdif, i,
751 SPPCRD_HDIF_SIG) {
752 const struct sppcrd_chip_info *cinfo;
753 const struct sppcrd_chip_tod *tinfo;
754 unsigned int size;
755 u32 ve, flags;
756
757 cinfo = HDIF_get_idata(hdif, SPPCRD_IDATA_CHIP_INFO, NULL);
758 if (!CHECK_SPPTR(cinfo)) {
759 prerror("CHIPTOD: Bad ChipID data %d\n", i);
760 continue;
761 }
762
763 ve = be32_to_cpu(cinfo->verif_exist_flags) & CHIP_VERIFY_MASK;
764 ve >>= CHIP_VERIFY_SHIFT;
765 if (ve == CHIP_VERIFY_NOT_INSTALLED ||
766 ve == CHIP_VERIFY_UNUSABLE)
767 continue;
768
769 tinfo = HDIF_get_idata(hdif, SPPCRD_IDATA_CHIP_TOD, &size);
770 if (!CHECK_SPPTR(tinfo)) {
771 prerror("CHIPTOD: Bad TOD data %d\n", i);
772 continue;
773 }
774
775 flags = be32_to_cpu(tinfo->flags);
776
777 /* The FSP may strip the chiptod info from HDAT; if we find
778 * a zero-ed out entry, assume that the chiptod is
779 * present, but we don't have any primary/secondary info. In
780 * this case, pick chip zero as the master.
781 */
782 if (!size) {
783 flags = CHIPTOD_ID_FLAGS_STATUS_OK;
784 if (be32_to_cpu(cinfo->xscom_id) == 0x0)
785 flags |= CHIPTOD_ID_FLAGS_PRIMARY;
786 }
787
788 add_chiptod_node(be32_to_cpu(cinfo->xscom_id), flags);
789 found = true;
790 }
791 return found;
792 }
793
add_nx_node(u32 gcid)794 static void add_nx_node(u32 gcid)
795 {
796 struct dt_node *nx;
797 u32 addr;
798 u32 size;
799 struct dt_node *xscom;
800
801 xscom = find_xscom_for_chip(gcid);
802 if (xscom == NULL) {
803 prerror("NX%d: did not found xscom node.\n", gcid);
804 return;
805 }
806
807 /*
808 * The NX register space is relatively self contained on P7+ but
809 * a bit more messy on P8. However it's all contained within the
810 * PB chiplet port 1 so we'll stick to that in the "reg" property
811 * and let the NX "driver" deal with the details.
812 */
813 addr = 0x2010000;
814 size = 0x0004000;
815
816 nx = dt_new_addr(xscom, "nx", addr);
817 if (!nx)
818 return;
819
820 switch (proc_gen) {
821 case proc_gen_p8:
822 dt_add_property_strings(nx, "compatible", "ibm,power-nx",
823 "ibm,power8-nx");
824 break;
825 case proc_gen_p9:
826 /* POWER9 NX is not software compatible with P7/P8 NX */
827 dt_add_property_strings(nx, "compatible", "ibm,power9-nx");
828 break;
829 default:
830 return;
831 }
832
833 dt_add_property_cells(nx, "reg", addr, size);
834 }
835
add_nx(void)836 static void add_nx(void)
837 {
838 unsigned int i;
839 void *hdif;
840
841 for_each_ntuple_idx(&spira.ntuples.proc_chip, hdif, i,
842 SPPCRD_HDIF_SIG) {
843 const struct sppcrd_chip_info *cinfo;
844 u32 ve;
845
846 cinfo = HDIF_get_idata(hdif, SPPCRD_IDATA_CHIP_INFO, NULL);
847 if (!CHECK_SPPTR(cinfo)) {
848 prerror("NX: Bad ChipID data %d\n", i);
849 continue;
850 }
851
852 ve = be32_to_cpu(cinfo->verif_exist_flags) & CHIP_VERIFY_MASK;
853 ve >>= CHIP_VERIFY_SHIFT;
854 if (ve == CHIP_VERIFY_NOT_INSTALLED ||
855 ve == CHIP_VERIFY_UNUSABLE)
856 continue;
857
858 if (cinfo->nx_state)
859 add_nx_node(be32_to_cpu(cinfo->xscom_id));
860 }
861 }
862
add_nmmu(void)863 static void add_nmmu(void)
864 {
865 struct dt_node *xscom, *nmmu;
866
867 /* Nest MMU only exists on POWER9 */
868 if (proc_gen != proc_gen_p9)
869 return;
870
871 dt_for_each_compatible(dt_root, xscom, "ibm,xscom") {
872 nmmu = dt_new_addr(xscom, "nmmu", 0x5012c40);
873 dt_add_property_strings(nmmu, "compatible", "ibm,power9-nest-mmu");
874 dt_add_property_cells(nmmu, "reg", 0x5012c40, 0x20);
875 }
876 }
877
dt_init_secureboot_node(const struct iplparams_sysparams * sysparams)878 static void dt_init_secureboot_node(const struct iplparams_sysparams *sysparams)
879 {
880 struct dt_node *node;
881 u16 sys_sec_setting;
882 u16 hw_key_hash_size;
883
884 node = dt_new(dt_root, "ibm,secureboot");
885 assert(node);
886
887 dt_add_property_string(node, "compatible", "ibm,secureboot-v2");
888
889 sys_sec_setting = be16_to_cpu(sysparams->sys_sec_setting);
890 if (sys_sec_setting & SEC_CONTAINER_SIG_CHECKING)
891 dt_add_property(node, "secure-enabled", NULL, 0);
892 if (sys_sec_setting & SEC_HASHES_EXTENDED_TO_TPM)
893 dt_add_property(node, "trusted-enabled", NULL, 0);
894
895 hw_key_hash_size = be16_to_cpu(sysparams->hw_key_hash_size);
896
897 /* Prevent hw-key-hash buffer overflow by truncating hw-key-hash-size if
898 * it is bigger than the hw-key-hash buffer.
899 * Secure boot will be enforced later in skiboot, if the hw-key-hash-size
900 * was not supposed to be SYSPARAMS_HW_KEY_HASH_MAX.
901 */
902 if (hw_key_hash_size > SYSPARAMS_HW_KEY_HASH_MAX) {
903 prlog(PR_ERR, "IPLPARAMS: hw-key-hash-size=%d too big, "
904 "truncating to %d\n", hw_key_hash_size,
905 SYSPARAMS_HW_KEY_HASH_MAX);
906 hw_key_hash_size = SYSPARAMS_HW_KEY_HASH_MAX;
907 }
908
909 dt_add_property(node, "hw-key-hash", sysparams->hw_key_hash,
910 hw_key_hash_size);
911 dt_add_property_cells(node, "hw-key-hash-size", hw_key_hash_size);
912 }
913
add_iplparams_sys_params(const void * iplp,struct dt_node * node)914 static void add_iplparams_sys_params(const void *iplp, struct dt_node *node)
915 {
916 const struct iplparams_sysparams *p;
917 const struct HDIF_common_hdr *hdif = iplp;
918 u16 version = be16_to_cpu(hdif->version);
919 const char *vendor = NULL;
920 u32 sys_attributes;
921
922 p = HDIF_get_idata(iplp, IPLPARAMS_SYSPARAMS, NULL);
923 if (!CHECK_SPPTR(p)) {
924 prerror("IPLPARAMS: No SYS Parameters\n");
925 /* Create a generic compatible property */
926 dt_add_property_string(dt_root, "compatible", "ibm,powernv");
927 return;
928 }
929
930 node = dt_new(node, "sys-params");
931 assert(node);
932 dt_add_property_cells(node, "#address-cells", 0);
933 dt_add_property_cells(node, "#size-cells", 0);
934
935 dt_add_property_nstr(node, "ibm,sys-model", p->sys_model, 4);
936
937 /*
938 * Compatible has up to three entries:
939 * "ibm,powernv", the system family and system type.
940 *
941 * On P9 and above the family and type strings come from the HDAT
942 * directly. On P8 we find it from the system ID numbers.
943 */
944 if (proc_gen >= proc_gen_p9) {
945 dt_add_property_strings(dt_root, "compatible", "ibm,powernv",
946 p->sys_family_str, p->sys_type_str);
947
948 prlog(PR_INFO, "IPLPARAMS: v0x70 Platform family/type: %s/%s\n",
949 p->sys_family_str, p->sys_type_str);
950 } else {
951 u32 sys_type = be32_to_cpu(p->system_type);
952 const char *sys_family;
953
954 switch (sys_type >> 28) {
955 case 0:
956 sys_family = "ibm,squadrons";
957 break;
958 case 1:
959 sys_family = "ibm,eclipz";
960 break;
961 case 2:
962 sys_family = "ibm,apollo";
963 break;
964 case 3:
965 sys_family = "ibm,firenze";
966 break;
967 default:
968 sys_family = NULL;
969 prerror("IPLPARAMS: Unknown system family\n");
970 break;
971 }
972
973 dt_add_property_strings(dt_root, "compatible", "ibm,powernv",
974 sys_family);
975 prlog(PR_INFO,
976 "IPLPARAMS: Legacy platform family: %s"
977 " (sys_type=0x%08x)\n", sys_family, sys_type);
978 }
979
980 /* Grab nest frequency when available */
981 if (version >= 0x005b) {
982 u64 freq = be32_to_cpu(p->nest_freq_mhz);
983
984 freq *= 1000000;
985 dt_add_property_u64(dt_root, "nest-frequency", freq);
986 }
987
988 if (version >= 0x5f)
989 vendor = p->sys_vendor;
990
991 /* Workaround a bug where we have NULL vendor */
992 if (!vendor || vendor[0] == '\0')
993 vendor = "IBM";
994
995 dt_add_property_string(dt_root, "vendor", vendor);
996
997 sys_attributes = be32_to_cpu(p->sys_attributes);
998 if (sys_attributes & SYS_ATTR_RISK_LEVEL)
999 dt_add_property(node, "elevated-risk-level", NULL, 0);
1000
1001 if (version >= 0x60 && proc_gen >= proc_gen_p9)
1002 dt_init_secureboot_node(p);
1003 }
1004
add_iplparams_ipl_params(const void * iplp,struct dt_node * node)1005 static void add_iplparams_ipl_params(const void *iplp, struct dt_node *node)
1006 {
1007 const struct iplparams_iplparams *p;
1008 struct dt_node *led_node;
1009
1010 p = HDIF_get_idata(iplp, IPLPARAMS_IPLPARAMS, NULL);
1011 if (!CHECK_SPPTR(p)) {
1012 prerror("IPLPARAMS: No IPL Parameters\n");
1013 return;
1014 }
1015
1016 node = dt_new(node, "ipl-params");
1017 assert(node);
1018 dt_add_property_cells(node, "#address-cells", 0);
1019 dt_add_property_cells(node, "#size-cells", 0);
1020
1021 /* On an ASM initiated factory reset, this bit will be set
1022 * and the FSP expects the firmware to reset the PCI bus
1023 * numbers and respond with a Power Down (CE,4D,02) message
1024 */
1025 if (be32_to_cpu(p->other_attrib) & IPLPARAMS_OATTR_RST_PCI_BUSNO)
1026 dt_add_property_cells(node, "pci-busno-reset-ipl", 1);
1027 dt_add_property_strings(node, "cec-ipl-side",
1028 (p->ipl_side & IPLPARAMS_CEC_FW_IPL_SIDE_TEMP) ?
1029 "temp" : "perm");
1030 if (proc_gen >= proc_gen_p9) {
1031 dt_add_property_strings(node, "sp-ipl-side",
1032 (p->ipl_side & IPLPARAMS_FSP_FW_IPL_SIDE_TEMP) ?
1033 "temp" : "perm");
1034 } else {
1035 dt_add_property_strings(node, "fsp-ipl-side",
1036 (p->ipl_side & IPLPARAMS_FSP_FW_IPL_SIDE_TEMP) ?
1037 "temp" : "perm");
1038 }
1039 dt_add_property_cells(node, "os-ipl-mode", p->os_ipl_mode);
1040 dt_add_property_strings(node, "cec-major-type",
1041 p->cec_ipl_maj_type ? "hot" : "cold");
1042
1043 /* Add LED type info under '/ibm,opal/led' node */
1044 led_node = dt_find_by_path(opal_node, DT_PROPERTY_LED_NODE);
1045 assert(led_node);
1046
1047 if (be32_to_cpu(p->other_attrib) & IPLPARAMS_OATRR_LIGHT_PATH)
1048 dt_add_property_strings(led_node, DT_PROPERTY_LED_MODE,
1049 LED_MODE_LIGHT_PATH);
1050 else
1051 dt_add_property_strings(led_node, DT_PROPERTY_LED_MODE,
1052 LED_MODE_GUIDING_LIGHT);
1053 }
1054
add_iplparams_serials(const void * iplp,struct dt_node * node)1055 static void add_iplparams_serials(const void *iplp, struct dt_node *node)
1056 {
1057 const struct iplparms_serial *ipser;
1058 struct dt_node *ser_node;
1059 int count, i;
1060
1061 count = HDIF_get_iarray_size(iplp, IPLPARMS_IDATA_SERIAL);
1062 if (count <= 0)
1063 return;
1064 prlog(PR_INFO, "IPLPARAMS: %d serial ports in array\n", count);
1065
1066 node = dt_new(node, "fsp-serial");
1067 assert(node);
1068 dt_add_property_cells(node, "#address-cells", 1);
1069 dt_add_property_cells(node, "#size-cells", 0);
1070
1071 for (i = 0; i < count; i++) {
1072 u16 rsrc_id;
1073 ipser = HDIF_get_iarray_item(iplp, IPLPARMS_IDATA_SERIAL,
1074 i, NULL);
1075 if (!CHECK_SPPTR(ipser))
1076 continue;
1077 rsrc_id = be16_to_cpu(ipser->rsrc_id);
1078 prlog(PR_INFO, "IPLPARAMS: Serial %d rsrc: %04x loc: %s\n",
1079 i, rsrc_id, ipser->loc_code);
1080 ser_node = dt_new_addr(node, "serial", rsrc_id);
1081 if (!ser_node)
1082 continue;
1083
1084 dt_add_property_cells(ser_node, "reg", rsrc_id);
1085 dt_add_property_nstr(ser_node, "ibm,loc-code",
1086 ipser->loc_code, LOC_CODE_SIZE);
1087 dt_add_property_string(ser_node, "compatible",
1088 "ibm,fsp-serial");
1089 /* XXX handle CALLHOME flag ? */
1090 }
1091 }
1092
1093 /*
1094 * Check for platform dump, if present populate DT
1095 */
add_iplparams_platform_dump(const void * iplp,struct dt_node * node)1096 static void add_iplparams_platform_dump(const void *iplp, struct dt_node *node)
1097 {
1098 const struct iplparams_dump *ipl_dump;
1099
1100 ipl_dump = HDIF_get_idata(iplp, IPLPARAMS_PLATFORM_DUMP, NULL);
1101 if (!CHECK_SPPTR(ipl_dump))
1102 return;
1103
1104 node = dt_new(node, "platform-dump");
1105 assert(node);
1106
1107 if (be32_to_cpu(ipl_dump->dump_id)) {
1108 dt_add_property_cells(node, "dump-id",
1109 be32_to_cpu(ipl_dump->dump_id));
1110 dt_add_property_u64(node, "total-size",
1111 be64_to_cpu(ipl_dump->act_dump_sz));
1112 dt_add_property_u64(node, "hw-dump-size",
1113 be32_to_cpu(ipl_dump->act_hw_dump_sz));
1114 dt_add_property_cells(node, "plog-id",
1115 be32_to_cpu(ipl_dump->plid));
1116 }
1117 }
1118
add_iplparams_features(const struct HDIF_common_hdr * iplp)1119 static void add_iplparams_features(const struct HDIF_common_hdr *iplp)
1120 {
1121 const struct iplparams_feature *feature;
1122 const struct HDIF_array_hdr *array;
1123 struct dt_node *fw_features;
1124 unsigned int count, i;
1125 char name[65];
1126
1127 array = HDIF_get_iarray(iplp, IPLPARAMS_FEATURES, &count);
1128 if (!array || !count)
1129 return;
1130
1131 opal_node = dt_new_check(dt_root, "ibm,opal");
1132 fw_features = dt_new(opal_node, "fw-features");
1133 if (!fw_features)
1134 return;
1135
1136 HDIF_iarray_for_each(array, i, feature) {
1137 struct dt_node *n;
1138 uint64_t flags;
1139
1140 /* the name field isn't necessarily null terminated */
1141 BUILD_ASSERT(sizeof(name) > sizeof(feature->name));
1142 strncpy(name, feature->name, sizeof(name)-1);
1143 name[sizeof(name)-1] = '\0';
1144 flags = be64_to_cpu(feature->flags);
1145
1146 if (strlen(name) == 0) {
1147 prlog(PR_DEBUG, "IPLPARAMS: FW feature name is NULL\n");
1148 continue;
1149 }
1150
1151 prlog(PR_DEBUG, "IPLPARAMS: FW feature %s = %016"PRIx64"\n",
1152 name, flags);
1153
1154 /* get rid of tm-suspend-mode-enabled being disabled */
1155 if (strcmp(name, "tm-suspend-mode-enabled") == 0)
1156 strcpy(name, "tm-suspend-mode");
1157
1158 n = dt_new(fw_features, name);
1159
1160 /*
1161 * This is a bit overkill, but we'll want seperate properties
1162 * for each flag bit(s).
1163 */
1164 if (flags & PPC_BIT(0))
1165 dt_add_property(n, "enabled", NULL, 0);
1166 else
1167 dt_add_property(n, "disabled", NULL, 0);
1168 }
1169 }
1170
add_iplparams(void)1171 static void add_iplparams(void)
1172 {
1173 struct dt_node *iplp_node;
1174 const void *ipl_parms;
1175
1176 ipl_parms = get_hdif(&spira.ntuples.ipl_parms, "IPLPMS");
1177 if (!ipl_parms) {
1178 prerror("IPLPARAMS: Cannot find IPL Parms in SPIRA\n");
1179 return;
1180 }
1181
1182 iplp_node = dt_new(dt_root, "ipl-params");
1183 assert(iplp_node);
1184 dt_add_property_cells(iplp_node, "#address-cells", 0);
1185 dt_add_property_cells(iplp_node, "#size-cells", 0);
1186
1187 add_iplparams_sys_params(ipl_parms, iplp_node);
1188 add_iplparams_ipl_params(ipl_parms, iplp_node);
1189 add_iplparams_serials(ipl_parms, iplp_node);
1190 add_iplparams_platform_dump(ipl_parms, iplp_node);
1191 add_iplparams_features(ipl_parms);
1192 }
1193
1194 /* Various structure contain a "proc_chip_id" which is an arbitrary
1195 * numbering used by HDAT to reference chips, which doesn't correspond
1196 * to the HW IDs. We want to use the HW IDs everywhere in the DT so
1197 * we convert using this.
1198 *
1199 * Note: On P7, the HW ID is the XSCOM "GCID" including the T bit which
1200 * is *different* from the chip ID portion of the interrupt server#
1201 * (or PIR). See the explanations in chip.h
1202 */
pcid_to_chip_id(uint32_t proc_chip_id)1203 uint32_t pcid_to_chip_id(uint32_t proc_chip_id)
1204 {
1205 unsigned int i;
1206 const void *hdif;
1207
1208 /* First, try the proc_chip ntuples for chip data */
1209 for_each_ntuple_idx(&spira.ntuples.proc_chip, hdif, i,
1210 SPPCRD_HDIF_SIG) {
1211 const struct sppcrd_chip_info *cinfo;
1212
1213 cinfo = HDIF_get_idata(hdif, SPPCRD_IDATA_CHIP_INFO,
1214 NULL);
1215 if (!CHECK_SPPTR(cinfo)) {
1216 prerror("XSCOM: Bad ChipID data %d\n", i);
1217 continue;
1218 }
1219 if (proc_chip_id == be32_to_cpu(cinfo->proc_chip_id))
1220 return be32_to_cpu(cinfo->xscom_id);
1221 }
1222
1223 /* Not found, what to do ? Assert ? For now return a number
1224 * guaranteed to not exist
1225 */
1226 return (uint32_t)-1;
1227 }
1228
1229 /* Create '/ibm,opal/led' node */
dt_init_led_node(void)1230 static void dt_init_led_node(void)
1231 {
1232 struct dt_node *led_node;
1233
1234 /* Create /ibm,opal node, if its not created already */
1235 if (!opal_node) {
1236 opal_node = dt_new(dt_root, "ibm,opal");
1237 assert(opal_node);
1238 }
1239
1240 /* Crete LED parent node */
1241 led_node = dt_new(opal_node, DT_PROPERTY_LED_NODE);
1242 assert(led_node);
1243 }
1244
hostservices_parse(void)1245 static void hostservices_parse(void)
1246 {
1247 struct HDIF_common_hdr *hs_hdr;
1248 const void *dt_blob;
1249 unsigned int size;
1250 unsigned int ntuples_size;
1251
1252 /* Deprecated on P9 */
1253 if (proc_gen >= proc_gen_p9)
1254 return;
1255
1256 ntuples_size = sizeof(struct HDIF_array_hdr) +
1257 be32_to_cpu(spira.ntuples.array_hdr.ecnt) *
1258 sizeof(struct spira_ntuple);
1259
1260 if (offsetof(struct spira_ntuples, hs_data) >= ntuples_size) {
1261 prerror("SPIRA: No host services data found\n");
1262 return;
1263 }
1264
1265 hs_hdr = get_hdif(&spira.ntuples.hs_data, HSERV_HDIF_SIG);
1266 if (!hs_hdr) {
1267 prerror("SPIRA: No host services data found\n");
1268 return;
1269 }
1270
1271 dt_blob = HDIF_get_idata(hs_hdr, 0, &size);
1272 if (!dt_blob) {
1273 prerror("SPIRA: No host services idata found\n");
1274 return;
1275 }
1276 hservices_from_hdat(dt_blob, size);
1277 }
1278
add_stop_levels(void)1279 static void add_stop_levels(void)
1280 {
1281 struct spira_ntuple *t = &spira.ntuples.proc_chip;
1282 struct HDIF_common_hdr *hdif;
1283 u32 stop_levels = ~0;
1284 bool valid = false;
1285 int i;
1286
1287 if (proc_gen < proc_gen_p9)
1288 return;
1289
1290 /*
1291 * OPAL only exports a single set of flags to indicate the supported
1292 * STOP modes while the HDAT descibes the support top levels *per chip*
1293 * We parse the list of chips to find a common set of STOP levels to
1294 * export.
1295 */
1296 for_each_ntuple_idx(t, hdif, i, SPPCRD_HDIF_SIG) {
1297 unsigned int size;
1298 const struct sppcrd_chip_info *cinfo =
1299 HDIF_get_idata(hdif, SPPCRD_IDATA_CHIP_INFO, &size);
1300 u32 ve, chip_levels;
1301
1302 if (!cinfo)
1303 continue;
1304
1305 /*
1306 * If the chip info field is too small then assume we have no
1307 * STOP level information.
1308 */
1309 if (size < 0x44) {
1310 stop_levels = 0;
1311 break;
1312 }
1313
1314 ve = be32_to_cpu(cinfo->verif_exist_flags) & CPU_ID_VERIFY_MASK;
1315 ve >>= CPU_ID_VERIFY_SHIFT;
1316 if (ve == CHIP_VERIFY_NOT_INSTALLED ||
1317 ve == CHIP_VERIFY_UNUSABLE)
1318 continue;
1319
1320 chip_levels = be32_to_cpu(cinfo->stop_levels);
1321
1322 prlog(PR_INSANE, "CHIP[%x] supported STOP mask 0x%.8x\n",
1323 be32_to_cpu(cinfo->proc_chip_id), chip_levels);
1324
1325 stop_levels &= chip_levels;
1326 valid = true;
1327 }
1328
1329 if (!valid)
1330 stop_levels = 0;
1331
1332 dt_add_property_cells(dt_new_check(opal_node, "power-mgt"),
1333 "ibm,enabled-stop-levels", stop_levels);
1334 }
1335
1336 #define NPU_BASE 0x5011000
1337 #define NPU_SIZE 0x2c
1338 #define NPU_INDIRECT0 0x8000000009010c3fULL
1339 #define NPU_INDIRECT1 0x800000000c010c3fULL
1340
add_npu(struct dt_node * xscom,const struct HDIF_array_hdr * links,int npu_index,int phb_index)1341 static void add_npu(struct dt_node *xscom, const struct HDIF_array_hdr *links,
1342 int npu_index, int phb_index)
1343 {
1344 const struct sppcrd_smp_link *link;
1345 struct dt_node *npu;
1346 int group_target[6]; /* Tracks the PCI slot targeted each link group */
1347 int group_count = 0;
1348 int link_count = 0;
1349 uint32_t size, chip_id;
1350 int i;
1351
1352 size = be32_to_cpu(links->esize);
1353 chip_id = dt_get_chip_id(xscom);
1354
1355 memset(group_target, 0, sizeof(group_target));
1356
1357 npu = dt_new_addr(xscom, "npu", NPU_BASE);
1358 dt_add_property_cells(npu, "reg", NPU_BASE, NPU_SIZE);
1359 dt_add_property_cells(npu, "#size-cells", 0);
1360 dt_add_property_cells(npu, "#address-cells", 1);
1361
1362 dt_add_property_strings(npu, "compatible", "ibm,power9-npu");
1363 dt_add_property_cells(npu, "ibm,phb-index", phb_index);
1364 dt_add_property_cells(npu, "ibm,npu-index", npu_index);
1365
1366 HDIF_iarray_for_each(links, i, link) {
1367 uint16_t slot_id = be16_to_cpu(link->pci_slot_idx);
1368 uint32_t link_id = be32_to_cpu(link->link_id);
1369 uint64_t speed = 0, nvlink_speed = 0;
1370 struct dt_node *node;
1371
1372 /*
1373 * Only add a link node if this link is targeted at a
1374 * GPU device.
1375 *
1376 * If we ever activate it for an opencapi device, we
1377 * should revisit the link definitions hard-coded
1378 * on ZZ.
1379 */
1380 if (be32_to_cpu(link->usage) != SMP_LINK_USE_GPU)
1381 continue;
1382
1383 /*
1384 * XXX: The link_id that we get from HDAT is essentially an
1385 * arbitrary ID number so we can't use it as the reg for the
1386 * link node.
1387 *
1388 * a) There's a 1-1 mapping between entries in the SMP link
1389 * structure and the NPU links.
1390 *
1391 * b) The SMP link array contains them in ascending order.
1392 *
1393 * We have some assurances that b) is correct, but if we get
1394 * broken link numbering it's something to watch for.
1395 *
1396 * If we every have actual A-Bus (SMP) link info in here
1397 * this is going to break.
1398 */
1399
1400 prlog(PR_DEBUG, "NPU: %04x:%d: Link (%d) targets slot %u\n",
1401 chip_id, link_count, link_count, slot_id);
1402
1403 if (link_count >= 6) {
1404 prerror("NPU: %04x:%d: Ignoring extra link (max 6)\n",
1405 chip_id, link_count);
1406 break;
1407 }
1408
1409 node = dt_new_addr(npu, "link", link_count);
1410 if (!node) {
1411 prerror("NPU: %04x:%d: Creating link node failed\n",
1412 chip_id, link_count);
1413 continue;
1414 }
1415
1416 dt_add_property_string(node, "compatible", "ibm,npu-link");
1417 dt_add_property_cells(node, "reg", link_count);
1418 dt_add_property_cells(node, "ibm,npu-link-index", link_count);
1419 dt_add_property_cells(node, "ibm,workbook-link-id", link_id);
1420
1421 dt_add_property_u64s(node, "ibm,npu-phy",
1422 link_count < 3 ? NPU_INDIRECT0 : NPU_INDIRECT1);
1423 dt_add_property_cells(node, "ibm,npu-lane-mask",
1424 be32_to_cpu(link->lane_mask));
1425 dt_add_property_cells(node, "ibm,npu-brick-id",
1426 be32_to_cpu(link->brick_id));
1427
1428 link_count++;
1429
1430 /*
1431 * Add the group details if this is an NVlink.
1432 *
1433 * TODO: Cable card stuff.
1434 */
1435 if (slot_id) {
1436 struct dt_node *slot;
1437 const char *name;
1438 int group;
1439
1440 /*
1441 * Search the existing groups for one targeting
1442 * this PCI slot
1443 */
1444 for (group = 0; group < group_count; group++)
1445 if (group_target[group] == slot_id)
1446 break;
1447
1448 /* no group, make a new one */
1449 if (group == group_count) {
1450 group_target[group] = slot_id;
1451 group_count++;
1452 }
1453
1454 dt_add_property_cells(node, "ibm,npu-group-id", group);
1455
1456 slot = find_slot_entry_node(dt_root, slot_id);
1457 if (!slot) {
1458 prerror("NPU: %04x:%d: Unable find node for targeted PCIe slot\n",
1459 chip_id, link_count - 1);
1460 continue;
1461 }
1462
1463 /*
1464 * The slot_id points to a node that indicates that
1465 * this GPU should appear under the slot. Grab the
1466 * slot-label from the parent node that represents
1467 * the actual slot.
1468 */
1469 name = dt_prop_get_def(slot->parent, "ibm,slot-label",
1470 (char *)"<SLOT NAME MISSING>");
1471
1472 prlog(PR_DEBUG, "NPU: %04x:%d: Target slot %s\n",
1473 chip_id, link_count - 1, name);
1474
1475 dt_add_property_string(node, "ibm,slot-label", name);
1476 dt_add_property_cells(node, "ibm,pcie-slot",
1477 slot->phandle);
1478 }
1479
1480 /* Newer fields which might not be populated */
1481 if (size <= 0x24)
1482 continue;
1483
1484 switch (link->link_speed) {
1485 case 0: /* 20Gbps */
1486 speed = 20000000000ul;
1487 nvlink_speed = 0x3;
1488 break;
1489 case 1: /* 25Gbps */
1490 speed = 25000000000ul;
1491 nvlink_speed = 0x9;
1492 break;
1493 case 2: /* 25.78125 Gbps */
1494 nvlink_speed = 0x8;
1495 speed = 25781250000ul;
1496 break;
1497 }
1498
1499 /* ibm,link-speed is in bps and nvidia,link-speed is ~magic~ */
1500 dt_add_property_u64s(node, "ibm,link-speed", speed);
1501 dt_add_property_cells(node, "nvidia,link-speed", nvlink_speed);
1502
1503 dt_add_property_cells(node, DT_PRIVATE "occ-flag-pos",
1504 PPC_BIT(link->occ_flag_bit));
1505 }
1506
1507 dt_add_property_cells(npu, "ibm,npu-links", link_count);
1508 }
1509
add_npus(void)1510 static void add_npus(void)
1511 {
1512 struct dt_node *xscom;
1513 int phb_index = 7; /* Start counting from 7, for no reason */
1514 int npu_index = 0;
1515
1516 if (proc_gen < proc_gen_p9)
1517 return;
1518
1519 dt_for_each_compatible(dt_root, xscom, "ibm,xscom") {
1520 const struct HDIF_array_hdr *links;
1521
1522 links = xscom_to_pcrd(xscom, SPPCRD_IDATA_SMP_LINK);
1523 if (!links) {
1524 prerror("NPU: Unable to find matching SPPCRD for %s\n",
1525 xscom->name);
1526 continue;
1527 }
1528
1529 /* should never happen, but stranger things have */
1530 if (!dt_find_by_name(dt_root, "ibm,pcie-slots")) {
1531 prerror("PCIe slot information missing, can't add npu");
1532 continue;
1533 }
1534
1535 /* some hostboots will give us an empty array */
1536 if (be32_to_cpu(links->ecnt))
1537 add_npu(xscom, links, npu_index++, phb_index++);
1538 }
1539 }
1540
1541 /*
1542 * Legacy SPIRA is being deprecated and we have new SPIRA-H/S structures.
1543 * But on older system (p7?) we will continue to get legacy SPIRA.
1544 *
1545 * SPIRA-S is initialized and provided by FSP. We use SPIRA-S signature
1546 * to identify supported format. Also if required adjust spira pointer.
1547 */
fixup_spira(void)1548 static void fixup_spira(void)
1549 {
1550 #if !defined(TEST)
1551 spiras = (struct spiras *)CPU_TO_BE64(SPIRA_HEAP_BASE);
1552 #endif
1553
1554 /* Validate SPIRA-S signature */
1555 if (!spiras)
1556 return;
1557 if (!HDIF_check(&spiras->hdr, SPIRAS_HDIF_SIG))
1558 return;
1559
1560 prlog(PR_DEBUG, "SPIRA-S found.\n");
1561
1562 spira.ntuples.sp_subsys = spiras->ntuples.sp_subsys;
1563 spira.ntuples.ipl_parms = spiras->ntuples.ipl_parms;
1564 spira.ntuples.nt_enclosure_vpd = spiras->ntuples.nt_enclosure_vpd;
1565 spira.ntuples.slca = spiras->ntuples.slca;
1566 spira.ntuples.backplane_vpd = spiras->ntuples.backplane_vpd;
1567 spira.ntuples.system_vpd = spiras->ntuples.system_vpd;
1568 spira.ntuples.proc_init = spirah.ntuples.proc_init;
1569 spira.ntuples.clock_vpd = spiras->ntuples.clock_vpd;
1570 spira.ntuples.anchor_vpd = spiras->ntuples.anchor_vpd;
1571 spira.ntuples.op_panel_vpd = spiras->ntuples.op_panel_vpd;
1572 spira.ntuples.misc_cec_fru_vpd = spiras->ntuples.misc_cec_fru_vpd;
1573 spira.ntuples.ms_vpd = spiras->ntuples.ms_vpd;
1574 spira.ntuples.cec_iohub_fru = spiras->ntuples.cec_iohub_fru;
1575 spira.ntuples.cpu_ctrl = spirah.ntuples.cpu_ctrl;
1576 spira.ntuples.mdump_src = spirah.ntuples.mdump_src;
1577 spira.ntuples.mdump_dst = spirah.ntuples.mdump_dst;
1578 spira.ntuples.mdump_res = spirah.ntuples.mdump_res;
1579 spira.ntuples.pcia = spiras->ntuples.pcia;
1580 spira.ntuples.proc_chip = spiras->ntuples.proc_chip;
1581 spira.ntuples.hs_data = spiras->ntuples.hs_data;
1582 spira.ntuples.ipmi_sensor = spiras->ntuples.ipmi_sensor;
1583 spira.ntuples.node_stb_data = spiras->ntuples.node_stb_data;
1584 }
1585
parse_hdat(bool is_opal)1586 int parse_hdat(bool is_opal)
1587 {
1588 cpu_type = PVR_TYPE(mfspr(SPR_PVR));
1589
1590 prlog(PR_DEBUG, "Parsing HDAT...\n");
1591
1592 fixup_spira();
1593
1594 /*
1595 * Basic DT root stuff
1596 */
1597 dt_add_property_cells(dt_root, "#address-cells", 2);
1598 dt_add_property_cells(dt_root, "#size-cells", 2);
1599
1600 if (proc_gen < proc_gen_p9)
1601 dt_add_property_string(dt_root, "lid-type", is_opal ? "opal" : "phyp");
1602
1603 /* Add any BMCs and enable the LPC UART */
1604 bmc_parse();
1605
1606 /* Create and populate /vpd node */
1607 dt_init_vpd_node();
1608
1609 /* Create /ibm,opal/led node */
1610 dt_init_led_node();
1611
1612 /* Parse SPPACA and/or PCIA */
1613 if (!pcia_parse())
1614 if (paca_parse() < 0)
1615 return -1;
1616
1617 /* IPL params */
1618 add_iplparams();
1619
1620 /* Add XSCOM node (must be before chiptod, IO and FSP) */
1621 add_xscom();
1622
1623 /* Parse MS VPD */
1624 memory_parse();
1625
1626 /* Add any FSPs */
1627 fsp_parse();
1628
1629 /* Add ChipTOD's */
1630 if (!add_chiptod_old() && !add_chiptod_new())
1631 prerror("CHIPTOD: No ChipTOD found !\n");
1632
1633 /* Add NX */
1634 add_nx();
1635
1636 /* Add nest mmu */
1637 add_nmmu();
1638
1639 /* Add IO HUBs and/or PHBs */
1640 io_parse();
1641
1642 /* Add NPU nodes */
1643 if (proc_gen >= proc_gen_p9)
1644 add_npus();
1645
1646 /* Parse VPD */
1647 vpd_parse();
1648
1649 /* Host services information. */
1650 hostservices_parse();
1651
1652 /* Parse System Attention Indicator inforamtion */
1653 slca_dt_add_sai_node();
1654
1655 add_stop_levels();
1656
1657 /* Parse node secure and trusted boot data */
1658 if (proc_gen >= proc_gen_p9)
1659 node_stb_parse();
1660
1661 prlog(PR_DEBUG, "Parsing HDAT...done\n");
1662
1663 return 0;
1664 }
1665