1 #ifndef __XSCOM_P8_REGS_H__ 2 #define __XSCOM_P8_REGS_H__ 3 4 /* Core FIR (Fault Isolation Register) */ 5 #define P8_CORE_FIR 0x10013100 6 7 /* Direct controls */ 8 #define P8_EX_TCTL_DIRECT_CONTROLS(t) (0x10013000 + (t) * 0x10) 9 #define P8_DIRECT_CTL_STOP PPC_BIT(63) 10 #define P8_DIRECT_CTL_PRENAP PPC_BIT(47) 11 #define P8_DIRECT_CTL_SRESET PPC_BIT(60) 12 13 /* pMisc Receive Malfunction Alert Register */ 14 #define P8_MALFUNC_ALERT 0x02020011 15 16 #define P8_NX_STATUS_REG 0x02013040 /* NX status register */ 17 #define P8_NX_DMA_ENGINE_FIR 0x02013100 /* DMA & Engine FIR Data Register */ 18 #define P8_NX_PBI_FIR 0x02013080 /* PowerBus Interface FIR Register */ 19 20 /* 21 * Bit 54 from NX status register is set to 1 when HMI interrupt is triggered 22 * due to NX checksop. 23 */ 24 #define NX_HMI_ACTIVE PPC_BIT(54) 25 26 /* Per core power mgt registers */ 27 #define PM_OHA_MODE_REG 0x1002000D 28 #define L2_FIR_ACTION1 0x10012807 29 30 /* EX slave per-core power mgt slave regisers */ 31 #define EX_PM_GP0 0x0100 32 #define EX_PM_GP1 0x0103 33 #define EX_PM_CLEAR_GP1 0x0104 /* AND SCOM */ 34 #define EX_PM_SET_GP1 0x0105 /* OR SCOM */ 35 #define EX_PM_SPECIAL_WAKEUP_FSP 0x010B 36 #define EX_PM_SPECIAL_WAKEUP_OCC 0x010C 37 #define EX_PM_SPECIAL_WAKEUP_PHYP 0x010D 38 #define EX_PM_IDLE_STATE_HISTORY_PHYP 0x0110 39 #define EX_PM_IDLE_STATE_HISTORY_FSP 0x0111 40 #define EX_PM_IDLE_STATE_HISTORY_OCC 0x0112 41 #define EX_PM_IDLE_STATE_HISTORY_PERF 0x0113 42 #define EX_PM_CORE_PFET_VRET 0x0130 43 #define EX_PM_CORE_ECO_VRET 0x0150 44 #define EX_PM_PPMSR 0x0153 45 #define EX_PM_PPMCR 0x0159 46 47 /* Power mgt bits in GP0 */ 48 #define EX_PM_GP0_SPECIAL_WAKEUP_DONE PPC_BIT(31) 49 50 /* Power mgt settings in GP1 */ 51 #define EX_PM_SETUP_GP1_FAST_SLEEP 0xD800000000000000ULL 52 #define EX_PM_SETUP_GP1_DEEP_SLEEP 0x2400000000000000ULL 53 #define EX_PM_SETUP_GP1_FAST_SLEEP_DEEP_WINKLE 0xC400000000000000ULL 54 #define EX_PM_GP1_SLEEP_WINKLE_MASK 0xFC00000000000000ULL 55 #define EX_PM_SETUP_GP1_PM_SPR_OVERRIDE_EN 0x0010000000000000ULL 56 #define EX_PM_SETUP_GP1_DPLL_FREQ_OVERRIDE_EN 0x0020000000000000ULL 57 58 /* Fields in history regs */ 59 #define EX_PM_IDLE_ST_HIST_PM_STATE_MASK PPC_BITMASK(0, 2) 60 #define EX_PM_IDLE_ST_HIST_PM_STATE_LSH PPC_BITLSHIFT(2) 61 62 #endif /* __XSCOM_P8_REGS_H__ */ 63