1 /* DO NOT EDIT THIS FILE 2 * Automatically generated by generate-def-headers.xsl 3 * DO NOT EDIT THIS FILE 4 */ 5 6 #ifndef __BFIN_DEF_ADSP_BF523_proc__ 7 #define __BFIN_DEF_ADSP_BF523_proc__ 8 9 #include "../mach-common/ADSP-EDN-core_def.h" 10 11 #include "ADSP-EDN-BF52x-extended_def.h" 12 13 #define PLL_CTL 0xFFC00000 /* PLL Control Register */ 14 #define PLL_DIV 0xFFC00004 /* PLL Divide Register */ 15 #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ 16 #define PLL_STAT 0xFFC0000C /* PLL Status Register */ 17 #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ 18 #define CHIPID 0xFFC00014 19 #define SWRST 0xFFC00100 /* Software Reset Register */ 20 #define SYSCR 0xFFC00104 /* System Configuration register */ 21 #define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ 22 #define DMEM_CONTROL 0xFFE00004 /* Data memory control */ 23 #define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ 24 #define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ 25 #define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ 26 #define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ 27 #define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ 28 #define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ 29 #define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ 30 #define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ 31 #define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ 32 #define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ 33 #define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ 34 #define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ 35 #define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ 36 #define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ 37 #define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ 38 #define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ 39 #define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ 40 #define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ 41 #define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ 42 #define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ 43 #define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ 44 #define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ 45 #define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ 46 #define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ 47 #define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ 48 #define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ 49 #define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ 50 #define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ 51 #define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ 52 #define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ 53 #define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ 54 #define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ 55 #define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ 56 #define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ 57 #define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ 58 #define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ 59 #define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ 60 #define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ 61 #define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */ 62 #define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ 63 #define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ 64 #define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ 65 #define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ 66 #define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ 67 #define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ 68 #define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ 69 #define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ 70 #define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ 71 #define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ 72 #define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ 73 #define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ 74 #define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ 75 #define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ 76 #define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ 77 #define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ 78 #define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ 79 #define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ 80 #define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ 81 #define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ 82 #define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ 83 #define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ 84 #define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ 85 #define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ 86 #define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ 87 #define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ 88 #define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ 89 #define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ 90 #define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ 91 #define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ 92 #define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ 93 #define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ 94 #define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ 95 #define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ 96 #define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ 97 #define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ 98 #define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ 99 #define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ 100 #define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ 101 #define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ 102 #define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ 103 #define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ 104 #define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ 105 #define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ 106 #define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ 107 #define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ 108 #define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ 109 #define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ 110 #define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ 111 #define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ 112 #define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ 113 #define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ 114 #define ILAT 0xFFE0210C /* Interrupt Latch Register */ 115 #define IMASK 0xFFE02104 /* Interrupt Mask Register */ 116 #define IPEND 0xFFE02108 /* Interrupt Pending Register */ 117 #define IPRIO 0xFFE02110 /* Interrupt Priority Register */ 118 #define TCNTL 0xFFE03000 /* Core Timer Control Register */ 119 #define TPERIOD 0xFFE03004 /* Core Timer Period Register */ 120 #define TSCALE 0xFFE03008 /* Core Timer Scale Register */ 121 #define TCOUNT 0xFFE0300C /* Core Timer Count Register */ 122 123 #endif /* __BFIN_DEF_ADSP_BF523_proc__ */ 124