1 /*
2 * arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c
3 * This SPD DDR detection code supports IBM/AMCC PPC44x cpu with a
4 * DDR controller. Those are 440GP/GX/EP/GR.
5 *
6 * (C) Copyright 2001
7 * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
8 *
9 * Based on code by:
10 *
11 * Kenneth Johansson ,Ericsson AB.
12 * kenneth.johansson@etx.ericsson.se
13 *
14 * hacked up by bill hunter. fixed so we could run before
15 * serial_init and console_init. previous version avoided this by
16 * running out of cache memory during serial/console init, then running
17 * this code later.
18 *
19 * (C) Copyright 2002
20 * Jun Gu, Artesyn Technology, jung@artesyncp.com
21 * Support for AMCC 440 based on OpenBIOS draminit.c from IBM.
22 *
23 * (C) Copyright 2005-2007
24 * Stefan Roese, DENX Software Engineering, sr@denx.de.
25 *
26 * See file CREDITS for list of people who contributed to this
27 * project.
28 *
29 * This program is free software; you can redistribute it and/or
30 * modify it under the terms of the GNU General Public License as
31 * published by the Free Software Foundation; either version 2 of
32 * the License, or (at your option) any later version.
33 *
34 * This program is distributed in the hope that it will be useful,
35 * but WITHOUT ANY WARRANTY; without even the implied warranty of
36 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
37 * GNU General Public License for more details.
38 *
39 * You should have received a copy of the GNU General Public License
40 * along with this program; if not, write to the Free Software
41 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
42 * MA 02111-1307 USA
43 */
44
45 /* define DEBUG for debugging output (obviously ;-)) */
46 #if 0
47 #define DEBUG
48 #endif
49
50 #include <common.h>
51 #include <asm/processor.h>
52 #include <i2c.h>
53 #include <asm/ppc4xx.h>
54 #include <asm/mmu.h>
55
56 #include "ecc.h"
57
58 #if defined(CONFIG_SPD_EEPROM) && \
59 (defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
60 defined(CONFIG_440EP) || defined(CONFIG_440GR))
61
62 /*
63 * Set default values
64 */
65 #ifndef CONFIG_SYS_I2C_SPEED
66 #define CONFIG_SYS_I2C_SPEED 50000
67 #endif
68
69 #define ONE_BILLION 1000000000
70
71 /*
72 * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
73 */
__spd_ddr_init_hang(void)74 void __spd_ddr_init_hang (void)
75 {
76 hang ();
77 }
78 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
79
80 /*-----------------------------------------------------------------------------+
81 | General Definition
82 +-----------------------------------------------------------------------------*/
83 #define DEFAULT_SPD_ADDR1 0x53
84 #define DEFAULT_SPD_ADDR2 0x52
85 #define MAXBANKS 4 /* at most 4 dimm banks */
86 #define MAX_SPD_BYTES 256
87 #define NUMHALFCYCLES 4
88 #define NUMMEMTESTS 8
89 #define NUMMEMWORDS 8
90 #define MAXBXCR 4
91 #define TRUE 1
92 #define FALSE 0
93
94 /*
95 * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
96 * region. Right now the cache should still be disabled in U-Boot because of the
97 * EMAC driver, that need it's buffer descriptor to be located in non cached
98 * memory.
99 *
100 * If at some time this restriction doesn't apply anymore, just define
101 * CONFIG_4xx_DCACHE in the board config file and this code should setup
102 * everything correctly.
103 */
104 #ifdef CONFIG_4xx_DCACHE
105 #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
106 #else
107 #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
108 #endif
109
110 /* bank_parms is used to sort the bank sizes by descending order */
111 struct bank_param {
112 unsigned long cr;
113 unsigned long bank_size_bytes;
114 };
115
116 typedef struct bank_param BANKPARMS;
117
118 #ifdef CONFIG_SYS_SIMULATE_SPD_EEPROM
119 extern const unsigned char cfg_simulate_spd_eeprom[128];
120 #endif
121
122 static unsigned char spd_read(uchar chip, uint addr);
123 static void get_spd_info(unsigned long *dimm_populated,
124 unsigned char *iic0_dimm_addr,
125 unsigned long num_dimm_banks);
126 static void check_mem_type(unsigned long *dimm_populated,
127 unsigned char *iic0_dimm_addr,
128 unsigned long num_dimm_banks);
129 static void check_volt_type(unsigned long *dimm_populated,
130 unsigned char *iic0_dimm_addr,
131 unsigned long num_dimm_banks);
132 static void program_cfg0(unsigned long *dimm_populated,
133 unsigned char *iic0_dimm_addr,
134 unsigned long num_dimm_banks);
135 static void program_cfg1(unsigned long *dimm_populated,
136 unsigned char *iic0_dimm_addr,
137 unsigned long num_dimm_banks);
138 static void program_rtr(unsigned long *dimm_populated,
139 unsigned char *iic0_dimm_addr,
140 unsigned long num_dimm_banks);
141 static void program_tr0(unsigned long *dimm_populated,
142 unsigned char *iic0_dimm_addr,
143 unsigned long num_dimm_banks);
144 static void program_tr1(void);
145
146 static unsigned long program_bxcr(unsigned long *dimm_populated,
147 unsigned char *iic0_dimm_addr,
148 unsigned long num_dimm_banks);
149
150 /*
151 * This function is reading data from the DIMM module EEPROM over the SPD bus
152 * and uses that to program the sdram controller.
153 *
154 * This works on boards that has the same schematics that the AMCC walnut has.
155 *
156 * BUG: Don't handle ECC memory
157 * BUG: A few values in the TR register is currently hardcoded
158 */
spd_sdram(void)159 long int spd_sdram(void) {
160 unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
161 unsigned long dimm_populated[sizeof(iic0_dimm_addr)];
162 unsigned long total_size;
163 unsigned long cfg0;
164 unsigned long mcsts;
165 unsigned long num_dimm_banks; /* on board dimm banks */
166
167 num_dimm_banks = sizeof(iic0_dimm_addr);
168
169 /*
170 * Make sure I2C controller is initialized
171 * before continuing.
172 */
173 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
174
175 /*
176 * Read the SPD information using I2C interface. Check to see if the
177 * DIMM slots are populated.
178 */
179 get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
180
181 /*
182 * Check the memory type for the dimms plugged.
183 */
184 check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
185
186 /*
187 * Check the voltage type for the dimms plugged.
188 */
189 check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
190
191 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
192 /*
193 * Soft-reset SDRAM controller.
194 */
195 mtsdr(SDR0_SRST, SDR0_SRST_DMC);
196 mtsdr(SDR0_SRST, 0x00000000);
197 #endif
198
199 /*
200 * program 440GP SDRAM controller options (SDRAM0_CFG0)
201 */
202 program_cfg0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
203
204 /*
205 * program 440GP SDRAM controller options (SDRAM0_CFG1)
206 */
207 program_cfg1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
208
209 /*
210 * program SDRAM refresh register (SDRAM0_RTR)
211 */
212 program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
213
214 /*
215 * program SDRAM Timing Register 0 (SDRAM0_TR0)
216 */
217 program_tr0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
218
219 /*
220 * program the BxCR registers to find out total sdram installed
221 */
222 total_size = program_bxcr(dimm_populated, iic0_dimm_addr,
223 num_dimm_banks);
224
225 #ifdef CONFIG_PROG_SDRAM_TLB /* this define should eventually be removed */
226 /* and program tlb entries for this size (dynamic) */
227 program_tlb(0, 0, total_size, MY_TLB_WORD2_I_ENABLE);
228 #endif
229
230 /*
231 * program SDRAM Clock Timing Register (SDRAM0_CLKTR)
232 */
233 mtsdram(SDRAM0_CLKTR, 0x40000000);
234
235 /*
236 * delay to ensure 200 usec has elapsed
237 */
238 udelay(400);
239
240 /*
241 * enable the memory controller
242 */
243 mfsdram(SDRAM0_CFG0, cfg0);
244 mtsdram(SDRAM0_CFG0, cfg0 | SDRAM_CFG0_DCEN);
245
246 /*
247 * wait for SDRAM_CFG0_DC_EN to complete
248 */
249 while (1) {
250 mfsdram(SDRAM0_MCSTS, mcsts);
251 if ((mcsts & SDRAM_MCSTS_MRSC) != 0)
252 break;
253 }
254
255 /*
256 * program SDRAM Timing Register 1, adding some delays
257 */
258 program_tr1();
259
260 #ifdef CONFIG_DDR_ECC
261 /*
262 * If ecc is enabled, initialize the parity bits.
263 */
264 ecc_init(CONFIG_SYS_SDRAM_BASE, total_size);
265 #endif
266
267 return total_size;
268 }
269
spd_read(uchar chip,uint addr)270 static unsigned char spd_read(uchar chip, uint addr)
271 {
272 unsigned char data[2];
273
274 #ifdef CONFIG_SYS_SIMULATE_SPD_EEPROM
275 if (chip == CONFIG_SYS_SIMULATE_SPD_EEPROM) {
276 /*
277 * Onboard spd eeprom requested -> simulate values
278 */
279 return cfg_simulate_spd_eeprom[addr];
280 }
281 #endif /* CONFIG_SYS_SIMULATE_SPD_EEPROM */
282
283 if (i2c_probe(chip) == 0) {
284 if (i2c_read(chip, addr, 1, data, 1) == 0) {
285 return data[0];
286 }
287 }
288
289 return 0;
290 }
291
get_spd_info(unsigned long * dimm_populated,unsigned char * iic0_dimm_addr,unsigned long num_dimm_banks)292 static void get_spd_info(unsigned long *dimm_populated,
293 unsigned char *iic0_dimm_addr,
294 unsigned long num_dimm_banks)
295 {
296 unsigned long dimm_num;
297 unsigned long dimm_found;
298 unsigned char num_of_bytes;
299 unsigned char total_size;
300
301 dimm_found = FALSE;
302 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
303 num_of_bytes = 0;
304 total_size = 0;
305
306 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
307 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
308
309 if ((num_of_bytes != 0) && (total_size != 0)) {
310 dimm_populated[dimm_num] = TRUE;
311 dimm_found = TRUE;
312 debug("DIMM slot %lu: populated\n", dimm_num);
313 } else {
314 dimm_populated[dimm_num] = FALSE;
315 debug("DIMM slot %lu: Not populated\n", dimm_num);
316 }
317 }
318
319 if (dimm_found == FALSE) {
320 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
321 spd_ddr_init_hang ();
322 }
323 }
324
check_mem_type(unsigned long * dimm_populated,unsigned char * iic0_dimm_addr,unsigned long num_dimm_banks)325 static void check_mem_type(unsigned long *dimm_populated,
326 unsigned char *iic0_dimm_addr,
327 unsigned long num_dimm_banks)
328 {
329 unsigned long dimm_num;
330 unsigned char dimm_type;
331
332 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
333 if (dimm_populated[dimm_num] == TRUE) {
334 dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
335 switch (dimm_type) {
336 case 7:
337 debug("DIMM slot %lu: DDR SDRAM detected\n", dimm_num);
338 break;
339 default:
340 printf("ERROR: Unsupported DIMM detected in slot %lu.\n",
341 dimm_num);
342 printf("Only DDR SDRAM DIMMs are supported.\n");
343 printf("Replace the DIMM module with a supported DIMM.\n\n");
344 spd_ddr_init_hang ();
345 break;
346 }
347 }
348 }
349 }
350
check_volt_type(unsigned long * dimm_populated,unsigned char * iic0_dimm_addr,unsigned long num_dimm_banks)351 static void check_volt_type(unsigned long *dimm_populated,
352 unsigned char *iic0_dimm_addr,
353 unsigned long num_dimm_banks)
354 {
355 unsigned long dimm_num;
356 unsigned long voltage_type;
357
358 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
359 if (dimm_populated[dimm_num] == TRUE) {
360 voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
361 if (voltage_type != 0x04) {
362 printf("ERROR: DIMM %lu with unsupported voltage level.\n",
363 dimm_num);
364 spd_ddr_init_hang ();
365 } else {
366 debug("DIMM %lu voltage level supported.\n", dimm_num);
367 }
368 break;
369 }
370 }
371 }
372
program_cfg0(unsigned long * dimm_populated,unsigned char * iic0_dimm_addr,unsigned long num_dimm_banks)373 static void program_cfg0(unsigned long *dimm_populated,
374 unsigned char *iic0_dimm_addr,
375 unsigned long num_dimm_banks)
376 {
377 unsigned long dimm_num;
378 unsigned long cfg0;
379 unsigned long ecc_enabled;
380 unsigned char ecc;
381 unsigned char attributes;
382 unsigned long data_width;
383 unsigned long dimm_32bit;
384 unsigned long dimm_64bit;
385
386 /*
387 * get Memory Controller Options 0 data
388 */
389 mfsdram(SDRAM0_CFG0, cfg0);
390
391 /*
392 * clear bits
393 */
394 cfg0 &= ~(SDRAM_CFG0_DCEN | SDRAM_CFG0_MCHK_MASK |
395 SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD |
396 SDRAM_CFG0_DMWD_MASK |
397 SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP);
398
399
400 /*
401 * FIXME: assume the DDR SDRAMs in both banks are the same
402 */
403 ecc_enabled = TRUE;
404 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
405 if (dimm_populated[dimm_num] == TRUE) {
406 ecc = spd_read(iic0_dimm_addr[dimm_num], 11);
407 if (ecc != 0x02) {
408 ecc_enabled = FALSE;
409 }
410
411 /*
412 * program Registered DIMM Enable
413 */
414 attributes = spd_read(iic0_dimm_addr[dimm_num], 21);
415 if ((attributes & 0x02) != 0x00) {
416 cfg0 |= SDRAM_CFG0_RDEN;
417 }
418
419 /*
420 * program DDR SDRAM Data Width
421 */
422 data_width =
423 (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) +
424 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8);
425 if (data_width == 64 || data_width == 72) {
426 dimm_64bit = TRUE;
427 cfg0 |= SDRAM_CFG0_DMWD_64;
428 } else if (data_width == 32 || data_width == 40) {
429 dimm_32bit = TRUE;
430 cfg0 |= SDRAM_CFG0_DMWD_32;
431 } else {
432 printf("WARNING: DIMM with datawidth of %lu bits.\n",
433 data_width);
434 printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
435 spd_ddr_init_hang ();
436 }
437 break;
438 }
439 }
440
441 /*
442 * program Memory Data Error Checking
443 */
444 if (ecc_enabled == TRUE) {
445 cfg0 |= SDRAM_CFG0_MCHK_GEN;
446 } else {
447 cfg0 |= SDRAM_CFG0_MCHK_NON;
448 }
449
450 /*
451 * program Page Management Unit (0 == enabled)
452 */
453 cfg0 &= ~SDRAM_CFG0_PMUD;
454
455 /*
456 * program Memory Controller Options 0
457 * Note: DCEN must be enabled after all DDR SDRAM controller
458 * configuration registers get initialized.
459 */
460 mtsdram(SDRAM0_CFG0, cfg0);
461 }
462
program_cfg1(unsigned long * dimm_populated,unsigned char * iic0_dimm_addr,unsigned long num_dimm_banks)463 static void program_cfg1(unsigned long *dimm_populated,
464 unsigned char *iic0_dimm_addr,
465 unsigned long num_dimm_banks)
466 {
467 unsigned long cfg1;
468 mfsdram(SDRAM0_CFG1, cfg1);
469
470 /*
471 * Self-refresh exit, disable PM
472 */
473 cfg1 &= ~(SDRAM_CFG1_SRE | SDRAM_CFG1_PMEN);
474
475 /*
476 * program Memory Controller Options 1
477 */
478 mtsdram(SDRAM0_CFG1, cfg1);
479 }
480
program_rtr(unsigned long * dimm_populated,unsigned char * iic0_dimm_addr,unsigned long num_dimm_banks)481 static void program_rtr(unsigned long *dimm_populated,
482 unsigned char *iic0_dimm_addr,
483 unsigned long num_dimm_banks)
484 {
485 unsigned long dimm_num;
486 unsigned long bus_period_x_10;
487 unsigned long refresh_rate = 0;
488 unsigned char refresh_rate_type;
489 unsigned long refresh_interval;
490 unsigned long sdram_rtr;
491 PPC4xx_SYS_INFO sys_info;
492
493 /*
494 * get the board info
495 */
496 get_sys_info(&sys_info);
497 bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
498
499 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
500 if (dimm_populated[dimm_num] == TRUE) {
501 refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
502 switch (refresh_rate_type) {
503 case 0x00:
504 refresh_rate = 15625;
505 break;
506 case 0x01:
507 refresh_rate = 15625/4;
508 break;
509 case 0x02:
510 refresh_rate = 15625/2;
511 break;
512 case 0x03:
513 refresh_rate = 15626*2;
514 break;
515 case 0x04:
516 refresh_rate = 15625*4;
517 break;
518 case 0x05:
519 refresh_rate = 15625*8;
520 break;
521 default:
522 printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n",
523 dimm_num);
524 printf("Replace the DIMM module with a supported DIMM.\n");
525 break;
526 }
527
528 break;
529 }
530 }
531
532 refresh_interval = refresh_rate * 10 / bus_period_x_10;
533 sdram_rtr = (refresh_interval & 0x3ff8) << 16;
534
535 /*
536 * program Refresh Timer Register (SDRAM0_RTR)
537 */
538 mtsdram(SDRAM0_RTR, sdram_rtr);
539 }
540
program_tr0(unsigned long * dimm_populated,unsigned char * iic0_dimm_addr,unsigned long num_dimm_banks)541 static void program_tr0(unsigned long *dimm_populated,
542 unsigned char *iic0_dimm_addr,
543 unsigned long num_dimm_banks)
544 {
545 unsigned long dimm_num;
546 unsigned long tr0;
547 unsigned char wcsbc;
548 unsigned char t_rp_ns;
549 unsigned char t_rcd_ns;
550 unsigned char t_ras_ns;
551 unsigned long t_rp_clk;
552 unsigned long t_ras_rcd_clk;
553 unsigned long t_rcd_clk;
554 unsigned long t_rfc_clk;
555 unsigned long plb_check;
556 unsigned char cas_bit;
557 unsigned long cas_index;
558 unsigned char cas_2_0_available;
559 unsigned char cas_2_5_available;
560 unsigned char cas_3_0_available;
561 unsigned long cycle_time_ns_x_10[3];
562 unsigned long tcyc_3_0_ns_x_10;
563 unsigned long tcyc_2_5_ns_x_10;
564 unsigned long tcyc_2_0_ns_x_10;
565 unsigned long tcyc_reg;
566 unsigned long bus_period_x_10;
567 PPC4xx_SYS_INFO sys_info;
568 unsigned long residue;
569
570 /*
571 * get the board info
572 */
573 get_sys_info(&sys_info);
574 bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
575
576 /*
577 * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
578 */
579 mfsdram(SDRAM0_TR0, tr0);
580 tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK |
581 SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK |
582 SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK |
583 SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK);
584
585 /*
586 * initialization
587 */
588 wcsbc = 0;
589 t_rp_ns = 0;
590 t_rcd_ns = 0;
591 t_ras_ns = 0;
592 cas_2_0_available = TRUE;
593 cas_2_5_available = TRUE;
594 cas_3_0_available = TRUE;
595 tcyc_2_0_ns_x_10 = 0;
596 tcyc_2_5_ns_x_10 = 0;
597 tcyc_3_0_ns_x_10 = 0;
598
599 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
600 if (dimm_populated[dimm_num] == TRUE) {
601 wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
602 t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
603 t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
604 t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30);
605 cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
606
607 for (cas_index = 0; cas_index < 3; cas_index++) {
608 switch (cas_index) {
609 case 0:
610 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
611 break;
612 case 1:
613 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
614 break;
615 default:
616 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
617 break;
618 }
619
620 if ((tcyc_reg & 0x0F) >= 10) {
621 printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
622 dimm_num);
623 spd_ddr_init_hang ();
624 }
625
626 cycle_time_ns_x_10[cas_index] =
627 (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F);
628 }
629
630 cas_index = 0;
631
632 if ((cas_bit & 0x80) != 0) {
633 cas_index += 3;
634 } else if ((cas_bit & 0x40) != 0) {
635 cas_index += 2;
636 } else if ((cas_bit & 0x20) != 0) {
637 cas_index += 1;
638 }
639
640 if (((cas_bit & 0x10) != 0) && (cas_index < 3)) {
641 tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
642 cas_index++;
643 } else {
644 if (cas_index != 0) {
645 cas_index++;
646 }
647 cas_3_0_available = FALSE;
648 }
649
650 if (((cas_bit & 0x08) != 0) || (cas_index < 3)) {
651 tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index];
652 cas_index++;
653 } else {
654 if (cas_index != 0) {
655 cas_index++;
656 }
657 cas_2_5_available = FALSE;
658 }
659
660 if (((cas_bit & 0x04) != 0) || (cas_index < 3)) {
661 tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
662 cas_index++;
663 } else {
664 if (cas_index != 0) {
665 cas_index++;
666 }
667 cas_2_0_available = FALSE;
668 }
669
670 break;
671 }
672 }
673
674 /*
675 * Program SD_WR and SD_WCSBC fields
676 */
677 tr0 |= SDRAM_TR0_SDWR_2_CLK; /* Write Recovery: 2 CLK */
678 switch (wcsbc) {
679 case 0:
680 tr0 |= SDRAM_TR0_SDWD_0_CLK;
681 break;
682 default:
683 tr0 |= SDRAM_TR0_SDWD_1_CLK;
684 break;
685 }
686
687 /*
688 * Program SD_CASL field
689 */
690 if ((cas_2_0_available == TRUE) &&
691 (bus_period_x_10 >= tcyc_2_0_ns_x_10)) {
692 tr0 |= SDRAM_TR0_SDCL_2_0_CLK;
693 } else if ((cas_2_5_available == TRUE) &&
694 (bus_period_x_10 >= tcyc_2_5_ns_x_10)) {
695 tr0 |= SDRAM_TR0_SDCL_2_5_CLK;
696 } else if ((cas_3_0_available == TRUE) &&
697 (bus_period_x_10 >= tcyc_3_0_ns_x_10)) {
698 tr0 |= SDRAM_TR0_SDCL_3_0_CLK;
699 } else {
700 printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
701 printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
702 printf("Make sure the PLB speed is within the supported range.\n");
703 spd_ddr_init_hang ();
704 }
705
706 /*
707 * Calculate Trp in clock cycles and round up if necessary
708 * Program SD_PTA field
709 */
710 t_rp_clk = sys_info.freqPLB * t_rp_ns / ONE_BILLION;
711 plb_check = ONE_BILLION * t_rp_clk / t_rp_ns;
712 if (sys_info.freqPLB != plb_check) {
713 t_rp_clk++;
714 }
715 switch ((unsigned long)t_rp_clk) {
716 case 0:
717 case 1:
718 case 2:
719 tr0 |= SDRAM_TR0_SDPA_2_CLK;
720 break;
721 case 3:
722 tr0 |= SDRAM_TR0_SDPA_3_CLK;
723 break;
724 default:
725 tr0 |= SDRAM_TR0_SDPA_4_CLK;
726 break;
727 }
728
729 /*
730 * Program SD_CTP field
731 */
732 t_ras_rcd_clk = sys_info.freqPLB * (t_ras_ns - t_rcd_ns) / ONE_BILLION;
733 plb_check = ONE_BILLION * t_ras_rcd_clk / (t_ras_ns - t_rcd_ns);
734 if (sys_info.freqPLB != plb_check) {
735 t_ras_rcd_clk++;
736 }
737 switch (t_ras_rcd_clk) {
738 case 0:
739 case 1:
740 case 2:
741 tr0 |= SDRAM_TR0_SDCP_2_CLK;
742 break;
743 case 3:
744 tr0 |= SDRAM_TR0_SDCP_3_CLK;
745 break;
746 case 4:
747 tr0 |= SDRAM_TR0_SDCP_4_CLK;
748 break;
749 default:
750 tr0 |= SDRAM_TR0_SDCP_5_CLK;
751 break;
752 }
753
754 /*
755 * Program SD_LDF field
756 */
757 tr0 |= SDRAM_TR0_SDLD_2_CLK;
758
759 /*
760 * Program SD_RFTA field
761 * FIXME tRFC hardcoded as 75 nanoseconds
762 */
763 t_rfc_clk = sys_info.freqPLB / (ONE_BILLION / 75);
764 residue = sys_info.freqPLB % (ONE_BILLION / 75);
765 if (residue >= (ONE_BILLION / 150)) {
766 t_rfc_clk++;
767 }
768 switch (t_rfc_clk) {
769 case 0:
770 case 1:
771 case 2:
772 case 3:
773 case 4:
774 case 5:
775 case 6:
776 tr0 |= SDRAM_TR0_SDRA_6_CLK;
777 break;
778 case 7:
779 tr0 |= SDRAM_TR0_SDRA_7_CLK;
780 break;
781 case 8:
782 tr0 |= SDRAM_TR0_SDRA_8_CLK;
783 break;
784 case 9:
785 tr0 |= SDRAM_TR0_SDRA_9_CLK;
786 break;
787 case 10:
788 tr0 |= SDRAM_TR0_SDRA_10_CLK;
789 break;
790 case 11:
791 tr0 |= SDRAM_TR0_SDRA_11_CLK;
792 break;
793 case 12:
794 tr0 |= SDRAM_TR0_SDRA_12_CLK;
795 break;
796 default:
797 tr0 |= SDRAM_TR0_SDRA_13_CLK;
798 break;
799 }
800
801 /*
802 * Program SD_RCD field
803 */
804 t_rcd_clk = sys_info.freqPLB * t_rcd_ns / ONE_BILLION;
805 plb_check = ONE_BILLION * t_rcd_clk / t_rcd_ns;
806 if (sys_info.freqPLB != plb_check) {
807 t_rcd_clk++;
808 }
809 switch (t_rcd_clk) {
810 case 0:
811 case 1:
812 case 2:
813 tr0 |= SDRAM_TR0_SDRD_2_CLK;
814 break;
815 case 3:
816 tr0 |= SDRAM_TR0_SDRD_3_CLK;
817 break;
818 default:
819 tr0 |= SDRAM_TR0_SDRD_4_CLK;
820 break;
821 }
822
823 debug("tr0: %x\n", tr0);
824 mtsdram(SDRAM0_TR0, tr0);
825 }
826
short_mem_test(void)827 static int short_mem_test(void)
828 {
829 unsigned long i, j;
830 unsigned long bxcr_num;
831 unsigned long *membase;
832 const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
833 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
834 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
835 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
836 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
837 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
838 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
839 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
840 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
841 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
842 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
843 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
844 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
845 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
846 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
847 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
848 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}};
849
850 for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
851 mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (bxcr_num << 2));
852 if ((mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
853 /* Bank is enabled */
854 membase = (unsigned long*)
855 (mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBA_MASK);
856
857 /*
858 * Run the short memory test
859 */
860 for (i = 0; i < NUMMEMTESTS; i++) {
861 for (j = 0; j < NUMMEMWORDS; j++) {
862 /* printf("bank enabled base:%x\n", &membase[j]); */
863 membase[j] = test[i][j];
864 ppcDcbf((unsigned long)&(membase[j]));
865 }
866
867 for (j = 0; j < NUMMEMWORDS; j++) {
868 if (membase[j] != test[i][j]) {
869 ppcDcbf((unsigned long)&(membase[j]));
870 return 0;
871 }
872 ppcDcbf((unsigned long)&(membase[j]));
873 }
874
875 if (j < NUMMEMWORDS)
876 return 0;
877 }
878
879 /*
880 * see if the rdclt value passed
881 */
882 if (i < NUMMEMTESTS)
883 return 0;
884 }
885 }
886
887 return 1;
888 }
889
program_tr1(void)890 static void program_tr1(void)
891 {
892 unsigned long tr0;
893 unsigned long tr1;
894 unsigned long cfg0;
895 unsigned long ecc_temp;
896 unsigned long dlycal;
897 unsigned long dly_val;
898 unsigned long k;
899 unsigned long max_pass_length;
900 unsigned long current_pass_length;
901 unsigned long current_fail_length;
902 unsigned long current_start;
903 unsigned long rdclt;
904 unsigned long rdclt_offset;
905 long max_start;
906 long max_end;
907 long rdclt_average;
908 unsigned char window_found;
909 unsigned char fail_found;
910 unsigned char pass_found;
911 PPC4xx_SYS_INFO sys_info;
912
913 /*
914 * get the board info
915 */
916 get_sys_info(&sys_info);
917
918 /*
919 * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
920 */
921 mfsdram(SDRAM0_TR1, tr1);
922 tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK |
923 SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK);
924
925 mfsdram(SDRAM0_TR0, tr0);
926 if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) &&
927 (sys_info.freqPLB > 100000000)) {
928 tr1 |= SDRAM_TR1_RDSS_TR2;
929 tr1 |= SDRAM_TR1_RDSL_STAGE3;
930 tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
931 } else {
932 tr1 |= SDRAM_TR1_RDSS_TR1;
933 tr1 |= SDRAM_TR1_RDSL_STAGE2;
934 tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
935 }
936
937 /*
938 * save CFG0 ECC setting to a temporary variable and turn ECC off
939 */
940 mfsdram(SDRAM0_CFG0, cfg0);
941 ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK;
942 mtsdram(SDRAM0_CFG0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON);
943
944 /*
945 * get the delay line calibration register value
946 */
947 mfsdram(SDRAM0_DLYCAL, dlycal);
948 dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
949
950 max_pass_length = 0;
951 max_start = 0;
952 max_end = 0;
953 current_pass_length = 0;
954 current_fail_length = 0;
955 current_start = 0;
956 rdclt_offset = 0;
957 window_found = FALSE;
958 fail_found = FALSE;
959 pass_found = FALSE;
960 debug("Starting memory test ");
961
962 for (k = 0; k < NUMHALFCYCLES; k++) {
963 for (rdclt = 0; rdclt < dly_val; rdclt++) {
964 /*
965 * Set the timing reg for the test.
966 */
967 mtsdram(SDRAM0_TR1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
968
969 if (short_mem_test()) {
970 if (fail_found == TRUE) {
971 pass_found = TRUE;
972 if (current_pass_length == 0) {
973 current_start = rdclt_offset + rdclt;
974 }
975
976 current_fail_length = 0;
977 current_pass_length++;
978
979 if (current_pass_length > max_pass_length) {
980 max_pass_length = current_pass_length;
981 max_start = current_start;
982 max_end = rdclt_offset + rdclt;
983 }
984 }
985 } else {
986 current_pass_length = 0;
987 current_fail_length++;
988
989 if (current_fail_length >= (dly_val>>2)) {
990 if (fail_found == FALSE) {
991 fail_found = TRUE;
992 } else if (pass_found == TRUE) {
993 window_found = TRUE;
994 break;
995 }
996 }
997 }
998 }
999 debug(".");
1000
1001 if (window_found == TRUE) {
1002 break;
1003 }
1004
1005 tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1006 rdclt_offset += dly_val;
1007 }
1008 debug("\n");
1009
1010 /*
1011 * make sure we find the window
1012 */
1013 if (window_found == FALSE) {
1014 printf("ERROR: Cannot determine a common read delay.\n");
1015 spd_ddr_init_hang ();
1016 }
1017
1018 /*
1019 * restore the orignal ECC setting
1020 */
1021 mtsdram(SDRAM0_CFG0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp);
1022
1023 /*
1024 * set the SDRAM TR1 RDCD value
1025 */
1026 tr1 &= ~SDRAM_TR1_RDCD_MASK;
1027 if ((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) {
1028 tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
1029 } else {
1030 tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
1031 }
1032
1033 /*
1034 * set the SDRAM TR1 RDCLT value
1035 */
1036 tr1 &= ~SDRAM_TR1_RDCT_MASK;
1037 while (max_end >= (dly_val << 1)) {
1038 max_end -= (dly_val << 1);
1039 max_start -= (dly_val << 1);
1040 }
1041
1042 rdclt_average = ((max_start + max_end) >> 1);
1043
1044 if (rdclt_average < 0) {
1045 rdclt_average = 0;
1046 }
1047
1048 if (rdclt_average >= dly_val) {
1049 rdclt_average -= dly_val;
1050 tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1051 }
1052 tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average);
1053
1054 debug("tr1: %x\n", tr1);
1055
1056 /*
1057 * program SDRAM Timing Register 1 TR1
1058 */
1059 mtsdram(SDRAM0_TR1, tr1);
1060 }
1061
program_bxcr(unsigned long * dimm_populated,unsigned char * iic0_dimm_addr,unsigned long num_dimm_banks)1062 static unsigned long program_bxcr(unsigned long *dimm_populated,
1063 unsigned char *iic0_dimm_addr,
1064 unsigned long num_dimm_banks)
1065 {
1066 unsigned long dimm_num;
1067 unsigned long bank_base_addr;
1068 unsigned long cr;
1069 unsigned long i;
1070 unsigned long j;
1071 unsigned long temp;
1072 unsigned char num_row_addr;
1073 unsigned char num_col_addr;
1074 unsigned char num_banks;
1075 unsigned char bank_size_id;
1076 unsigned long ctrl_bank_num[MAXBANKS];
1077 unsigned long bx_cr_num;
1078 unsigned long largest_size_index;
1079 unsigned long largest_size;
1080 unsigned long current_size_index;
1081 BANKPARMS bank_parms[MAXBXCR];
1082 unsigned long sorted_bank_num[MAXBXCR]; /* DDR Controller bank number table (sorted by size) */
1083 unsigned long sorted_bank_size[MAXBXCR]; /* DDR Controller bank size table (sorted by size)*/
1084
1085 /*
1086 * Set the BxCR regs. First, wipe out the bank config registers.
1087 */
1088 for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
1089 mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (bx_cr_num << 2));
1090 mtdcr(SDRAM0_CFGDATA, 0x00000000);
1091 bank_parms[bx_cr_num].bank_size_bytes = 0;
1092 }
1093
1094 #ifdef CONFIG_BAMBOO
1095 /*
1096 * This next section is hardware dependent and must be programmed
1097 * to match the hardware. For bamboo, the following holds...
1098 * 1. SDRAM0_B0CR: Bank 0 of dimm 0 ctrl_bank_num : 0 (soldered onboard)
1099 * 2. SDRAM0_B1CR: Bank 0 of dimm 1 ctrl_bank_num : 1
1100 * 3. SDRAM0_B2CR: Bank 1 of dimm 1 ctrl_bank_num : 1
1101 * 4. SDRAM0_B3CR: Bank 0 of dimm 2 ctrl_bank_num : 3
1102 * ctrl_bank_num corresponds to the first usable DDR controller bank number by DIMM
1103 */
1104 ctrl_bank_num[0] = 0;
1105 ctrl_bank_num[1] = 1;
1106 ctrl_bank_num[2] = 3;
1107 #else
1108 /*
1109 * Ocotea, Ebony and the other IBM/AMCC eval boards have
1110 * 2 DIMM slots with each max 2 banks
1111 */
1112 ctrl_bank_num[0] = 0;
1113 ctrl_bank_num[1] = 2;
1114 #endif
1115
1116 /*
1117 * reset the bank_base address
1118 */
1119 bank_base_addr = CONFIG_SYS_SDRAM_BASE;
1120
1121 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1122 if (dimm_populated[dimm_num] == TRUE) {
1123 num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3);
1124 num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
1125 num_banks = spd_read(iic0_dimm_addr[dimm_num], 5);
1126 bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
1127 debug("DIMM%d: row=%d col=%d banks=%d\n", dimm_num,
1128 num_row_addr, num_col_addr, num_banks);
1129
1130 /*
1131 * Set the SDRAM0_BxCR regs
1132 */
1133 cr = 0;
1134 switch (bank_size_id) {
1135 case 0x02:
1136 cr |= SDRAM_BXCR_SDSZ_8;
1137 break;
1138 case 0x04:
1139 cr |= SDRAM_BXCR_SDSZ_16;
1140 break;
1141 case 0x08:
1142 cr |= SDRAM_BXCR_SDSZ_32;
1143 break;
1144 case 0x10:
1145 cr |= SDRAM_BXCR_SDSZ_64;
1146 break;
1147 case 0x20:
1148 cr |= SDRAM_BXCR_SDSZ_128;
1149 break;
1150 case 0x40:
1151 cr |= SDRAM_BXCR_SDSZ_256;
1152 break;
1153 case 0x80:
1154 cr |= SDRAM_BXCR_SDSZ_512;
1155 break;
1156 default:
1157 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1158 dimm_num);
1159 printf("ERROR: Unsupported value for the banksize: %d.\n",
1160 bank_size_id);
1161 printf("Replace the DIMM module with a supported DIMM.\n\n");
1162 spd_ddr_init_hang ();
1163 }
1164
1165 switch (num_col_addr) {
1166 case 0x08:
1167 cr |= SDRAM_BXCR_SDAM_1;
1168 break;
1169 case 0x09:
1170 cr |= SDRAM_BXCR_SDAM_2;
1171 break;
1172 case 0x0A:
1173 cr |= SDRAM_BXCR_SDAM_3;
1174 break;
1175 case 0x0B:
1176 cr |= SDRAM_BXCR_SDAM_4;
1177 break;
1178 default:
1179 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1180 dimm_num);
1181 printf("ERROR: Unsupported value for number of "
1182 "column addresses: %d.\n", num_col_addr);
1183 printf("Replace the DIMM module with a supported DIMM.\n\n");
1184 spd_ddr_init_hang ();
1185 }
1186
1187 /*
1188 * enable the bank
1189 */
1190 cr |= SDRAM_BXCR_SDBE;
1191
1192 for (i = 0; i < num_banks; i++) {
1193 bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes =
1194 (4 << 20) * bank_size_id;
1195 bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr;
1196 debug("DIMM%d-bank %d (SDRAM0_B%dCR): bank_size_bytes=%d\n",
1197 dimm_num, i, ctrl_bank_num[dimm_num]+i,
1198 bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes);
1199 }
1200 }
1201 }
1202
1203 /* Initialize sort tables */
1204 for (i = 0; i < MAXBXCR; i++) {
1205 sorted_bank_num[i] = i;
1206 sorted_bank_size[i] = bank_parms[i].bank_size_bytes;
1207 }
1208
1209 for (i = 0; i < MAXBXCR-1; i++) {
1210 largest_size = sorted_bank_size[i];
1211 largest_size_index = 255;
1212
1213 /* Find the largest remaining value */
1214 for (j = i + 1; j < MAXBXCR; j++) {
1215 if (sorted_bank_size[j] > largest_size) {
1216 /* Save largest remaining value and its index */
1217 largest_size = sorted_bank_size[j];
1218 largest_size_index = j;
1219 }
1220 }
1221
1222 if (largest_size_index != 255) {
1223 /* Swap the current and largest values */
1224 current_size_index = sorted_bank_num[largest_size_index];
1225 sorted_bank_size[largest_size_index] = sorted_bank_size[i];
1226 sorted_bank_size[i] = largest_size;
1227 sorted_bank_num[largest_size_index] = sorted_bank_num[i];
1228 sorted_bank_num[i] = current_size_index;
1229 }
1230 }
1231
1232 /* Set the SDRAM0_BxCR regs thanks to sort tables */
1233 for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
1234 if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) {
1235 mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (sorted_bank_num[bx_cr_num] << 2));
1236 temp = mfdcr(SDRAM0_CFGDATA) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK |
1237 SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE);
1238 temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) |
1239 bank_parms[sorted_bank_num[bx_cr_num]].cr;
1240 mtdcr(SDRAM0_CFGDATA, temp);
1241 bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes;
1242 debug("SDRAM0_B%dCR=0x%08lx\n", sorted_bank_num[bx_cr_num], temp);
1243 }
1244 }
1245
1246 return(bank_base_addr);
1247 }
1248 #endif /* CONFIG_SPD_EEPROM */
1249