1 /* 2 * (C) Copyright 2003 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * This file is based on mpc4200fec.h 6 * (C) Copyright Motorola, Inc., 2000 7 * 8 * odin ethernet header file 9 */ 10 11 #ifndef __MPC5XXX_FEC_H 12 #define __MPC5XXX_FEC_H 13 14 typedef unsigned long uint32; 15 typedef unsigned short uint16; 16 typedef unsigned char uint8; 17 18 typedef struct ethernet_register_set { 19 20 /* [10:2]addr = 00 */ 21 22 /* Control and status Registers (offset 000-1FF) */ 23 24 volatile uint32 fec_id; /* MBAR_ETH + 0x000 */ 25 volatile uint32 ievent; /* MBAR_ETH + 0x004 */ 26 volatile uint32 imask; /* MBAR_ETH + 0x008 */ 27 28 volatile uint32 RES0[1]; /* MBAR_ETH + 0x00C */ 29 volatile uint32 r_des_active; /* MBAR_ETH + 0x010 */ 30 volatile uint32 x_des_active; /* MBAR_ETH + 0x014 */ 31 volatile uint32 r_des_active_cl; /* MBAR_ETH + 0x018 */ 32 volatile uint32 x_des_active_cl; /* MBAR_ETH + 0x01C */ 33 volatile uint32 ivent_set; /* MBAR_ETH + 0x020 */ 34 volatile uint32 ecntrl; /* MBAR_ETH + 0x024 */ 35 36 volatile uint32 RES1[6]; /* MBAR_ETH + 0x028-03C */ 37 volatile uint32 mii_data; /* MBAR_ETH + 0x040 */ 38 volatile uint32 mii_speed; /* MBAR_ETH + 0x044 */ 39 volatile uint32 mii_status; /* MBAR_ETH + 0x048 */ 40 41 volatile uint32 RES2[5]; /* MBAR_ETH + 0x04C-05C */ 42 volatile uint32 mib_data; /* MBAR_ETH + 0x060 */ 43 volatile uint32 mib_control; /* MBAR_ETH + 0x064 */ 44 45 volatile uint32 RES3[6]; /* MBAR_ETH + 0x068-7C */ 46 volatile uint32 r_activate; /* MBAR_ETH + 0x080 */ 47 volatile uint32 r_cntrl; /* MBAR_ETH + 0x084 */ 48 volatile uint32 r_hash; /* MBAR_ETH + 0x088 */ 49 volatile uint32 r_data; /* MBAR_ETH + 0x08C */ 50 volatile uint32 ar_done; /* MBAR_ETH + 0x090 */ 51 volatile uint32 r_test; /* MBAR_ETH + 0x094 */ 52 volatile uint32 r_mib; /* MBAR_ETH + 0x098 */ 53 volatile uint32 r_da_low; /* MBAR_ETH + 0x09C */ 54 volatile uint32 r_da_high; /* MBAR_ETH + 0x0A0 */ 55 56 volatile uint32 RES4[7]; /* MBAR_ETH + 0x0A4-0BC */ 57 volatile uint32 x_activate; /* MBAR_ETH + 0x0C0 */ 58 volatile uint32 x_cntrl; /* MBAR_ETH + 0x0C4 */ 59 volatile uint32 backoff; /* MBAR_ETH + 0x0C8 */ 60 volatile uint32 x_data; /* MBAR_ETH + 0x0CC */ 61 volatile uint32 x_status; /* MBAR_ETH + 0x0D0 */ 62 volatile uint32 x_mib; /* MBAR_ETH + 0x0D4 */ 63 volatile uint32 x_test; /* MBAR_ETH + 0x0D8 */ 64 volatile uint32 fdxfc_da1; /* MBAR_ETH + 0x0DC */ 65 volatile uint32 fdxfc_da2; /* MBAR_ETH + 0x0E0 */ 66 volatile uint32 paddr1; /* MBAR_ETH + 0x0E4 */ 67 volatile uint32 paddr2; /* MBAR_ETH + 0x0E8 */ 68 volatile uint32 op_pause; /* MBAR_ETH + 0x0EC */ 69 70 volatile uint32 RES5[4]; /* MBAR_ETH + 0x0F0-0FC */ 71 volatile uint32 instr_reg; /* MBAR_ETH + 0x100 */ 72 volatile uint32 context_reg; /* MBAR_ETH + 0x104 */ 73 volatile uint32 test_cntrl; /* MBAR_ETH + 0x108 */ 74 volatile uint32 acc_reg; /* MBAR_ETH + 0x10C */ 75 volatile uint32 ones; /* MBAR_ETH + 0x110 */ 76 volatile uint32 zeros; /* MBAR_ETH + 0x114 */ 77 volatile uint32 iaddr1; /* MBAR_ETH + 0x118 */ 78 volatile uint32 iaddr2; /* MBAR_ETH + 0x11C */ 79 volatile uint32 gaddr1; /* MBAR_ETH + 0x120 */ 80 volatile uint32 gaddr2; /* MBAR_ETH + 0x124 */ 81 volatile uint32 random; /* MBAR_ETH + 0x128 */ 82 volatile uint32 rand1; /* MBAR_ETH + 0x12C */ 83 volatile uint32 tmp; /* MBAR_ETH + 0x130 */ 84 85 volatile uint32 RES6[3]; /* MBAR_ETH + 0x134-13C */ 86 volatile uint32 fifo_id; /* MBAR_ETH + 0x140 */ 87 volatile uint32 x_wmrk; /* MBAR_ETH + 0x144 */ 88 volatile uint32 fcntrl; /* MBAR_ETH + 0x148 */ 89 volatile uint32 r_bound; /* MBAR_ETH + 0x14C */ 90 volatile uint32 r_fstart; /* MBAR_ETH + 0x150 */ 91 volatile uint32 r_count; /* MBAR_ETH + 0x154 */ 92 volatile uint32 r_lag; /* MBAR_ETH + 0x158 */ 93 volatile uint32 r_read; /* MBAR_ETH + 0x15C */ 94 volatile uint32 r_write; /* MBAR_ETH + 0x160 */ 95 volatile uint32 x_count; /* MBAR_ETH + 0x164 */ 96 volatile uint32 x_lag; /* MBAR_ETH + 0x168 */ 97 volatile uint32 x_retry; /* MBAR_ETH + 0x16C */ 98 volatile uint32 x_write; /* MBAR_ETH + 0x170 */ 99 volatile uint32 x_read; /* MBAR_ETH + 0x174 */ 100 101 volatile uint32 RES7[2]; /* MBAR_ETH + 0x178-17C */ 102 volatile uint32 fm_cntrl; /* MBAR_ETH + 0x180 */ 103 volatile uint32 rfifo_data; /* MBAR_ETH + 0x184 */ 104 volatile uint32 rfifo_status; /* MBAR_ETH + 0x188 */ 105 volatile uint32 rfifo_cntrl; /* MBAR_ETH + 0x18C */ 106 volatile uint32 rfifo_lrf_ptr; /* MBAR_ETH + 0x190 */ 107 volatile uint32 rfifo_lwf_ptr; /* MBAR_ETH + 0x194 */ 108 volatile uint32 rfifo_alarm; /* MBAR_ETH + 0x198 */ 109 volatile uint32 rfifo_rdptr; /* MBAR_ETH + 0x19C */ 110 volatile uint32 rfifo_wrptr; /* MBAR_ETH + 0x1A0 */ 111 volatile uint32 tfifo_data; /* MBAR_ETH + 0x1A4 */ 112 volatile uint32 tfifo_status; /* MBAR_ETH + 0x1A8 */ 113 volatile uint32 tfifo_cntrl; /* MBAR_ETH + 0x1AC */ 114 volatile uint32 tfifo_lrf_ptr; /* MBAR_ETH + 0x1B0 */ 115 volatile uint32 tfifo_lwf_ptr; /* MBAR_ETH + 0x1B4 */ 116 volatile uint32 tfifo_alarm; /* MBAR_ETH + 0x1B8 */ 117 volatile uint32 tfifo_rdptr; /* MBAR_ETH + 0x1BC */ 118 volatile uint32 tfifo_wrptr; /* MBAR_ETH + 0x1C0 */ 119 120 volatile uint32 reset_cntrl; /* MBAR_ETH + 0x1C4 */ 121 volatile uint32 xmit_fsm; /* MBAR_ETH + 0x1C8 */ 122 123 volatile uint32 RES8[3]; /* MBAR_ETH + 0x1CC-1D4 */ 124 volatile uint32 rdes_data0; /* MBAR_ETH + 0x1D8 */ 125 volatile uint32 rdes_data1; /* MBAR_ETH + 0x1DC */ 126 volatile uint32 r_length; /* MBAR_ETH + 0x1E0 */ 127 volatile uint32 x_length; /* MBAR_ETH + 0x1E4 */ 128 volatile uint32 x_addr; /* MBAR_ETH + 0x1E8 */ 129 volatile uint32 cdes_data; /* MBAR_ETH + 0x1EC */ 130 volatile uint32 status; /* MBAR_ETH + 0x1F0 */ 131 volatile uint32 dma_control; /* MBAR_ETH + 0x1F4 */ 132 volatile uint32 des_cmnd; /* MBAR_ETH + 0x1F8 */ 133 volatile uint32 data; /* MBAR_ETH + 0x1FC */ 134 135 /* MIB COUNTERS (Offset 200-2FF) */ 136 137 volatile uint32 rmon_t_drop; /* MBAR_ETH + 0x200 */ 138 volatile uint32 rmon_t_packets; /* MBAR_ETH + 0x204 */ 139 volatile uint32 rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */ 140 volatile uint32 rmon_t_mc_pkt; /* MBAR_ETH + 0x20C */ 141 volatile uint32 rmon_t_crc_align; /* MBAR_ETH + 0x210 */ 142 volatile uint32 rmon_t_undersize; /* MBAR_ETH + 0x214 */ 143 volatile uint32 rmon_t_oversize; /* MBAR_ETH + 0x218 */ 144 volatile uint32 rmon_t_frag; /* MBAR_ETH + 0x21C */ 145 volatile uint32 rmon_t_jab; /* MBAR_ETH + 0x220 */ 146 volatile uint32 rmon_t_col; /* MBAR_ETH + 0x224 */ 147 volatile uint32 rmon_t_p64; /* MBAR_ETH + 0x228 */ 148 volatile uint32 rmon_t_p65to127; /* MBAR_ETH + 0x22C */ 149 volatile uint32 rmon_t_p128to255; /* MBAR_ETH + 0x230 */ 150 volatile uint32 rmon_t_p256to511; /* MBAR_ETH + 0x234 */ 151 volatile uint32 rmon_t_p512to1023; /* MBAR_ETH + 0x238 */ 152 volatile uint32 rmon_t_p1024to2047; /* MBAR_ETH + 0x23C */ 153 volatile uint32 rmon_t_p_gte2048; /* MBAR_ETH + 0x240 */ 154 volatile uint32 rmon_t_octets; /* MBAR_ETH + 0x244 */ 155 volatile uint32 ieee_t_drop; /* MBAR_ETH + 0x248 */ 156 volatile uint32 ieee_t_frame_ok; /* MBAR_ETH + 0x24C */ 157 volatile uint32 ieee_t_1col; /* MBAR_ETH + 0x250 */ 158 volatile uint32 ieee_t_mcol; /* MBAR_ETH + 0x254 */ 159 volatile uint32 ieee_t_def; /* MBAR_ETH + 0x258 */ 160 volatile uint32 ieee_t_lcol; /* MBAR_ETH + 0x25C */ 161 volatile uint32 ieee_t_excol; /* MBAR_ETH + 0x260 */ 162 volatile uint32 ieee_t_macerr; /* MBAR_ETH + 0x264 */ 163 volatile uint32 ieee_t_cserr; /* MBAR_ETH + 0x268 */ 164 volatile uint32 ieee_t_sqe; /* MBAR_ETH + 0x26C */ 165 volatile uint32 t_fdxfc; /* MBAR_ETH + 0x270 */ 166 volatile uint32 ieee_t_octets_ok; /* MBAR_ETH + 0x274 */ 167 168 volatile uint32 RES9[2]; /* MBAR_ETH + 0x278-27C */ 169 volatile uint32 rmon_r_drop; /* MBAR_ETH + 0x280 */ 170 volatile uint32 rmon_r_packets; /* MBAR_ETH + 0x284 */ 171 volatile uint32 rmon_r_bc_pkt; /* MBAR_ETH + 0x288 */ 172 volatile uint32 rmon_r_mc_pkt; /* MBAR_ETH + 0x28C */ 173 volatile uint32 rmon_r_crc_align; /* MBAR_ETH + 0x290 */ 174 volatile uint32 rmon_r_undersize; /* MBAR_ETH + 0x294 */ 175 volatile uint32 rmon_r_oversize; /* MBAR_ETH + 0x298 */ 176 volatile uint32 rmon_r_frag; /* MBAR_ETH + 0x29C */ 177 volatile uint32 rmon_r_jab; /* MBAR_ETH + 0x2A0 */ 178 179 volatile uint32 rmon_r_resvd_0; /* MBAR_ETH + 0x2A4 */ 180 181 volatile uint32 rmon_r_p64; /* MBAR_ETH + 0x2A8 */ 182 volatile uint32 rmon_r_p65to127; /* MBAR_ETH + 0x2AC */ 183 volatile uint32 rmon_r_p128to255; /* MBAR_ETH + 0x2B0 */ 184 volatile uint32 rmon_r_p256to511; /* MBAR_ETH + 0x2B4 */ 185 volatile uint32 rmon_r_p512to1023; /* MBAR_ETH + 0x2B8 */ 186 volatile uint32 rmon_r_p1024to2047; /* MBAR_ETH + 0x2BC */ 187 volatile uint32 rmon_r_p_gte2048; /* MBAR_ETH + 0x2C0 */ 188 volatile uint32 rmon_r_octets; /* MBAR_ETH + 0x2C4 */ 189 volatile uint32 ieee_r_drop; /* MBAR_ETH + 0x2C8 */ 190 volatile uint32 ieee_r_frame_ok; /* MBAR_ETH + 0x2CC */ 191 volatile uint32 ieee_r_crc; /* MBAR_ETH + 0x2D0 */ 192 volatile uint32 ieee_r_align; /* MBAR_ETH + 0x2D4 */ 193 volatile uint32 r_macerr; /* MBAR_ETH + 0x2D8 */ 194 volatile uint32 r_fdxfc; /* MBAR_ETH + 0x2DC */ 195 volatile uint32 ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */ 196 197 volatile uint32 RES10[6]; /* MBAR_ETH + 0x2E4-2FC */ 198 199 volatile uint32 RES11[64]; /* MBAR_ETH + 0x300-3FF */ 200 } ethernet_regs; 201 202 /* Receive & Transmit Buffer Descriptor definitions */ 203 typedef struct BufferDescriptor { 204 uint16 status; 205 uint16 dataLength; 206 uint32 dataPointer; 207 } FEC_RBD; 208 typedef struct { 209 uint16 status; 210 uint16 dataLength; 211 uint32 dataPointer; 212 } FEC_TBD; 213 214 /* private structure */ 215 typedef enum { 216 SEVENWIRE, /* 7-wire */ 217 MII10, /* MII 10Mbps */ 218 MII100 /* MII 100Mbps */ 219 } xceiver_type; 220 221 typedef struct { 222 ethernet_regs *eth; 223 xceiver_type xcv_type; /* transceiver type */ 224 FEC_RBD *rbdBase; /* RBD ring */ 225 FEC_TBD *tbdBase; /* TBD ring */ 226 uint16 rbdIndex; /* next receive BD to read */ 227 uint16 tbdIndex; /* next transmit BD to send */ 228 uint16 usedTbdIndex; /* next transmit BD to clean */ 229 uint16 cleanTbdNum; /* the number of available transmit BDs */ 230 } mpc5xxx_fec_priv; 231 232 /* Ethernet parameter area */ 233 #define FEC_TBD_BASE (FEC_PARAM_BASE + 0x00) 234 #define FEC_TBD_NEXT (FEC_PARAM_BASE + 0x04) 235 #define FEC_RBD_BASE (FEC_PARAM_BASE + 0x08) 236 #define FEC_RBD_NEXT (FEC_PARAM_BASE + 0x0c) 237 238 /* BD Numer definitions */ 239 #define FEC_TBD_NUM 48 /* The user can adjust this value */ 240 #define FEC_RBD_NUM 32 /* The user can adjust this value */ 241 242 /* packet size limit */ 243 #define FEC_MAX_PKT_SIZE 1536 244 245 /* RBD bits definitions */ 246 #define FEC_RBD_EMPTY 0x8000 /* Buffer is empty */ 247 #define FEC_RBD_WRAP 0x2000 /* Last BD in ring */ 248 #define FEC_RBD_INT 0x1000 /* Interrupt */ 249 #define FEC_RBD_LAST 0x0800 /* Buffer is last in frame(useless) */ 250 #define FEC_RBD_MISS 0x0100 /* Miss bit for prom mode */ 251 #define FEC_RBD_BC 0x0080 /* The received frame is broadcast frame */ 252 #define FEC_RBD_MC 0x0040 /* The received frame is multicast frame */ 253 #define FEC_RBD_LG 0x0020 /* Frame length violation */ 254 #define FEC_RBD_NO 0x0010 /* Nonoctet align frame */ 255 #define FEC_RBD_SH 0x0008 /* Short frame */ 256 #define FEC_RBD_CR 0x0004 /* CRC error */ 257 #define FEC_RBD_OV 0x0002 /* Receive FIFO overrun */ 258 #define FEC_RBD_TR 0x0001 /* Frame is truncated */ 259 #define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \ 260 FEC_RBD_OV | FEC_RBD_TR) 261 262 /* TBD bits definitions */ 263 #define FEC_TBD_READY 0x8000 /* Buffer is ready */ 264 #define FEC_TBD_WRAP 0x2000 /* Last BD in ring */ 265 #define FEC_TBD_INT 0x1000 /* Interrupt */ 266 #define FEC_TBD_LAST 0x0800 /* Buffer is last in frame */ 267 #define FEC_TBD_TC 0x0400 /* Transmit the CRC */ 268 #define FEC_TBD_ABC 0x0200 /* Append bad CRC */ 269 270 /* MII-related definitios */ 271 #define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */ 272 #define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */ 273 #define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */ 274 #define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */ 275 #define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */ 276 #define FEC_MII_DATA_TA 0x00020000 /* Turnaround */ 277 #define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */ 278 279 #define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */ 280 #define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */ 281 282 #endif /* __MPC5XXX_FEC_H */ 283