1 /* 2 * MPC8xx Communication Processor Module. 3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 4 * 5 * (C) Copyright 2000-2006 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7 * 8 * This file contains structures and information for the communication 9 * processor channels. Some CPM control and status is available 10 * throught the MPC8xx internal memory map. See immap.h for details. 11 * This file only contains what I need for the moment, not the total 12 * CPM capabilities. I (or someone else) will add definitions as they 13 * are needed. -- Dan 14 * 15 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512 16 * bytes of the DP RAM and relocates the I2C parameter area to the 17 * IDMA1 space. The remaining DP RAM is available for buffer descriptors 18 * or other use. 19 */ 20 #ifndef __CPM_8XX__ 21 #define __CPM_8XX__ 22 23 #include <linux/config.h> 24 #include <asm/8xx_immap.h> 25 26 /* CPM Command register. 27 */ 28 #define CPM_CR_RST ((ushort)0x8000) 29 #define CPM_CR_OPCODE ((ushort)0x0f00) 30 #define CPM_CR_CHAN ((ushort)0x00f0) 31 #define CPM_CR_FLG ((ushort)0x0001) 32 33 /* Some commands (there are more...later) 34 */ 35 #define CPM_CR_INIT_TRX ((ushort)0x0000) 36 #define CPM_CR_INIT_RX ((ushort)0x0001) 37 #define CPM_CR_INIT_TX ((ushort)0x0002) 38 #define CPM_CR_HUNT_MODE ((ushort)0x0003) 39 #define CPM_CR_STOP_TX ((ushort)0x0004) 40 #define CPM_CR_RESTART_TX ((ushort)0x0006) 41 #define CPM_CR_SET_GADDR ((ushort)0x0008) 42 43 /* Channel numbers. 44 */ 45 #define CPM_CR_CH_SCC1 ((ushort)0x0000) 46 #define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */ 47 #define CPM_CR_CH_SCC2 ((ushort)0x0004) 48 #define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI/IDMA2/Timers */ 49 #define CPM_CR_CH_SCC3 ((ushort)0x0008) 50 #define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */ 51 #define CPM_CR_CH_SCC4 ((ushort)0x000c) 52 #define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */ 53 54 #define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) 55 56 /* 57 * DPRAM defines and allocation functions 58 */ 59 60 /* The dual ported RAM is multi-functional. Some areas can be (and are 61 * being) used for microcode. There is an area that can only be used 62 * as data ram for buffer descriptors, which is all we use right now. 63 * Currently the first 512 and last 256 bytes are used for microcode. 64 */ 65 #ifdef CONFIG_SYS_ALLOC_DPRAM 66 67 #define CPM_DATAONLY_BASE ((uint)0x0800) 68 #define CPM_DATAONLY_SIZE ((uint)0x0700) 69 #define CPM_DP_NOSPACE ((uint)0x7fffffff) 70 71 #else 72 73 #define CPM_SERIAL_BASE 0x0800 74 #define CPM_I2C_BASE 0x0820 75 #define CPM_SPI_BASE 0x0840 76 #define CPM_FEC_BASE 0x0860 77 #define CPM_SERIAL2_BASE 0x08E0 78 #define CPM_SCC_BASE 0x0900 79 #define CPM_POST_BASE 0x0980 80 #define CPM_WLKBD_BASE 0x0a00 81 82 #endif 83 84 #ifndef CONFIG_SYS_CPM_POST_WORD_ADDR 85 #define CPM_POST_WORD_ADDR 0x07FC 86 #else 87 #define CPM_POST_WORD_ADDR CONFIG_SYS_CPM_POST_WORD_ADDR 88 #endif 89 90 #ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR 91 #define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong)) 92 #else 93 #define CPM_BOOTCOUNT_ADDR CONFIG_SYS_CPM_BOOTCOUNT_ADDR 94 #endif 95 96 #define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */ 97 98 /* Export the base address of the communication processor registers 99 * and dual port ram. 100 */ 101 extern cpm8xx_t *cpmp; /* Pointer to comm processor */ 102 103 /* Buffer descriptors used by many of the CPM protocols. 104 */ 105 typedef struct cpm_buf_desc { 106 ushort cbd_sc; /* Status and Control */ 107 ushort cbd_datlen; /* Data length in buffer */ 108 uint cbd_bufaddr; /* Buffer address in host memory */ 109 } cbd_t; 110 111 #define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ 112 #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ 113 #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ 114 #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ 115 #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ 116 #define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ 117 #define BD_SC_CM ((ushort)0x0200) /* Continous mode */ 118 #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ 119 #define BD_SC_P ((ushort)0x0100) /* xmt preamble */ 120 #define BD_SC_BR ((ushort)0x0020) /* Break received */ 121 #define BD_SC_FR ((ushort)0x0010) /* Framing error */ 122 #define BD_SC_PR ((ushort)0x0008) /* Parity error */ 123 #define BD_SC_OV ((ushort)0x0002) /* Overrun */ 124 #define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */ 125 126 /* Parameter RAM offsets. 127 */ 128 #define PROFF_SCC1 ((uint)0x0000) 129 #define PROFF_IIC ((uint)0x0080) 130 #define PROFF_SCC2 ((uint)0x0100) 131 #define PROFF_SPI ((uint)0x0180) 132 #define PROFF_SCC3 ((uint)0x0200) 133 #define PROFF_SMC1 ((uint)0x0280) 134 #define PROFF_SCC4 ((uint)0x0300) 135 #define PROFF_SMC2 ((uint)0x0380) 136 137 /* Define enough so I can at least use the serial port as a UART. 138 * The MBX uses SMC1 as the host serial port. 139 */ 140 typedef struct smc_uart { 141 ushort smc_rbase; /* Rx Buffer descriptor base address */ 142 ushort smc_tbase; /* Tx Buffer descriptor base address */ 143 u_char smc_rfcr; /* Rx function code */ 144 u_char smc_tfcr; /* Tx function code */ 145 ushort smc_mrblr; /* Max receive buffer length */ 146 uint smc_rstate; /* Internal */ 147 uint smc_idp; /* Internal */ 148 ushort smc_rbptr; /* Internal */ 149 ushort smc_ibc; /* Internal */ 150 uint smc_rxtmp; /* Internal */ 151 uint smc_tstate; /* Internal */ 152 uint smc_tdp; /* Internal */ 153 ushort smc_tbptr; /* Internal */ 154 ushort smc_tbc; /* Internal */ 155 uint smc_txtmp; /* Internal */ 156 ushort smc_maxidl; /* Maximum idle characters */ 157 ushort smc_tmpidl; /* Temporary idle counter */ 158 ushort smc_brklen; /* Last received break length */ 159 ushort smc_brkec; /* rcv'd break condition counter */ 160 ushort smc_brkcr; /* xmt break count register */ 161 ushort smc_rmask; /* Temporary bit mask */ 162 u_char res1[8]; 163 ushort smc_rpbase; /* Relocation pointer */ 164 } smc_uart_t; 165 166 /* Function code bits. 167 */ 168 #define SMC_EB ((u_char)0x10) /* Set big endian byte order */ 169 170 /* SMC uart mode register. 171 */ 172 #define SMCMR_REN ((ushort)0x0001) 173 #define SMCMR_TEN ((ushort)0x0002) 174 #define SMCMR_DM ((ushort)0x000c) 175 #define SMCMR_SM_GCI ((ushort)0x0000) 176 #define SMCMR_SM_UART ((ushort)0x0020) 177 #define SMCMR_SM_TRANS ((ushort)0x0030) 178 #define SMCMR_SM_MASK ((ushort)0x0030) 179 #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ 180 #define SMCMR_REVD SMCMR_PM_EVEN 181 #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ 182 #define SMCMR_BS SMCMR_PEN 183 #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ 184 #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ 185 #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) 186 187 /* SMC2 as Centronics parallel printer. It is half duplex, in that 188 * it can only receive or transmit. The parameter ram values for 189 * each direction are either unique or properly overlap, so we can 190 * include them in one structure. 191 */ 192 typedef struct smc_centronics { 193 ushort scent_rbase; 194 ushort scent_tbase; 195 u_char scent_cfcr; 196 u_char scent_smask; 197 ushort scent_mrblr; 198 uint scent_rstate; 199 uint scent_r_ptr; 200 ushort scent_rbptr; 201 ushort scent_r_cnt; 202 uint scent_rtemp; 203 uint scent_tstate; 204 uint scent_t_ptr; 205 ushort scent_tbptr; 206 ushort scent_t_cnt; 207 uint scent_ttemp; 208 ushort scent_max_sl; 209 ushort scent_sl_cnt; 210 ushort scent_character1; 211 ushort scent_character2; 212 ushort scent_character3; 213 ushort scent_character4; 214 ushort scent_character5; 215 ushort scent_character6; 216 ushort scent_character7; 217 ushort scent_character8; 218 ushort scent_rccm; 219 ushort scent_rccr; 220 } smc_cent_t; 221 222 /* Centronics Status Mask Register. 223 */ 224 #define SMC_CENT_F ((u_char)0x08) 225 #define SMC_CENT_PE ((u_char)0x04) 226 #define SMC_CENT_S ((u_char)0x02) 227 228 /* SMC Event and Mask register. 229 */ 230 #define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ 231 #define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ 232 #define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */ 233 #define SMCM_BSY ((unsigned char)0x04) 234 #define SMCM_TX ((unsigned char)0x02) 235 #define SMCM_RX ((unsigned char)0x01) 236 237 /* Baud rate generators. 238 */ 239 #define CPM_BRG_RST ((uint)0x00020000) 240 #define CPM_BRG_EN ((uint)0x00010000) 241 #define CPM_BRG_EXTC_INT ((uint)0x00000000) 242 #define CPM_BRG_EXTC_CLK2 ((uint)0x00004000) 243 #define CPM_BRG_EXTC_CLK6 ((uint)0x00008000) 244 #define CPM_BRG_ATB ((uint)0x00002000) 245 #define CPM_BRG_CD_MASK ((uint)0x00001ffe) 246 #define CPM_BRG_DIV16 ((uint)0x00000001) 247 248 /* SI Clock Route Register 249 */ 250 #define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000) 251 #define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000) 252 #define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800) 253 #define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100) 254 #define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000) 255 #define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000) 256 #define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000) 257 #define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000) 258 259 /* SCCs. 260 */ 261 #define SCC_GSMRH_IRP ((uint)0x00040000) 262 #define SCC_GSMRH_GDE ((uint)0x00010000) 263 #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) 264 #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) 265 #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) 266 #define SCC_GSMRH_REVD ((uint)0x00002000) 267 #define SCC_GSMRH_TRX ((uint)0x00001000) 268 #define SCC_GSMRH_TTX ((uint)0x00000800) 269 #define SCC_GSMRH_CDP ((uint)0x00000400) 270 #define SCC_GSMRH_CTSP ((uint)0x00000200) 271 #define SCC_GSMRH_CDS ((uint)0x00000100) 272 #define SCC_GSMRH_CTSS ((uint)0x00000080) 273 #define SCC_GSMRH_TFL ((uint)0x00000040) 274 #define SCC_GSMRH_RFW ((uint)0x00000020) 275 #define SCC_GSMRH_TXSY ((uint)0x00000010) 276 #define SCC_GSMRH_SYNL16 ((uint)0x0000000c) 277 #define SCC_GSMRH_SYNL8 ((uint)0x00000008) 278 #define SCC_GSMRH_SYNL4 ((uint)0x00000004) 279 #define SCC_GSMRH_RTSM ((uint)0x00000002) 280 #define SCC_GSMRH_RSYN ((uint)0x00000001) 281 282 #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ 283 #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) 284 #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) 285 #define SCC_GSMRL_EDGE_POS ((uint)0x20000000) 286 #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) 287 #define SCC_GSMRL_TCI ((uint)0x10000000) 288 #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) 289 #define SCC_GSMRL_TSNC_4 ((uint)0x08000000) 290 #define SCC_GSMRL_TSNC_14 ((uint)0x04000000) 291 #define SCC_GSMRL_TSNC_INF ((uint)0x00000000) 292 #define SCC_GSMRL_RINV ((uint)0x02000000) 293 #define SCC_GSMRL_TINV ((uint)0x01000000) 294 #define SCC_GSMRL_TPL_128 ((uint)0x00c00000) 295 #define SCC_GSMRL_TPL_64 ((uint)0x00a00000) 296 #define SCC_GSMRL_TPL_48 ((uint)0x00800000) 297 #define SCC_GSMRL_TPL_32 ((uint)0x00600000) 298 #define SCC_GSMRL_TPL_16 ((uint)0x00400000) 299 #define SCC_GSMRL_TPL_8 ((uint)0x00200000) 300 #define SCC_GSMRL_TPL_NONE ((uint)0x00000000) 301 #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) 302 #define SCC_GSMRL_TPP_01 ((uint)0x00100000) 303 #define SCC_GSMRL_TPP_10 ((uint)0x00080000) 304 #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) 305 #define SCC_GSMRL_TEND ((uint)0x00040000) 306 #define SCC_GSMRL_TDCR_32 ((uint)0x00030000) 307 #define SCC_GSMRL_TDCR_16 ((uint)0x00020000) 308 #define SCC_GSMRL_TDCR_8 ((uint)0x00010000) 309 #define SCC_GSMRL_TDCR_1 ((uint)0x00000000) 310 #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) 311 #define SCC_GSMRL_RDCR_16 ((uint)0x00008000) 312 #define SCC_GSMRL_RDCR_8 ((uint)0x00004000) 313 #define SCC_GSMRL_RDCR_1 ((uint)0x00000000) 314 #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) 315 #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) 316 #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) 317 #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) 318 #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) 319 #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) 320 #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) 321 #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) 322 #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) 323 #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) 324 #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ 325 #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) 326 #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) 327 #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) 328 #define SCC_GSMRL_ENR ((uint)0x00000020) 329 #define SCC_GSMRL_ENT ((uint)0x00000010) 330 #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) 331 #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) 332 #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) 333 #define SCC_GSMRL_MODE_V14 ((uint)0x00000007) 334 #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) 335 #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) 336 #define SCC_GSMRL_MODE_UART ((uint)0x00000004) 337 #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) 338 #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) 339 #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) 340 341 #define SCC_TODR_TOD ((ushort)0x8000) 342 343 /* SCC Event and Mask register. 344 */ 345 #define SCCM_TXE ((unsigned char)0x10) 346 #define SCCM_BSY ((unsigned char)0x04) 347 #define SCCM_TX ((unsigned char)0x02) 348 #define SCCM_RX ((unsigned char)0x01) 349 350 typedef struct scc_param { 351 ushort scc_rbase; /* Rx Buffer descriptor base address */ 352 ushort scc_tbase; /* Tx Buffer descriptor base address */ 353 u_char scc_rfcr; /* Rx function code */ 354 u_char scc_tfcr; /* Tx function code */ 355 ushort scc_mrblr; /* Max receive buffer length */ 356 uint scc_rstate; /* Internal */ 357 uint scc_idp; /* Internal */ 358 ushort scc_rbptr; /* Internal */ 359 ushort scc_ibc; /* Internal */ 360 uint scc_rxtmp; /* Internal */ 361 uint scc_tstate; /* Internal */ 362 uint scc_tdp; /* Internal */ 363 ushort scc_tbptr; /* Internal */ 364 ushort scc_tbc; /* Internal */ 365 uint scc_txtmp; /* Internal */ 366 uint scc_rcrc; /* Internal */ 367 uint scc_tcrc; /* Internal */ 368 } sccp_t; 369 370 /* Function code bits. 371 */ 372 #define SCC_EB ((u_char)0x10) /* Set big endian byte order */ 373 374 /* CPM Ethernet through SCCx. 375 */ 376 typedef struct scc_enet { 377 sccp_t sen_genscc; 378 uint sen_cpres; /* Preset CRC */ 379 uint sen_cmask; /* Constant mask for CRC */ 380 uint sen_crcec; /* CRC Error counter */ 381 uint sen_alec; /* alignment error counter */ 382 uint sen_disfc; /* discard frame counter */ 383 ushort sen_pads; /* Tx short frame pad character */ 384 ushort sen_retlim; /* Retry limit threshold */ 385 ushort sen_retcnt; /* Retry limit counter */ 386 ushort sen_maxflr; /* maximum frame length register */ 387 ushort sen_minflr; /* minimum frame length register */ 388 ushort sen_maxd1; /* maximum DMA1 length */ 389 ushort sen_maxd2; /* maximum DMA2 length */ 390 ushort sen_maxd; /* Rx max DMA */ 391 ushort sen_dmacnt; /* Rx DMA counter */ 392 ushort sen_maxb; /* Max BD byte count */ 393 ushort sen_gaddr1; /* Group address filter */ 394 ushort sen_gaddr2; 395 ushort sen_gaddr3; 396 ushort sen_gaddr4; 397 uint sen_tbuf0data0; /* Save area 0 - current frame */ 398 uint sen_tbuf0data1; /* Save area 1 - current frame */ 399 uint sen_tbuf0rba; /* Internal */ 400 uint sen_tbuf0crc; /* Internal */ 401 ushort sen_tbuf0bcnt; /* Internal */ 402 ushort sen_paddrh; /* physical address (MSB) */ 403 ushort sen_paddrm; 404 ushort sen_paddrl; /* physical address (LSB) */ 405 ushort sen_pper; /* persistence */ 406 ushort sen_rfbdptr; /* Rx first BD pointer */ 407 ushort sen_tfbdptr; /* Tx first BD pointer */ 408 ushort sen_tlbdptr; /* Tx last BD pointer */ 409 uint sen_tbuf1data0; /* Save area 0 - current frame */ 410 uint sen_tbuf1data1; /* Save area 1 - current frame */ 411 uint sen_tbuf1rba; /* Internal */ 412 uint sen_tbuf1crc; /* Internal */ 413 ushort sen_tbuf1bcnt; /* Internal */ 414 ushort sen_txlen; /* Tx Frame length counter */ 415 ushort sen_iaddr1; /* Individual address filter */ 416 ushort sen_iaddr2; 417 ushort sen_iaddr3; 418 ushort sen_iaddr4; 419 ushort sen_boffcnt; /* Backoff counter */ 420 421 /* NOTE: Some versions of the manual have the following items 422 * incorrectly documented. Below is the proper order. 423 */ 424 ushort sen_taddrh; /* temp address (MSB) */ 425 ushort sen_taddrm; 426 ushort sen_taddrl; /* temp address (LSB) */ 427 } scc_enet_t; 428 429 /********************************************************************** 430 * 431 * Board specific configuration settings. 432 * 433 * Please note that we use the presence of a #define SCC_ENET and/or 434 * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers. 435 **********************************************************************/ 436 437 438 /*** ADS *************************************************************/ 439 440 #if defined(CONFIG_MPC860) && defined(CONFIG_ADS) 441 /* This ENET stuff is for the MPC860ADS with ethernet on SCC1. 442 */ 443 444 #define PROFF_ENET PROFF_SCC1 445 #define CPM_CR_ENET CPM_CR_CH_SCC1 446 #define SCC_ENET 0 447 448 #define PA_ENET_RXD ((ushort)0x0001) 449 #define PA_ENET_TXD ((ushort)0x0002) 450 #define PA_ENET_TCLK ((ushort)0x0100) 451 #define PA_ENET_RCLK ((ushort)0x0200) 452 453 #define PB_ENET_TENA ((uint)0x00001000) 454 455 #define PC_ENET_CLSN ((ushort)0x0010) 456 #define PC_ENET_RENA ((ushort)0x0020) 457 458 #define SICR_ENET_MASK ((uint)0x000000ff) 459 #define SICR_ENET_CLKRT ((uint)0x0000002c) 460 461 /* 68160 PHY control */ 462 463 #define PC_ENET_ETHLOOP ((ushort)0x0800) 464 #define PC_ENET_TPFLDL ((ushort)0x0400) 465 #define PC_ENET_TPSQEL ((ushort)0x0200) 466 467 #endif /* MPC860ADS */ 468 469 /*** AMX860 **********************************************/ 470 471 #if defined(CONFIG_AMX860) 472 473 /* This ENET stuff is for the AMX860 with ethernet on SCC1. 474 */ 475 476 #define PROFF_ENET PROFF_SCC1 477 #define CPM_CR_ENET CPM_CR_CH_SCC1 478 #define SCC_ENET 0 479 480 #define PA_ENET_RXD ((ushort)0x0001) 481 #define PA_ENET_TXD ((ushort)0x0002) 482 #define PA_ENET_TCLK ((ushort)0x0400) 483 #define PA_ENET_RCLK ((ushort)0x0800) 484 485 #define PB_ENET_TENA ((uint)0x00001000) 486 487 #define PC_ENET_CLSN ((ushort)0x0010) 488 #define PC_ENET_RENA ((ushort)0x0020) 489 490 #define SICR_ENET_MASK ((uint)0x000000ff) 491 #define SICR_ENET_CLKRT ((uint)0x0000003e) 492 493 /* 68160 PHY control */ 494 495 #define PB_ENET_ETHLOOP ((uint)0x00020000) 496 #define PB_ENET_TPFLDL ((uint)0x00010000) 497 #define PB_ENET_TPSQEL ((uint)0x00008000) 498 #define PD_ENET_ETH_EN ((ushort)0x0004) 499 500 #endif /* CONFIG_AMX860 */ 501 502 /*** BSEIP **********************************************************/ 503 504 #ifdef CONFIG_BSEIP 505 /* This ENET stuff is for the MPC823 with ethernet on SCC2. 506 * This is unique to the BSE ip-Engine board. 507 */ 508 #define PROFF_ENET PROFF_SCC2 509 #define CPM_CR_ENET CPM_CR_CH_SCC2 510 #define SCC_ENET 1 511 #define PA_ENET_RXD ((ushort)0x0004) 512 #define PA_ENET_TXD ((ushort)0x0008) 513 #define PA_ENET_TCLK ((ushort)0x0100) 514 #define PA_ENET_RCLK ((ushort)0x0200) 515 #define PB_ENET_TENA ((uint)0x00002000) 516 #define PC_ENET_CLSN ((ushort)0x0040) 517 #define PC_ENET_RENA ((ushort)0x0080) 518 519 /* BSE uses port B and C bits for PHY control also. 520 */ 521 #define PB_BSE_POWERUP ((uint)0x00000004) 522 #define PB_BSE_FDXDIS ((uint)0x00008000) 523 #define PC_BSE_LOOPBACK ((ushort)0x0800) 524 525 #define SICR_ENET_MASK ((uint)0x0000ff00) 526 #define SICR_ENET_CLKRT ((uint)0x00002c00) 527 #endif /* CONFIG_BSEIP */ 528 529 /*** BSEIP **********************************************************/ 530 531 #ifdef CONFIG_FLAGADM 532 /* Enet configuration for the FLAGADM */ 533 /* Enet on SCC2 */ 534 535 #define PROFF_ENET PROFF_SCC2 536 #define CPM_CR_ENET CPM_CR_CH_SCC2 537 #define SCC_ENET 1 538 #define PA_ENET_RXD ((ushort)0x0004) 539 #define PA_ENET_TXD ((ushort)0x0008) 540 #define PA_ENET_TCLK ((ushort)0x0100) 541 #define PA_ENET_RCLK ((ushort)0x0400) 542 #define PB_ENET_TENA ((uint)0x00002000) 543 #define PC_ENET_CLSN ((ushort)0x0040) 544 #define PC_ENET_RENA ((ushort)0x0080) 545 546 #define SICR_ENET_MASK ((uint)0x0000ff00) 547 #define SICR_ENET_CLKRT ((uint)0x00003400) 548 #endif /* CONFIG_FLAGADM */ 549 550 /*** C2MON **********************************************************/ 551 552 #ifdef CONFIG_C2MON 553 554 # ifndef CONFIG_FEC_ENET /* use SCC for 10Mbps Ethernet */ 555 # error "Ethernet on SCC not supported on C2MON Board!" 556 # else /* Use FEC for Fast Ethernet */ 557 558 #undef SCC_ENET 559 #define FEC_ENET 560 561 #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ 562 #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ 563 #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ 564 #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ 565 #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ 566 #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ 567 #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ 568 #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ 569 #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ 570 #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ 571 #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ 572 #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ 573 #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ 574 575 #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ 576 577 # endif /* CONFIG_FEC_ENET */ 578 #endif /* CONFIG_C2MON */ 579 580 /*********************************************************************/ 581 582 583 /*** CCM and PCU E ***********************************************/ 584 585 /* The PCU E and CCM use the FEC on a MPC860T for Ethernet */ 586 587 #if defined (CONFIG_PCU_E) || defined(CONFIG_CCM) 588 589 #define FEC_ENET /* use FEC for EThernet */ 590 #undef SCC_ENET 591 592 #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ 593 #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ 594 #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ 595 #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ 596 #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ 597 #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ 598 #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ 599 #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ 600 #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ 601 #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ 602 #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ 603 #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ 604 #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ 605 606 #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ 607 608 #endif /* CONFIG_PCU_E, CONFIG_CCM */ 609 610 /*** ELPT860 *********************************************************/ 611 612 #ifdef CONFIG_ELPT860 613 /* Bits in parallel I/O port registers that have to be set/cleared 614 * to configure the pins for SCC1 use. 615 */ 616 # define PROFF_ENET PROFF_SCC1 617 # define CPM_CR_ENET CPM_CR_CH_SCC1 618 # define SCC_ENET 0 619 620 # define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ 621 # define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ 622 # define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ 623 # define PA_ENET_TCLK ((ushort)0x0200) /* PA 6 */ 624 625 # define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ 626 # define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ 627 # define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ 628 629 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK1) to 630 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. 631 */ 632 # define SICR_ENET_MASK ((uint)0x000000FF) 633 # define SICR_ENET_CLKRT ((uint)0x00000025) 634 #endif /* CONFIG_ELPT860 */ 635 636 /*** ESTEEM 192E **************************************************/ 637 #ifdef CONFIG_ESTEEM192E 638 /* ESTEEM192E 639 * This ENET stuff is for the MPC850 with ethernet on SCC2. This 640 * is very similar to the RPX-Lite configuration. 641 * Note TENA , LOOPBACK , FDPLEX_DIS on Port B. 642 */ 643 644 #define PROFF_ENET PROFF_SCC2 645 #define CPM_CR_ENET CPM_CR_CH_SCC2 646 #define SCC_ENET 1 647 648 #define PA_ENET_RXD ((ushort)0x0004) 649 #define PA_ENET_TXD ((ushort)0x0008) 650 #define PA_ENET_TCLK ((ushort)0x0200) 651 #define PA_ENET_RCLK ((ushort)0x0800) 652 #define PB_ENET_TENA ((uint)0x00002000) 653 #define PC_ENET_CLSN ((ushort)0x0040) 654 #define PC_ENET_RENA ((ushort)0x0080) 655 656 #define SICR_ENET_MASK ((uint)0x0000ff00) 657 #define SICR_ENET_CLKRT ((uint)0x00003d00) 658 659 #define PB_ENET_LOOPBACK ((uint)0x00004000) 660 #define PB_ENET_FDPLEX_DIS ((uint)0x00008000) 661 662 #endif 663 664 /*** FADS823 ********************************************************/ 665 666 #if defined(CONFIG_MPC823FADS) && defined(CONFIG_FADS) 667 /* This ENET stuff is for the MPC823FADS with ethernet on SCC2. 668 */ 669 #ifdef CONFIG_SCC2_ENET 670 #define PROFF_ENET PROFF_SCC2 671 #define CPM_CR_ENET CPM_CR_CH_SCC2 672 #define SCC_ENET 1 673 #define CPMVEC_ENET CPMVEC_SCC2 674 #endif 675 676 #ifdef CONFIG_SCC1_ENET 677 #define PROFF_ENET PROFF_SCC1 678 #define CPM_CR_ENET CPM_CR_CH_SCC1 679 #define SCC_ENET 0 680 #define CPMVEC_ENET CPMVEC_SCC1 681 #endif 682 683 #define PA_ENET_RXD ((ushort)0x0004) 684 #define PA_ENET_TXD ((ushort)0x0008) 685 #define PA_ENET_TCLK ((ushort)0x0400) 686 #define PA_ENET_RCLK ((ushort)0x0200) 687 688 #define PB_ENET_TENA ((uint)0x00002000) 689 690 #define PC_ENET_CLSN ((ushort)0x0040) 691 #define PC_ENET_RENA ((ushort)0x0080) 692 693 #define SICR_ENET_MASK ((uint)0x0000ff00) 694 #define SICR_ENET_CLKRT ((uint)0x00002e00) 695 696 #endif /* CONFIG_FADS823FADS */ 697 698 /*** FADS850SAR ********************************************************/ 699 700 #if defined(CONFIG_MPC850SAR) && defined(CONFIG_FADS) 701 /* This ENET stuff is for the MPC850SAR with ethernet on SCC2. Some of 702 * this may be unique to the FADS850SAR configuration. 703 * Note TENA is on Port B. 704 */ 705 #define PROFF_ENET PROFF_SCC2 706 #define CPM_CR_ENET CPM_CR_CH_SCC2 707 #define SCC_ENET 1 708 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 709 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 710 #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ 711 #define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ 712 #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ 713 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 714 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 715 716 #define SICR_ENET_MASK ((uint)0x0000ff00) 717 #define SICR_ENET_CLKRT ((uint)0x00002f00) /* RCLK-CLK2, TCLK-CLK4 */ 718 #endif /* CONFIG_FADS850SAR */ 719 720 /*** FADS860T********************************************************/ 721 722 #if defined(CONFIG_FADS) && defined(CONFIG_MPC86x) 723 /* 724 * This ENET stuff is for the MPC86xFADS/MPC8xxADS with ethernet on SCC1. 725 */ 726 #ifdef CONFIG_SCC1_ENET 727 728 #define SCC_ENET 0 729 730 #define PROFF_ENET PROFF_SCC1 731 #define CPM_CR_ENET CPM_CR_CH_SCC1 732 733 #define PA_ENET_RXD ((ushort)0x0001) 734 #define PA_ENET_TXD ((ushort)0x0002) 735 #define PA_ENET_TCLK ((ushort)0x0100) 736 #define PA_ENET_RCLK ((ushort)0x0200) 737 738 #define PB_ENET_TENA ((uint)0x00001000) 739 740 #define PC_ENET_CLSN ((ushort)0x0010) 741 #define PC_ENET_RENA ((ushort)0x0020) 742 743 #define SICR_ENET_MASK ((uint)0x000000ff) 744 #define SICR_ENET_CLKRT ((uint)0x0000002c) 745 746 #endif /* CONFIG_SCC1_ETHERNET */ 747 748 /* 749 * This ENET stuff is for the MPC860TFADS/MPC86xADS/MPC885ADS 750 * with ethernet on FEC. 751 */ 752 753 #ifdef CONFIG_FEC_ENET 754 #define FEC_ENET /* Use FEC for Ethernet */ 755 #endif /* CONFIG_FEC_ENET */ 756 757 #endif /* CONFIG_FADS && CONFIG_MPC86x */ 758 759 /*** FPS850L, FPS860L ************************************************/ 760 761 #if defined(CONFIG_FPS850L) || defined(CONFIG_FPS860L) 762 /* Bits in parallel I/O port registers that have to be set/cleared 763 * to configure the pins for SCC2 use. 764 */ 765 #define PROFF_ENET PROFF_SCC2 766 #define CPM_CR_ENET CPM_CR_CH_SCC2 767 #define SCC_ENET 1 768 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 769 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 770 #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ 771 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ 772 773 #define PC_ENET_TENA ((ushort)0x0002) /* PC 14 */ 774 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 775 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 776 777 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to 778 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. 779 */ 780 #define SICR_ENET_MASK ((uint)0x0000ff00) 781 #define SICR_ENET_CLKRT ((uint)0x00002600) 782 #endif /* CONFIG_FPS850L, CONFIG_FPS860L */ 783 784 /*** GEN860T **********************************************************/ 785 #if defined(CONFIG_GEN860T) 786 #undef SCC_ENET 787 #define FEC_ENET 788 789 #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ 790 #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ 791 #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ 792 #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ 793 #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ 794 #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ 795 #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ 796 #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ 797 #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ 798 #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ 799 #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ 800 #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ 801 #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ 802 #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3-15 */ 803 #endif /* CONFIG_GEN860T */ 804 805 /*** GENIETV ********************************************************/ 806 807 #if defined(CONFIG_GENIETV) 808 /* Ethernet is only on SCC2 */ 809 810 #define CONFIG_SCC2_ENET 811 #define PROFF_ENET PROFF_SCC2 812 #define CPM_CR_ENET CPM_CR_CH_SCC2 813 #define SCC_ENET 1 814 #define CPMVEC_ENET CPMVEC_SCC2 815 816 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 817 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 818 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ 819 #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ 820 821 #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ 822 823 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 824 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 825 826 #define SICR_ENET_MASK ((uint)0x0000ff00) 827 #define SICR_ENET_CLKRT ((uint)0x00002e00) 828 829 #endif /* CONFIG_GENIETV */ 830 831 /*** GTH ******************************************************/ 832 833 #ifdef CONFIG_GTH 834 #ifdef CONFIG_FEC_ENET 835 #define FEC_ENET /* use FEC for EThernet */ 836 #endif /* CONFIG_FEC_ETHERNET */ 837 838 /* This ENET stuff is for GTH 10 Mbit ( SCC ) */ 839 #define PROFF_ENET PROFF_SCC1 840 #define CPM_CR_ENET CPM_CR_CH_SCC1 841 #define SCC_ENET 0 842 843 #define PA_ENET_RXD ((ushort)0x0001) /* PA15 */ 844 #define PA_ENET_TXD ((ushort)0x0002) /* PA14 */ 845 #define PA_ENET_TCLK ((ushort)0x0800) /* PA4 */ 846 #define PA_ENET_RCLK ((ushort)0x0400) /* PA5 */ 847 848 #define PB_ENET_TENA ((uint)0x00001000) /* PB19 */ 849 850 #define PC_ENET_CLSN ((ushort)0x0010) /* PC11 */ 851 #define PC_ENET_RENA ((ushort)0x0020) /* PC10 */ 852 853 /* NOTE. This is reset for 10Mbit port only */ 854 #define PC_ENET_RESET ((ushort)0x0100) /* PC 7 */ 855 856 #define SICR_ENET_MASK ((uint)0x000000ff) 857 858 /* TCLK PA4 -->CLK4, RCLK PA5 -->CLK3 */ 859 #define SICR_ENET_CLKRT ((uint)0x00000037) 860 861 #endif /* CONFIG_GTH */ 862 863 /*** HERMES-PRO ******************************************************/ 864 865 /* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */ 866 867 #ifdef CONFIG_HERMES 868 869 #define FEC_ENET /* use FEC for EThernet */ 870 #undef SCC_ENET 871 872 873 #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ 874 #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ 875 #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ 876 #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ 877 #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ 878 #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ 879 #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ 880 #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ 881 #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ 882 #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ 883 #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ 884 #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ 885 #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ 886 887 #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ 888 889 #endif /* CONFIG_HERMES */ 890 891 /*** IAD210 **********************************************************/ 892 893 /* The IAD210 uses the FEC on a MPC860P for Ethernet */ 894 895 #if defined(CONFIG_IAD210) 896 897 # define FEC_ENET /* use FEC for Ethernet */ 898 # undef SCC_ENET 899 900 # define PD_MII_TXD1 ((ushort) 0x1000 ) /* PD 3 */ 901 # define PD_MII_TXD2 ((ushort) 0x0800 ) /* PD 4 */ 902 # define PD_MII_TXD3 ((ushort) 0x0400 ) /* PD 5 */ 903 # define PD_MII_RX_DV ((ushort) 0x0200 ) /* PD 6 */ 904 # define PD_MII_RX_ERR ((ushort) 0x0100 ) /* PD 7 */ 905 # define PD_MII_RX_CLK ((ushort) 0x0080 ) /* PD 8 */ 906 # define PD_MII_TXD0 ((ushort) 0x0040 ) /* PD 9 */ 907 # define PD_MII_RXD0 ((ushort) 0x0020 ) /* PD 10 */ 908 # define PD_MII_TX_ERR ((ushort) 0x0010 ) /* PD 11 */ 909 # define PD_MII_MDC ((ushort) 0x0008 ) /* PD 12 */ 910 # define PD_MII_RXD1 ((ushort) 0x0004 ) /* PD 13 */ 911 # define PD_MII_RXD2 ((ushort) 0x0002 ) /* PD 14 */ 912 # define PD_MII_RXD3 ((ushort) 0x0001 ) /* PD 15 */ 913 914 # define PD_MII_MASK ((ushort) 0x1FFF ) /* PD 3...15 */ 915 916 #endif /* CONFIG_IAD210 */ 917 918 /*** ICU862 **********************************************************/ 919 920 #if defined(CONFIG_ICU862) 921 922 #ifdef CONFIG_FEC_ENET 923 #define FEC_ENET /* use FEC for EThernet */ 924 #endif /* CONFIG_FEC_ETHERNET */ 925 926 #endif /* CONFIG_ICU862 */ 927 928 /*** IP860 **********************************************************/ 929 930 #if defined(CONFIG_IP860) 931 /* Bits in parallel I/O port registers that have to be set/cleared 932 * to configure the pins for SCC1 use. 933 */ 934 #define PROFF_ENET PROFF_SCC1 935 #define CPM_CR_ENET CPM_CR_CH_SCC1 936 #define SCC_ENET 0 937 #define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ 938 #define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ 939 #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ 940 #define PA_ENET_TCLK ((ushort)0x0100) /* PA 7 */ 941 942 #define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ 943 #define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ 944 #define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ 945 946 #define PB_ENET_RESET (uint)0x00000008 /* PB 28 */ 947 #define PB_ENET_JABD (uint)0x00000004 /* PB 29 */ 948 949 /* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to 950 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. 951 */ 952 #define SICR_ENET_MASK ((uint)0x000000ff) 953 #define SICR_ENET_CLKRT ((uint)0x0000002C) 954 #endif /* CONFIG_IP860 */ 955 956 /*** IVMS8 **********************************************************/ 957 958 /* The IVMS8 uses the FEC on a MPC860T for Ethernet */ 959 960 #if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) 961 962 #define FEC_ENET /* use FEC for EThernet */ 963 #undef SCC_ENET 964 965 #define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */ 966 967 #define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */ 968 969 #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ 970 #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ 971 #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ 972 #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ 973 #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ 974 #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ 975 #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ 976 #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ 977 #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ 978 #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ 979 #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ 980 #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ 981 #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ 982 983 #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ 984 985 #endif /* CONFIG_IVMS8, CONFIG_IVML24 */ 986 987 /*** KUP4K, KUP4X ****************************************************/ 988 /* The KUP4 boards uses the FEC on a MPC8xx for Ethernet */ 989 990 #if defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) 991 992 #define FEC_ENET /* use FEC for EThernet */ 993 #undef SCC_ENET 994 995 #define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */ 996 997 #define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */ 998 999 #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ 1000 #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ 1001 #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ 1002 #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ 1003 #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ 1004 #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ 1005 #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ 1006 #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ 1007 #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ 1008 #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ 1009 #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ 1010 #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ 1011 #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ 1012 1013 #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ 1014 1015 #endif /* CONFIG_KUP4K */ 1016 1017 1018 /*** LANTEC *********************************************************/ 1019 1020 #if defined(CONFIG_LANTEC) && CONFIG_LANTEC >= 2 1021 /* Bits in parallel I/O port registers that have to be set/cleared 1022 * to configure the pins for SCC2 use. 1023 */ 1024 #define PROFF_ENET PROFF_SCC2 1025 #define CPM_CR_ENET CPM_CR_CH_SCC2 1026 #define SCC_ENET 1 1027 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 1028 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 1029 #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ 1030 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ 1031 1032 #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ 1033 1034 #define PC_ENET_LBK ((ushort)0x0010) /* PC 11 */ 1035 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 1036 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 1037 1038 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to 1039 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. 1040 */ 1041 #define SICR_ENET_MASK ((uint)0x0000FF00) 1042 #define SICR_ENET_CLKRT ((uint)0x00002E00) 1043 #endif /* CONFIG_LANTEC v2 */ 1044 1045 /*** LWMON **********************************************************/ 1046 1047 #if defined(CONFIG_LWMON) 1048 /* Bits in parallel I/O port registers that have to be set/cleared 1049 * to configure the pins for SCC2 use. 1050 */ 1051 #define PROFF_ENET PROFF_SCC2 1052 #define CPM_CR_ENET CPM_CR_CH_SCC2 1053 #define SCC_ENET 1 1054 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 1055 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 1056 #define PA_ENET_RCLK ((ushort)0x0800) /* PA 4 */ 1057 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ 1058 1059 #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ 1060 1061 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 1062 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 1063 1064 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK4) to 1065 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. 1066 */ 1067 #define SICR_ENET_MASK ((uint)0x0000ff00) 1068 #define SICR_ENET_CLKRT ((uint)0x00003E00) 1069 #endif /* CONFIG_LWMON */ 1070 1071 /*** NX823 ***********************************************/ 1072 1073 #if defined(CONFIG_NX823) 1074 /* Bits in parallel I/O port registers that have to be set/cleared 1075 * to configure the pins for SCC1 use. 1076 */ 1077 #define PROFF_ENET PROFF_SCC2 1078 #define CPM_CR_ENET CPM_CR_CH_SCC2 1079 #define SCC_ENET 1 1080 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 1081 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 1082 #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ 1083 #define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ 1084 1085 #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ 1086 1087 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 1088 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 1089 1090 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to 1091 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. 1092 */ 1093 #define SICR_ENET_MASK ((uint)0x0000ff00) 1094 #define SICR_ENET_CLKRT ((uint)0x00002f00) 1095 1096 #endif /* CONFIG_NX823 */ 1097 1098 /*** MBX ************************************************************/ 1099 1100 #ifdef CONFIG_MBX 1101 /* Bits in parallel I/O port registers that have to be set/cleared 1102 * to configure the pins for SCC1 use. The TCLK and RCLK seem unique 1103 * to the MBX860 board. Any two of the four available clocks could be 1104 * used, and the MPC860 cookbook manual has an example using different 1105 * clock pins. 1106 */ 1107 #define PROFF_ENET PROFF_SCC1 1108 #define CPM_CR_ENET CPM_CR_CH_SCC1 1109 #define SCC_ENET 0 1110 #define PA_ENET_RXD ((ushort)0x0001) 1111 #define PA_ENET_TXD ((ushort)0x0002) 1112 #define PA_ENET_TCLK ((ushort)0x0200) 1113 #define PA_ENET_RCLK ((ushort)0x0800) 1114 #define PC_ENET_TENA ((ushort)0x0001) 1115 #define PC_ENET_CLSN ((ushort)0x0010) 1116 #define PC_ENET_RENA ((ushort)0x0020) 1117 1118 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to 1119 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. 1120 */ 1121 #define SICR_ENET_MASK ((uint)0x000000ff) 1122 #define SICR_ENET_CLKRT ((uint)0x0000003d) 1123 #endif /* CONFIG_MBX */ 1124 1125 /*** KM8XX *********************************************************/ 1126 1127 /* The KM8XX Service Module uses SCC3 for Ethernet */ 1128 1129 #ifdef CONFIG_KM8XX 1130 #define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */ 1131 #define CPM_CR_ENET CPM_CR_CH_SCC3 1132 #define SCC_ENET 2 1133 #define PA_ENET_RXD ((ushort)0x0010) /* PA 11 */ 1134 #define PA_ENET_TXD ((ushort)0x0020) /* PA 10 */ 1135 #define PA_ENET_RCLK ((ushort)0x1000) /* PA 3 CLK 5 */ 1136 #define PA_ENET_TCLK ((ushort)0x2000) /* PA 2 CLK 6 */ 1137 1138 #define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */ 1139 1140 #define PC_ENET_RENA ((ushort)0x0200) /* PC 6 */ 1141 #define PC_ENET_CLSN ((ushort)0x0100) /* PC 7 */ 1142 1143 /* Control bits in the SICR to route TCLK (CLK6) and RCLK (CLK5) to 1144 * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero. 1145 */ 1146 #define SICR_ENET_MASK ((uint)0x00FF0000) 1147 #define SICR_ENET_CLKRT ((uint)0x00250000) 1148 #endif /* CONFIG_KM8XX */ 1149 1150 1151 /*** MHPC ********************************************************/ 1152 1153 #if defined(CONFIG_MHPC) 1154 /* This ENET stuff is for the MHPC with ethernet on SCC2. 1155 * Note TENA is on Port B. 1156 */ 1157 #define PROFF_ENET PROFF_SCC2 1158 #define CPM_CR_ENET CPM_CR_CH_SCC2 1159 #define SCC_ENET 1 1160 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 1161 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 1162 #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ 1163 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ 1164 #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ 1165 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 1166 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 1167 1168 #define SICR_ENET_MASK ((uint)0x0000ff00) 1169 #define SICR_ENET_CLKRT ((uint)0x00002e00) /* RCLK-CLK2, TCLK-CLK3 */ 1170 #endif /* CONFIG_MHPC */ 1171 1172 /*** NETVIA *******************************************************/ 1173 1174 /* SinoVee Microsystems SC8xx series FEL8xx-AT,SC823,SC850,SC855T,SC860T */ 1175 #if ( defined CONFIG_SVM_SC8xx ) 1176 # ifndef CONFIG_FEC_ENET 1177 1178 #define PROFF_ENET PROFF_SCC2 1179 #define CPM_CR_ENET CPM_CR_CH_SCC2 1180 #define SCC_ENET 1 1181 1182 /* Bits in parallel I/O port registers that have to be set/cleared 1183 * * * * to configure the pins for SCC2 use. 1184 * * * */ 1185 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 1186 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 1187 #define PA_ENET_RCLK ((ushort)0x0400) /* PA 5 */ 1188 #define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ 1189 1190 #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ 1191 1192 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 1193 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 1194 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to 1195 * * * * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. 1196 * * * */ 1197 #define SICR_ENET_MASK ((uint)0x0000ff00) 1198 #define SICR_ENET_CLKRT ((uint)0x00003700) 1199 1200 # else /* Use FEC for Fast Ethernet */ 1201 1202 #undef SCC_ENET 1203 #define FEC_ENET 1204 1205 #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ 1206 #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ 1207 #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ 1208 #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ 1209 #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ 1210 #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ 1211 #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ 1212 #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ 1213 #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ 1214 #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ 1215 #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ 1216 #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ 1217 #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ 1218 1219 #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ 1220 1221 # endif /* CONFIG_FEC_ENET */ 1222 #endif /* CONFIG_SVM_SC8xx */ 1223 1224 1225 #if defined(CONFIG_NETVIA) 1226 /* Bits in parallel I/O port registers that have to be set/cleared 1227 * to configure the pins for SCC2 use. 1228 */ 1229 #define PROFF_ENET PROFF_SCC2 1230 #define CPM_CR_ENET CPM_CR_CH_SCC2 1231 #define SCC_ENET 1 1232 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 1233 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 1234 #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ 1235 #define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ 1236 1237 #if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1 1238 # define PB_ENET_PDN ((ushort)0x4000) /* PB 17 */ 1239 #elif CONFIG_NETVIA_VERSION >= 2 1240 # define PC_ENET_PDN ((ushort)0x0008) /* PC 12 */ 1241 #endif 1242 1243 #define PB_ENET_TENA ((ushort)0x2000) /* PB 18 */ 1244 1245 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 1246 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 1247 1248 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to 1249 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. 1250 */ 1251 #define SICR_ENET_MASK ((uint)0x0000ff00) 1252 #define SICR_ENET_CLKRT ((uint)0x00002f00) 1253 1254 #endif /* CONFIG_NETVIA */ 1255 1256 /*** QS850/QS823 ***************************************************/ 1257 1258 #if defined(CONFIG_QS850) || defined(CONFIG_QS823) 1259 #undef FEC_ENET /* Don't use FEC for EThernet */ 1260 1261 #define PROFF_ENET PROFF_SCC2 1262 #define CPM_CR_ENET CPM_CR_CH_SCC2 1263 #define SCC_ENET 1 1264 1265 #define PA_ENET_RXD ((ushort)0x0004) /* RXD on PA13 (Pin D9) */ 1266 #define PA_ENET_TXD ((ushort)0x0008) /* TXD on PA12 (Pin D7) */ 1267 #define PC_ENET_RENA ((ushort)0x0080) /* RENA on PC8 (Pin D12) */ 1268 #define PC_ENET_CLSN ((ushort)0x0040) /* CLSN on PC9 (Pin C12) */ 1269 #define PA_ENET_TCLK ((ushort)0x0200) /* TCLK on PA6 (Pin D8) */ 1270 #define PA_ENET_RCLK ((ushort)0x0800) /* RCLK on PA4 (Pin D10) */ 1271 #define PB_ENET_TENA ((uint)0x00002000) /* TENA on PB18 (Pin D11) */ 1272 #define PC_ENET_LBK ((ushort)0x0010) /* Loopback control on PC11 (Pin B14) */ 1273 #define PC_ENET_LI ((ushort)0x0020) /* Link Integrity control PC10 (A15) */ 1274 #define PC_ENET_SQE ((ushort)0x0100) /* SQE Disable control PC7 (B15) */ 1275 1276 /* SCC2 TXCLK from CLK2 1277 * SCC2 RXCLK from CLK4 1278 * SCC2 Connected to NMSI */ 1279 #define SICR_ENET_MASK ((uint)0x00007F00) 1280 #define SICR_ENET_CLKRT ((uint)0x00003D00) 1281 1282 #endif /* CONFIG_QS850/QS823 */ 1283 1284 /*** QS860T ***************************************************/ 1285 1286 #ifdef CONFIG_QS860T 1287 #ifdef CONFIG_FEC_ENET 1288 #define FEC_ENET /* use FEC for EThernet */ 1289 #endif /* CONFIG_FEC_ETHERNET */ 1290 1291 /* This ENET stuff is for GTH 10 Mbit ( SCC ) */ 1292 #define PROFF_ENET PROFF_SCC1 1293 #define CPM_CR_ENET CPM_CR_CH_SCC1 1294 #define SCC_ENET 0 1295 1296 #define PA_ENET_RXD ((ushort)0x0001) /* PA15 */ 1297 #define PA_ENET_TXD ((ushort)0x0002) /* PA14 */ 1298 #define PA_ENET_TCLK ((ushort)0x0800) /* PA4 */ 1299 #define PA_ENET_RCLK ((ushort)0x0200) /* PA6 */ 1300 #define PB_ENET_TENA ((uint)0x00001000) /* PB19 */ 1301 #define PC_ENET_CLSN ((ushort)0x0010) /* PC11 */ 1302 #define PC_ENET_RENA ((ushort)0x0020) /* PC10 */ 1303 1304 #define SICR_ENET_MASK ((uint)0x000000ff) 1305 /* RCLK PA4 -->CLK4, TCLK PA6 -->CLK2 */ 1306 #define SICR_ENET_CLKRT ((uint)0x0000003D) 1307 1308 #endif /* CONFIG_QS860T */ 1309 1310 /*** RPXCLASSIC *****************************************************/ 1311 1312 #ifdef CONFIG_RPXCLASSIC 1313 1314 #ifdef CONFIG_FEC_ENET 1315 1316 # define FEC_ENET /* use FEC for EThernet */ 1317 # undef SCC_ENET 1318 1319 #else /* ! CONFIG_FEC_ENET */ 1320 1321 /* Bits in parallel I/O port registers that have to be set/cleared 1322 * to configure the pins for SCC1 use. 1323 */ 1324 #define PROFF_ENET PROFF_SCC1 1325 #define CPM_CR_ENET CPM_CR_CH_SCC1 1326 #define SCC_ENET 0 1327 #define PA_ENET_RXD ((ushort)0x0001) 1328 #define PA_ENET_TXD ((ushort)0x0002) 1329 #define PA_ENET_TCLK ((ushort)0x0200) 1330 #define PA_ENET_RCLK ((ushort)0x0800) 1331 #define PB_ENET_TENA ((uint)0x00001000) 1332 #define PC_ENET_CLSN ((ushort)0x0010) 1333 #define PC_ENET_RENA ((ushort)0x0020) 1334 1335 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to 1336 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. 1337 */ 1338 #define SICR_ENET_MASK ((uint)0x000000ff) 1339 #define SICR_ENET_CLKRT ((uint)0x0000003d) 1340 1341 #endif /* CONFIG_FEC_ENET */ 1342 1343 #endif /* CONFIG_RPXCLASSIC */ 1344 1345 /*** RPXLITE ********************************************************/ 1346 1347 #ifdef CONFIG_RPXLITE 1348 /* This ENET stuff is for the MPC850 with ethernet on SCC2. Some of 1349 * this may be unique to the RPX-Lite configuration. 1350 * Note TENA is on Port B. 1351 */ 1352 #define PROFF_ENET PROFF_SCC2 1353 #define CPM_CR_ENET CPM_CR_CH_SCC2 1354 #define SCC_ENET 1 1355 #define PA_ENET_RXD ((ushort)0x0004) 1356 #define PA_ENET_TXD ((ushort)0x0008) 1357 #define PA_ENET_TCLK ((ushort)0x0200) 1358 #define PA_ENET_RCLK ((ushort)0x0800) 1359 #if defined(CONFIG_RMU) 1360 #define PC_ENET_TENA ((uint)0x00000002) /* PC14 */ 1361 #else 1362 #define PB_ENET_TENA ((uint)0x00002000) 1363 #endif 1364 #define PC_ENET_CLSN ((ushort)0x0040) 1365 #define PC_ENET_RENA ((ushort)0x0080) 1366 1367 #define SICR_ENET_MASK ((uint)0x0000ff00) 1368 #define SICR_ENET_CLKRT ((uint)0x00003d00) 1369 #endif /* CONFIG_RPXLITE */ 1370 1371 /*** SM850 *********************************************************/ 1372 1373 /* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */ 1374 1375 #ifdef CONFIG_SM850 1376 #define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */ 1377 #define CPM_CR_ENET CPM_CR_CH_SCC3 1378 #define SCC_ENET 2 1379 #define PB_ENET_RXD ((uint)0x00000004) /* PB 29 */ 1380 #define PB_ENET_TXD ((uint)0x00000002) /* PB 30 */ 1381 #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ 1382 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ 1383 1384 #define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */ 1385 #define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */ 1386 1387 #define PC_ENET_RENA ((ushort)0x0800) /* PC 4 */ 1388 #define PC_ENET_CLSN ((ushort)0x0400) /* PC 5 */ 1389 1390 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to 1391 * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero. 1392 */ 1393 #define SICR_ENET_MASK ((uint)0x00FF0000) 1394 #define SICR_ENET_CLKRT ((uint)0x00260000) 1395 #endif /* CONFIG_SM850 */ 1396 1397 /*** SPD823TS ******************************************************/ 1398 1399 #ifdef CONFIG_SPD823TS 1400 /* Bits in parallel I/O port registers that have to be set/cleared 1401 * to configure the pins for SCC2 use. 1402 */ 1403 #define PROFF_ENET PROFF_SCC2 /* Ethernet on SCC2 */ 1404 #define CPM_CR_ENET CPM_CR_CH_SCC2 1405 #define SCC_ENET 1 1406 #define PA_ENET_MDC ((ushort)0x0001) /* PA 15 !!! */ 1407 #define PA_ENET_MDIO ((ushort)0x0002) /* PA 14 !!! */ 1408 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 1409 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 1410 #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ 1411 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ 1412 1413 #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ 1414 1415 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 1416 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 1417 #define PC_ENET_RESET ((ushort)0x0100) /* PC 7 !!! */ 1418 1419 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to 1420 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. 1421 */ 1422 #define SICR_ENET_MASK ((uint)0x0000ff00) 1423 #define SICR_ENET_CLKRT ((uint)0x00002E00) 1424 #endif /* CONFIG_SPD823TS */ 1425 1426 /*** SXNI855T ******************************************************/ 1427 1428 #if defined(CONFIG_SXNI855T) 1429 1430 #ifdef CONFIG_FEC_ENET 1431 #define FEC_ENET /* use FEC for Ethernet */ 1432 #endif /* CONFIG_FEC_ETHERNET */ 1433 1434 #endif /* CONFIG_SXNI855T */ 1435 1436 /*** MVS1, TQM823L/M, TQM850L/M, TQM885D, ETX094, R360MPI **********/ 1437 1438 #if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \ 1439 defined(CONFIG_R360MPI) || defined(CONFIG_RBC823) || \ 1440 defined(CONFIG_TQM823L) || defined(CONFIG_TQM823M) || \ 1441 defined(CONFIG_TQM850L) || defined(CONFIG_TQM850M) || \ 1442 defined(CONFIG_TQM885D) || defined(CONFIG_ETX094) || \ 1443 defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2)|| \ 1444 (defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2) 1445 1446 /* Bits in parallel I/O port registers that have to be set/cleared 1447 * to configure the pins for SCC2 use. 1448 */ 1449 #define PROFF_ENET PROFF_SCC2 1450 #define CPM_CR_ENET CPM_CR_CH_SCC2 1451 #if (!defined(CONFIG_TK885D)) /* TK885D does not use SCC Ethernet */ 1452 #define SCC_ENET 1 1453 #endif 1454 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 1455 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 1456 #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ 1457 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ 1458 1459 #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ 1460 1461 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 1462 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 1463 #if defined(CONFIG_R360MPI) 1464 #define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */ 1465 #endif /* CONFIG_R360MPI */ 1466 1467 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to 1468 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. 1469 */ 1470 #define SICR_ENET_MASK ((uint)0x0000ff00) 1471 #define SICR_ENET_CLKRT ((uint)0x00002600) 1472 1473 # ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */ 1474 #define FEC_ENET 1475 # endif /* CONFIG_FEC_ENET */ 1476 1477 #endif /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */ 1478 1479 /*** TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M *********************/ 1480 1481 #if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \ 1482 defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \ 1483 defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M) || \ 1484 defined(CONFIG_TQM866L) || defined(CONFIG_TQM866M) 1485 1486 # ifdef CONFIG_SCC1_ENET /* use SCC for 10Mbps Ethernet */ 1487 1488 /* Bits in parallel I/O port registers that have to be set/cleared 1489 * to configure the pins for SCC1 use. 1490 */ 1491 #define PROFF_ENET PROFF_SCC1 1492 #define CPM_CR_ENET CPM_CR_CH_SCC1 1493 #define SCC_ENET 0 1494 #define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ 1495 #define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ 1496 #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ 1497 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ 1498 1499 #define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ 1500 #define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ 1501 #define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ 1502 1503 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to 1504 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. 1505 */ 1506 #define SICR_ENET_MASK ((uint)0x000000ff) 1507 #define SICR_ENET_CLKRT ((uint)0x00000026) 1508 1509 # endif /* CONFIG_SCC1_ENET */ 1510 1511 # ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */ 1512 1513 #define FEC_ENET 1514 1515 #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ 1516 #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ 1517 #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ 1518 #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ 1519 #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ 1520 #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ 1521 #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ 1522 #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ 1523 #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ 1524 #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ 1525 #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ 1526 #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ 1527 #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ 1528 1529 #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ 1530 1531 # endif /* CONFIG_FEC_ENET */ 1532 #endif /* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */ 1533 1534 /*** V37 **********************************************************/ 1535 1536 #ifdef CONFIG_V37 1537 /* This ENET stuff is for the MPC823 with ethernet on SCC2. Some of 1538 * this may be unique to the Marel V37 configuration. 1539 * Note TENA is on Port B. 1540 */ 1541 #define PROFF_ENET PROFF_SCC2 1542 #define CPM_CR_ENET CPM_CR_CH_SCC2 1543 #define SCC_ENET 1 1544 #define PA_ENET_RXD ((ushort)0x0004) 1545 #define PA_ENET_TXD ((ushort)0x0008) 1546 #define PA_ENET_TCLK ((ushort)0x0400) 1547 #define PA_ENET_RCLK ((ushort)0x0200) 1548 #define PB_ENET_TENA ((uint)0x00002000) 1549 #define PC_ENET_CLSN ((ushort)0x0040) 1550 #define PC_ENET_RENA ((ushort)0x0080) 1551 1552 #define SICR_ENET_MASK ((uint)0x0000ff00) 1553 #define SICR_ENET_CLKRT ((uint)0x00002e00) 1554 #endif /* CONFIG_V37 */ 1555 1556 1557 /*********************************************************************/ 1558 1559 /* SCC Event register as used by Ethernet. 1560 */ 1561 #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ 1562 #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ 1563 #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ 1564 #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ 1565 #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ 1566 #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ 1567 1568 /* SCC Mode Register (PSMR) as used by Ethernet. 1569 */ 1570 #define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ 1571 #define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ 1572 #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ 1573 #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ 1574 #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ 1575 #define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ 1576 #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ 1577 #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ 1578 #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ 1579 #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ 1580 #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ 1581 #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ 1582 #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ 1583 1584 /* Buffer descriptor control/status used by Ethernet receive. 1585 */ 1586 #define BD_ENET_RX_EMPTY ((ushort)0x8000) 1587 #define BD_ENET_RX_WRAP ((ushort)0x2000) 1588 #define BD_ENET_RX_INTR ((ushort)0x1000) 1589 #define BD_ENET_RX_LAST ((ushort)0x0800) 1590 #define BD_ENET_RX_FIRST ((ushort)0x0400) 1591 #define BD_ENET_RX_MISS ((ushort)0x0100) 1592 #define BD_ENET_RX_LG ((ushort)0x0020) 1593 #define BD_ENET_RX_NO ((ushort)0x0010) 1594 #define BD_ENET_RX_SH ((ushort)0x0008) 1595 #define BD_ENET_RX_CR ((ushort)0x0004) 1596 #define BD_ENET_RX_OV ((ushort)0x0002) 1597 #define BD_ENET_RX_CL ((ushort)0x0001) 1598 #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ 1599 1600 /* Buffer descriptor control/status used by Ethernet transmit. 1601 */ 1602 #define BD_ENET_TX_READY ((ushort)0x8000) 1603 #define BD_ENET_TX_PAD ((ushort)0x4000) 1604 #define BD_ENET_TX_WRAP ((ushort)0x2000) 1605 #define BD_ENET_TX_INTR ((ushort)0x1000) 1606 #define BD_ENET_TX_LAST ((ushort)0x0800) 1607 #define BD_ENET_TX_TC ((ushort)0x0400) 1608 #define BD_ENET_TX_DEF ((ushort)0x0200) 1609 #define BD_ENET_TX_HB ((ushort)0x0100) 1610 #define BD_ENET_TX_LC ((ushort)0x0080) 1611 #define BD_ENET_TX_RL ((ushort)0x0040) 1612 #define BD_ENET_TX_RCMASK ((ushort)0x003c) 1613 #define BD_ENET_TX_UN ((ushort)0x0002) 1614 #define BD_ENET_TX_CSL ((ushort)0x0001) 1615 #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ 1616 1617 /* SCC as UART 1618 */ 1619 typedef struct scc_uart { 1620 sccp_t scc_genscc; 1621 uint scc_res1; /* Reserved */ 1622 uint scc_res2; /* Reserved */ 1623 ushort scc_maxidl; /* Maximum idle chars */ 1624 ushort scc_idlc; /* temp idle counter */ 1625 ushort scc_brkcr; /* Break count register */ 1626 ushort scc_parec; /* receive parity error counter */ 1627 ushort scc_frmec; /* receive framing error counter */ 1628 ushort scc_nosec; /* receive noise counter */ 1629 ushort scc_brkec; /* receive break condition counter */ 1630 ushort scc_brkln; /* last received break length */ 1631 ushort scc_uaddr1; /* UART address character 1 */ 1632 ushort scc_uaddr2; /* UART address character 2 */ 1633 ushort scc_rtemp; /* Temp storage */ 1634 ushort scc_toseq; /* Transmit out of sequence char */ 1635 ushort scc_char1; /* control character 1 */ 1636 ushort scc_char2; /* control character 2 */ 1637 ushort scc_char3; /* control character 3 */ 1638 ushort scc_char4; /* control character 4 */ 1639 ushort scc_char5; /* control character 5 */ 1640 ushort scc_char6; /* control character 6 */ 1641 ushort scc_char7; /* control character 7 */ 1642 ushort scc_char8; /* control character 8 */ 1643 ushort scc_rccm; /* receive control character mask */ 1644 ushort scc_rccr; /* receive control character register */ 1645 ushort scc_rlbc; /* receive last break character */ 1646 } scc_uart_t; 1647 1648 /* SCC Event and Mask registers when it is used as a UART. 1649 */ 1650 #define UART_SCCM_GLR ((ushort)0x1000) 1651 #define UART_SCCM_GLT ((ushort)0x0800) 1652 #define UART_SCCM_AB ((ushort)0x0200) 1653 #define UART_SCCM_IDL ((ushort)0x0100) 1654 #define UART_SCCM_GRA ((ushort)0x0080) 1655 #define UART_SCCM_BRKE ((ushort)0x0040) 1656 #define UART_SCCM_BRKS ((ushort)0x0020) 1657 #define UART_SCCM_CCR ((ushort)0x0008) 1658 #define UART_SCCM_BSY ((ushort)0x0004) 1659 #define UART_SCCM_TX ((ushort)0x0002) 1660 #define UART_SCCM_RX ((ushort)0x0001) 1661 1662 /* The SCC PSMR when used as a UART. 1663 */ 1664 #define SCU_PSMR_FLC ((ushort)0x8000) 1665 #define SCU_PSMR_SL ((ushort)0x4000) 1666 #define SCU_PSMR_CL ((ushort)0x3000) 1667 #define SCU_PSMR_UM ((ushort)0x0c00) 1668 #define SCU_PSMR_FRZ ((ushort)0x0200) 1669 #define SCU_PSMR_RZS ((ushort)0x0100) 1670 #define SCU_PSMR_SYN ((ushort)0x0080) 1671 #define SCU_PSMR_DRT ((ushort)0x0040) 1672 #define SCU_PSMR_PEN ((ushort)0x0010) 1673 #define SCU_PSMR_RPM ((ushort)0x000c) 1674 #define SCU_PSMR_REVP ((ushort)0x0008) 1675 #define SCU_PSMR_TPM ((ushort)0x0003) 1676 #define SCU_PSMR_TEVP ((ushort)0x0003) 1677 1678 /* CPM Transparent mode SCC. 1679 */ 1680 typedef struct scc_trans { 1681 sccp_t st_genscc; 1682 uint st_cpres; /* Preset CRC */ 1683 uint st_cmask; /* Constant mask for CRC */ 1684 } scc_trans_t; 1685 1686 #define BD_SCC_TX_LAST ((ushort)0x0800) 1687 1688 /* IIC parameter RAM. 1689 */ 1690 typedef struct iic { 1691 ushort iic_rbase; /* Rx Buffer descriptor base address */ 1692 ushort iic_tbase; /* Tx Buffer descriptor base address */ 1693 u_char iic_rfcr; /* Rx function code */ 1694 u_char iic_tfcr; /* Tx function code */ 1695 ushort iic_mrblr; /* Max receive buffer length */ 1696 uint iic_rstate; /* Internal */ 1697 uint iic_rdp; /* Internal */ 1698 ushort iic_rbptr; /* Internal */ 1699 ushort iic_rbc; /* Internal */ 1700 uint iic_rxtmp; /* Internal */ 1701 uint iic_tstate; /* Internal */ 1702 uint iic_tdp; /* Internal */ 1703 ushort iic_tbptr; /* Internal */ 1704 ushort iic_tbc; /* Internal */ 1705 uint iic_txtmp; /* Internal */ 1706 uint iic_res; /* reserved */ 1707 ushort iic_rpbase; /* Relocation pointer */ 1708 ushort iic_res2; /* reserved */ 1709 } iic_t; 1710 1711 /* SPI parameter RAM. 1712 */ 1713 typedef struct spi { 1714 ushort spi_rbase; /* Rx Buffer descriptor base address */ 1715 ushort spi_tbase; /* Tx Buffer descriptor base address */ 1716 u_char spi_rfcr; /* Rx function code */ 1717 u_char spi_tfcr; /* Tx function code */ 1718 ushort spi_mrblr; /* Max receive buffer length */ 1719 uint spi_rstate; /* Internal */ 1720 uint spi_rdp; /* Internal */ 1721 ushort spi_rbptr; /* Internal */ 1722 ushort spi_rbc; /* Internal */ 1723 uint spi_rxtmp; /* Internal */ 1724 uint spi_tstate; /* Internal */ 1725 uint spi_tdp; /* Internal */ 1726 ushort spi_tbptr; /* Internal */ 1727 ushort spi_tbc; /* Internal */ 1728 uint spi_txtmp; /* Internal */ 1729 uint spi_res; 1730 ushort spi_rpbase; /* Relocation pointer */ 1731 ushort spi_res2; 1732 } spi_t; 1733 1734 /* SPI Mode register. 1735 */ 1736 #define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ 1737 #define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ 1738 #define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ 1739 #define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ 1740 #define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ 1741 #define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ 1742 #define SPMODE_EN ((ushort)0x0100) /* Enable */ 1743 #define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ 1744 #define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ 1745 1746 #define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) 1747 #define SPMODE_PM(x) ((x) &0xF) 1748 1749 /* HDLC parameter RAM. 1750 */ 1751 1752 typedef struct hdlc_pram_s { 1753 /* 1754 * SCC parameter RAM 1755 */ 1756 ushort rbase; /* Rx Buffer descriptor base address */ 1757 ushort tbase; /* Tx Buffer descriptor base address */ 1758 uchar rfcr; /* Rx function code */ 1759 uchar tfcr; /* Tx function code */ 1760 ushort mrblr; /* Rx buffer length */ 1761 ulong rstate; /* Rx internal state */ 1762 ulong rptr; /* Rx internal data pointer */ 1763 ushort rbptr; /* rb BD Pointer */ 1764 ushort rcount; /* Rx internal byte count */ 1765 ulong rtemp; /* Rx temp */ 1766 ulong tstate; /* Tx internal state */ 1767 ulong tptr; /* Tx internal data pointer */ 1768 ushort tbptr; /* Tx BD pointer */ 1769 ushort tcount; /* Tx byte count */ 1770 ulong ttemp; /* Tx temp */ 1771 ulong rcrc; /* temp receive CRC */ 1772 ulong tcrc; /* temp transmit CRC */ 1773 /* 1774 * HDLC specific parameter RAM 1775 */ 1776 uchar res[4]; /* reserved */ 1777 ulong c_mask; /* CRC constant */ 1778 ulong c_pres; /* CRC preset */ 1779 ushort disfc; /* discarded frame counter */ 1780 ushort crcec; /* CRC error counter */ 1781 ushort abtsc; /* abort sequence counter */ 1782 ushort nmarc; /* nonmatching address rx cnt */ 1783 ushort retrc; /* frame retransmission cnt */ 1784 ushort mflr; /* maximum frame length reg */ 1785 ushort max_cnt; /* maximum length counter */ 1786 ushort rfthr; /* received frames threshold */ 1787 ushort rfcnt; /* received frames count */ 1788 ushort hmask; /* user defined frm addr mask */ 1789 ushort haddr1; /* user defined frm address 1 */ 1790 ushort haddr2; /* user defined frm address 2 */ 1791 ushort haddr3; /* user defined frm address 3 */ 1792 ushort haddr4; /* user defined frm address 4 */ 1793 ushort tmp; /* temp */ 1794 ushort tmp_mb; /* temp */ 1795 } hdlc_pram_t; 1796 1797 /* CPM interrupts. There are nearly 32 interrupts generated by CPM 1798 * channels or devices. All of these are presented to the PPC core 1799 * as a single interrupt. The CPM interrupt handler dispatches its 1800 * own handlers, in a similar fashion to the PPC core handler. We 1801 * use the table as defined in the manuals (i.e. no special high 1802 * priority and SCC1 == SCCa, etc...). 1803 */ 1804 #define CPMVEC_NR 32 1805 #define CPMVEC_OFFSET 0x00010000 1806 #define CPMVEC_PIO_PC15 ((ushort)0x1f | CPMVEC_OFFSET) 1807 #define CPMVEC_SCC1 ((ushort)0x1e | CPMVEC_OFFSET) 1808 #define CPMVEC_SCC2 ((ushort)0x1d | CPMVEC_OFFSET) 1809 #define CPMVEC_SCC3 ((ushort)0x1c | CPMVEC_OFFSET) 1810 #define CPMVEC_SCC4 ((ushort)0x1b | CPMVEC_OFFSET) 1811 #define CPMVEC_PIO_PC14 ((ushort)0x1a | CPMVEC_OFFSET) 1812 #define CPMVEC_TIMER1 ((ushort)0x19 | CPMVEC_OFFSET) 1813 #define CPMVEC_PIO_PC13 ((ushort)0x18 | CPMVEC_OFFSET) 1814 #define CPMVEC_PIO_PC12 ((ushort)0x17 | CPMVEC_OFFSET) 1815 #define CPMVEC_SDMA_CB_ERR ((ushort)0x16 | CPMVEC_OFFSET) 1816 #define CPMVEC_IDMA1 ((ushort)0x15 | CPMVEC_OFFSET) 1817 #define CPMVEC_IDMA2 ((ushort)0x14 | CPMVEC_OFFSET) 1818 #define CPMVEC_TIMER2 ((ushort)0x12 | CPMVEC_OFFSET) 1819 #define CPMVEC_RISCTIMER ((ushort)0x11 | CPMVEC_OFFSET) 1820 #define CPMVEC_I2C ((ushort)0x10 | CPMVEC_OFFSET) 1821 #define CPMVEC_PIO_PC11 ((ushort)0x0f | CPMVEC_OFFSET) 1822 #define CPMVEC_PIO_PC10 ((ushort)0x0e | CPMVEC_OFFSET) 1823 #define CPMVEC_TIMER3 ((ushort)0x0c | CPMVEC_OFFSET) 1824 #define CPMVEC_PIO_PC9 ((ushort)0x0b | CPMVEC_OFFSET) 1825 #define CPMVEC_PIO_PC8 ((ushort)0x0a | CPMVEC_OFFSET) 1826 #define CPMVEC_PIO_PC7 ((ushort)0x09 | CPMVEC_OFFSET) 1827 #define CPMVEC_TIMER4 ((ushort)0x07 | CPMVEC_OFFSET) 1828 #define CPMVEC_PIO_PC6 ((ushort)0x06 | CPMVEC_OFFSET) 1829 #define CPMVEC_SPI ((ushort)0x05 | CPMVEC_OFFSET) 1830 #define CPMVEC_SMC1 ((ushort)0x04 | CPMVEC_OFFSET) 1831 #define CPMVEC_SMC2 ((ushort)0x03 | CPMVEC_OFFSET) 1832 #define CPMVEC_PIO_PC5 ((ushort)0x02 | CPMVEC_OFFSET) 1833 #define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET) 1834 #define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET) 1835 1836 extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id); 1837 1838 /* CPM interrupt configuration vector. 1839 */ 1840 #define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ 1841 #define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ 1842 #define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ 1843 #define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ 1844 #define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */ 1845 #define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ 1846 #define CICR_IEN ((uint)0x00000080) /* Int. enable */ 1847 #define CICR_SPS ((uint)0x00000001) /* SCC Spread */ 1848 #endif /* __CPM_8XX__ */ 1849