1 /* 2 * (C) Copyright 2003-2005 3 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> 4 * 5 * (C) Copyright 2003 6 * DAVE Srl 7 * 8 * http://www.dave-tech.it 9 * http://www.wawnet.biz 10 * mailto:info@wawnet.biz 11 * 12 * Credits: Stefan Roese, Wolfgang Denk 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * MA 02111-1307 USA 28 */ 29 30 /* 31 * board/config.h - configuration options, board specific 32 */ 33 34 #ifndef __CONFIG_H 35 #define __CONFIG_H 36 37 #define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */ 38 #define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */ 39 #define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */ 40 #ifndef CONFIG_PPCHAMELEON_MODULE_MODEL 41 #define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA 42 #endif 43 44 45 /* Only one of the following two symbols must be defined (default is 25 MHz) 46 * CONFIG_PPCHAMELEON_CLK_25 47 * CONFIG_PPCHAMELEON_CLK_33 48 */ 49 #if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33)) 50 #define CONFIG_PPCHAMELEON_CLK_25 51 #endif 52 53 #if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33)) 54 #error "* Two external frequencies (SysClk) are defined! *" 55 #endif 56 57 #undef CONFIG_PPCHAMELEON_SMI712 58 59 /* 60 * Debug stuff 61 */ 62 #undef __DEBUG_START_FROM_SRAM__ 63 #define __DISABLE_MACHINE_EXCEPTION__ 64 65 #ifdef __DEBUG_START_FROM_SRAM__ 66 #define CONFIG_SYS_DUMMY_FLASH_SIZE 1024*1024*4 67 #endif 68 69 /* 70 * High Level Configuration Options 71 * (easy to change) 72 */ 73 74 #define CONFIG_405EP 1 /* This is a PPC405 CPU */ 75 #define CONFIG_4xx 1 /* ...member of PPC4xx family */ 76 #define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */ 77 78 #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ 79 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ 80 81 82 #ifdef CONFIG_PPCHAMELEON_CLK_25 83 # define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ 84 #elif (defined (CONFIG_PPCHAMELEON_CLK_33)) 85 # define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ 86 #else 87 # error "* External frequency (SysClk) not defined! *" 88 #endif 89 90 #define CONFIG_BAUDRATE 115200 91 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 92 93 #undef CONFIG_BOOTARGS 94 95 /* Ethernet stuff */ 96 #define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */ 97 #define CONFIG_ETHADDR 00:50:c2:1e:af:fe 98 #define CONFIG_HAS_ETH1 99 #define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd 100 101 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 102 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 103 104 #undef CONFIG_EXT_PHY 105 #define CONFIG_NET_MULTI 1 106 107 #define CONFIG_PPC4xx_EMAC 108 #define CONFIG_MII 1 /* MII PHY management */ 109 #ifndef CONFIG_EXT_PHY 110 #define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */ 111 #define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */ 112 #else 113 #define CONFIG_PHY_ADDR 2 /* PHY address */ 114 #endif 115 #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ 116 117 118 /* 119 * BOOTP options 120 */ 121 #define CONFIG_BOOTP_BOOTFILESIZE 122 #define CONFIG_BOOTP_BOOTPATH 123 #define CONFIG_BOOTP_GATEWAY 124 #define CONFIG_BOOTP_HOSTNAME 125 126 127 /* 128 * Command line configuration. 129 */ 130 #include <config_cmd_default.h> 131 132 #define CONFIG_CMD_DATE 133 #define CONFIG_CMD_DHCP 134 #define CONFIG_CMD_ELF 135 #define CONFIG_CMD_EEPROM 136 #define CONFIG_CMD_I2C 137 #define CONFIG_CMD_IRQ 138 #define CONFIG_CMD_JFFS2 139 #define CONFIG_CMD_MII 140 #define CONFIG_CMD_NAND 141 #define CONFIG_CMD_NFS 142 #define CONFIG_CMD_PCI 143 #define CONFIG_CMD_SNTP 144 145 146 #define CONFIG_MAC_PARTITION 147 #define CONFIG_DOS_PARTITION 148 149 #undef CONFIG_WATCHDOG /* watchdog disabled */ 150 151 #define CONFIG_RTC_M41T11 1 /* uses a M41T00 RTC */ 152 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 153 #define CONFIG_SYS_M41T11_BASE_YEAR 1900 154 155 /* 156 * SDRAM configuration (please see cpu/ppc/sdram.[ch]) 157 */ 158 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ 159 160 /* SDRAM timings used in datasheet */ 161 #define CONFIG_SYS_SDRAM_CL 2 162 #define CONFIG_SYS_SDRAM_tRP 20 163 #define CONFIG_SYS_SDRAM_tRC 65 164 #define CONFIG_SYS_SDRAM_tRCD 20 165 #undef CONFIG_SYS_SDRAM_tRFC 166 167 /* 168 * Miscellaneous configurable options 169 */ 170 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 171 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 172 173 #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 174 #ifdef CONFIG_SYS_HUSH_PARSER 175 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 176 #endif 177 178 #if defined(CONFIG_CMD_KGDB) 179 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 180 #else 181 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 182 #endif 183 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 184 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 185 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 186 187 #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ 188 189 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ 190 191 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 192 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 193 194 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ 195 #define CONFIG_SYS_BASE_BAUD 691200 196 197 /* The following table includes the supported baudrates */ 198 #define CONFIG_SYS_BAUDRATE_TABLE \ 199 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ 200 57600, 115200, 230400, 460800, 921600 } 201 202 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 203 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ 204 205 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 206 207 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ 208 209 /*----------------------------------------------------------------------- 210 * NAND-FLASH stuff 211 *----------------------------------------------------------------------- 212 */ 213 214 /* 215 * nand device 1 on dave (PPChameleonEVB) needs more time, 216 * so we just introduce additional wait in nand_wait(), 217 * effectively for both devices. 218 */ 219 #define PPCHAMELON_NAND_TIMER_HACK 220 221 #define CONFIG_SYS_NAND0_BASE 0xFF400000 222 #define CONFIG_SYS_NAND1_BASE 0xFF000000 223 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, CONFIG_SYS_NAND1_BASE } 224 #define NAND_BIG_DELAY_US 25 225 #define CONFIG_SYS_MAX_NAND_DEVICE 2 /* Max number of NAND devices */ 226 227 #define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */ 228 #define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ 229 #define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ 230 #define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ 231 232 #define CONFIG_SYS_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */ 233 #define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */ 234 #define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */ 235 #define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */ 236 237 #define MACRO_NAND_DISABLE_CE(nandptr) do \ 238 { \ 239 switch((unsigned long)nandptr) \ 240 { \ 241 case CONFIG_SYS_NAND0_BASE: \ 242 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \ 243 break; \ 244 case CONFIG_SYS_NAND1_BASE: \ 245 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \ 246 break; \ 247 } \ 248 } while(0) 249 250 #define MACRO_NAND_ENABLE_CE(nandptr) do \ 251 { \ 252 switch((unsigned long)nandptr) \ 253 { \ 254 case CONFIG_SYS_NAND0_BASE: \ 255 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \ 256 break; \ 257 case CONFIG_SYS_NAND1_BASE: \ 258 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \ 259 break; \ 260 } \ 261 } while(0) 262 263 #define MACRO_NAND_CTL_CLRALE(nandptr) do \ 264 { \ 265 switch((unsigned long)nandptr) \ 266 { \ 267 case CONFIG_SYS_NAND0_BASE: \ 268 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \ 269 break; \ 270 case CONFIG_SYS_NAND1_BASE: \ 271 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \ 272 break; \ 273 } \ 274 } while(0) 275 276 #define MACRO_NAND_CTL_SETALE(nandptr) do \ 277 { \ 278 switch((unsigned long)nandptr) \ 279 { \ 280 case CONFIG_SYS_NAND0_BASE: \ 281 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \ 282 break; \ 283 case CONFIG_SYS_NAND1_BASE: \ 284 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \ 285 break; \ 286 } \ 287 } while(0) 288 289 #define MACRO_NAND_CTL_CLRCLE(nandptr) do \ 290 { \ 291 switch((unsigned long)nandptr) \ 292 { \ 293 case CONFIG_SYS_NAND0_BASE: \ 294 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \ 295 break; \ 296 case CONFIG_SYS_NAND1_BASE: \ 297 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \ 298 break; \ 299 } \ 300 } while(0) 301 302 #define MACRO_NAND_CTL_SETCLE(nandptr) do { \ 303 switch((unsigned long)nandptr) { \ 304 case CONFIG_SYS_NAND0_BASE: \ 305 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \ 306 break; \ 307 case CONFIG_SYS_NAND1_BASE: \ 308 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \ 309 break; \ 310 } \ 311 } while(0) 312 313 /*----------------------------------------------------------------------- 314 * PCI stuff 315 *----------------------------------------------------------------------- 316 */ 317 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ 318 #define PCI_HOST_FORCE 1 /* configure as pci host */ 319 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ 320 321 #define CONFIG_PCI /* include pci support */ 322 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ 323 #undef CONFIG_PCI_PNP /* do pci plug-and-play */ 324 /* resource configuration */ 325 326 #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ 327 328 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */ 329 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */ 330 #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ 331 332 #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ 333 #define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ 334 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ 335 #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ 336 #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ 337 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ 338 339 /*----------------------------------------------------------------------- 340 * Start addresses for the final memory configuration 341 * (Set up by the startup code) 342 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 343 */ 344 #define CONFIG_SYS_SDRAM_BASE 0x00000000 345 346 /* Reserve 256 kB for Monitor */ 347 /* 348 #define CONFIG_SYS_FLASH_BASE 0xFFFC0000 349 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 350 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 351 */ 352 353 /* Reserve 320 kB for Monitor */ 354 #define CONFIG_SYS_FLASH_BASE 0xFFFB0000 355 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 356 #define CONFIG_SYS_MONITOR_LEN (320 * 1024) 357 358 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ 359 360 /* 361 * For booting Linux, the board info and command line data 362 * have to be in the first 8 MB of memory, since this is 363 * the maximum mapped by the Linux kernel during initialization. 364 */ 365 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 366 /*----------------------------------------------------------------------- 367 * FLASH organization 368 */ 369 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 370 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 371 372 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 373 #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ 374 375 #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ 376 #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ 377 #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ 378 /* 379 * The following defines are added for buggy IOP480 byte interface. 380 * All other boards should use the standard values (CPCI405 etc.) 381 */ 382 #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ 383 #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ 384 #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ 385 386 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 387 388 /*----------------------------------------------------------------------- 389 * Environment Variable setup 390 */ 391 #ifdef ENVIRONMENT_IN_EEPROM 392 393 #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ 394 #define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ 395 #define CONFIG_ENV_SIZE 0x700 /* 2048-256 bytes may be used for env vars (total size of a CAT24WC16 is 2048 bytes)*/ 396 397 #else /* DEFAULT: environment in flash, using redundand flash sectors */ 398 399 #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ 400 #define CONFIG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */ 401 #define CONFIG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/ 402 #define CONFIG_ENV_ADDR_REDUND 0xFFFFA000 403 #define CONFIG_ENV_SIZE_REDUND 0x2000 404 405 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 406 407 #endif /* ENVIRONMENT_IN_EEPROM */ 408 409 410 #define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ 411 #define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */ 412 413 /*----------------------------------------------------------------------- 414 * I2C EEPROM (CAT24WC16) for environment 415 */ 416 #define CONFIG_HARD_I2C /* I2c with hardware support */ 417 #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ 418 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 419 #define CONFIG_SYS_I2C_SLAVE 0x7F 420 421 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ 422 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ 423 /* mask of address bits that overflow into the "EEPROM chip address" */ 424 /*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07*/ 425 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ 426 /* 16 byte page write mode using*/ 427 /* last 4 bits of the address */ 428 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 429 430 /* 431 * Init Memory Controller: 432 * 433 * BR0/1 and OR0/1 (FLASH) 434 */ 435 436 #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ 437 438 /*----------------------------------------------------------------------- 439 * External Bus Controller (EBC) Setup 440 */ 441 442 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ 443 #define CONFIG_SYS_EBC_PB0AP 0x92015480 444 #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ 445 446 /* Memory Bank 1 (External SRAM) initialization */ 447 /* Since this must replace NOR Flash, we use the same settings for CS0 */ 448 #define CONFIG_SYS_EBC_PB1AP 0x92015480 449 #define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */ 450 451 /* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */ 452 #define CONFIG_SYS_EBC_PB2AP 0x92015480 453 #define CONFIG_SYS_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */ 454 455 /* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */ 456 #define CONFIG_SYS_EBC_PB3AP 0x92015480 457 #define CONFIG_SYS_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */ 458 459 #ifdef CONFIG_PPCHAMELEON_SMI712 460 /* 461 * Video console (graphic: SMI LynxEM) 462 */ 463 #define CONFIG_VIDEO 464 #define CONFIG_CFB_CONSOLE 465 #define CONFIG_VIDEO_SMI_LYNXEM 466 #define CONFIG_VIDEO_LOGO 467 /*#define CONFIG_VIDEO_BMP_LOGO*/ 468 #define CONFIG_CONSOLE_EXTRA_INFO 469 #define CONFIG_VGA_AS_SINGLE_DEVICE 470 /* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */ 471 #define CONFIG_SYS_ISA_IO 0xE8000000 472 /* see also drivers/video/videomodes.c */ 473 #define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303 474 #endif 475 476 /*----------------------------------------------------------------------- 477 * FPGA stuff 478 */ 479 /* FPGA internal regs */ 480 #define CONFIG_SYS_FPGA_MODE 0x00 481 #define CONFIG_SYS_FPGA_STATUS 0x02 482 #define CONFIG_SYS_FPGA_TS 0x04 483 #define CONFIG_SYS_FPGA_TS_LOW 0x06 484 #define CONFIG_SYS_FPGA_TS_CAP0 0x10 485 #define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12 486 #define CONFIG_SYS_FPGA_TS_CAP1 0x14 487 #define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16 488 #define CONFIG_SYS_FPGA_TS_CAP2 0x18 489 #define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a 490 #define CONFIG_SYS_FPGA_TS_CAP3 0x1c 491 #define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e 492 493 /* FPGA Mode Reg */ 494 #define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001 495 #define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100 496 #define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000 497 #define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000 498 499 /* FPGA Status Reg */ 500 #define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001 501 #define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002 502 #define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004 503 #define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008 504 #define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000 505 506 #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ 507 #define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ 508 509 /* FPGA program pin configuration */ 510 #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ 511 #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ 512 #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ 513 #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ 514 #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ 515 516 /*----------------------------------------------------------------------- 517 * Definitions for initial stack pointer and data area (in data cache) 518 */ 519 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ 520 #define CONFIG_SYS_TEMP_STACK_OCM 1 521 522 /* On Chip Memory location */ 523 #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 524 #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 525 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ 526 #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */ 527 528 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 529 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 530 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 531 532 /*----------------------------------------------------------------------- 533 * Definitions for GPIO setup (PPC405EP specific) 534 * 535 * GPIO0[0] - External Bus Controller BLAST output 536 * GPIO0[1-9] - Instruction trace outputs -> GPIO 537 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs 538 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO 539 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs 540 * GPIO0[24-27] - UART0 control signal inputs/outputs 541 * GPIO0[28-29] - UART1 data signal input/output 542 * GPIO0[30] - EMAC0 input 543 * GPIO0[31] - EMAC1 reject packet as output 544 */ 545 #define CONFIG_SYS_GPIO0_OSRH 0x40000550 546 #define CONFIG_SYS_GPIO0_OSRL 0x00000110 547 #define CONFIG_SYS_GPIO0_ISR1H 0x00000000 548 /*#define CONFIG_SYS_GPIO0_ISR1L 0x15555445*/ 549 #define CONFIG_SYS_GPIO0_ISR1L 0x15555444 550 #define CONFIG_SYS_GPIO0_TSRH 0x00000000 551 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 552 #define CONFIG_SYS_GPIO0_TCR 0xF7FF8014 553 554 /* 555 * Internal Definitions 556 * 557 * Boot Flags 558 */ 559 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 560 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 561 562 563 #define CONFIG_NO_SERIAL_EEPROM 564 565 /*--------------------------------------------------------------------*/ 566 567 #ifdef CONFIG_NO_SERIAL_EEPROM 568 569 /* 570 !----------------------------------------------------------------------- 571 ! Defines for entry options. 572 ! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that 573 ! are plugged in the board will be utilized as non-ECC DIMMs. 574 !----------------------------------------------------------------------- 575 */ 576 #undef AUTO_MEMORY_CONFIG 577 #define DIMM_READ_ADDR 0xAB 578 #define DIMM_WRITE_ADDR 0xAA 579 580 #define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ 581 #define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ 582 #define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ 583 #define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */ 584 #define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ 585 #define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ 586 #define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ 587 #define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ 588 #define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ 589 #define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ 590 591 /* Defines for CPC0_PLLMR1 Register fields */ 592 #define PLL_ACTIVE 0x80000000 593 #define CPC0_PLLMR1_SSCS 0x80000000 594 #define PLL_RESET 0x40000000 595 #define CPC0_PLLMR1_PLLR 0x40000000 596 /* Feedback multiplier */ 597 #define PLL_FBKDIV 0x00F00000 598 #define CPC0_PLLMR1_FBDV 0x00F00000 599 #define PLL_FBKDIV_16 0x00000000 600 #define PLL_FBKDIV_1 0x00100000 601 #define PLL_FBKDIV_2 0x00200000 602 #define PLL_FBKDIV_3 0x00300000 603 #define PLL_FBKDIV_4 0x00400000 604 #define PLL_FBKDIV_5 0x00500000 605 #define PLL_FBKDIV_6 0x00600000 606 #define PLL_FBKDIV_7 0x00700000 607 #define PLL_FBKDIV_8 0x00800000 608 #define PLL_FBKDIV_9 0x00900000 609 #define PLL_FBKDIV_10 0x00A00000 610 #define PLL_FBKDIV_11 0x00B00000 611 #define PLL_FBKDIV_12 0x00C00000 612 #define PLL_FBKDIV_13 0x00D00000 613 #define PLL_FBKDIV_14 0x00E00000 614 #define PLL_FBKDIV_15 0x00F00000 615 /* Forward A divisor */ 616 #define PLL_FWDDIVA 0x00070000 617 #define CPC0_PLLMR1_FWDVA 0x00070000 618 #define PLL_FWDDIVA_8 0x00000000 619 #define PLL_FWDDIVA_7 0x00010000 620 #define PLL_FWDDIVA_6 0x00020000 621 #define PLL_FWDDIVA_5 0x00030000 622 #define PLL_FWDDIVA_4 0x00040000 623 #define PLL_FWDDIVA_3 0x00050000 624 #define PLL_FWDDIVA_2 0x00060000 625 #define PLL_FWDDIVA_1 0x00070000 626 /* Forward B divisor */ 627 #define PLL_FWDDIVB 0x00007000 628 #define CPC0_PLLMR1_FWDVB 0x00007000 629 #define PLL_FWDDIVB_8 0x00000000 630 #define PLL_FWDDIVB_7 0x00001000 631 #define PLL_FWDDIVB_6 0x00002000 632 #define PLL_FWDDIVB_5 0x00003000 633 #define PLL_FWDDIVB_4 0x00004000 634 #define PLL_FWDDIVB_3 0x00005000 635 #define PLL_FWDDIVB_2 0x00006000 636 #define PLL_FWDDIVB_1 0x00007000 637 /* PLL tune bits */ 638 #define PLL_TUNE_MASK 0x000003FF 639 #define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ 640 #define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ 641 #define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ 642 #define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ 643 #define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ 644 #define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ 645 #define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ 646 647 /* Defines for CPC0_PLLMR0 Register fields */ 648 /* CPU divisor */ 649 #define PLL_CPUDIV 0x00300000 650 #define CPC0_PLLMR0_CCDV 0x00300000 651 #define PLL_CPUDIV_1 0x00000000 652 #define PLL_CPUDIV_2 0x00100000 653 #define PLL_CPUDIV_3 0x00200000 654 #define PLL_CPUDIV_4 0x00300000 655 /* PLB divisor */ 656 #define PLL_PLBDIV 0x00030000 657 #define CPC0_PLLMR0_CBDV 0x00030000 658 #define PLL_PLBDIV_1 0x00000000 659 #define PLL_PLBDIV_2 0x00010000 660 #define PLL_PLBDIV_3 0x00020000 661 #define PLL_PLBDIV_4 0x00030000 662 /* OPB divisor */ 663 #define PLL_OPBDIV 0x00003000 664 #define CPC0_PLLMR0_OPDV 0x00003000 665 #define PLL_OPBDIV_1 0x00000000 666 #define PLL_OPBDIV_2 0x00001000 667 #define PLL_OPBDIV_3 0x00002000 668 #define PLL_OPBDIV_4 0x00003000 669 /* EBC divisor */ 670 #define PLL_EXTBUSDIV 0x00000300 671 #define CPC0_PLLMR0_EPDV 0x00000300 672 #define PLL_EXTBUSDIV_2 0x00000000 673 #define PLL_EXTBUSDIV_3 0x00000100 674 #define PLL_EXTBUSDIV_4 0x00000200 675 #define PLL_EXTBUSDIV_5 0x00000300 676 /* MAL divisor */ 677 #define PLL_MALDIV 0x00000030 678 #define CPC0_PLLMR0_MPDV 0x00000030 679 #define PLL_MALDIV_1 0x00000000 680 #define PLL_MALDIV_2 0x00000010 681 #define PLL_MALDIV_3 0x00000020 682 #define PLL_MALDIV_4 0x00000030 683 /* PCI divisor */ 684 #define PLL_PCIDIV 0x00000003 685 #define CPC0_PLLMR0_PPFD 0x00000003 686 #define PLL_PCIDIV_1 0x00000000 687 #define PLL_PCIDIV_2 0x00000001 688 #define PLL_PCIDIV_3 0x00000002 689 #define PLL_PCIDIV_4 0x00000003 690 691 #ifdef CONFIG_PPCHAMELEON_CLK_25 692 /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */ 693 #define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ 694 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ 695 PLL_MALDIV_1 | PLL_PCIDIV_4) 696 #define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \ 697 PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \ 698 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) 699 700 #define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ 701 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ 702 PLL_MALDIV_1 | PLL_PCIDIV_4) 703 #define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \ 704 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ 705 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) 706 707 #define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ 708 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ 709 PLL_MALDIV_1 | PLL_PCIDIV_4) 710 #define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ 711 PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \ 712 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) 713 714 #define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ 715 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ 716 PLL_MALDIV_1 | PLL_PCIDIV_2) 717 #define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ 718 PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \ 719 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) 720 721 #elif (defined (CONFIG_PPCHAMELEON_CLK_33)) 722 723 /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */ 724 #define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ 725 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ 726 PLL_MALDIV_1 | PLL_PCIDIV_4) 727 #define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \ 728 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ 729 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) 730 731 #define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ 732 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ 733 PLL_MALDIV_1 | PLL_PCIDIV_4) 734 #define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ 735 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ 736 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) 737 738 #define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ 739 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ 740 PLL_MALDIV_1 | PLL_PCIDIV_4) 741 #define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ 742 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ 743 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) 744 745 #define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ 746 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ 747 PLL_MALDIV_1 | PLL_PCIDIV_2) 748 #define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ 749 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ 750 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) 751 752 #else 753 #error "* External frequency (SysClk) not defined! *" 754 #endif 755 756 #if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI) 757 /* Model HI */ 758 #define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55 759 #define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55 760 #define CONFIG_SYS_OPB_FREQ 55555555 761 /* Model ME */ 762 #elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) 763 #define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33 764 #define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33 765 #define CONFIG_SYS_OPB_FREQ 66666666 766 #else 767 /* Model BA (default) */ 768 #define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33 769 #define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33 770 #define CONFIG_SYS_OPB_FREQ 66666666 771 #endif 772 773 #endif /* CONFIG_NO_SERIAL_EEPROM */ 774 775 #define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ 776 #define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */ 777 778 /* 779 * JFFS2 partitions 780 */ 781 782 /* No command line, one static partition */ 783 #undef CONFIG_CMD_MTDPARTS 784 #define CONFIG_JFFS2_DEV "nand0" 785 #define CONFIG_JFFS2_PART_SIZE 0x00400000 786 #define CONFIG_JFFS2_PART_OFFSET 0x00000000 787 788 /* mtdparts command line support */ 789 /* 790 #define CONFIG_CMD_MTDPARTS 791 #define MTDIDS_DEFAULT "nor0=PPChameleon-0,nand0=ppchameleonevb-nand" 792 */ 793 794 /* 256 kB U-boot image */ 795 /* 796 #define MTDPARTS_DEFAULT "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \ 797 "1792k(user),256k(u-boot);" \ 798 "ppchameleonevb-nand:-(nand)" 799 */ 800 801 /* 320 kB U-boot image */ 802 /* 803 #define MTDPARTS_DEFAULT "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \ 804 "1728k(user),320k(u-boot);" \ 805 "ppchameleonevb-nand:-(nand)" 806 */ 807 808 #endif /* __CONFIG_H */ 809