1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4 * Copyright (C) 2016, George McCollister <george.mccollister@gmail.com>
5 */
6
7/dts-v1/;
8
9#include <asm/arch-baytrail/fsp/fsp_configs.h>
10#include <dt-bindings/gpio/x86-gpio.h>
11#include <dt-bindings/interrupt-router/intel-irq.h>
12
13/include/ "skeleton.dtsi"
14/include/ "serial.dtsi"
15/include/ "reset.dtsi"
16/include/ "rtc.dtsi"
17/include/ "tsc_timer.dtsi"
18
19/ {
20	model = "Advantech SOM-DB5800-SOM-6867";
21	compatible = "advantech,som-db5800-som-6867", "intel,baytrail";
22
23	aliases {
24		serial0 = &serial;
25		spi0 = &spi;
26	};
27
28	config {
29		silent_console = <0>;
30	};
31
32	pch_pinctrl {
33		compatible = "intel,x86-pinctrl";
34		reg = <0 0>;
35
36		/* HDA_RSTB */
37		soc_gpio_s0_8@0 {
38			pad-offset = <0x220>;
39			mode-func = <2>;
40		};
41
42		/* HDA_SYNC */
43		soc_gpio_s0_9@0 {
44			pad-offset = <0x250>;
45			mode-func = <2>;
46			pull-assign = <1>;
47		};
48
49		/* HDA_CLK */
50		soc_gpio_s0_10@0 {
51			pad-offset = <0x240>;
52			mode-func = <2>;
53		};
54
55		/* HDA_SDO */
56		soc_gpio_s0_11@0 {
57			pad-offset = <0x260>;
58			mode-func = <2>;
59			pull-assign = <1>;
60		};
61
62		/* HDA_SDI0 */
63		soc_gpio_s0_12@0 {
64			pad-offset = <0x270>;
65			mode-func = <2>;
66		};
67
68		/* SERIRQ */
69		soc_gpio_s0_50@0 {
70			pad-offset = <0x560>;
71			mode-func = <1>;
72		};
73	};
74
75	chosen {
76		stdout-path = "/serial";
77	};
78
79	cpus {
80		#address-cells = <1>;
81		#size-cells = <0>;
82
83		cpu@0 {
84			device_type = "cpu";
85			compatible = "intel,baytrail-cpu";
86			reg = <0>;
87			intel,apic-id = <0>;
88		};
89
90		cpu@1 {
91			device_type = "cpu";
92			compatible = "intel,baytrail-cpu";
93			reg = <1>;
94			intel,apic-id = <2>;
95		};
96
97		cpu@2 {
98			device_type = "cpu";
99			compatible = "intel,baytrail-cpu";
100			reg = <2>;
101			intel,apic-id = <4>;
102		};
103
104		cpu@3 {
105			device_type = "cpu";
106			compatible = "intel,baytrail-cpu";
107			reg = <3>;
108			intel,apic-id = <6>;
109		};
110
111	};
112
113	pci {
114		compatible = "intel,pci-baytrail", "pci-x86";
115		#address-cells = <3>;
116		#size-cells = <2>;
117		u-boot,dm-pre-reloc;
118		ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
119			  0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
120			  0x01000000 0x0 0x2000 0x2000 0 0xe000>;
121
122		pch@1f,0 {
123			reg = <0x0000f800 0 0 0 0>;
124			compatible = "pci8086,0f1c", "intel,pch9";
125			#address-cells = <1>;
126			#size-cells = <1>;
127
128			irq-router {
129				compatible = "intel,irq-router";
130				intel,pirq-config = "ibase";
131				intel,ibase-offset = <0x50>;
132				intel,actl-addr = <0>;
133				intel,pirq-link = <8 8>;
134				intel,pirq-mask = <0xdee0>;
135				intel,pirq-routing = <
136					/* BayTrail PCI devices */
137					PCI_BDF(0, 2, 0) INTA PIRQA
138					PCI_BDF(0, 3, 0) INTA PIRQA
139					PCI_BDF(0, 16, 0) INTA PIRQA
140					PCI_BDF(0, 17, 0) INTA PIRQA
141					PCI_BDF(0, 18, 0) INTA PIRQA
142					PCI_BDF(0, 19, 0) INTA PIRQA
143					PCI_BDF(0, 20, 0) INTA PIRQA
144					PCI_BDF(0, 21, 0) INTA PIRQA
145					PCI_BDF(0, 22, 0) INTA PIRQA
146					PCI_BDF(0, 23, 0) INTA PIRQA
147					PCI_BDF(0, 24, 0) INTA PIRQA
148					PCI_BDF(0, 24, 1) INTC PIRQC
149					PCI_BDF(0, 24, 2) INTD PIRQD
150					PCI_BDF(0, 24, 3) INTB PIRQB
151					PCI_BDF(0, 24, 4) INTA PIRQA
152					PCI_BDF(0, 24, 5) INTC PIRQC
153					PCI_BDF(0, 24, 6) INTD PIRQD
154					PCI_BDF(0, 24, 7) INTB PIRQB
155					PCI_BDF(0, 26, 0) INTA PIRQA
156					PCI_BDF(0, 27, 0) INTA PIRQA
157					PCI_BDF(0, 28, 0) INTA PIRQA
158					PCI_BDF(0, 28, 1) INTB PIRQB
159					PCI_BDF(0, 28, 2) INTC PIRQC
160					PCI_BDF(0, 28, 3) INTD PIRQD
161					PCI_BDF(0, 29, 0) INTA PIRQA
162					PCI_BDF(0, 30, 0) INTA PIRQA
163					PCI_BDF(0, 30, 1) INTD PIRQD
164					PCI_BDF(0, 30, 2) INTB PIRQB
165					PCI_BDF(0, 30, 3) INTC PIRQC
166					PCI_BDF(0, 30, 4) INTD PIRQD
167					PCI_BDF(0, 30, 5) INTB PIRQB
168					PCI_BDF(0, 31, 3) INTB PIRQB
169
170					/*
171					 * PCIe root ports downstream
172					 * interrupts
173					 */
174					PCI_BDF(1, 0, 0) INTA PIRQA
175					PCI_BDF(1, 0, 0) INTB PIRQB
176					PCI_BDF(1, 0, 0) INTC PIRQC
177					PCI_BDF(1, 0, 0) INTD PIRQD
178					PCI_BDF(2, 0, 0) INTA PIRQB
179					PCI_BDF(2, 0, 0) INTB PIRQC
180					PCI_BDF(2, 0, 0) INTC PIRQD
181					PCI_BDF(2, 0, 0) INTD PIRQA
182					PCI_BDF(3, 0, 0) INTA PIRQC
183					PCI_BDF(3, 0, 0) INTB PIRQD
184					PCI_BDF(3, 0, 0) INTC PIRQA
185					PCI_BDF(3, 0, 0) INTD PIRQB
186					PCI_BDF(4, 0, 0) INTA PIRQD
187					PCI_BDF(4, 0, 0) INTB PIRQA
188					PCI_BDF(4, 0, 0) INTC PIRQB
189					PCI_BDF(4, 0, 0) INTD PIRQC
190				>;
191			};
192
193			spi: spi {
194				#address-cells = <1>;
195				#size-cells = <0>;
196				compatible = "intel,ich9-spi";
197				spi-flash@0 {
198					#address-cells = <1>;
199					#size-cells = <1>;
200					reg = <0>;
201					compatible = "macronix,mx25l6405d",
202						"spi-flash";
203					memory-map = <0xff800000 0x00800000>;
204					rw-mrc-cache {
205						label = "rw-mrc-cache";
206						reg = <0x006f0000 0x00010000>;
207					};
208				};
209			};
210
211			gpioa {
212				compatible = "intel,ich6-gpio";
213				u-boot,dm-pre-reloc;
214				reg = <0 0x20>;
215				bank-name = "A";
216				use-lvl-write-cache;
217			};
218
219			gpiob {
220				compatible = "intel,ich6-gpio";
221				u-boot,dm-pre-reloc;
222				reg = <0x20 0x20>;
223				bank-name = "B";
224				use-lvl-write-cache;
225			};
226
227			gpioc {
228				compatible = "intel,ich6-gpio";
229				u-boot,dm-pre-reloc;
230				reg = <0x40 0x20>;
231				bank-name = "C";
232				use-lvl-write-cache;
233			};
234
235			gpiod {
236				compatible = "intel,ich6-gpio";
237				u-boot,dm-pre-reloc;
238				reg = <0x60 0x20>;
239				bank-name = "D";
240				use-lvl-write-cache;
241			};
242
243			gpioe {
244				compatible = "intel,ich6-gpio";
245				u-boot,dm-pre-reloc;
246				reg = <0x80 0x20>;
247				bank-name = "E";
248				use-lvl-write-cache;
249			};
250
251			gpiof {
252				compatible = "intel,ich6-gpio";
253				u-boot,dm-pre-reloc;
254				reg = <0xA0 0x20>;
255				bank-name = "F";
256				use-lvl-write-cache;
257			};
258		};
259	};
260
261	fsp {
262		compatible = "intel,baytrail-fsp";
263		fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
264		fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
265		fsp,mrc-init-spd-addr1 = <0xa0>;
266		fsp,mrc-init-spd-addr2 = <0xa2>;
267		fsp,enable-spi;
268		fsp,enable-sata;
269		fsp,sata-mode = <SATA_MODE_AHCI>;
270		fsp,enable-azalia;
271		fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
272		fsp,enable-dma0;
273		fsp,enable-dma1;
274		fsp,enable-i2c0;
275		fsp,enable-i2c1;
276		fsp,enable-i2c2;
277		fsp,enable-i2c3;
278		fsp,enable-i2c4;
279		fsp,enable-i2c5;
280		fsp,enable-i2c6;
281		fsp,enable-pwm0;
282		fsp,enable-pwm1;
283		fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
284		fsp,aperture-size = <APERTURE_SIZE_256MB>;
285		fsp,gtt-size = <GTT_SIZE_2MB>;
286		fsp,scc-mode = <SCC_MODE_PCI>;
287		fsp,os-selection = <OS_SELECTION_LINUX>;
288		fsp,enable-igd;
289	};
290
291	microcode {
292		update@0 {
293#include "microcode/m0130673325.dtsi"
294		};
295		update@1 {
296#include "microcode/m0130679907.dtsi"
297		};
298	};
299
300};
301