1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2011 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <asm/io.h>
8 #include <asm/arch/imx-regs.h>
9 #include <asm/arch/sys_proto.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/iomux-mx53.h>
13 #include <linux/errno.h>
14 #include <netdev.h>
15 #include <mmc.h>
16 #include <fsl_esdhc.h>
17 #include <asm/gpio.h>
18
19 #define ETHERNET_INT IMX_GPIO_NR(2, 31)
20
21 DECLARE_GLOBAL_DATA_PTR;
22
dram_init(void)23 int dram_init(void)
24 {
25 u32 size1, size2;
26
27 size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
28 size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
29
30 gd->ram_size = size1 + size2;
31
32 return 0;
33 }
dram_init_banksize(void)34 int dram_init_banksize(void)
35 {
36 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
37 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
38
39 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
40 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
41
42 return 0;
43 }
44
45 #ifdef CONFIG_NAND_MXC
setup_iomux_nand(void)46 static void setup_iomux_nand(void)
47 {
48 static const iomux_v3_cfg_t nand_pads[] = {
49 NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
50 PAD_CTL_DSE_HIGH),
51 NEW_PAD_CTRL(MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1,
52 PAD_CTL_DSE_HIGH),
53 NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
54 PAD_CTL_PUS_100K_UP),
55 NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
56 PAD_CTL_DSE_HIGH),
57 NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
58 PAD_CTL_DSE_HIGH),
59 NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
60 PAD_CTL_PUS_100K_UP),
61 NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
62 PAD_CTL_DSE_HIGH),
63 NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
64 PAD_CTL_DSE_HIGH),
65 NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
66 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
67 NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
68 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
69 NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
70 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
71 NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
72 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
73 NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
74 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
75 NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
76 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
77 NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
78 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
79 NEW_PAD_CTRL(MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7,
80 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
81 };
82
83 u32 i, reg;
84
85 reg = __raw_readl(M4IF_BASE_ADDR + 0xc);
86 reg &= ~M4IF_GENP_WEIM_MM_MASK;
87 __raw_writel(reg, M4IF_BASE_ADDR + 0xc);
88 for (i = 0x4; i < 0x94; i += 0x18) {
89 reg = __raw_readl(WEIM_BASE_ADDR + i);
90 reg &= ~WEIM_GCR2_MUX16_BYP_GRANT_MASK;
91 __raw_writel(reg, WEIM_BASE_ADDR + i);
92 }
93
94 imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
95 }
96 #else
setup_iomux_nand(void)97 static void setup_iomux_nand(void)
98 {
99 }
100 #endif
101
102 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
103 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
104
setup_iomux_uart(void)105 static void setup_iomux_uart(void)
106 {
107 static const iomux_v3_cfg_t uart_pads[] = {
108 NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__UART1_RXD_MUX, UART_PAD_CTRL),
109 NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__UART1_TXD_MUX, UART_PAD_CTRL),
110 };
111
112 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
113 }
114
115 #ifdef CONFIG_FSL_ESDHC
116 struct fsl_esdhc_cfg esdhc_cfg[2] = {
117 {MMC_SDHC1_BASE_ADDR},
118 {MMC_SDHC2_BASE_ADDR},
119 };
120
board_mmc_getcd(struct mmc * mmc)121 int board_mmc_getcd(struct mmc *mmc)
122 {
123 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
124 int ret;
125
126 imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
127 gpio_direction_input(IMX_GPIO_NR(1, 1));
128 imx_iomux_v3_setup_pad(MX53_PAD_GPIO_4__GPIO1_4);
129 gpio_direction_input(IMX_GPIO_NR(1, 4));
130
131 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
132 ret = !gpio_get_value(IMX_GPIO_NR(1, 1));
133 else
134 ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
135
136 return ret;
137 }
138
139 #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
140 PAD_CTL_PUS_100K_UP)
141 #define SD_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH)
142 #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
143 PAD_CTL_DSE_HIGH)
144
board_mmc_init(bd_t * bis)145 int board_mmc_init(bd_t *bis)
146 {
147 static const iomux_v3_cfg_t sd1_pads[] = {
148 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
149 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_CLK_PAD_CTRL),
150 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
151 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
152 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
153 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
154 };
155
156 static const iomux_v3_cfg_t sd2_pads[] = {
157 NEW_PAD_CTRL(MX53_PAD_SD2_CMD__ESDHC2_CMD, SD_CMD_PAD_CTRL),
158 NEW_PAD_CTRL(MX53_PAD_SD2_CLK__ESDHC2_CLK, SD_CLK_PAD_CTRL),
159 NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__ESDHC2_DAT0, SD_PAD_CTRL),
160 NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__ESDHC2_DAT1, SD_PAD_CTRL),
161 NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__ESDHC2_DAT2, SD_PAD_CTRL),
162 NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__ESDHC2_DAT3, SD_PAD_CTRL),
163 NEW_PAD_CTRL(MX53_PAD_PATA_DATA12__ESDHC2_DAT4, SD_PAD_CTRL),
164 NEW_PAD_CTRL(MX53_PAD_PATA_DATA13__ESDHC2_DAT5, SD_PAD_CTRL),
165 NEW_PAD_CTRL(MX53_PAD_PATA_DATA14__ESDHC2_DAT6, SD_PAD_CTRL),
166 NEW_PAD_CTRL(MX53_PAD_PATA_DATA15__ESDHC2_DAT7, SD_PAD_CTRL),
167 };
168
169 u32 index;
170 int ret;
171
172 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
173 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
174
175 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
176 switch (index) {
177 case 0:
178 imx_iomux_v3_setup_multiple_pads(sd1_pads,
179 ARRAY_SIZE(sd1_pads));
180 break;
181 case 1:
182 imx_iomux_v3_setup_multiple_pads(sd2_pads,
183 ARRAY_SIZE(sd2_pads));
184 break;
185 default:
186 printf("Warning: you configured more ESDHC controller"
187 "(%d) as supported by the board(2)\n",
188 CONFIG_SYS_FSL_ESDHC_NUM);
189 return -EINVAL;
190 }
191 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
192 if (ret)
193 return ret;
194 }
195
196 return 0;
197 }
198 #endif
199
weim_smc911x_iomux(void)200 static void weim_smc911x_iomux(void)
201 {
202 static const iomux_v3_cfg_t weim_smc911x_pads[] = {
203 /* Data bus */
204 NEW_PAD_CTRL(MX53_PAD_EIM_D16__EMI_WEIM_D_16,
205 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
206 NEW_PAD_CTRL(MX53_PAD_EIM_D17__EMI_WEIM_D_17,
207 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
208 NEW_PAD_CTRL(MX53_PAD_EIM_D18__EMI_WEIM_D_18,
209 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
210 NEW_PAD_CTRL(MX53_PAD_EIM_D19__EMI_WEIM_D_19,
211 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
212 NEW_PAD_CTRL(MX53_PAD_EIM_D20__EMI_WEIM_D_20,
213 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
214 NEW_PAD_CTRL(MX53_PAD_EIM_D21__EMI_WEIM_D_21,
215 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
216 NEW_PAD_CTRL(MX53_PAD_EIM_D22__EMI_WEIM_D_22,
217 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
218 NEW_PAD_CTRL(MX53_PAD_EIM_D23__EMI_WEIM_D_23,
219 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
220 NEW_PAD_CTRL(MX53_PAD_EIM_D24__EMI_WEIM_D_24,
221 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
222 NEW_PAD_CTRL(MX53_PAD_EIM_D25__EMI_WEIM_D_25,
223 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
224 NEW_PAD_CTRL(MX53_PAD_EIM_D26__EMI_WEIM_D_26,
225 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
226 NEW_PAD_CTRL(MX53_PAD_EIM_D27__EMI_WEIM_D_27,
227 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
228 NEW_PAD_CTRL(MX53_PAD_EIM_D28__EMI_WEIM_D_28,
229 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
230 NEW_PAD_CTRL(MX53_PAD_EIM_D29__EMI_WEIM_D_29,
231 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
232 NEW_PAD_CTRL(MX53_PAD_EIM_D30__EMI_WEIM_D_30,
233 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
234 NEW_PAD_CTRL(MX53_PAD_EIM_D31__EMI_WEIM_D_31,
235 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
236
237 /* Address lines */
238 NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
239 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
240 NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
241 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
242 NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
243 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
244 NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
245 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
246 NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
247 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
248 NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
249 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
250 NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
251 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
252
253 /* other EIM signals for ethernet */
254 MX53_PAD_EIM_OE__EMI_WEIM_OE,
255 MX53_PAD_EIM_RW__EMI_WEIM_RW,
256 MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
257 };
258
259 /* ETHERNET_INT as GPIO2_31 */
260 imx_iomux_v3_setup_pad(MX53_PAD_EIM_EB3__GPIO2_31);
261 gpio_direction_input(ETHERNET_INT);
262
263 /* WEIM bus */
264 imx_iomux_v3_setup_multiple_pads(weim_smc911x_pads,
265 ARRAY_SIZE(weim_smc911x_pads));
266 }
267
weim_cs1_settings(void)268 static void weim_cs1_settings(void)
269 {
270 struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
271
272 writel(MX53ARD_CS1GCR1, &weim_regs->cs1gcr1);
273 writel(0x0, &weim_regs->cs1gcr2);
274 writel(MX53ARD_CS1RCR1, &weim_regs->cs1rcr1);
275 writel(MX53ARD_CS1RCR2, &weim_regs->cs1rcr2);
276 writel(MX53ARD_CS1WCR1, &weim_regs->cs1wcr1);
277 writel(0x0, &weim_regs->cs1wcr2);
278 writel(0x0, &weim_regs->wcr);
279
280 set_chipselect_size(CS0_64M_CS1_64M);
281 }
282
board_early_init_f(void)283 int board_early_init_f(void)
284 {
285 setup_iomux_nand();
286 setup_iomux_uart();
287 return 0;
288 }
289
board_init(void)290 int board_init(void)
291 {
292 /* address of boot parameters */
293 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
294
295 return 0;
296 }
297
board_eth_init(bd_t * bis)298 int board_eth_init(bd_t *bis)
299 {
300 int rc = -ENODEV;
301
302 weim_smc911x_iomux();
303 weim_cs1_settings();
304
305 #ifdef CONFIG_SMC911X
306 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
307 #endif
308 return rc;
309 }
310
checkboard(void)311 int checkboard(void)
312 {
313 puts("Board: MX53ARD\n");
314
315 return 0;
316 }
317